/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2015, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef _input_system_defs_h
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#define _input_system_defs_h
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/* csi controller modes */
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#define HIVE_CSI_CONFIG_MAIN 0
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#define HIVE_CSI_CONFIG_STEREO1 4
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#define HIVE_CSI_CONFIG_STEREO2 8
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/* general purpose register IDs */
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/* Stream Multicast select modes */
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#define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0
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#define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1
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#define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2
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/* Stream Mux select modes */
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#define HIVE_ISYS_GPREG_MUX_IDX 3
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/* streaming monitor status and control */
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#define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4
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#define HIVE_ISYS_GPREG_STRMON_COND_IDX 5
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#define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6
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#define HIVE_ISYS_GPREG_SRST_IDX 7
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#define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8
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#define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9
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#define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10
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/* Bit numbers of the soft reset register */
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#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0
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#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1
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#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2
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#define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3
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#define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4
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#define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5
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#define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6
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#define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7
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#define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8
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#define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9
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/* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */
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#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */
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#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10
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#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11
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#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12
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#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13
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#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14
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/* -- */
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#define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15
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#define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16
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#define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17
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#define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv
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#define HIVE_ISYS_GPREG_SRST_DMA_BIT 19
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#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20
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#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21
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#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22
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#define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23
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#define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24
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#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0
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#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1
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#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2
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#define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3
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#define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4
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#define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5
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/* streaming monitor port id's */
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#define HIVE_ISYS_STR_MON_PORT_CAPA 0
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#define HIVE_ISYS_STR_MON_PORT_CAPB 1
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#define HIVE_ISYS_STR_MON_PORT_CAPC 2
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#define HIVE_ISYS_STR_MON_PORT_ACQ 3
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#define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4
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#define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5
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#define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6
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#define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7
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#define HIVE_ISYS_STR_MON_PORT_PIXA 8
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#define HIVE_ISYS_STR_MON_PORT_PIXB 9
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/* interrupt bit ID's */
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#define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0
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#define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1
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#define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2
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#define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3
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#define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4
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#define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5
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#define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6
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#define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7
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/*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/
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#define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8
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#define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9
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/*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/
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#define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10
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#define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11
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/*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/
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#define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12
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/*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/
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#define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13
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#define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14
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#define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15
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#define HIVE_ISYS_IRQ_CIO2AHB 16
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#define HIVE_ISYS_IRQ_DMA_BIT_ID 17
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#define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18
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#define HIVE_ISYS_IRQ_NUM_BITS 19
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/* DMA */
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#define HIVE_ISYS_DMA_CHANNEL 0
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#define HIVE_ISYS_DMA_IBUF_DDR_CONN 0
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#define HIVE_ISYS_DMA_HEIGHT 1
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#define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */
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#define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */
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#define HIVE_ISYS_DMA_CROP 0 /* no cropping */
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#define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */
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#endif /* _input_system_defs_h */
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