/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Support for Medifield PNW Camera Imaging ISP subsystem.
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*
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* Copyright (c) 2012 Intel Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*
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*/
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#ifndef ATOMISP_REGS_H
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#define ATOMISP_REGS_H
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/* common register definitions */
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#define PCICMDSTS 0x01
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#define INTR 0x0f
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#define MSI_CAPID 0x24
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#define MSI_ADDRESS 0x25
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#define MSI_DATA 0x26
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#define INTR_CTL 0x27
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#define PCI_MSI_CAPID 0x90
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#define PCI_MSI_ADDR 0x94
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#define PCI_MSI_DATA 0x98
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#define PCI_INTERRUPT_CTRL 0x9C
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#define PCI_I_CONTROL 0xfc
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/* MRFLD specific register definitions */
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#define MRFLD_CSI_AFE 0x39
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#define MRFLD_CSI_CONTROL 0x3a
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#define MRFLD_CSI_RCOMP 0x3d
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#define MRFLD_PCI_PMCS 0x84
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#define MRFLD_PCI_CSI_ACCESS_CTRL_VIOL 0xd4
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#define MRFLD_PCI_CSI_AFE_HS_CONTROL 0xdc
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#define MRFLD_PCI_CSI_AFE_RCOMP_CONTROL 0xe0
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#define MRFLD_PCI_CSI_CONTROL 0xe8
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#define MRFLD_PCI_CSI_AFE_TRIM_CONTROL 0xe4
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#define MRFLD_PCI_CSI_DEADLINE_CONTROL 0xec
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#define MRFLD_PCI_CSI_RCOMP_CONTROL 0xf4
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/* Select Arasan (legacy)/Intel input system */
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#define MRFLD_PCI_CSI_CONTROL_PARPATHEN BIT(24)
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/* Enable CSI interface (ANN B0/K0) */
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#define MRFLD_PCI_CSI_CONTROL_CSI_READY BIT(25)
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/*
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* Enables the combining of adjacent 32-byte read requests to the same
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* cache line. When cleared, each 32-byte read request is sent as a
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* separate request on the IB interface.
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*/
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#define MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING 0x1
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/*
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* Register: MRFLD_PCI_CSI_RCOMP_CONTROL
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* If cleared, the high speed clock going to the digital logic is gated when
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* RCOMP update is happening. The clock is gated for a minimum of 100 nsec.
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* If this bit is set, then the high speed clock is not gated during the
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* update cycle.
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*/
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#define MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE 0x800000
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/*
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* Enables the combining of adjacent 32-byte write requests to the same
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* cache line. When cleared, each 32-byte write request is sent as a
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* separate request on the IB interface.
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*/
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#define MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING 0x2
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#define MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK 0xc
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#define MRFLD_PCI_CSI1_HSRXCLKTRIM 0x2
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#define MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT 16
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#define MRFLD_PCI_CSI2_HSRXCLKTRIM 0x3
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#define MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT 24
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#define MRFLD_PCI_CSI3_HSRXCLKTRIM 0x2
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#define MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT 28
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#define MRFLD_PCI_CSI_HSRXCLKTRIM_MASK 0xf
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/*
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* This register is IUINT MMIO register, it is used to select the CSI
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* receiver backend.
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* 1: SH CSI backend
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* 0: Arasan CSI backend
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*/
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#define MRFLD_CSI_RECEIVER_SELECTION_REG 0x8081c
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#define MRFLD_INTR_CLEAR_REG 0x50c
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#define MRFLD_INTR_STATUS_REG 0x508
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#define MRFLD_INTR_ENABLE_REG 0x510
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#define MRFLD_MAX_ZOOM_FACTOR 1024
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/* MRFLD ISP POWER related */
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#define MRFLD_ISPSSPM0 0x39
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#define MRFLD_ISPSSPM0_ISPSSC_OFFSET 0
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#define MRFLD_ISPSSPM0_ISPSSS_OFFSET 24
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#define MRFLD_ISPSSPM0_ISPSSC_MASK 0x3
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#define MRFLD_ISPSSPM0_IUNIT_POWER_ON 0
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#define MRFLD_ISPSSPM0_IUNIT_POWER_OFF 0x3
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#define MRFLD_ISPSSDVFS 0x13F
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#define MRFLD_BIT0 0x0001
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#define MRFLD_BIT1 0x0002
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/* MRFLD CSI lane configuration related */
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#define MRFLD_PORT_CONFIG_NUM 8
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#define MRFLD_PORT_NUM 3
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#define MRFLD_PORT1_ENABLE_SHIFT 0
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#define MRFLD_PORT2_ENABLE_SHIFT 1
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#define MRFLD_PORT3_ENABLE_SHIFT 2
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#define MRFLD_PORT1_LANES_SHIFT 3
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#define MRFLD_PORT2_LANES_SHIFT 7
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#define MRFLD_PORT3_LANES_SHIFT 8
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#define MRFLD_PORT_CONFIG_MASK 0x000f03ff
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#define MRFLD_PORT_CONFIGCODE_SHIFT 16
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#define MRFLD_ALL_CSI_PORTS_OFF_MASK 0x7
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#define CHV_PORT3_LANES_SHIFT 9
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#define CHV_PORT_CONFIG_MASK 0x1f07ff
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#define ISPSSPM1 0x3a
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#define ISP_FREQ_STAT_MASK (0x1f << ISP_FREQ_STAT_OFFSET)
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#define ISP_REQ_FREQ_MASK 0x1f
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#define ISP_FREQ_VALID_MASK (0x1 << ISP_FREQ_VALID_OFFSET)
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#define ISP_FREQ_STAT_OFFSET 0x18
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#define ISP_REQ_GUAR_FREQ_OFFSET 0x8
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#define ISP_REQ_FREQ_OFFSET 0x0
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#define ISP_FREQ_VALID_OFFSET 0x7
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#define ISP_FREQ_RULE_ANY 0x0
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#define ISP_FREQ_457MHZ 0x1C9
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#define ISP_FREQ_400MHZ 0x190
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#define ISP_FREQ_356MHZ 0x164
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#define ISP_FREQ_320MHZ 0x140
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#define ISP_FREQ_266MHZ 0x10a
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#define ISP_FREQ_200MHZ 0xc8
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#define ISP_FREQ_100MHZ 0x64
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#define HPLL_FREQ_800MHZ 0x320
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#define HPLL_FREQ_1600MHZ 0x640
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#define HPLL_FREQ_2000MHZ 0x7D0
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#define CCK_FUSE_REG_0 0x08
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#define CCK_FUSE_HPLL_FREQ_MASK 0x03
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/* ISP2401 CSI2+ receiver delay settings */
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#define CSI2_PORT_A_BASE 0xC0000
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#define CSI2_PORT_B_BASE 0xC2000
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#define CSI2_PORT_C_BASE 0xC4000
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#define CSI2_LANE_CL_BASE 0x418
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#define CSI2_LANE_D0_BASE 0x420
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#define CSI2_LANE_D1_BASE 0x428
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#define CSI2_LANE_D2_BASE 0x430
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#define CSI2_LANE_D3_BASE 0x438
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#define CSI2_REG_RX_CSI_DLY_CNT_TERMEN 0
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#define CSI2_REG_RX_CSI_DLY_CNT_SETTLE 0x4
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#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC0418
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#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC041C
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#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC0420
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#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC0424
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#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC0428
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#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC042C
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#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE2 0xC0430
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#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE2 0xC0434
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#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE3 0xC0438
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#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE3 0xC043C
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#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC2418
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#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC241C
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#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC2420
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#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC2424
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#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC2428
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#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC242C
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#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC4418
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#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC441C
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#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC4420
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#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC4424
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#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC4428
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#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC442C
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#define DMA_BURST_SIZE_REG 0xCD408
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#define ISP_DFS_TRY_TIMES 2
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#endif /* ATOMISP_REGS_H */
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