// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel Speed Select Interface: Mbox via MSR Interface
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* Copyright (c) 2019, Intel Corporation.
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* All rights reserved.
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*
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* Author: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
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*/
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#include <linux/module.h>
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#include <linux/cpuhotplug.h>
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#include <linux/pci.h>
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#include <linux/sched/signal.h>
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#include <linux/slab.h>
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#include <linux/suspend.h>
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#include <linux/topology.h>
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#include <linux/uaccess.h>
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#include <uapi/linux/isst_if.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include "isst_if_common.h"
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#define MSR_OS_MAILBOX_INTERFACE 0xB0
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#define MSR_OS_MAILBOX_DATA 0xB1
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#define MSR_OS_MAILBOX_BUSY_BIT 31
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/*
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* Based on experiments count is never more than 1, as the MSR overhead
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* is enough to finish the command. So here this is the worst case number.
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*/
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#define OS_MAILBOX_RETRY_COUNT 3
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static int isst_if_send_mbox_cmd(u8 command, u8 sub_command, u32 parameter,
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u32 command_data, u32 *response_data)
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{
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u32 retries;
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u64 data;
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int ret;
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/* Poll for rb bit == 0 */
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retries = OS_MAILBOX_RETRY_COUNT;
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do {
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rdmsrl(MSR_OS_MAILBOX_INTERFACE, data);
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if (data & BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT)) {
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ret = -EBUSY;
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continue;
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}
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ret = 0;
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break;
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} while (--retries);
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if (ret)
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return ret;
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/* Write DATA register */
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wrmsrl(MSR_OS_MAILBOX_DATA, command_data);
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/* Write command register */
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data = BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT) |
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(parameter & GENMASK_ULL(13, 0)) << 16 |
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(sub_command << 8) |
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command;
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wrmsrl(MSR_OS_MAILBOX_INTERFACE, data);
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/* Poll for rb bit == 0 */
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retries = OS_MAILBOX_RETRY_COUNT;
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do {
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rdmsrl(MSR_OS_MAILBOX_INTERFACE, data);
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if (data & BIT_ULL(MSR_OS_MAILBOX_BUSY_BIT)) {
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ret = -EBUSY;
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continue;
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}
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if (data & 0xff)
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return -ENXIO;
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if (response_data) {
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rdmsrl(MSR_OS_MAILBOX_DATA, data);
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*response_data = data;
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}
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ret = 0;
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break;
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} while (--retries);
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return ret;
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}
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struct msrl_action {
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int err;
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struct isst_if_mbox_cmd *mbox_cmd;
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};
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/* revisit, smp_call_function_single should be enough for atomic mailbox! */
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static void msrl_update_func(void *info)
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{
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struct msrl_action *act = info;
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act->err = isst_if_send_mbox_cmd(act->mbox_cmd->command,
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act->mbox_cmd->sub_command,
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act->mbox_cmd->parameter,
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act->mbox_cmd->req_data,
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&act->mbox_cmd->resp_data);
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}
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static long isst_if_mbox_proc_cmd(u8 *cmd_ptr, int *write_only, int resume)
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{
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struct msrl_action action;
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int ret;
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action.mbox_cmd = (struct isst_if_mbox_cmd *)cmd_ptr;
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if (isst_if_mbox_cmd_invalid(action.mbox_cmd))
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return -EINVAL;
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if (isst_if_mbox_cmd_set_req(action.mbox_cmd) &&
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!capable(CAP_SYS_ADMIN))
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return -EPERM;
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/*
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* To complete mailbox command, we need to access two MSRs.
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* So we don't want race to complete a mailbox transcation.
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* Here smp_call ensures that msrl_update_func() has no race
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* and also with wait flag, wait for completion.
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* smp_call_function_single is using get_cpu() and put_cpu().
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*/
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ret = smp_call_function_single(action.mbox_cmd->logical_cpu,
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msrl_update_func, &action, 1);
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if (ret)
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return ret;
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if (!action.err && !resume && isst_if_mbox_cmd_set_req(action.mbox_cmd))
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action.err = isst_store_cmd(action.mbox_cmd->command,
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action.mbox_cmd->sub_command,
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action.mbox_cmd->logical_cpu, 1,
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action.mbox_cmd->parameter,
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action.mbox_cmd->req_data);
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*write_only = 0;
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return action.err;
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}
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static int isst_pm_notify(struct notifier_block *nb,
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unsigned long mode, void *_unused)
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{
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switch (mode) {
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case PM_POST_HIBERNATION:
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case PM_POST_RESTORE:
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case PM_POST_SUSPEND:
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isst_resume_common();
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break;
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default:
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break;
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}
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return 0;
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}
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static struct notifier_block isst_pm_nb = {
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.notifier_call = isst_pm_notify,
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};
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static const struct x86_cpu_id isst_if_cpu_ids[] = {
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X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL),
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{}
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};
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MODULE_DEVICE_TABLE(x86cpu, isst_if_cpu_ids);
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static int __init isst_if_mbox_init(void)
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{
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struct isst_if_cmd_cb cb;
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const struct x86_cpu_id *id;
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u64 data;
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int ret;
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id = x86_match_cpu(isst_if_cpu_ids);
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if (!id)
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return -ENODEV;
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/* Check presence of mailbox MSRs */
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ret = rdmsrl_safe(MSR_OS_MAILBOX_INTERFACE, &data);
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if (ret)
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return ret;
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ret = rdmsrl_safe(MSR_OS_MAILBOX_DATA, &data);
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if (ret)
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return ret;
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memset(&cb, 0, sizeof(cb));
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cb.cmd_size = sizeof(struct isst_if_mbox_cmd);
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cb.offset = offsetof(struct isst_if_mbox_cmds, mbox_cmd);
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cb.cmd_callback = isst_if_mbox_proc_cmd;
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cb.owner = THIS_MODULE;
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ret = isst_if_cdev_register(ISST_IF_DEV_MBOX, &cb);
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if (ret)
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return ret;
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ret = register_pm_notifier(&isst_pm_nb);
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if (ret)
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isst_if_cdev_unregister(ISST_IF_DEV_MBOX);
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return ret;
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}
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module_init(isst_if_mbox_init)
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static void __exit isst_if_mbox_exit(void)
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{
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unregister_pm_notifier(&isst_pm_nb);
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isst_if_cdev_unregister(ISST_IF_DEV_MBOX);
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}
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module_exit(isst_if_mbox_exit)
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Intel speed select interface mailbox driver");
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