/* SPDX-License-Identifier: GPL-2.0 */
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/** @file pcie_core.c
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*
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* Contains PCIe related functions that are shared between different driver models (e.g. firmware
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* builds, DHD builds, BMAC builds), in order to avoid code duplication.
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*
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* Copyright (C) 1999-2017, Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a license
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* other than the GPL, without Broadcom's express prior written consent.
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*
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*
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* <<Broadcom-WL-IPTag/Open:>>
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*
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* $Id: pcie_core.c 658668 2016-09-09 00:42:11Z $
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*/
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#include <bcm_cfg.h>
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#include <typedefs.h>
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#include <bcmutils.h>
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#include <bcmdefs.h>
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#include <osl.h>
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#include <siutils.h>
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#include <hndsoc.h>
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#include <sbchipc.h>
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#include <pcicfg.h>
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#include "pcie_core.h"
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/* local prototypes */
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/* local variables */
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/* function definitions */
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#ifdef BCMDRIVER
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void pcie_watchdog_reset(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs)
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{
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uint32 val, i, lsc;
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uint16 cfg_offset[] = {PCIECFGREG_STATUS_CMD, PCIECFGREG_PM_CSR,
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PCIECFGREG_MSI_CAP, PCIECFGREG_MSI_ADDR_L,
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PCIECFGREG_MSI_ADDR_H, PCIECFGREG_MSI_DATA,
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PCIECFGREG_LINK_STATUS_CTRL2, PCIECFGREG_RBAR_CTRL,
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PCIECFGREG_PML1_SUB_CTRL1, PCIECFGREG_REG_BAR2_CONFIG,
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PCIECFGREG_REG_BAR3_CONFIG};
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sbpcieregs_t *pcie = NULL;
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uint32 origidx = si_coreidx(sih);
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/* Switch to PCIE2 core */
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pcie = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);
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BCM_REFERENCE(pcie);
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ASSERT(pcie != NULL);
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/* Disable/restore ASPM Control to protect the watchdog reset */
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W_REG(osh, &sbpcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
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lsc = R_REG(osh, &sbpcieregs->configdata);
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val = lsc & (~PCIE_ASPM_ENAB);
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W_REG(osh, &sbpcieregs->configdata, val);
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si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, 4);
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OSL_DELAY(100000);
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W_REG(osh, &sbpcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
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W_REG(osh, &sbpcieregs->configdata, lsc);
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if (sih->buscorerev <= 13) {
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/* Write configuration registers back to the shadow registers
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* cause shadow registers are cleared out after watchdog reset.
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*/
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for (i = 0; i < ARRAYSIZE(cfg_offset); i++) {
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W_REG(osh, &sbpcieregs->configaddr, cfg_offset[i]);
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val = R_REG(osh, &sbpcieregs->configdata);
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W_REG(osh, &sbpcieregs->configdata, val);
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}
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}
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si_setcoreidx(sih, origidx);
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}
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/* CRWLPCIEGEN2-117 pcie_pipe_Iddq should be controlled
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* by the L12 state from MAC to save power by putting the
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* SerDes analog in IDDQ mode
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*/
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void pcie_serdes_iddqdisable(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs)
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{
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sbpcieregs_t *pcie = NULL;
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uint crwlpciegen2_117_disable = 0;
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uint32 origidx = si_coreidx(sih);
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crwlpciegen2_117_disable = PCIE_PipeIddqDisable0 | PCIE_PipeIddqDisable1;
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/* Switch to PCIE2 core */
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pcie = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);
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BCM_REFERENCE(pcie);
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ASSERT(pcie != NULL);
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OR_REG(osh, &sbpcieregs->control,
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crwlpciegen2_117_disable);
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si_setcoreidx(sih, origidx);
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}
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#define PCIE_PMCR_REFUP_MASK 0x3f0001e0
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#define PCIE_PMCR_REFEXT_MASK 0x400000
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#define PCIE_PMCR_REFUP_100US 0x38000080
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#define PCIE_PMCR_REFEXT_100US 0x400000
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/* Set PCIE TRefUp time to 100us */
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void pcie_set_trefup_time_100us(si_t *sih)
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{
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si_corereg(sih, sih->buscoreidx,
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OFFSETOF(sbpcieregs_t, configaddr), ~0, PCI_PMCR_REFUP);
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si_corereg(sih, sih->buscoreidx,
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OFFSETOF(sbpcieregs_t, configdata), PCIE_PMCR_REFUP_MASK, PCIE_PMCR_REFUP_100US);
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si_corereg(sih, sih->buscoreidx,
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OFFSETOF(sbpcieregs_t, configaddr), ~0, PCI_PMCR_REFUP_EXT);
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si_corereg(sih, sih->buscoreidx,
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OFFSETOF(sbpcieregs_t, configdata), PCIE_PMCR_REFEXT_MASK, PCIE_PMCR_REFEXT_100US);
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}
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#endif /* BCMDRIVER */
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