/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Rockchip PCIe Apis For WIFI
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*
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* Copyright (c) 2022, Rockchip Electronics Co., Ltd.
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*/
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#ifndef __RK_DHD_PCIE_LINUX_H__
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#define __RK_DHD_PCIE_LINUX_H__
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#include <typedefs.h>
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#include <sbchipc.h>
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#include <pcie_core.h>
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#include <dhd_pcie.h>
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#include <linux/aspm_ext.h>
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static inline void
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rk_dhd_bus_l1ss_enable_rc_ep(dhd_bus_t *bus, bool enable)
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{
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if (!bus->rc_ep_aspm_cap || !bus->rc_ep_l1ss_cap) {
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pr_err("%s: NOT L1SS CAPABLE rc_ep_aspm_cap: %d rc_ep_l1ss_cap: %d\n",
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__func__, bus->rc_ep_aspm_cap, bus->rc_ep_l1ss_cap);
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return;
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}
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/* Disable ASPM of RC and EP */
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pcie_aspm_ext_l1ss_enable(bus->dev, bus->rc_dev, enable);
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}
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static inline bool
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rk_dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t *bus)
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{
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return pcie_aspm_ext_is_rc_ep_l1ss_capable(bus->dev, bus->rc_dev);
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}
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#endif /* __RK_DHD_PCIE_LINUX_H__ */
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