/** @file pcie_core.c
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*
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* Contains PCIe related functions that are shared between different driver models (e.g. firmware
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* builds, DHD builds, BMAC builds), in order to avoid code duplication.
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*
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* Copyright (C) 2020, Broadcom.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2 (the "GPL"),
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* available at http://www.broadcom.com/licenses/GPLv2.php, with the
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* following added to such license:
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*
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* As a special exception, the copyright holders of this software give you
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* permission to link this software with independent modules, and to copy and
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* distribute the resulting executable under terms of your choice, provided that
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* you also meet, for each linked independent module, the terms and conditions of
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* the license of that module. An independent module is a module which is not
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* derived from this software. The special exception does not apply to any
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* modifications of the software.
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*
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*
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* <<Broadcom-WL-IPTag/Dual:>>
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*/
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#include <typedefs.h>
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#include <bcmutils.h>
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#include <bcmdefs.h>
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#include <osl.h>
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#include <siutils.h>
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#include <hndsoc.h>
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#include <sbchipc.h>
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#include <pcicfg.h>
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#if defined(DONGLEBUILD)
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#include <pcieregsoffs.h>
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#include <pcicfg.h>
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#endif
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#include "pcie_core.h"
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#include <bcmdevs.h>
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/* local prototypes */
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/* local variables */
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/* function definitions */
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#ifdef BCMDRIVER /* this workaround can only be run on the host side since it resets the chip */
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#if !defined(DONGLEBUILD) || defined(BCMSTANDALONE_TEST)
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/* To avoid build error for dongle standalone test, define CAN_SLEEP if not defined */
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#ifndef CAN_SLEEP
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#define CAN_SLEEP() (FALSE)
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#endif
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#ifndef USEC_PER_MSEC
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#define USEC_PER_MSEC 1000
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#endif
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/**
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* WAR for CRWLPCIEGEN2-163, needed for all the chips at this point.
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* The PCIe core contains a 'snoop bus', that allows the logic in the PCIe core to read and write
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* to the PCIe configuration registers. When chip backplane reset hits, e.g. on driver unload, the
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* pcie snoop out will reset to default values and may get out of sync with pcie config registers.
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* This is causing failures because the LTR enable bit on the snoop bus gets out of sync. Also on
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* the snoop bus are the device power state, MSI info, L1subenable which may potentially cause
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* problems.
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*/
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/* wd_mask/wd_val is only for chipc_corerev >= 65 */
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void pcie_watchdog_reset(osl_t *osh, si_t *sih, uint32 wd_mask, uint32 wd_val)
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{
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uint32 val, i, lsc;
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uint16 cfg_offset[] = {PCIECFGREG_STATUS_CMD, PCIECFGREG_PM_CSR,
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PCIECFGREG_MSI_CAP, PCIECFGREG_MSI_ADDR_L,
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PCIECFGREG_MSI_ADDR_H, PCIECFGREG_MSI_DATA,
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PCIECFGREG_LINK_STATUS_CTRL2, PCIECFGREG_RBAR_CTRL,
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PCIECFGREG_PML1_SUB_CTRL1, PCIECFGREG_REG_BAR2_CONFIG,
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PCIECFGREG_REG_BAR3_CONFIG};
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sbpcieregs_t *pcieregs = NULL;
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uint32 origidx = si_coreidx(sih);
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#if defined(BCMQT) || defined(BCMFPGA_HW)
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/*
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* JIRA : SWWLAN-283651, 4397A0 WAR : During insmod avoid existing
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* PCIE WAR to avoid 'pcie_watchdog_reset'
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*/
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if (BCM4397_CHIP(sih->chip)) {
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return;
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}
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/* To avoid hang on FPGA, donot reset watchdog */
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if (CCREV(sih->ccrev) < 65) {
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si_setcoreidx(sih, origidx);
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return;
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}
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#endif
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#ifdef BCMFPGA_HW
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if (CCREV(sih->ccrev) < 67) {
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/* To avoid hang on FPGA, donot reset watchdog */
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si_setcoreidx(sih, origidx);
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return;
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}
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#endif
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/* Switch to PCIE2 core */
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pcieregs = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);
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BCM_REFERENCE(pcieregs);
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ASSERT(pcieregs != NULL);
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/* Disable/restore ASPM Control to protect the watchdog reset */
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W_REG(osh, &pcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
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lsc = R_REG(osh, &pcieregs->configdata);
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val = lsc & (~PCIE_ASPM_ENAB);
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W_REG(osh, &pcieregs->configdata, val);
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if (CCREV(sih->ccrev) >= 65) {
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si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), wd_mask, wd_val);
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si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), WD_COUNTER_MASK, 4);
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CAN_SLEEP() ? OSL_SLEEP(2) : OSL_DELAY(2 * USEC_PER_MSEC); /* 2 ms */
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val = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, intstatus), 0, 0);
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si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, intstatus),
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wd_mask, val & wd_mask);
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} else {
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si_corereg_writeonly(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, watchdog), ~0, 4);
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/* Read a config space to make sure the above write gets flushed on PCIe bus */
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val = OSL_PCI_READ_CONFIG(osh, PCI_CFG_VID, sizeof(uint32));
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CAN_SLEEP() ? OSL_SLEEP(100) : OSL_DELAY(100 * USEC_PER_MSEC); /* 100 ms */
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}
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W_REG(osh, &pcieregs->configaddr, PCIECFGREG_LINK_STATUS_CTRL);
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W_REG(osh, &pcieregs->configdata, lsc);
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if (sih->buscorerev <= 13) {
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/* Write configuration registers back to the shadow registers
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* cause shadow registers are cleared out after watchdog reset.
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*/
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for (i = 0; i < ARRAYSIZE(cfg_offset); i++) {
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W_REG(osh, &pcieregs->configaddr, cfg_offset[i]);
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val = R_REG(osh, &pcieregs->configdata);
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W_REG(osh, &pcieregs->configdata, val);
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}
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}
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si_setcoreidx(sih, origidx);
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}
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/* CRWLPCIEGEN2-117 pcie_pipe_Iddq should be controlled
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* by the L12 state from MAC to save power by putting the
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* SerDes analog in IDDQ mode
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*/
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void pcie_serdes_iddqdisable(osl_t *osh, si_t *sih, sbpcieregs_t *sbpcieregs)
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{
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sbpcieregs_t *pcie = NULL;
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uint crwlpciegen2_117_disable = 0;
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uint32 origidx = si_coreidx(sih);
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crwlpciegen2_117_disable = PCIE_PipeIddqDisable0 | PCIE_PipeIddqDisable1;
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/* Switch to PCIE2 core */
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pcie = (sbpcieregs_t *)si_setcore(sih, PCIE2_CORE_ID, 0);
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BCM_REFERENCE(pcie);
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ASSERT(pcie != NULL);
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OR_REG(osh, &sbpcieregs->control,
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crwlpciegen2_117_disable);
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si_setcoreidx(sih, origidx);
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}
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#define PCIE_PMCR_REFUP_MASK 0x3f0001e0
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#define PCIE_PMCR_REFEXT_MASK 0x400000
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#define PCIE_PMCR_REFUP_100US 0x38000080
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#define PCIE_PMCR_REFEXT_100US 0x400000
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/* Set PCIE TRefUp time to 100us */
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void pcie_set_trefup_time_100us(si_t *sih)
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{
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si_corereg(sih, sih->buscoreidx,
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OFFSETOF(sbpcieregs_t, configaddr), ~0, PCI_PMCR_REFUP);
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si_corereg(sih, sih->buscoreidx,
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OFFSETOF(sbpcieregs_t, configdata), PCIE_PMCR_REFUP_MASK, PCIE_PMCR_REFUP_100US);
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si_corereg(sih, sih->buscoreidx,
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OFFSETOF(sbpcieregs_t, configaddr), ~0, PCI_PMCR_REFUP_EXT);
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si_corereg(sih, sih->buscoreidx,
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OFFSETOF(sbpcieregs_t, configdata), PCIE_PMCR_REFEXT_MASK, PCIE_PMCR_REFEXT_100US);
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}
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uint32
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pcie_cto_to_thresh_default(uint corerev)
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{
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return REV_GE_69(corerev) ?
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PCIE_CTO_TO_THRESH_DEFAULT_REV69 : PCIE_CTO_TO_THRESH_DEFAULT;
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}
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uint32
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pcie_corereg(osl_t *osh, volatile void *regs, uint32 offset, uint32 mask, uint32 val)
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{
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volatile uint32 *regsva =
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(volatile uint32 *)((volatile char *)regs + PCI_16KB0_PCIREGS_OFFSET + offset);
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if (mask || val) {
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uint32 w = R_REG(osh, regsva);
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w &= ~mask;
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w |= val;
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W_REG(osh, regsva, w);
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}
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return (R_REG(osh, regsva));
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}
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#endif /* !defined(DONGLEBUILD) || defined(BCMSTANDALONE_TEST) */
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#if defined(DONGLEBUILD)
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void pcie_coherent_accenable(osl_t *osh, si_t *sih)
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{
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pcieregs_t *pcie = NULL;
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uint32 val;
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uint32 origidx = si_coreidx(sih);
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if ((pcie = si_setcore(sih, PCIE2_CORE_ID, 0)) != NULL) {
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/* PCIe BAR1 coherent access enabled */
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W_REG(osh, PCIE_configindaddr_ALTBASE(pcie, 0), PCIECFGREG_SPROM_CTRL);
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val = R_REG(osh, PCIE_configinddata_ALTBASE(pcie, 0));
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val |= (SPROM_BAR1_COHERENT_ACC_EN | SPROM_BAR2_COHERENT_ACC_EN);
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W_REG(osh, PCIE_configinddata_ALTBASE(pcie, 0), val);
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}
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si_setcoreidx(sih, origidx);
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}
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#endif /* DONGLEBUILD */
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#endif /* BCMDRIVER */
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