/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/* Copyright 2013-2016 Freescale Semiconductor Inc.
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* Copyright 2019 NXP
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*/
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#ifndef _FSL_DPMAC_CMD_H
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#define _FSL_DPMAC_CMD_H
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/* DPMAC Version */
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#define DPMAC_VER_MAJOR 4
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#define DPMAC_VER_MINOR 4
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#define DPMAC_CMD_BASE_VERSION 1
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#define DPMAC_CMD_2ND_VERSION 2
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#define DPMAC_CMD_ID_OFFSET 4
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#define DPMAC_CMD(id) (((id) << DPMAC_CMD_ID_OFFSET) | DPMAC_CMD_BASE_VERSION)
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#define DPMAC_CMD_V2(id) (((id) << DPMAC_CMD_ID_OFFSET) | DPMAC_CMD_2ND_VERSION)
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/* Command IDs */
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#define DPMAC_CMDID_CLOSE DPMAC_CMD(0x800)
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#define DPMAC_CMDID_OPEN DPMAC_CMD(0x80c)
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#define DPMAC_CMDID_GET_ATTR DPMAC_CMD(0x004)
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#define DPMAC_CMDID_SET_LINK_STATE DPMAC_CMD_V2(0x0c3)
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#define DPMAC_CMDID_GET_COUNTER DPMAC_CMD(0x0c4)
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/* Macros for accessing command fields smaller than 1byte */
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#define DPMAC_MASK(field) \
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GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \
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DPMAC_##field##_SHIFT)
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#define dpmac_set_field(var, field, val) \
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((var) |= (((val) << DPMAC_##field##_SHIFT) & DPMAC_MASK(field)))
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#define dpmac_get_field(var, field) \
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(((var) & DPMAC_MASK(field)) >> DPMAC_##field##_SHIFT)
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struct dpmac_cmd_open {
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__le32 dpmac_id;
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};
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struct dpmac_rsp_get_attributes {
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u8 eth_if;
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u8 link_type;
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__le16 id;
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__le32 max_rate;
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};
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#define DPMAC_STATE_SIZE 1
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#define DPMAC_STATE_SHIFT 0
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#define DPMAC_STATE_VALID_SIZE 1
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#define DPMAC_STATE_VALID_SHIFT 1
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struct dpmac_cmd_set_link_state {
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__le64 options;
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__le32 rate;
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__le32 pad0;
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/* from lsb: up:1, state_valid:1 */
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u8 state;
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u8 pad1[7];
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__le64 supported;
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__le64 advertising;
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};
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struct dpmac_cmd_get_counter {
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u8 id;
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};
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struct dpmac_rsp_get_counter {
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__le64 pad;
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__le64 counter;
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};
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#endif /* _FSL_DPMAC_CMD_H */
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