/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC5_RTR_REGS_H_
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#define ASIC_REG_TPC5_RTR_REGS_H_
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/*
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*****************************************
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* TPC5_RTR (Prototype: TPC_RTR)
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*****************************************
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*/
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#define mmTPC5_RTR_HBW_RD_RQ_E_ARB 0xF40100
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#define mmTPC5_RTR_HBW_RD_RQ_W_ARB 0xF40104
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#define mmTPC5_RTR_HBW_RD_RQ_N_ARB 0xF40108
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#define mmTPC5_RTR_HBW_RD_RQ_S_ARB 0xF4010C
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#define mmTPC5_RTR_HBW_RD_RQ_L_ARB 0xF40110
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#define mmTPC5_RTR_HBW_E_ARB_MAX 0xF40120
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#define mmTPC5_RTR_HBW_W_ARB_MAX 0xF40124
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#define mmTPC5_RTR_HBW_N_ARB_MAX 0xF40128
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#define mmTPC5_RTR_HBW_S_ARB_MAX 0xF4012C
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#define mmTPC5_RTR_HBW_L_ARB_MAX 0xF40130
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#define mmTPC5_RTR_HBW_RD_RS_E_ARB 0xF40140
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#define mmTPC5_RTR_HBW_RD_RS_W_ARB 0xF40144
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#define mmTPC5_RTR_HBW_RD_RS_N_ARB 0xF40148
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#define mmTPC5_RTR_HBW_RD_RS_S_ARB 0xF4014C
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#define mmTPC5_RTR_HBW_RD_RS_L_ARB 0xF40150
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#define mmTPC5_RTR_HBW_WR_RQ_E_ARB 0xF40170
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#define mmTPC5_RTR_HBW_WR_RQ_W_ARB 0xF40174
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#define mmTPC5_RTR_HBW_WR_RQ_N_ARB 0xF40178
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#define mmTPC5_RTR_HBW_WR_RQ_S_ARB 0xF4017C
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#define mmTPC5_RTR_HBW_WR_RQ_L_ARB 0xF40180
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#define mmTPC5_RTR_HBW_WR_RS_E_ARB 0xF40190
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#define mmTPC5_RTR_HBW_WR_RS_W_ARB 0xF40194
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#define mmTPC5_RTR_HBW_WR_RS_N_ARB 0xF40198
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#define mmTPC5_RTR_HBW_WR_RS_S_ARB 0xF4019C
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#define mmTPC5_RTR_HBW_WR_RS_L_ARB 0xF401A0
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#define mmTPC5_RTR_LBW_RD_RQ_E_ARB 0xF40200
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#define mmTPC5_RTR_LBW_RD_RQ_W_ARB 0xF40204
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#define mmTPC5_RTR_LBW_RD_RQ_N_ARB 0xF40208
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#define mmTPC5_RTR_LBW_RD_RQ_S_ARB 0xF4020C
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#define mmTPC5_RTR_LBW_RD_RQ_L_ARB 0xF40210
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#define mmTPC5_RTR_LBW_E_ARB_MAX 0xF40220
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#define mmTPC5_RTR_LBW_W_ARB_MAX 0xF40224
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#define mmTPC5_RTR_LBW_N_ARB_MAX 0xF40228
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#define mmTPC5_RTR_LBW_S_ARB_MAX 0xF4022C
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#define mmTPC5_RTR_LBW_L_ARB_MAX 0xF40230
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#define mmTPC5_RTR_LBW_RD_RS_E_ARB 0xF40250
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#define mmTPC5_RTR_LBW_RD_RS_W_ARB 0xF40254
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#define mmTPC5_RTR_LBW_RD_RS_N_ARB 0xF40258
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#define mmTPC5_RTR_LBW_RD_RS_S_ARB 0xF4025C
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#define mmTPC5_RTR_LBW_RD_RS_L_ARB 0xF40260
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#define mmTPC5_RTR_LBW_WR_RQ_E_ARB 0xF40270
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#define mmTPC5_RTR_LBW_WR_RQ_W_ARB 0xF40274
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#define mmTPC5_RTR_LBW_WR_RQ_N_ARB 0xF40278
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#define mmTPC5_RTR_LBW_WR_RQ_S_ARB 0xF4027C
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#define mmTPC5_RTR_LBW_WR_RQ_L_ARB 0xF40280
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#define mmTPC5_RTR_LBW_WR_RS_E_ARB 0xF40290
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#define mmTPC5_RTR_LBW_WR_RS_W_ARB 0xF40294
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#define mmTPC5_RTR_LBW_WR_RS_N_ARB 0xF40298
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#define mmTPC5_RTR_LBW_WR_RS_S_ARB 0xF4029C
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#define mmTPC5_RTR_LBW_WR_RS_L_ARB 0xF402A0
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#define mmTPC5_RTR_DBG_E_ARB 0xF40300
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#define mmTPC5_RTR_DBG_W_ARB 0xF40304
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#define mmTPC5_RTR_DBG_N_ARB 0xF40308
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#define mmTPC5_RTR_DBG_S_ARB 0xF4030C
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#define mmTPC5_RTR_DBG_L_ARB 0xF40310
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#define mmTPC5_RTR_DBG_E_ARB_MAX 0xF40320
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#define mmTPC5_RTR_DBG_W_ARB_MAX 0xF40324
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#define mmTPC5_RTR_DBG_N_ARB_MAX 0xF40328
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#define mmTPC5_RTR_DBG_S_ARB_MAX 0xF4032C
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#define mmTPC5_RTR_DBG_L_ARB_MAX 0xF40330
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#define mmTPC5_RTR_SPLIT_COEF_0 0xF40400
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#define mmTPC5_RTR_SPLIT_COEF_1 0xF40404
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#define mmTPC5_RTR_SPLIT_COEF_2 0xF40408
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#define mmTPC5_RTR_SPLIT_COEF_3 0xF4040C
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#define mmTPC5_RTR_SPLIT_COEF_4 0xF40410
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#define mmTPC5_RTR_SPLIT_COEF_5 0xF40414
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#define mmTPC5_RTR_SPLIT_COEF_6 0xF40418
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#define mmTPC5_RTR_SPLIT_COEF_7 0xF4041C
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#define mmTPC5_RTR_SPLIT_COEF_8 0xF40420
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#define mmTPC5_RTR_SPLIT_COEF_9 0xF40424
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#define mmTPC5_RTR_SPLIT_CFG 0xF40440
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#define mmTPC5_RTR_SPLIT_RD_SAT 0xF40444
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#define mmTPC5_RTR_SPLIT_RD_RST_TOKEN 0xF40448
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#define mmTPC5_RTR_SPLIT_RD_TIMEOUT_0 0xF4044C
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#define mmTPC5_RTR_SPLIT_RD_TIMEOUT_1 0xF40450
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#define mmTPC5_RTR_SPLIT_WR_SAT 0xF40454
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#define mmTPC5_RTR_WPLIT_WR_TST_TOLEN 0xF40458
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#define mmTPC5_RTR_SPLIT_WR_TIMEOUT_0 0xF4045C
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#define mmTPC5_RTR_SPLIT_WR_TIMEOUT_1 0xF40460
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#define mmTPC5_RTR_HBW_RANGE_HIT 0xF40470
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#define mmTPC5_RTR_HBW_RANGE_MASK_L_0 0xF40480
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#define mmTPC5_RTR_HBW_RANGE_MASK_L_1 0xF40484
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#define mmTPC5_RTR_HBW_RANGE_MASK_L_2 0xF40488
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#define mmTPC5_RTR_HBW_RANGE_MASK_L_3 0xF4048C
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#define mmTPC5_RTR_HBW_RANGE_MASK_L_4 0xF40490
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#define mmTPC5_RTR_HBW_RANGE_MASK_L_5 0xF40494
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#define mmTPC5_RTR_HBW_RANGE_MASK_L_6 0xF40498
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#define mmTPC5_RTR_HBW_RANGE_MASK_L_7 0xF4049C
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#define mmTPC5_RTR_HBW_RANGE_MASK_H_0 0xF404A0
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#define mmTPC5_RTR_HBW_RANGE_MASK_H_1 0xF404A4
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#define mmTPC5_RTR_HBW_RANGE_MASK_H_2 0xF404A8
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#define mmTPC5_RTR_HBW_RANGE_MASK_H_3 0xF404AC
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#define mmTPC5_RTR_HBW_RANGE_MASK_H_4 0xF404B0
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#define mmTPC5_RTR_HBW_RANGE_MASK_H_5 0xF404B4
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#define mmTPC5_RTR_HBW_RANGE_MASK_H_6 0xF404B8
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#define mmTPC5_RTR_HBW_RANGE_MASK_H_7 0xF404BC
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#define mmTPC5_RTR_HBW_RANGE_BASE_L_0 0xF404C0
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#define mmTPC5_RTR_HBW_RANGE_BASE_L_1 0xF404C4
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#define mmTPC5_RTR_HBW_RANGE_BASE_L_2 0xF404C8
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#define mmTPC5_RTR_HBW_RANGE_BASE_L_3 0xF404CC
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#define mmTPC5_RTR_HBW_RANGE_BASE_L_4 0xF404D0
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#define mmTPC5_RTR_HBW_RANGE_BASE_L_5 0xF404D4
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#define mmTPC5_RTR_HBW_RANGE_BASE_L_6 0xF404D8
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#define mmTPC5_RTR_HBW_RANGE_BASE_L_7 0xF404DC
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#define mmTPC5_RTR_HBW_RANGE_BASE_H_0 0xF404E0
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#define mmTPC5_RTR_HBW_RANGE_BASE_H_1 0xF404E4
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#define mmTPC5_RTR_HBW_RANGE_BASE_H_2 0xF404E8
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#define mmTPC5_RTR_HBW_RANGE_BASE_H_3 0xF404EC
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#define mmTPC5_RTR_HBW_RANGE_BASE_H_4 0xF404F0
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#define mmTPC5_RTR_HBW_RANGE_BASE_H_5 0xF404F4
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#define mmTPC5_RTR_HBW_RANGE_BASE_H_6 0xF404F8
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#define mmTPC5_RTR_HBW_RANGE_BASE_H_7 0xF404FC
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#define mmTPC5_RTR_LBW_RANGE_HIT 0xF40500
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#define mmTPC5_RTR_LBW_RANGE_MASK_0 0xF40510
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#define mmTPC5_RTR_LBW_RANGE_MASK_1 0xF40514
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#define mmTPC5_RTR_LBW_RANGE_MASK_2 0xF40518
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#define mmTPC5_RTR_LBW_RANGE_MASK_3 0xF4051C
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#define mmTPC5_RTR_LBW_RANGE_MASK_4 0xF40520
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#define mmTPC5_RTR_LBW_RANGE_MASK_5 0xF40524
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#define mmTPC5_RTR_LBW_RANGE_MASK_6 0xF40528
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#define mmTPC5_RTR_LBW_RANGE_MASK_7 0xF4052C
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#define mmTPC5_RTR_LBW_RANGE_MASK_8 0xF40530
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#define mmTPC5_RTR_LBW_RANGE_MASK_9 0xF40534
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#define mmTPC5_RTR_LBW_RANGE_MASK_10 0xF40538
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#define mmTPC5_RTR_LBW_RANGE_MASK_11 0xF4053C
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#define mmTPC5_RTR_LBW_RANGE_MASK_12 0xF40540
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#define mmTPC5_RTR_LBW_RANGE_MASK_13 0xF40544
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#define mmTPC5_RTR_LBW_RANGE_MASK_14 0xF40548
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#define mmTPC5_RTR_LBW_RANGE_MASK_15 0xF4054C
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#define mmTPC5_RTR_LBW_RANGE_BASE_0 0xF40550
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#define mmTPC5_RTR_LBW_RANGE_BASE_1 0xF40554
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#define mmTPC5_RTR_LBW_RANGE_BASE_2 0xF40558
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#define mmTPC5_RTR_LBW_RANGE_BASE_3 0xF4055C
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#define mmTPC5_RTR_LBW_RANGE_BASE_4 0xF40560
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#define mmTPC5_RTR_LBW_RANGE_BASE_5 0xF40564
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#define mmTPC5_RTR_LBW_RANGE_BASE_6 0xF40568
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#define mmTPC5_RTR_LBW_RANGE_BASE_7 0xF4056C
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#define mmTPC5_RTR_LBW_RANGE_BASE_8 0xF40570
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#define mmTPC5_RTR_LBW_RANGE_BASE_9 0xF40574
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#define mmTPC5_RTR_LBW_RANGE_BASE_10 0xF40578
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#define mmTPC5_RTR_LBW_RANGE_BASE_11 0xF4057C
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#define mmTPC5_RTR_LBW_RANGE_BASE_12 0xF40580
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#define mmTPC5_RTR_LBW_RANGE_BASE_13 0xF40584
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#define mmTPC5_RTR_LBW_RANGE_BASE_14 0xF40588
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#define mmTPC5_RTR_LBW_RANGE_BASE_15 0xF4058C
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#define mmTPC5_RTR_RGLTR 0xF40590
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#define mmTPC5_RTR_RGLTR_WR_RESULT 0xF40594
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#define mmTPC5_RTR_RGLTR_RD_RESULT 0xF40598
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#define mmTPC5_RTR_SCRAMB_EN 0xF40600
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#define mmTPC5_RTR_NON_LIN_SCRAMB 0xF40604
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#endif /* ASIC_REG_TPC5_RTR_REGS_H_ */
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