/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC4_QM_REGS_H_
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#define ASIC_REG_TPC4_QM_REGS_H_
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/*
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*****************************************
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* TPC4_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmTPC4_QM_GLBL_CFG0 0xF08000
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#define mmTPC4_QM_GLBL_CFG1 0xF08004
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#define mmTPC4_QM_GLBL_PROT 0xF08008
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#define mmTPC4_QM_GLBL_ERR_CFG 0xF0800C
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#define mmTPC4_QM_GLBL_ERR_ADDR_LO 0xF08010
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#define mmTPC4_QM_GLBL_ERR_ADDR_HI 0xF08014
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#define mmTPC4_QM_GLBL_ERR_WDATA 0xF08018
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#define mmTPC4_QM_GLBL_SECURE_PROPS 0xF0801C
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#define mmTPC4_QM_GLBL_NON_SECURE_PROPS 0xF08020
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#define mmTPC4_QM_GLBL_STS0 0xF08024
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#define mmTPC4_QM_GLBL_STS1 0xF08028
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#define mmTPC4_QM_PQ_BASE_LO 0xF08060
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#define mmTPC4_QM_PQ_BASE_HI 0xF08064
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#define mmTPC4_QM_PQ_SIZE 0xF08068
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#define mmTPC4_QM_PQ_PI 0xF0806C
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#define mmTPC4_QM_PQ_CI 0xF08070
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#define mmTPC4_QM_PQ_CFG0 0xF08074
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#define mmTPC4_QM_PQ_CFG1 0xF08078
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#define mmTPC4_QM_PQ_ARUSER 0xF0807C
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#define mmTPC4_QM_PQ_PUSH0 0xF08080
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#define mmTPC4_QM_PQ_PUSH1 0xF08084
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#define mmTPC4_QM_PQ_PUSH2 0xF08088
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#define mmTPC4_QM_PQ_PUSH3 0xF0808C
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#define mmTPC4_QM_PQ_STS0 0xF08090
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#define mmTPC4_QM_PQ_STS1 0xF08094
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#define mmTPC4_QM_PQ_RD_RATE_LIM_EN 0xF080A0
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#define mmTPC4_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xF080A4
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#define mmTPC4_QM_PQ_RD_RATE_LIM_SAT 0xF080A8
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#define mmTPC4_QM_PQ_RD_RATE_LIM_TOUT 0xF080AC
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#define mmTPC4_QM_CQ_CFG0 0xF080B0
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#define mmTPC4_QM_CQ_CFG1 0xF080B4
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#define mmTPC4_QM_CQ_ARUSER 0xF080B8
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#define mmTPC4_QM_CQ_PTR_LO 0xF080C0
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#define mmTPC4_QM_CQ_PTR_HI 0xF080C4
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#define mmTPC4_QM_CQ_TSIZE 0xF080C8
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#define mmTPC4_QM_CQ_CTL 0xF080CC
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#define mmTPC4_QM_CQ_PTR_LO_STS 0xF080D4
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#define mmTPC4_QM_CQ_PTR_HI_STS 0xF080D8
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#define mmTPC4_QM_CQ_TSIZE_STS 0xF080DC
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#define mmTPC4_QM_CQ_CTL_STS 0xF080E0
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#define mmTPC4_QM_CQ_STS0 0xF080E4
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#define mmTPC4_QM_CQ_STS1 0xF080E8
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#define mmTPC4_QM_CQ_RD_RATE_LIM_EN 0xF080F0
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#define mmTPC4_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xF080F4
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#define mmTPC4_QM_CQ_RD_RATE_LIM_SAT 0xF080F8
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#define mmTPC4_QM_CQ_RD_RATE_LIM_TOUT 0xF080FC
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#define mmTPC4_QM_CQ_IFIFO_CNT 0xF08108
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#define mmTPC4_QM_CP_MSG_BASE0_ADDR_LO 0xF08120
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#define mmTPC4_QM_CP_MSG_BASE0_ADDR_HI 0xF08124
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#define mmTPC4_QM_CP_MSG_BASE1_ADDR_LO 0xF08128
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#define mmTPC4_QM_CP_MSG_BASE1_ADDR_HI 0xF0812C
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#define mmTPC4_QM_CP_MSG_BASE2_ADDR_LO 0xF08130
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#define mmTPC4_QM_CP_MSG_BASE2_ADDR_HI 0xF08134
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#define mmTPC4_QM_CP_MSG_BASE3_ADDR_LO 0xF08138
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#define mmTPC4_QM_CP_MSG_BASE3_ADDR_HI 0xF0813C
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#define mmTPC4_QM_CP_LDMA_TSIZE_OFFSET 0xF08140
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#define mmTPC4_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xF08144
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#define mmTPC4_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xF08148
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#define mmTPC4_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xF0814C
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#define mmTPC4_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xF08150
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#define mmTPC4_QM_CP_LDMA_COMMIT_OFFSET 0xF08154
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#define mmTPC4_QM_CP_FENCE0_RDATA 0xF08158
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#define mmTPC4_QM_CP_FENCE1_RDATA 0xF0815C
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#define mmTPC4_QM_CP_FENCE2_RDATA 0xF08160
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#define mmTPC4_QM_CP_FENCE3_RDATA 0xF08164
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#define mmTPC4_QM_CP_FENCE0_CNT 0xF08168
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#define mmTPC4_QM_CP_FENCE1_CNT 0xF0816C
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#define mmTPC4_QM_CP_FENCE2_CNT 0xF08170
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#define mmTPC4_QM_CP_FENCE3_CNT 0xF08174
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#define mmTPC4_QM_CP_STS 0xF08178
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#define mmTPC4_QM_CP_CURRENT_INST_LO 0xF0817C
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#define mmTPC4_QM_CP_CURRENT_INST_HI 0xF08180
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#define mmTPC4_QM_CP_BARRIER_CFG 0xF08184
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#define mmTPC4_QM_CP_DBG_0 0xF08188
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#define mmTPC4_QM_PQ_BUF_ADDR 0xF08300
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#define mmTPC4_QM_PQ_BUF_RDATA 0xF08304
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#define mmTPC4_QM_CQ_BUF_ADDR 0xF08308
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#define mmTPC4_QM_CQ_BUF_RDATA 0xF0830C
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#endif /* ASIC_REG_TPC4_QM_REGS_H_ */
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