/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC4_CFG_REGS_H_
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#define ASIC_REG_TPC4_CFG_REGS_H_
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/*
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*****************************************
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* TPC4_CFG (Prototype: TPC)
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*****************************************
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*/
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#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF06400
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#define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF06404
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#define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF06408
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#define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF0640C
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF06410
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF06414
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF06418
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF0641C
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF06420
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF06424
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF06428
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF0642C
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF06430
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF06434
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF06438
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF0643C
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF06440
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF06444
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#define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF06448
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#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF0644C
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#define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF06450
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#define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF06454
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#define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF06458
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF0645C
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF06460
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF06464
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF06468
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF0646C
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF06470
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF06474
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF06478
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF0647C
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF06480
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF06484
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF06488
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF0648C
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF06490
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#define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF06494
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#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF06498
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#define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF0649C
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#define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF064A0
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#define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF064A4
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF064A8
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF064AC
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF064B0
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF064B4
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF064B8
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF064BC
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF064C0
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF064C4
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF064C8
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF064CC
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF064D0
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF064D4
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF064D8
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF064DC
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#define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF064E0
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#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF064E4
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#define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF064E8
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#define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF064EC
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#define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF064F0
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF064F4
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF064F8
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF064FC
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF06500
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF06504
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF06508
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF0650C
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF06510
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF06514
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF06518
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF0651C
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF06520
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF06524
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF06528
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#define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF0652C
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#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF06530
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#define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF06534
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#define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF06538
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#define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF0653C
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF06540
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF06544
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF06548
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF0654C
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF06550
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF06554
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF06558
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF0655C
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF06560
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF06564
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF06568
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF0656C
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF06570
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF06574
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#define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF06578
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#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF0657C
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#define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF06580
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#define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF06584
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#define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF06588
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF0658C
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF06590
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF06594
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF06598
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF0659C
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF065A0
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF065A4
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF065A8
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF065AC
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF065B0
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF065B4
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF065B8
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF065BC
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF065C0
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#define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF065C4
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#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF065C8
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#define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF065CC
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#define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF065D0
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#define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF065D4
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF065D8
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF065DC
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF065E0
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF065E4
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF065E8
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF065EC
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF065F0
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF065F4
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF065F8
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF065FC
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF06600
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF06604
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF06608
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF0660C
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#define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF06610
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#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF06614
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#define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF06618
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#define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF0661C
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#define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF06620
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF06624
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF06628
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF0662C
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF06630
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF06634
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF06638
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF0663C
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF06640
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF06644
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF06648
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF0664C
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF06650
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF06654
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF06658
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#define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF0665C
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#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF06660
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#define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF06664
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#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0 0xF06668
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#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0 0xF0666C
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#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1 0xF06670
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#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1 0xF06674
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#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2 0xF06678
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#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2 0xF0667C
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#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3 0xF06680
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#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3 0xF06684
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#define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4 0xF06688
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#define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4 0xF0668C
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#define mmTPC4_CFG_KERNEL_SRF_0 0xF06690
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#define mmTPC4_CFG_KERNEL_SRF_1 0xF06694
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#define mmTPC4_CFG_KERNEL_SRF_2 0xF06698
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#define mmTPC4_CFG_KERNEL_SRF_3 0xF0669C
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#define mmTPC4_CFG_KERNEL_SRF_4 0xF066A0
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#define mmTPC4_CFG_KERNEL_SRF_5 0xF066A4
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#define mmTPC4_CFG_KERNEL_SRF_6 0xF066A8
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#define mmTPC4_CFG_KERNEL_SRF_7 0xF066AC
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#define mmTPC4_CFG_KERNEL_SRF_8 0xF066B0
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#define mmTPC4_CFG_KERNEL_SRF_9 0xF066B4
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#define mmTPC4_CFG_KERNEL_SRF_10 0xF066B8
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#define mmTPC4_CFG_KERNEL_SRF_11 0xF066BC
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#define mmTPC4_CFG_KERNEL_SRF_12 0xF066C0
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#define mmTPC4_CFG_KERNEL_SRF_13 0xF066C4
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#define mmTPC4_CFG_KERNEL_SRF_14 0xF066C8
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#define mmTPC4_CFG_KERNEL_SRF_15 0xF066CC
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#define mmTPC4_CFG_KERNEL_SRF_16 0xF066D0
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#define mmTPC4_CFG_KERNEL_SRF_17 0xF066D4
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#define mmTPC4_CFG_KERNEL_SRF_18 0xF066D8
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#define mmTPC4_CFG_KERNEL_SRF_19 0xF066DC
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#define mmTPC4_CFG_KERNEL_SRF_20 0xF066E0
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#define mmTPC4_CFG_KERNEL_SRF_21 0xF066E4
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#define mmTPC4_CFG_KERNEL_SRF_22 0xF066E8
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#define mmTPC4_CFG_KERNEL_SRF_23 0xF066EC
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#define mmTPC4_CFG_KERNEL_SRF_24 0xF066F0
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#define mmTPC4_CFG_KERNEL_SRF_25 0xF066F4
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#define mmTPC4_CFG_KERNEL_SRF_26 0xF066F8
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#define mmTPC4_CFG_KERNEL_SRF_27 0xF066FC
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#define mmTPC4_CFG_KERNEL_SRF_28 0xF06700
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#define mmTPC4_CFG_KERNEL_SRF_29 0xF06704
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#define mmTPC4_CFG_KERNEL_SRF_30 0xF06708
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#define mmTPC4_CFG_KERNEL_SRF_31 0xF0670C
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#define mmTPC4_CFG_KERNEL_KERNEL_CONFIG 0xF06710
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#define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF06714
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#define mmTPC4_CFG_RESERVED_DESC_END 0xF06738
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#define mmTPC4_CFG_ROUND_CSR 0xF067FC
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#define mmTPC4_CFG_TBUF_BASE_ADDR_LOW 0xF06800
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#define mmTPC4_CFG_TBUF_BASE_ADDR_HIGH 0xF06804
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#define mmTPC4_CFG_SEMAPHORE 0xF06808
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#define mmTPC4_CFG_VFLAGS 0xF0680C
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#define mmTPC4_CFG_SFLAGS 0xF06810
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#define mmTPC4_CFG_LFSR_POLYNOM 0xF06818
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#define mmTPC4_CFG_STATUS 0xF0681C
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#define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH 0xF06820
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#define mmTPC4_CFG_CFG_SUBTRACT_VALUE 0xF06824
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#define mmTPC4_CFG_SM_BASE_ADDRESS_LOW 0xF06828
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#define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH 0xF0682C
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#define mmTPC4_CFG_TPC_CMD 0xF06830
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#define mmTPC4_CFG_TPC_EXECUTE 0xF06838
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#define mmTPC4_CFG_TPC_STALL 0xF0683C
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#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW 0xF06840
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#define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF06844
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#define mmTPC4_CFG_MSS_CONFIG 0xF06854
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#define mmTPC4_CFG_TPC_INTR_CAUSE 0xF06858
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#define mmTPC4_CFG_TPC_INTR_MASK 0xF0685C
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#define mmTPC4_CFG_TSB_CONFIG 0xF06860
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#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF06A00
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#define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF06A04
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#define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE 0xF06A08
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#define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF06A0C
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF06A10
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF06A14
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF06A18
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF06A1C
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF06A20
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF06A24
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF06A28
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF06A2C
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF06A30
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF06A34
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF06A38
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF06A3C
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF06A40
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF06A44
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#define mmTPC4_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF06A48
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#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF06A4C
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#define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF06A50
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#define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE 0xF06A54
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#define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF06A58
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF06A5C
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF06A60
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF06A64
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF06A68
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF06A6C
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF06A70
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF06A74
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF06A78
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF06A7C
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF06A80
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF06A84
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF06A88
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF06A8C
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF06A90
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#define mmTPC4_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF06A94
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#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF06A98
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#define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF06A9C
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#define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE 0xF06AA0
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#define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF06AA4
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF06AA8
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF06AAC
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF06AB0
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF06AB4
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF06AB8
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF06ABC
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF06AC0
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF06AC4
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF06AC8
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF06ACC
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF06AD0
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF06AD4
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF06AD8
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF06ADC
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#define mmTPC4_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF06AE0
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#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF06AE4
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#define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF06AE8
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#define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE 0xF06AEC
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#define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF06AF0
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF06AF4
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF06AF8
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF06AFC
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF06B00
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF06B04
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF06B08
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF06B0C
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF06B10
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF06B14
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF06B18
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF06B1C
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF06B20
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF06B24
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF06B28
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#define mmTPC4_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF06B2C
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#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF06B30
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#define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF06B34
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#define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE 0xF06B38
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#define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF06B3C
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF06B40
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF06B44
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF06B48
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF06B4C
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF06B50
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF06B54
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF06B58
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF06B5C
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF06B60
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF06B64
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF06B68
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF06B6C
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF06B70
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF06B74
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#define mmTPC4_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF06B78
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#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF06B7C
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#define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF06B80
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#define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE 0xF06B84
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#define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF06B88
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF06B8C
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF06B90
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF06B94
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF06B98
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF06B9C
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF06BA0
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF06BA4
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF06BA8
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF06BAC
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF06BB0
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF06BB4
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF06BB8
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF06BBC
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF06BC0
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#define mmTPC4_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF06BC4
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#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF06BC8
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#define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF06BCC
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#define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE 0xF06BD0
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#define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF06BD4
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF06BD8
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF06BDC
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF06BE0
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF06BE4
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF06BE8
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF06BEC
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF06BF0
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF06BF4
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF06BF8
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF06BFC
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF06C00
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF06C04
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF06C08
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF06C0C
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#define mmTPC4_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF06C10
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#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF06C14
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#define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF06C18
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#define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE 0xF06C1C
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#define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF06C20
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF06C24
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF06C28
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF06C2C
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF06C30
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF06C34
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF06C38
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF06C3C
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF06C40
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF06C44
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF06C48
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF06C4C
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF06C50
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF06C54
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF06C58
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#define mmTPC4_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF06C5C
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#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF06C60
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#define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF06C64
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#define mmTPC4_CFG_QM_TID_BASE_DIM_0 0xF06C68
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#define mmTPC4_CFG_QM_TID_SIZE_DIM_0 0xF06C6C
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#define mmTPC4_CFG_QM_TID_BASE_DIM_1 0xF06C70
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#define mmTPC4_CFG_QM_TID_SIZE_DIM_1 0xF06C74
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#define mmTPC4_CFG_QM_TID_BASE_DIM_2 0xF06C78
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#define mmTPC4_CFG_QM_TID_SIZE_DIM_2 0xF06C7C
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#define mmTPC4_CFG_QM_TID_BASE_DIM_3 0xF06C80
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#define mmTPC4_CFG_QM_TID_SIZE_DIM_3 0xF06C84
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#define mmTPC4_CFG_QM_TID_BASE_DIM_4 0xF06C88
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#define mmTPC4_CFG_QM_TID_SIZE_DIM_4 0xF06C8C
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#define mmTPC4_CFG_QM_SRF_0 0xF06C90
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#define mmTPC4_CFG_QM_SRF_1 0xF06C94
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#define mmTPC4_CFG_QM_SRF_2 0xF06C98
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#define mmTPC4_CFG_QM_SRF_3 0xF06C9C
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#define mmTPC4_CFG_QM_SRF_4 0xF06CA0
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#define mmTPC4_CFG_QM_SRF_5 0xF06CA4
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#define mmTPC4_CFG_QM_SRF_6 0xF06CA8
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#define mmTPC4_CFG_QM_SRF_7 0xF06CAC
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#define mmTPC4_CFG_QM_SRF_8 0xF06CB0
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#define mmTPC4_CFG_QM_SRF_9 0xF06CB4
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#define mmTPC4_CFG_QM_SRF_10 0xF06CB8
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#define mmTPC4_CFG_QM_SRF_11 0xF06CBC
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#define mmTPC4_CFG_QM_SRF_12 0xF06CC0
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#define mmTPC4_CFG_QM_SRF_13 0xF06CC4
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#define mmTPC4_CFG_QM_SRF_14 0xF06CC8
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#define mmTPC4_CFG_QM_SRF_15 0xF06CCC
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#define mmTPC4_CFG_QM_SRF_16 0xF06CD0
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#define mmTPC4_CFG_QM_SRF_17 0xF06CD4
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#define mmTPC4_CFG_QM_SRF_18 0xF06CD8
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#define mmTPC4_CFG_QM_SRF_19 0xF06CDC
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#define mmTPC4_CFG_QM_SRF_20 0xF06CE0
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#define mmTPC4_CFG_QM_SRF_21 0xF06CE4
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#define mmTPC4_CFG_QM_SRF_22 0xF06CE8
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#define mmTPC4_CFG_QM_SRF_23 0xF06CEC
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#define mmTPC4_CFG_QM_SRF_24 0xF06CF0
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#define mmTPC4_CFG_QM_SRF_25 0xF06CF4
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#define mmTPC4_CFG_QM_SRF_26 0xF06CF8
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#define mmTPC4_CFG_QM_SRF_27 0xF06CFC
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#define mmTPC4_CFG_QM_SRF_28 0xF06D00
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#define mmTPC4_CFG_QM_SRF_29 0xF06D04
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#define mmTPC4_CFG_QM_SRF_30 0xF06D08
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#define mmTPC4_CFG_QM_SRF_31 0xF06D0C
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#define mmTPC4_CFG_QM_KERNEL_CONFIG 0xF06D10
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#define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE 0xF06D14
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#define mmTPC4_CFG_ARUSER 0xF06D18
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#define mmTPC4_CFG_AWUSER 0xF06D1C
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#define mmTPC4_CFG_FUNC_MBIST_CNTRL 0xF06E00
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#define mmTPC4_CFG_FUNC_MBIST_PAT 0xF06E04
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#define mmTPC4_CFG_FUNC_MBIST_MEM_0 0xF06E08
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#define mmTPC4_CFG_FUNC_MBIST_MEM_1 0xF06E0C
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#define mmTPC4_CFG_FUNC_MBIST_MEM_2 0xF06E10
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#define mmTPC4_CFG_FUNC_MBIST_MEM_3 0xF06E14
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#define mmTPC4_CFG_FUNC_MBIST_MEM_4 0xF06E18
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#define mmTPC4_CFG_FUNC_MBIST_MEM_5 0xF06E1C
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#define mmTPC4_CFG_FUNC_MBIST_MEM_6 0xF06E20
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#define mmTPC4_CFG_FUNC_MBIST_MEM_7 0xF06E24
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#define mmTPC4_CFG_FUNC_MBIST_MEM_8 0xF06E28
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#define mmTPC4_CFG_FUNC_MBIST_MEM_9 0xF06E2C
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#endif /* ASIC_REG_TPC4_CFG_REGS_H_ */
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