/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_MME_CMDQ_REGS_H_
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#define ASIC_REG_MME_CMDQ_REGS_H_
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/*
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*****************************************
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* MME_CMDQ (Prototype: CMDQ)
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*****************************************
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*/
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#define mmMME_CMDQ_GLBL_CFG0 0xD9000
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#define mmMME_CMDQ_GLBL_CFG1 0xD9004
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#define mmMME_CMDQ_GLBL_PROT 0xD9008
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#define mmMME_CMDQ_GLBL_ERR_CFG 0xD900C
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#define mmMME_CMDQ_GLBL_ERR_ADDR_LO 0xD9010
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#define mmMME_CMDQ_GLBL_ERR_ADDR_HI 0xD9014
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#define mmMME_CMDQ_GLBL_ERR_WDATA 0xD9018
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#define mmMME_CMDQ_GLBL_SECURE_PROPS 0xD901C
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#define mmMME_CMDQ_GLBL_NON_SECURE_PROPS 0xD9020
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#define mmMME_CMDQ_GLBL_STS0 0xD9024
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#define mmMME_CMDQ_GLBL_STS1 0xD9028
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#define mmMME_CMDQ_CQ_CFG0 0xD90B0
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#define mmMME_CMDQ_CQ_CFG1 0xD90B4
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#define mmMME_CMDQ_CQ_ARUSER 0xD90B8
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#define mmMME_CMDQ_CQ_PTR_LO 0xD90C0
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#define mmMME_CMDQ_CQ_PTR_HI 0xD90C4
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#define mmMME_CMDQ_CQ_TSIZE 0xD90C8
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#define mmMME_CMDQ_CQ_CTL 0xD90CC
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#define mmMME_CMDQ_CQ_PTR_LO_STS 0xD90D4
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#define mmMME_CMDQ_CQ_PTR_HI_STS 0xD90D8
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#define mmMME_CMDQ_CQ_TSIZE_STS 0xD90DC
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#define mmMME_CMDQ_CQ_CTL_STS 0xD90E0
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#define mmMME_CMDQ_CQ_STS0 0xD90E4
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#define mmMME_CMDQ_CQ_STS1 0xD90E8
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#define mmMME_CMDQ_CQ_RD_RATE_LIM_EN 0xD90F0
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#define mmMME_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xD90F4
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#define mmMME_CMDQ_CQ_RD_RATE_LIM_SAT 0xD90F8
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#define mmMME_CMDQ_CQ_RD_RATE_LIM_TOUT 0xD90FC
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#define mmMME_CMDQ_CQ_IFIFO_CNT 0xD9108
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#define mmMME_CMDQ_CP_MSG_BASE0_ADDR_LO 0xD9120
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#define mmMME_CMDQ_CP_MSG_BASE0_ADDR_HI 0xD9124
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#define mmMME_CMDQ_CP_MSG_BASE1_ADDR_LO 0xD9128
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#define mmMME_CMDQ_CP_MSG_BASE1_ADDR_HI 0xD912C
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#define mmMME_CMDQ_CP_MSG_BASE2_ADDR_LO 0xD9130
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#define mmMME_CMDQ_CP_MSG_BASE2_ADDR_HI 0xD9134
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#define mmMME_CMDQ_CP_MSG_BASE3_ADDR_LO 0xD9138
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#define mmMME_CMDQ_CP_MSG_BASE3_ADDR_HI 0xD913C
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#define mmMME_CMDQ_CP_LDMA_TSIZE_OFFSET 0xD9140
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#define mmMME_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xD9144
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#define mmMME_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xD9148
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#define mmMME_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xD914C
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#define mmMME_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xD9150
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#define mmMME_CMDQ_CP_LDMA_COMMIT_OFFSET 0xD9154
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#define mmMME_CMDQ_CP_FENCE0_RDATA 0xD9158
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#define mmMME_CMDQ_CP_FENCE1_RDATA 0xD915C
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#define mmMME_CMDQ_CP_FENCE2_RDATA 0xD9160
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#define mmMME_CMDQ_CP_FENCE3_RDATA 0xD9164
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#define mmMME_CMDQ_CP_FENCE0_CNT 0xD9168
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#define mmMME_CMDQ_CP_FENCE1_CNT 0xD916C
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#define mmMME_CMDQ_CP_FENCE2_CNT 0xD9170
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#define mmMME_CMDQ_CP_FENCE3_CNT 0xD9174
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#define mmMME_CMDQ_CP_STS 0xD9178
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#define mmMME_CMDQ_CP_CURRENT_INST_LO 0xD917C
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#define mmMME_CMDQ_CP_CURRENT_INST_HI 0xD9180
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#define mmMME_CMDQ_CP_BARRIER_CFG 0xD9184
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#define mmMME_CMDQ_CP_DBG_0 0xD9188
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#define mmMME_CMDQ_CQ_BUF_ADDR 0xD9308
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#define mmMME_CMDQ_CQ_BUF_RDATA 0xD930C
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#endif /* ASIC_REG_MME_CMDQ_REGS_H_ */
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