/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_MME0_QM_REGS_H_
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#define ASIC_REG_MME0_QM_REGS_H_
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/*
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*****************************************
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* MME0_QM (Prototype: QMAN)
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*****************************************
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*/
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#define mmMME0_QM_GLBL_CFG0 0x68000
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#define mmMME0_QM_GLBL_CFG1 0x68004
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#define mmMME0_QM_GLBL_PROT 0x68008
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#define mmMME0_QM_GLBL_ERR_CFG 0x6800C
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#define mmMME0_QM_GLBL_SECURE_PROPS_0 0x68010
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#define mmMME0_QM_GLBL_SECURE_PROPS_1 0x68014
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#define mmMME0_QM_GLBL_SECURE_PROPS_2 0x68018
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#define mmMME0_QM_GLBL_SECURE_PROPS_3 0x6801C
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#define mmMME0_QM_GLBL_SECURE_PROPS_4 0x68020
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#define mmMME0_QM_GLBL_NON_SECURE_PROPS_0 0x68024
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#define mmMME0_QM_GLBL_NON_SECURE_PROPS_1 0x68028
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#define mmMME0_QM_GLBL_NON_SECURE_PROPS_2 0x6802C
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#define mmMME0_QM_GLBL_NON_SECURE_PROPS_3 0x68030
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#define mmMME0_QM_GLBL_NON_SECURE_PROPS_4 0x68034
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#define mmMME0_QM_GLBL_STS0 0x68038
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#define mmMME0_QM_GLBL_STS1_0 0x68040
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#define mmMME0_QM_GLBL_STS1_1 0x68044
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#define mmMME0_QM_GLBL_STS1_2 0x68048
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#define mmMME0_QM_GLBL_STS1_3 0x6804C
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#define mmMME0_QM_GLBL_STS1_4 0x68050
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#define mmMME0_QM_GLBL_MSG_EN_0 0x68054
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#define mmMME0_QM_GLBL_MSG_EN_1 0x68058
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#define mmMME0_QM_GLBL_MSG_EN_2 0x6805C
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#define mmMME0_QM_GLBL_MSG_EN_3 0x68060
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#define mmMME0_QM_GLBL_MSG_EN_4 0x68068
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#define mmMME0_QM_PQ_BASE_LO_0 0x68070
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#define mmMME0_QM_PQ_BASE_LO_1 0x68074
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#define mmMME0_QM_PQ_BASE_LO_2 0x68078
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#define mmMME0_QM_PQ_BASE_LO_3 0x6807C
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#define mmMME0_QM_PQ_BASE_HI_0 0x68080
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#define mmMME0_QM_PQ_BASE_HI_1 0x68084
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#define mmMME0_QM_PQ_BASE_HI_2 0x68088
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#define mmMME0_QM_PQ_BASE_HI_3 0x6808C
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#define mmMME0_QM_PQ_SIZE_0 0x68090
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#define mmMME0_QM_PQ_SIZE_1 0x68094
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#define mmMME0_QM_PQ_SIZE_2 0x68098
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#define mmMME0_QM_PQ_SIZE_3 0x6809C
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#define mmMME0_QM_PQ_PI_0 0x680A0
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#define mmMME0_QM_PQ_PI_1 0x680A4
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#define mmMME0_QM_PQ_PI_2 0x680A8
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#define mmMME0_QM_PQ_PI_3 0x680AC
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#define mmMME0_QM_PQ_CI_0 0x680B0
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#define mmMME0_QM_PQ_CI_1 0x680B4
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#define mmMME0_QM_PQ_CI_2 0x680B8
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#define mmMME0_QM_PQ_CI_3 0x680BC
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#define mmMME0_QM_PQ_CFG0_0 0x680C0
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#define mmMME0_QM_PQ_CFG0_1 0x680C4
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#define mmMME0_QM_PQ_CFG0_2 0x680C8
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#define mmMME0_QM_PQ_CFG0_3 0x680CC
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#define mmMME0_QM_PQ_CFG1_0 0x680D0
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#define mmMME0_QM_PQ_CFG1_1 0x680D4
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#define mmMME0_QM_PQ_CFG1_2 0x680D8
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#define mmMME0_QM_PQ_CFG1_3 0x680DC
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#define mmMME0_QM_PQ_ARUSER_31_11_0 0x680E0
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#define mmMME0_QM_PQ_ARUSER_31_11_1 0x680E4
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#define mmMME0_QM_PQ_ARUSER_31_11_2 0x680E8
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#define mmMME0_QM_PQ_ARUSER_31_11_3 0x680EC
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#define mmMME0_QM_PQ_STS0_0 0x680F0
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#define mmMME0_QM_PQ_STS0_1 0x680F4
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#define mmMME0_QM_PQ_STS0_2 0x680F8
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#define mmMME0_QM_PQ_STS0_3 0x680FC
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#define mmMME0_QM_PQ_STS1_0 0x68100
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#define mmMME0_QM_PQ_STS1_1 0x68104
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#define mmMME0_QM_PQ_STS1_2 0x68108
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#define mmMME0_QM_PQ_STS1_3 0x6810C
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#define mmMME0_QM_CQ_CFG0_0 0x68110
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#define mmMME0_QM_CQ_CFG0_1 0x68114
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#define mmMME0_QM_CQ_CFG0_2 0x68118
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#define mmMME0_QM_CQ_CFG0_3 0x6811C
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#define mmMME0_QM_CQ_CFG0_4 0x68120
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#define mmMME0_QM_CQ_CFG1_0 0x68124
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#define mmMME0_QM_CQ_CFG1_1 0x68128
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#define mmMME0_QM_CQ_CFG1_2 0x6812C
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#define mmMME0_QM_CQ_CFG1_3 0x68130
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#define mmMME0_QM_CQ_CFG1_4 0x68134
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#define mmMME0_QM_CQ_ARUSER_31_11_0 0x68138
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#define mmMME0_QM_CQ_ARUSER_31_11_1 0x6813C
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#define mmMME0_QM_CQ_ARUSER_31_11_2 0x68140
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#define mmMME0_QM_CQ_ARUSER_31_11_3 0x68144
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#define mmMME0_QM_CQ_ARUSER_31_11_4 0x68148
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#define mmMME0_QM_CQ_STS0_0 0x6814C
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#define mmMME0_QM_CQ_STS0_1 0x68150
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#define mmMME0_QM_CQ_STS0_2 0x68154
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#define mmMME0_QM_CQ_STS0_3 0x68158
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#define mmMME0_QM_CQ_STS0_4 0x6815C
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#define mmMME0_QM_CQ_STS1_0 0x68160
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#define mmMME0_QM_CQ_STS1_1 0x68164
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#define mmMME0_QM_CQ_STS1_2 0x68168
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#define mmMME0_QM_CQ_STS1_3 0x6816C
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#define mmMME0_QM_CQ_STS1_4 0x68170
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#define mmMME0_QM_CQ_PTR_LO_0 0x68174
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#define mmMME0_QM_CQ_PTR_HI_0 0x68178
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#define mmMME0_QM_CQ_TSIZE_0 0x6817C
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#define mmMME0_QM_CQ_CTL_0 0x68180
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#define mmMME0_QM_CQ_PTR_LO_1 0x68184
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#define mmMME0_QM_CQ_PTR_HI_1 0x68188
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#define mmMME0_QM_CQ_TSIZE_1 0x6818C
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#define mmMME0_QM_CQ_CTL_1 0x68190
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#define mmMME0_QM_CQ_PTR_LO_2 0x68194
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#define mmMME0_QM_CQ_PTR_HI_2 0x68198
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#define mmMME0_QM_CQ_TSIZE_2 0x6819C
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#define mmMME0_QM_CQ_CTL_2 0x681A0
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#define mmMME0_QM_CQ_PTR_LO_3 0x681A4
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#define mmMME0_QM_CQ_PTR_HI_3 0x681A8
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#define mmMME0_QM_CQ_TSIZE_3 0x681AC
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#define mmMME0_QM_CQ_CTL_3 0x681B0
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#define mmMME0_QM_CQ_PTR_LO_4 0x681B4
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#define mmMME0_QM_CQ_PTR_HI_4 0x681B8
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#define mmMME0_QM_CQ_TSIZE_4 0x681BC
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#define mmMME0_QM_CQ_CTL_4 0x681C0
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#define mmMME0_QM_CQ_PTR_LO_STS_0 0x681C4
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#define mmMME0_QM_CQ_PTR_LO_STS_1 0x681C8
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#define mmMME0_QM_CQ_PTR_LO_STS_2 0x681CC
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#define mmMME0_QM_CQ_PTR_LO_STS_3 0x681D0
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#define mmMME0_QM_CQ_PTR_LO_STS_4 0x681D4
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#define mmMME0_QM_CQ_PTR_HI_STS_0 0x681D8
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#define mmMME0_QM_CQ_PTR_HI_STS_1 0x681DC
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#define mmMME0_QM_CQ_PTR_HI_STS_2 0x681E0
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#define mmMME0_QM_CQ_PTR_HI_STS_3 0x681E4
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#define mmMME0_QM_CQ_PTR_HI_STS_4 0x681E8
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#define mmMME0_QM_CQ_TSIZE_STS_0 0x681EC
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#define mmMME0_QM_CQ_TSIZE_STS_1 0x681F0
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#define mmMME0_QM_CQ_TSIZE_STS_2 0x681F4
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#define mmMME0_QM_CQ_TSIZE_STS_3 0x681F8
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#define mmMME0_QM_CQ_TSIZE_STS_4 0x681FC
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#define mmMME0_QM_CQ_CTL_STS_0 0x68200
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#define mmMME0_QM_CQ_CTL_STS_1 0x68204
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#define mmMME0_QM_CQ_CTL_STS_2 0x68208
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#define mmMME0_QM_CQ_CTL_STS_3 0x6820C
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#define mmMME0_QM_CQ_CTL_STS_4 0x68210
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#define mmMME0_QM_CQ_IFIFO_CNT_0 0x68214
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#define mmMME0_QM_CQ_IFIFO_CNT_1 0x68218
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#define mmMME0_QM_CQ_IFIFO_CNT_2 0x6821C
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#define mmMME0_QM_CQ_IFIFO_CNT_3 0x68220
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#define mmMME0_QM_CQ_IFIFO_CNT_4 0x68224
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#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 0x68228
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#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 0x6822C
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#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 0x68230
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#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 0x68234
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#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 0x68238
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#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 0x6823C
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#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 0x68240
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#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 0x68244
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#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 0x68248
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#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 0x6824C
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#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 0x68250
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#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 0x68254
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#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 0x68258
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#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 0x6825C
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#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 0x68260
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#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 0x68264
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#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 0x68268
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#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 0x6826C
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#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 0x68270
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#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 0x68274
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#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 0x68278
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#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 0x6827C
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#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 0x68280
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#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 0x68284
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#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 0x68288
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#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 0x6828C
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#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 0x68290
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#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 0x68294
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#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 0x68298
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#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 0x6829C
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#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 0x682A0
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#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 0x682A4
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#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 0x682A8
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#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 0x682AC
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#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 0x682B0
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#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 0x682B4
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#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 0x682B8
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#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 0x682BC
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#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 0x682C0
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#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 0x682C4
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#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 0x682C8
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#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 0x682CC
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#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 0x682D0
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#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 0x682D4
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#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 0x682D8
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#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x682E0
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#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x682E4
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#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x682E8
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#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x682EC
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#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x682F0
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#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x682F4
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#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x682F8
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#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x682FC
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#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x68300
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#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x68304
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#define mmMME0_QM_CP_FENCE0_RDATA_0 0x68308
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#define mmMME0_QM_CP_FENCE0_RDATA_1 0x6830C
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#define mmMME0_QM_CP_FENCE0_RDATA_2 0x68310
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#define mmMME0_QM_CP_FENCE0_RDATA_3 0x68314
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#define mmMME0_QM_CP_FENCE0_RDATA_4 0x68318
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#define mmMME0_QM_CP_FENCE1_RDATA_0 0x6831C
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#define mmMME0_QM_CP_FENCE1_RDATA_1 0x68320
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#define mmMME0_QM_CP_FENCE1_RDATA_2 0x68324
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#define mmMME0_QM_CP_FENCE1_RDATA_3 0x68328
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#define mmMME0_QM_CP_FENCE1_RDATA_4 0x6832C
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#define mmMME0_QM_CP_FENCE2_RDATA_0 0x68330
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#define mmMME0_QM_CP_FENCE2_RDATA_1 0x68334
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#define mmMME0_QM_CP_FENCE2_RDATA_2 0x68338
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#define mmMME0_QM_CP_FENCE2_RDATA_3 0x6833C
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#define mmMME0_QM_CP_FENCE2_RDATA_4 0x68340
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#define mmMME0_QM_CP_FENCE3_RDATA_0 0x68344
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#define mmMME0_QM_CP_FENCE3_RDATA_1 0x68348
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#define mmMME0_QM_CP_FENCE3_RDATA_2 0x6834C
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#define mmMME0_QM_CP_FENCE3_RDATA_3 0x68350
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#define mmMME0_QM_CP_FENCE3_RDATA_4 0x68354
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#define mmMME0_QM_CP_FENCE0_CNT_0 0x68358
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#define mmMME0_QM_CP_FENCE0_CNT_1 0x6835C
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#define mmMME0_QM_CP_FENCE0_CNT_2 0x68360
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#define mmMME0_QM_CP_FENCE0_CNT_3 0x68364
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#define mmMME0_QM_CP_FENCE0_CNT_4 0x68368
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#define mmMME0_QM_CP_FENCE1_CNT_0 0x6836C
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#define mmMME0_QM_CP_FENCE1_CNT_1 0x68370
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#define mmMME0_QM_CP_FENCE1_CNT_2 0x68374
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#define mmMME0_QM_CP_FENCE1_CNT_3 0x68378
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#define mmMME0_QM_CP_FENCE1_CNT_4 0x6837C
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#define mmMME0_QM_CP_FENCE2_CNT_0 0x68380
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#define mmMME0_QM_CP_FENCE2_CNT_1 0x68384
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#define mmMME0_QM_CP_FENCE2_CNT_2 0x68388
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#define mmMME0_QM_CP_FENCE2_CNT_3 0x6838C
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#define mmMME0_QM_CP_FENCE2_CNT_4 0x68390
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#define mmMME0_QM_CP_FENCE3_CNT_0 0x68394
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#define mmMME0_QM_CP_FENCE3_CNT_1 0x68398
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#define mmMME0_QM_CP_FENCE3_CNT_2 0x6839C
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#define mmMME0_QM_CP_FENCE3_CNT_3 0x683A0
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#define mmMME0_QM_CP_FENCE3_CNT_4 0x683A4
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#define mmMME0_QM_CP_STS_0 0x683A8
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#define mmMME0_QM_CP_STS_1 0x683AC
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#define mmMME0_QM_CP_STS_2 0x683B0
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#define mmMME0_QM_CP_STS_3 0x683B4
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#define mmMME0_QM_CP_STS_4 0x683B8
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#define mmMME0_QM_CP_CURRENT_INST_LO_0 0x683BC
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#define mmMME0_QM_CP_CURRENT_INST_LO_1 0x683C0
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#define mmMME0_QM_CP_CURRENT_INST_LO_2 0x683C4
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#define mmMME0_QM_CP_CURRENT_INST_LO_3 0x683C8
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#define mmMME0_QM_CP_CURRENT_INST_LO_4 0x683CC
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#define mmMME0_QM_CP_CURRENT_INST_HI_0 0x683D0
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#define mmMME0_QM_CP_CURRENT_INST_HI_1 0x683D4
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#define mmMME0_QM_CP_CURRENT_INST_HI_2 0x683D8
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#define mmMME0_QM_CP_CURRENT_INST_HI_3 0x683DC
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#define mmMME0_QM_CP_CURRENT_INST_HI_4 0x683E0
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#define mmMME0_QM_CP_BARRIER_CFG_0 0x683F4
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#define mmMME0_QM_CP_BARRIER_CFG_1 0x683F8
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#define mmMME0_QM_CP_BARRIER_CFG_2 0x683FC
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#define mmMME0_QM_CP_BARRIER_CFG_3 0x68400
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#define mmMME0_QM_CP_BARRIER_CFG_4 0x68404
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#define mmMME0_QM_CP_DBG_0_0 0x68408
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#define mmMME0_QM_CP_DBG_0_1 0x6840C
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#define mmMME0_QM_CP_DBG_0_2 0x68410
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#define mmMME0_QM_CP_DBG_0_3 0x68414
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#define mmMME0_QM_CP_DBG_0_4 0x68418
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#define mmMME0_QM_CP_ARUSER_31_11_0 0x6841C
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#define mmMME0_QM_CP_ARUSER_31_11_1 0x68420
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#define mmMME0_QM_CP_ARUSER_31_11_2 0x68424
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#define mmMME0_QM_CP_ARUSER_31_11_3 0x68428
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#define mmMME0_QM_CP_ARUSER_31_11_4 0x6842C
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#define mmMME0_QM_CP_AWUSER_31_11_0 0x68430
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#define mmMME0_QM_CP_AWUSER_31_11_1 0x68434
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#define mmMME0_QM_CP_AWUSER_31_11_2 0x68438
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#define mmMME0_QM_CP_AWUSER_31_11_3 0x6843C
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#define mmMME0_QM_CP_AWUSER_31_11_4 0x68440
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#define mmMME0_QM_ARB_CFG_0 0x68A00
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#define mmMME0_QM_ARB_CHOISE_Q_PUSH 0x68A04
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#define mmMME0_QM_ARB_WRR_WEIGHT_0 0x68A08
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#define mmMME0_QM_ARB_WRR_WEIGHT_1 0x68A0C
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#define mmMME0_QM_ARB_WRR_WEIGHT_2 0x68A10
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#define mmMME0_QM_ARB_WRR_WEIGHT_3 0x68A14
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#define mmMME0_QM_ARB_CFG_1 0x68A18
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_0 0x68A20
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_1 0x68A24
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_2 0x68A28
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_3 0x68A2C
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_4 0x68A30
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_5 0x68A34
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_6 0x68A38
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_7 0x68A3C
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_8 0x68A40
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_9 0x68A44
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_10 0x68A48
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_11 0x68A4C
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_12 0x68A50
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_13 0x68A54
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_14 0x68A58
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_15 0x68A5C
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_16 0x68A60
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_17 0x68A64
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_18 0x68A68
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_19 0x68A6C
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_20 0x68A70
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_21 0x68A74
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_22 0x68A78
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_23 0x68A7C
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_24 0x68A80
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_25 0x68A84
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_26 0x68A88
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_27 0x68A8C
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_28 0x68A90
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_29 0x68A94
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_30 0x68A98
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#define mmMME0_QM_ARB_MST_AVAIL_CRED_31 0x68A9C
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#define mmMME0_QM_ARB_MST_CRED_INC 0x68AA0
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x68AA4
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x68AA8
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x68AAC
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x68AB0
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x68AB4
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x68AB8
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x68ABC
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x68AC0
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x68AC4
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x68AC8
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x68ACC
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x68AD0
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x68AD4
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x68AD8
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x68ADC
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x68AE0
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x68AE4
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x68AE8
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x68AEC
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x68AF0
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x68AF4
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x68AF8
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x68AFC
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x68B00
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x68B04
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x68B08
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x68B0C
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x68B10
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x68B14
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x68B18
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x68B1C
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#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x68B20
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#define mmMME0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x68B28
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#define mmMME0_QM_ARB_MST_SLAVE_EN 0x68B2C
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#define mmMME0_QM_ARB_MST_QUIET_PER 0x68B34
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#define mmMME0_QM_ARB_SLV_CHOISE_WDT 0x68B38
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#define mmMME0_QM_ARB_SLV_ID 0x68B3C
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#define mmMME0_QM_ARB_MSG_MAX_INFLIGHT 0x68B44
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#define mmMME0_QM_ARB_MSG_AWUSER_31_11 0x68B48
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#define mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP 0x68B4C
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#define mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x68B50
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#define mmMME0_QM_ARB_BASE_LO 0x68B54
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#define mmMME0_QM_ARB_BASE_HI 0x68B58
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#define mmMME0_QM_ARB_STATE_STS 0x68B80
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#define mmMME0_QM_ARB_CHOISE_FULLNESS_STS 0x68B84
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#define mmMME0_QM_ARB_MSG_STS 0x68B88
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#define mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD 0x68B8C
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#define mmMME0_QM_ARB_ERR_CAUSE 0x68B9C
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#define mmMME0_QM_ARB_ERR_MSG_EN 0x68BA0
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#define mmMME0_QM_ARB_ERR_STS_DRP 0x68BA8
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#define mmMME0_QM_ARB_MST_CRED_STS_0 0x68BB0
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#define mmMME0_QM_ARB_MST_CRED_STS_1 0x68BB4
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#define mmMME0_QM_ARB_MST_CRED_STS_2 0x68BB8
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#define mmMME0_QM_ARB_MST_CRED_STS_3 0x68BBC
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#define mmMME0_QM_ARB_MST_CRED_STS_4 0x68BC0
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#define mmMME0_QM_ARB_MST_CRED_STS_5 0x68BC4
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#define mmMME0_QM_ARB_MST_CRED_STS_6 0x68BC8
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#define mmMME0_QM_ARB_MST_CRED_STS_7 0x68BCC
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#define mmMME0_QM_ARB_MST_CRED_STS_8 0x68BD0
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#define mmMME0_QM_ARB_MST_CRED_STS_9 0x68BD4
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#define mmMME0_QM_ARB_MST_CRED_STS_10 0x68BD8
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#define mmMME0_QM_ARB_MST_CRED_STS_11 0x68BDC
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#define mmMME0_QM_ARB_MST_CRED_STS_12 0x68BE0
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#define mmMME0_QM_ARB_MST_CRED_STS_13 0x68BE4
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#define mmMME0_QM_ARB_MST_CRED_STS_14 0x68BE8
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#define mmMME0_QM_ARB_MST_CRED_STS_15 0x68BEC
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#define mmMME0_QM_ARB_MST_CRED_STS_16 0x68BF0
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#define mmMME0_QM_ARB_MST_CRED_STS_17 0x68BF4
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#define mmMME0_QM_ARB_MST_CRED_STS_18 0x68BF8
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#define mmMME0_QM_ARB_MST_CRED_STS_19 0x68BFC
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#define mmMME0_QM_ARB_MST_CRED_STS_20 0x68C00
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#define mmMME0_QM_ARB_MST_CRED_STS_21 0x68C04
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#define mmMME0_QM_ARB_MST_CRED_STS_22 0x68C08
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#define mmMME0_QM_ARB_MST_CRED_STS_23 0x68C0C
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#define mmMME0_QM_ARB_MST_CRED_STS_24 0x68C10
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#define mmMME0_QM_ARB_MST_CRED_STS_25 0x68C14
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#define mmMME0_QM_ARB_MST_CRED_STS_26 0x68C18
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#define mmMME0_QM_ARB_MST_CRED_STS_27 0x68C1C
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#define mmMME0_QM_ARB_MST_CRED_STS_28 0x68C20
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#define mmMME0_QM_ARB_MST_CRED_STS_29 0x68C24
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#define mmMME0_QM_ARB_MST_CRED_STS_30 0x68C28
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#define mmMME0_QM_ARB_MST_CRED_STS_31 0x68C2C
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#define mmMME0_QM_CGM_CFG 0x68C70
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#define mmMME0_QM_CGM_STS 0x68C74
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#define mmMME0_QM_CGM_CFG1 0x68C78
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#define mmMME0_QM_LOCAL_RANGE_BASE 0x68C80
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#define mmMME0_QM_LOCAL_RANGE_SIZE 0x68C84
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#define mmMME0_QM_CSMR_STRICT_PRIO_CFG 0x68C90
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#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 0x68C94
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#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 0x68C98
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#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 0x68C9C
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#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 0x68CA0
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#define mmMME0_QM_GLBL_AXCACHE 0x68CA4
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#define mmMME0_QM_IND_GW_APB_CFG 0x68CB0
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#define mmMME0_QM_IND_GW_APB_WDATA 0x68CB4
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#define mmMME0_QM_IND_GW_APB_RDATA 0x68CB8
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#define mmMME0_QM_IND_GW_APB_STATUS 0x68CBC
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#define mmMME0_QM_GLBL_ERR_ADDR_LO 0x68CD0
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#define mmMME0_QM_GLBL_ERR_ADDR_HI 0x68CD4
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#define mmMME0_QM_GLBL_ERR_WDATA 0x68CD8
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#define mmMME0_QM_GLBL_MEM_INIT_BUSY 0x68D00
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#endif /* ASIC_REG_MME0_QM_REGS_H_ */
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