/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* IOMMU API for ARM architected SMMU implementations.
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*
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* Copyright (C) 2013 ARM Limited
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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#ifndef _ARM_SMMU_H
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#define _ARM_SMMU_H
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#include <linux/atomic.h>
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/io-64-nonatomic-hi-lo.h>
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#include <linux/io-pgtable.h>
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#include <linux/iommu.h>
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#include <linux/irqreturn.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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/* Configuration registers */
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#define ARM_SMMU_GR0_sCR0 0x0
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#define ARM_SMMU_sCR0_VMID16EN BIT(31)
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#define ARM_SMMU_sCR0_BSU GENMASK(15, 14)
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#define ARM_SMMU_sCR0_FB BIT(13)
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#define ARM_SMMU_sCR0_PTM BIT(12)
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#define ARM_SMMU_sCR0_VMIDPNE BIT(11)
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#define ARM_SMMU_sCR0_USFCFG BIT(10)
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#define ARM_SMMU_sCR0_GCFGFIE BIT(5)
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#define ARM_SMMU_sCR0_GCFGFRE BIT(4)
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#define ARM_SMMU_sCR0_EXIDENABLE BIT(3)
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#define ARM_SMMU_sCR0_GFIE BIT(2)
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#define ARM_SMMU_sCR0_GFRE BIT(1)
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#define ARM_SMMU_sCR0_CLIENTPD BIT(0)
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/* Auxiliary Configuration register */
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#define ARM_SMMU_GR0_sACR 0x10
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/* Identification registers */
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#define ARM_SMMU_GR0_ID0 0x20
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#define ARM_SMMU_ID0_S1TS BIT(30)
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#define ARM_SMMU_ID0_S2TS BIT(29)
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#define ARM_SMMU_ID0_NTS BIT(28)
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#define ARM_SMMU_ID0_SMS BIT(27)
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#define ARM_SMMU_ID0_ATOSNS BIT(26)
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#define ARM_SMMU_ID0_PTFS_NO_AARCH32 BIT(25)
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#define ARM_SMMU_ID0_PTFS_NO_AARCH32S BIT(24)
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#define ARM_SMMU_ID0_NUMIRPT GENMASK(23, 16)
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#define ARM_SMMU_ID0_CTTW BIT(14)
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#define ARM_SMMU_ID0_NUMSIDB GENMASK(12, 9)
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#define ARM_SMMU_ID0_EXIDS BIT(8)
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#define ARM_SMMU_ID0_NUMSMRG GENMASK(7, 0)
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#define ARM_SMMU_GR0_ID1 0x24
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#define ARM_SMMU_ID1_PAGESIZE BIT(31)
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#define ARM_SMMU_ID1_NUMPAGENDXB GENMASK(30, 28)
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#define ARM_SMMU_ID1_NUMS2CB GENMASK(23, 16)
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#define ARM_SMMU_ID1_NUMCB GENMASK(7, 0)
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#define ARM_SMMU_GR0_ID2 0x28
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#define ARM_SMMU_ID2_VMID16 BIT(15)
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#define ARM_SMMU_ID2_PTFS_64K BIT(14)
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#define ARM_SMMU_ID2_PTFS_16K BIT(13)
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#define ARM_SMMU_ID2_PTFS_4K BIT(12)
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#define ARM_SMMU_ID2_UBS GENMASK(11, 8)
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#define ARM_SMMU_ID2_OAS GENMASK(7, 4)
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#define ARM_SMMU_ID2_IAS GENMASK(3, 0)
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#define ARM_SMMU_GR0_ID3 0x2c
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#define ARM_SMMU_GR0_ID4 0x30
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#define ARM_SMMU_GR0_ID5 0x34
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#define ARM_SMMU_GR0_ID6 0x38
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#define ARM_SMMU_GR0_ID7 0x3c
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#define ARM_SMMU_ID7_MAJOR GENMASK(7, 4)
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#define ARM_SMMU_ID7_MINOR GENMASK(3, 0)
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#define ARM_SMMU_GR0_sGFSR 0x48
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#define ARM_SMMU_sGFSR_USF BIT(1)
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#define ARM_SMMU_GR0_sGFSYNR0 0x50
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#define ARM_SMMU_GR0_sGFSYNR1 0x54
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#define ARM_SMMU_GR0_sGFSYNR2 0x58
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/* Global TLB invalidation */
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#define ARM_SMMU_GR0_TLBIVMID 0x64
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#define ARM_SMMU_GR0_TLBIALLNSNH 0x68
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#define ARM_SMMU_GR0_TLBIALLH 0x6c
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#define ARM_SMMU_GR0_sTLBGSYNC 0x70
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#define ARM_SMMU_GR0_sTLBGSTATUS 0x74
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#define ARM_SMMU_sTLBGSTATUS_GSACTIVE BIT(0)
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/* Stream mapping registers */
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#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
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#define ARM_SMMU_SMR_VALID BIT(31)
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#define ARM_SMMU_SMR_MASK GENMASK(31, 16)
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#define ARM_SMMU_SMR_ID GENMASK(15, 0)
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#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
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#define ARM_SMMU_S2CR_PRIVCFG GENMASK(25, 24)
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enum arm_smmu_s2cr_privcfg {
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S2CR_PRIVCFG_DEFAULT,
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S2CR_PRIVCFG_DIPAN,
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S2CR_PRIVCFG_UNPRIV,
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S2CR_PRIVCFG_PRIV,
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};
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#define ARM_SMMU_S2CR_TYPE GENMASK(17, 16)
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enum arm_smmu_s2cr_type {
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S2CR_TYPE_TRANS,
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S2CR_TYPE_BYPASS,
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S2CR_TYPE_FAULT,
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};
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#define ARM_SMMU_S2CR_EXIDVALID BIT(10)
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#define ARM_SMMU_S2CR_CBNDX GENMASK(7, 0)
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/* Context bank attribute registers */
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#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
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#define ARM_SMMU_CBAR_IRPTNDX GENMASK(31, 24)
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#define ARM_SMMU_CBAR_TYPE GENMASK(17, 16)
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enum arm_smmu_cbar_type {
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CBAR_TYPE_S2_TRANS,
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CBAR_TYPE_S1_TRANS_S2_BYPASS,
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CBAR_TYPE_S1_TRANS_S2_FAULT,
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CBAR_TYPE_S1_TRANS_S2_TRANS,
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};
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#define ARM_SMMU_CBAR_S1_MEMATTR GENMASK(15, 12)
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#define ARM_SMMU_CBAR_S1_MEMATTR_WB 0xf
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#define ARM_SMMU_CBAR_S1_BPSHCFG GENMASK(9, 8)
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#define ARM_SMMU_CBAR_S1_BPSHCFG_NSH 3
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#define ARM_SMMU_CBAR_VMID GENMASK(7, 0)
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#define ARM_SMMU_GR1_CBFRSYNRA(n) (0x400 + ((n) << 2))
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#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
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#define ARM_SMMU_CBA2R_VMID16 GENMASK(31, 16)
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#define ARM_SMMU_CBA2R_VA64 BIT(0)
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#define ARM_SMMU_CB_SCTLR 0x0
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#define ARM_SMMU_SCTLR_S1_ASIDPNE BIT(12)
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#define ARM_SMMU_SCTLR_CFCFG BIT(7)
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#define ARM_SMMU_SCTLR_CFIE BIT(6)
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#define ARM_SMMU_SCTLR_CFRE BIT(5)
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#define ARM_SMMU_SCTLR_E BIT(4)
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#define ARM_SMMU_SCTLR_AFE BIT(2)
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#define ARM_SMMU_SCTLR_TRE BIT(1)
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#define ARM_SMMU_SCTLR_M BIT(0)
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#define ARM_SMMU_CB_ACTLR 0x4
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#define ARM_SMMU_CB_RESUME 0x8
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#define ARM_SMMU_RESUME_TERMINATE BIT(0)
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#define ARM_SMMU_CB_TCR2 0x10
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#define ARM_SMMU_TCR2_SEP GENMASK(17, 15)
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#define ARM_SMMU_TCR2_SEP_UPSTREAM 0x7
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#define ARM_SMMU_TCR2_AS BIT(4)
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#define ARM_SMMU_TCR2_PASIZE GENMASK(3, 0)
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#define ARM_SMMU_CB_TTBR0 0x20
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#define ARM_SMMU_CB_TTBR1 0x28
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#define ARM_SMMU_TTBRn_ASID GENMASK_ULL(63, 48)
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#define ARM_SMMU_CB_TCR 0x30
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#define ARM_SMMU_TCR_EAE BIT(31)
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#define ARM_SMMU_TCR_EPD1 BIT(23)
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#define ARM_SMMU_TCR_A1 BIT(22)
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#define ARM_SMMU_TCR_TG0 GENMASK(15, 14)
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#define ARM_SMMU_TCR_SH0 GENMASK(13, 12)
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#define ARM_SMMU_TCR_ORGN0 GENMASK(11, 10)
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#define ARM_SMMU_TCR_IRGN0 GENMASK(9, 8)
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#define ARM_SMMU_TCR_EPD0 BIT(7)
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#define ARM_SMMU_TCR_T0SZ GENMASK(5, 0)
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#define ARM_SMMU_VTCR_RES1 BIT(31)
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#define ARM_SMMU_VTCR_PS GENMASK(18, 16)
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#define ARM_SMMU_VTCR_TG0 ARM_SMMU_TCR_TG0
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#define ARM_SMMU_VTCR_SH0 ARM_SMMU_TCR_SH0
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#define ARM_SMMU_VTCR_ORGN0 ARM_SMMU_TCR_ORGN0
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#define ARM_SMMU_VTCR_IRGN0 ARM_SMMU_TCR_IRGN0
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#define ARM_SMMU_VTCR_SL0 GENMASK(7, 6)
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#define ARM_SMMU_VTCR_T0SZ ARM_SMMU_TCR_T0SZ
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#define ARM_SMMU_CB_CONTEXTIDR 0x34
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#define ARM_SMMU_CB_S1_MAIR0 0x38
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#define ARM_SMMU_CB_S1_MAIR1 0x3c
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#define ARM_SMMU_CB_PAR 0x50
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#define ARM_SMMU_CB_PAR_F BIT(0)
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#define ARM_SMMU_CB_FSR 0x58
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#define ARM_SMMU_FSR_MULTI BIT(31)
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#define ARM_SMMU_FSR_SS BIT(30)
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#define ARM_SMMU_FSR_UUT BIT(8)
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#define ARM_SMMU_FSR_ASF BIT(7)
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#define ARM_SMMU_FSR_TLBLKF BIT(6)
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#define ARM_SMMU_FSR_TLBMCF BIT(5)
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#define ARM_SMMU_FSR_EF BIT(4)
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#define ARM_SMMU_FSR_PF BIT(3)
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#define ARM_SMMU_FSR_AFF BIT(2)
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#define ARM_SMMU_FSR_TF BIT(1)
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#define ARM_SMMU_FSR_IGN (ARM_SMMU_FSR_AFF | \
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ARM_SMMU_FSR_ASF | \
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ARM_SMMU_FSR_TLBMCF | \
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ARM_SMMU_FSR_TLBLKF)
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#define ARM_SMMU_FSR_FAULT (ARM_SMMU_FSR_MULTI | \
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ARM_SMMU_FSR_SS | \
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ARM_SMMU_FSR_UUT | \
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ARM_SMMU_FSR_EF | \
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ARM_SMMU_FSR_PF | \
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ARM_SMMU_FSR_TF | \
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ARM_SMMU_FSR_IGN)
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#define ARM_SMMU_CB_FAR 0x60
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#define ARM_SMMU_CB_FSYNR0 0x68
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#define ARM_SMMU_FSYNR0_WNR BIT(4)
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#define ARM_SMMU_CB_S1_TLBIVA 0x600
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#define ARM_SMMU_CB_S1_TLBIASID 0x610
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#define ARM_SMMU_CB_S1_TLBIVAL 0x620
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#define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
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#define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
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#define ARM_SMMU_CB_TLBSYNC 0x7f0
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#define ARM_SMMU_CB_TLBSTATUS 0x7f4
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#define ARM_SMMU_CB_ATS1PR 0x800
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#define ARM_SMMU_CB_ATSR 0x8f0
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#define ARM_SMMU_ATSR_ACTIVE BIT(0)
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/* Maximum number of context banks per SMMU */
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#define ARM_SMMU_MAX_CBS 128
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#define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
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#define TLB_SPIN_COUNT 10
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/* Shared driver definitions */
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enum arm_smmu_arch_version {
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ARM_SMMU_V1,
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ARM_SMMU_V1_64K,
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ARM_SMMU_V2,
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};
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enum arm_smmu_implementation {
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GENERIC_SMMU,
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ARM_MMU500,
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CAVIUM_SMMUV2,
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QCOM_SMMUV2,
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};
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struct arm_smmu_s2cr {
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struct iommu_group *group;
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int count;
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enum arm_smmu_s2cr_type type;
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enum arm_smmu_s2cr_privcfg privcfg;
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u8 cbndx;
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bool pinned;
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};
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struct arm_smmu_smr {
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u16 mask;
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u16 id;
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bool valid;
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};
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struct arm_smmu_device {
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struct device *dev;
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void __iomem *base;
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unsigned int numpage;
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unsigned int pgshift;
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#define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
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#define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
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#define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
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#define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
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#define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
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#define ARM_SMMU_FEAT_TRANS_OPS (1 << 5)
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#define ARM_SMMU_FEAT_VMID16 (1 << 6)
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#define ARM_SMMU_FEAT_FMT_AARCH64_4K (1 << 7)
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#define ARM_SMMU_FEAT_FMT_AARCH64_16K (1 << 8)
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#define ARM_SMMU_FEAT_FMT_AARCH64_64K (1 << 9)
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#define ARM_SMMU_FEAT_FMT_AARCH32_L (1 << 10)
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#define ARM_SMMU_FEAT_FMT_AARCH32_S (1 << 11)
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#define ARM_SMMU_FEAT_EXIDS (1 << 12)
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u32 features;
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enum arm_smmu_arch_version version;
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enum arm_smmu_implementation model;
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const struct arm_smmu_impl *impl;
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u32 num_context_banks;
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u32 num_s2_context_banks;
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DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
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struct arm_smmu_cb *cbs;
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atomic_t irptndx;
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u32 num_mapping_groups;
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u16 streamid_mask;
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u16 smr_mask_mask;
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struct arm_smmu_smr *smrs;
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struct arm_smmu_s2cr *s2crs;
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struct mutex stream_map_mutex;
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unsigned long va_size;
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unsigned long ipa_size;
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unsigned long pa_size;
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unsigned long pgsize_bitmap;
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u32 num_global_irqs;
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u32 num_context_irqs;
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unsigned int *irqs;
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struct clk_bulk_data *clks;
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int num_clks;
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spinlock_t global_sync_lock;
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/* IOMMU core code handle */
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struct iommu_device iommu;
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};
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enum arm_smmu_context_fmt {
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ARM_SMMU_CTX_FMT_NONE,
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ARM_SMMU_CTX_FMT_AARCH64,
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ARM_SMMU_CTX_FMT_AARCH32_L,
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ARM_SMMU_CTX_FMT_AARCH32_S,
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};
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struct arm_smmu_cfg {
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u8 cbndx;
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u8 irptndx;
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union {
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u16 asid;
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u16 vmid;
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};
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enum arm_smmu_cbar_type cbar;
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enum arm_smmu_context_fmt fmt;
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};
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#define ARM_SMMU_INVALID_IRPTNDX 0xff
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struct arm_smmu_cb {
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u64 ttbr[2];
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u32 tcr[2];
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u32 mair[2];
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struct arm_smmu_cfg *cfg;
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};
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enum arm_smmu_domain_stage {
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ARM_SMMU_DOMAIN_S1 = 0,
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ARM_SMMU_DOMAIN_S2,
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ARM_SMMU_DOMAIN_NESTED,
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ARM_SMMU_DOMAIN_BYPASS,
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};
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struct arm_smmu_domain {
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struct arm_smmu_device *smmu;
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struct io_pgtable_ops *pgtbl_ops;
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const struct iommu_flush_ops *flush_ops;
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struct arm_smmu_cfg cfg;
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enum arm_smmu_domain_stage stage;
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bool non_strict;
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struct mutex init_mutex; /* Protects smmu pointer */
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spinlock_t cb_lock; /* Serialises ATS1* ops and TLB syncs */
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struct iommu_domain domain;
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};
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struct arm_smmu_master_cfg {
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struct arm_smmu_device *smmu;
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s16 smendx[];
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};
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static inline u32 arm_smmu_lpae_tcr(const struct io_pgtable_cfg *cfg)
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{
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u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) |
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FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) |
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FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) |
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FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) |
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FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz);
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/*
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* When TTBR1 is selected shift the TCR fields by 16 bits and disable
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* translation in TTBR0
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*/
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if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_TTBR1) {
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tcr = (tcr << 16) & ~ARM_SMMU_TCR_A1;
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tcr |= ARM_SMMU_TCR_EPD0;
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} else
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tcr |= ARM_SMMU_TCR_EPD1;
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return tcr;
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}
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static inline u32 arm_smmu_lpae_tcr2(const struct io_pgtable_cfg *cfg)
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{
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return FIELD_PREP(ARM_SMMU_TCR2_PASIZE, cfg->arm_lpae_s1_cfg.tcr.ips) |
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FIELD_PREP(ARM_SMMU_TCR2_SEP, ARM_SMMU_TCR2_SEP_UPSTREAM);
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}
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static inline u32 arm_smmu_lpae_vtcr(const struct io_pgtable_cfg *cfg)
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{
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return ARM_SMMU_VTCR_RES1 |
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FIELD_PREP(ARM_SMMU_VTCR_PS, cfg->arm_lpae_s2_cfg.vtcr.ps) |
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FIELD_PREP(ARM_SMMU_VTCR_TG0, cfg->arm_lpae_s2_cfg.vtcr.tg) |
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FIELD_PREP(ARM_SMMU_VTCR_SH0, cfg->arm_lpae_s2_cfg.vtcr.sh) |
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FIELD_PREP(ARM_SMMU_VTCR_ORGN0, cfg->arm_lpae_s2_cfg.vtcr.orgn) |
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FIELD_PREP(ARM_SMMU_VTCR_IRGN0, cfg->arm_lpae_s2_cfg.vtcr.irgn) |
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FIELD_PREP(ARM_SMMU_VTCR_SL0, cfg->arm_lpae_s2_cfg.vtcr.sl) |
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FIELD_PREP(ARM_SMMU_VTCR_T0SZ, cfg->arm_lpae_s2_cfg.vtcr.tsz);
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}
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/* Implementation details, yay! */
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struct arm_smmu_impl {
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u32 (*read_reg)(struct arm_smmu_device *smmu, int page, int offset);
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void (*write_reg)(struct arm_smmu_device *smmu, int page, int offset,
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u32 val);
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u64 (*read_reg64)(struct arm_smmu_device *smmu, int page, int offset);
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void (*write_reg64)(struct arm_smmu_device *smmu, int page, int offset,
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u64 val);
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int (*cfg_probe)(struct arm_smmu_device *smmu);
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int (*reset)(struct arm_smmu_device *smmu);
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int (*init_context)(struct arm_smmu_domain *smmu_domain,
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struct io_pgtable_cfg *cfg, struct device *dev);
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void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync,
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int status);
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int (*def_domain_type)(struct device *dev);
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irqreturn_t (*global_fault)(int irq, void *dev);
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irqreturn_t (*context_fault)(int irq, void *dev);
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int (*alloc_context_bank)(struct arm_smmu_domain *smmu_domain,
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struct arm_smmu_device *smmu,
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struct device *dev, int start);
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void (*write_s2cr)(struct arm_smmu_device *smmu, int idx);
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};
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#define INVALID_SMENDX -1
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#define cfg_smendx(cfg, fw, i) \
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(i >= fw->num_ids ? INVALID_SMENDX : cfg->smendx[i])
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#define for_each_cfg_sme(cfg, fw, i, idx) \
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for (i = 0; idx = cfg_smendx(cfg, fw, i), i < fw->num_ids; ++i)
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static inline int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
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{
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int idx;
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do {
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idx = find_next_zero_bit(map, end, start);
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if (idx == end)
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return -ENOSPC;
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} while (test_and_set_bit(idx, map));
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return idx;
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}
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static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n)
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{
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return smmu->base + (n << smmu->pgshift);
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}
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static inline u32 arm_smmu_readl(struct arm_smmu_device *smmu, int page, int offset)
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{
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if (smmu->impl && unlikely(smmu->impl->read_reg))
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return smmu->impl->read_reg(smmu, page, offset);
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return readl_relaxed(arm_smmu_page(smmu, page) + offset);
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}
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static inline void arm_smmu_writel(struct arm_smmu_device *smmu, int page,
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int offset, u32 val)
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{
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if (smmu->impl && unlikely(smmu->impl->write_reg))
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smmu->impl->write_reg(smmu, page, offset, val);
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else
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writel_relaxed(val, arm_smmu_page(smmu, page) + offset);
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}
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static inline u64 arm_smmu_readq(struct arm_smmu_device *smmu, int page, int offset)
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{
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if (smmu->impl && unlikely(smmu->impl->read_reg64))
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return smmu->impl->read_reg64(smmu, page, offset);
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return readq_relaxed(arm_smmu_page(smmu, page) + offset);
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}
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static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page,
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int offset, u64 val)
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{
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if (smmu->impl && unlikely(smmu->impl->write_reg64))
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smmu->impl->write_reg64(smmu, page, offset, val);
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else
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writeq_relaxed(val, arm_smmu_page(smmu, page) + offset);
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}
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#define ARM_SMMU_GR0 0
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#define ARM_SMMU_GR1 1
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#define ARM_SMMU_CB(s, n) ((s)->numpage + (n))
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#define arm_smmu_gr0_read(s, o) \
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arm_smmu_readl((s), ARM_SMMU_GR0, (o))
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#define arm_smmu_gr0_write(s, o, v) \
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arm_smmu_writel((s), ARM_SMMU_GR0, (o), (v))
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#define arm_smmu_gr1_read(s, o) \
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arm_smmu_readl((s), ARM_SMMU_GR1, (o))
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#define arm_smmu_gr1_write(s, o, v) \
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arm_smmu_writel((s), ARM_SMMU_GR1, (o), (v))
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#define arm_smmu_cb_read(s, n, o) \
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arm_smmu_readl((s), ARM_SMMU_CB((s), (n)), (o))
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#define arm_smmu_cb_write(s, n, o, v) \
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arm_smmu_writel((s), ARM_SMMU_CB((s), (n)), (o), (v))
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#define arm_smmu_cb_readq(s, n, o) \
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arm_smmu_readq((s), ARM_SMMU_CB((s), (n)), (o))
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#define arm_smmu_cb_writeq(s, n, o, v) \
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arm_smmu_writeq((s), ARM_SMMU_CB((s), (n)), (o), (v))
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struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu);
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struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu);
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struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu);
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struct arm_smmu_device *qcom_adreno_smmu_impl_init(struct arm_smmu_device *smmu);
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void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx);
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int arm_mmu500_reset(struct arm_smmu_device *smmu);
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#endif /* _ARM_SMMU_H */
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