/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
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#ifndef _SUN8I_TCON_TOP_H_
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#define _SUN8I_TCON_TOP_H_
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/reset.h>
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#include <linux/spinlock.h>
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#define TCON_TOP_TCON_TV_SETUP_REG 0x00
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#define TCON_TOP_PORT_SEL_REG 0x1C
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#define TCON_TOP_PORT_DE0_MSK GENMASK(1, 0)
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#define TCON_TOP_PORT_DE1_MSK GENMASK(5, 4)
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#define TCON_TOP_GATE_SRC_REG 0x20
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#define TCON_TOP_HDMI_SRC_MSK GENMASK(29, 28)
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#define TCON_TOP_TCON_TV1_GATE 24
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#define TCON_TOP_TCON_TV0_GATE 20
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#define TCON_TOP_TCON_DSI_GATE 16
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#define CLK_NUM 3
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struct sun8i_tcon_top {
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struct clk *bus;
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struct clk_hw_onecell_data *clk_data;
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void __iomem *regs;
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struct reset_control *rst;
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/*
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* spinlock is used to synchronize access to same
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* register where multiple clock gates can be set.
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*/
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spinlock_t reg_lock;
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};
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extern const struct of_device_id sun8i_tcon_top_of_table[];
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int sun8i_tcon_top_set_hdmi_src(struct device *dev, int tcon);
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int sun8i_tcon_top_de_config(struct device *dev, int mixer, int tcon);
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#endif /* _SUN8I_TCON_TOP_H_ */
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