/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv31.h"
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#include <subdev/instmem.h>
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#include <nvif/class.h>
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bool
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nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
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{
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struct nvkm_instmem *imem = device->imem;
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struct nv31_mpeg *mpeg = nv31_mpeg(device->mpeg);
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struct nvkm_subdev *subdev = &mpeg->engine.subdev;
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u32 inst = data << 4;
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u32 dma0 = nvkm_instmem_rd32(imem, inst + 0);
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u32 dma1 = nvkm_instmem_rd32(imem, inst + 4);
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u32 dma2 = nvkm_instmem_rd32(imem, inst + 8);
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u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
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u32 size = dma1 + 1;
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/* only allow linear DMA objects */
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if (!(dma0 & 0x00002000)) {
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nvkm_error(subdev, "inst %08x dma0 %08x dma1 %08x dma2 %08x\n",
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inst, dma0, dma1, dma2);
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return false;
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}
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if (mthd == 0x0190) {
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/* DMA_CMD */
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nvkm_mask(device, 0x00b300, 0x00030000, (dma0 & 0x00030000));
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nvkm_wr32(device, 0x00b334, base);
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nvkm_wr32(device, 0x00b324, size);
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} else
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if (mthd == 0x01a0) {
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/* DMA_DATA */
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nvkm_mask(device, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
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nvkm_wr32(device, 0x00b360, base);
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nvkm_wr32(device, 0x00b364, size);
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} else {
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/* DMA_IMAGE, VRAM only */
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if (dma0 & 0x00030000)
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return false;
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nvkm_wr32(device, 0x00b370, base);
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nvkm_wr32(device, 0x00b374, size);
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}
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return true;
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}
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static const struct nv31_mpeg_func
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nv40_mpeg = {
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.mthd_dma = nv40_mpeg_mthd_dma,
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};
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int
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nv40_mpeg_new(struct nvkm_device *device, int index, struct nvkm_engine **pmpeg)
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{
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return nv31_mpeg_new_(&nv40_mpeg, device, index, pmpeg);
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}
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