/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "nv40.h"
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#include "regs.h"
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#include <subdev/fb.h>
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#include <engine/fifo.h>
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static void
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nv44_gr_tile(struct nvkm_gr *base, int i, struct nvkm_fb_tile *tile)
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{
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struct nv40_gr *gr = nv40_gr(base);
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struct nvkm_device *device = gr->base.engine.subdev.device;
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struct nvkm_fifo *fifo = device->fifo;
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unsigned long flags;
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nvkm_fifo_pause(fifo, &flags);
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nv04_gr_idle(&gr->base);
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switch (device->chipset) {
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case 0x44:
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case 0x4a:
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nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
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nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
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nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
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break;
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case 0x46:
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case 0x4c:
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case 0x63:
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case 0x67:
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case 0x68:
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nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch);
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nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit);
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nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr);
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nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
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nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
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nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
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break;
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case 0x4e:
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nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch);
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nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit);
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nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr);
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nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch);
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nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit);
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nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr);
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break;
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default:
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WARN_ON(1);
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break;
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}
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nvkm_fifo_start(fifo, &flags);
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}
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static const struct nvkm_gr_func
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nv44_gr = {
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.init = nv40_gr_init,
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.intr = nv40_gr_intr,
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.tile = nv44_gr_tile,
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.units = nv40_gr_units,
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.chan_new = nv40_gr_chan_new,
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.sclass = {
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{ -1, -1, 0x0012, &nv40_gr_object }, /* beta1 */
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{ -1, -1, 0x0019, &nv40_gr_object }, /* clip */
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{ -1, -1, 0x0030, &nv40_gr_object }, /* null */
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{ -1, -1, 0x0039, &nv40_gr_object }, /* m2mf */
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{ -1, -1, 0x0043, &nv40_gr_object }, /* rop */
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{ -1, -1, 0x0044, &nv40_gr_object }, /* patt */
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{ -1, -1, 0x004a, &nv40_gr_object }, /* gdi */
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{ -1, -1, 0x0062, &nv40_gr_object }, /* surf2d */
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{ -1, -1, 0x0072, &nv40_gr_object }, /* beta4 */
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{ -1, -1, 0x0089, &nv40_gr_object }, /* sifm */
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{ -1, -1, 0x008a, &nv40_gr_object }, /* ifc */
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{ -1, -1, 0x009f, &nv40_gr_object }, /* imageblit */
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{ -1, -1, 0x3062, &nv40_gr_object }, /* surf2d (nv40) */
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{ -1, -1, 0x3089, &nv40_gr_object }, /* sifm (nv40) */
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{ -1, -1, 0x309e, &nv40_gr_object }, /* swzsurf (nv40) */
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{ -1, -1, 0x4497, &nv40_gr_object }, /* curie */
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{}
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}
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};
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int
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nv44_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
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{
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return nv40_gr_new_(&nv44_gr, device, index, pgr);
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}
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