/* SPDX-License-Identifier: MIT */
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#ifndef __NV40_GR_H__
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#define __NV40_GR_H__
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#define nv40_gr(p) container_of((p), struct nv40_gr, base)
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#include "priv.h"
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struct nv40_gr {
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struct nvkm_gr base;
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u32 size;
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struct list_head chan;
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};
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int nv40_gr_new_(const struct nvkm_gr_func *, struct nvkm_device *, int index,
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struct nvkm_gr **);
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int nv40_gr_init(struct nvkm_gr *);
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void nv40_gr_intr(struct nvkm_gr *);
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u64 nv40_gr_units(struct nvkm_gr *);
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#define nv40_gr_chan(p) container_of((p), struct nv40_gr_chan, object)
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#include <core/object.h>
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struct nv40_gr_chan {
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struct nvkm_object object;
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struct nv40_gr *gr;
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struct nvkm_fifo_chan *fifo;
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u32 inst;
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struct list_head head;
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};
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int nv40_gr_chan_new(struct nvkm_gr *, struct nvkm_fifo_chan *,
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const struct nvkm_oclass *, struct nvkm_object **);
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extern const struct nvkm_object_func nv40_gr_object;
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/* returns 1 if device is one of the nv4x using the 0x4497 object class,
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* helpful to determine a number of other hardware features
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*/
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static inline int
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nv44_gr_class(struct nvkm_device *device)
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{
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if ((device->chipset & 0xf0) == 0x60)
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return 1;
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return !(0x0aaf & (1 << (device->chipset & 0x0f)));
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}
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int nv40_grctx_init(struct nvkm_device *, u32 *size);
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void nv40_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *);
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#endif
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