/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#include "intel_pm.h" /* intel_gpu_freq() */
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#include "selftest_llc.h"
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#include "intel_rps.h"
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static int gen6_verify_ring_freq(struct intel_llc *llc)
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{
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struct drm_i915_private *i915 = llc_to_gt(llc)->i915;
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struct ia_constants consts;
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intel_wakeref_t wakeref;
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unsigned int gpu_freq;
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int err = 0;
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wakeref = intel_runtime_pm_get(llc_to_gt(llc)->uncore->rpm);
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if (!get_ia_constants(llc, &consts))
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goto out_rpm;
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for (gpu_freq = consts.min_gpu_freq;
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gpu_freq <= consts.max_gpu_freq;
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gpu_freq++) {
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struct intel_rps *rps = &llc_to_gt(llc)->rps;
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unsigned int ia_freq, ring_freq, found;
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u32 val;
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calc_ia_freq(llc, gpu_freq, &consts, &ia_freq, &ring_freq);
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val = gpu_freq;
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if (sandybridge_pcode_read(i915,
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GEN6_PCODE_READ_MIN_FREQ_TABLE,
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&val, NULL)) {
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pr_err("Failed to read freq table[%d], range [%d, %d]\n",
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gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq);
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err = -ENXIO;
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break;
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}
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found = (val >> 0) & 0xff;
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if (found != ia_freq) {
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pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected CPU freq, found %d, expected %d\n",
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gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
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intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
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found, ia_freq);
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err = -EINVAL;
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break;
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}
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found = (val >> 8) & 0xff;
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if (found != ring_freq) {
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pr_err("Min freq table(%d/[%d, %d]):%dMHz did not match expected ring freq, found %d, expected %d\n",
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gpu_freq, consts.min_gpu_freq, consts.max_gpu_freq,
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intel_gpu_freq(rps, gpu_freq * (INTEL_GEN(i915) >= 9 ? GEN9_FREQ_SCALER : 1)),
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found, ring_freq);
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err = -EINVAL;
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break;
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}
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}
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out_rpm:
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intel_runtime_pm_put(llc_to_gt(llc)->uncore->rpm, wakeref);
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return err;
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}
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int st_llc_verify(struct intel_llc *llc)
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{
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return gen6_verify_ring_freq(llc);
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}
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