/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef INTEL_RPS_TYPES_H
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#define INTEL_RPS_TYPES_H
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#include <linux/atomic.h>
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#include <linux/ktime.h>
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#include <linux/mutex.h>
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#include <linux/types.h>
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#include <linux/workqueue.h>
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struct intel_ips {
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u64 last_count1;
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unsigned long last_time1;
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unsigned long chipset_power;
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u64 last_count2;
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u64 last_time2;
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unsigned long gfx_power;
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u8 corr;
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int c, m;
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};
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struct intel_rps_ei {
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ktime_t ktime;
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u32 render_c0;
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u32 media_c0;
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};
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enum {
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INTEL_RPS_ENABLED = 0,
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INTEL_RPS_ACTIVE,
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INTEL_RPS_INTERRUPTS,
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INTEL_RPS_TIMER,
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};
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struct intel_rps {
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struct mutex lock; /* protects enabling and the worker */
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/*
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* work, interrupts_enabled and pm_iir are protected by
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* dev_priv->irq_lock
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*/
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struct timer_list timer;
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struct work_struct work;
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unsigned long flags;
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ktime_t pm_timestamp;
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u32 pm_interval;
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u32 pm_iir;
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/* PM interrupt bits that should never be masked */
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u32 pm_intrmsk_mbz;
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u32 pm_events;
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/* Frequencies are stored in potentially platform dependent multiples.
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* In other words, *_freq needs to be multiplied by X to be interesting.
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* Soft limits are those which are used for the dynamic reclocking done
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* by the driver (raise frequencies under heavy loads, and lower for
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* lighter loads). Hard limits are those imposed by the hardware.
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*
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* A distinction is made for overclocking, which is never enabled by
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* default, and is considered to be above the hard limit if it's
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* possible at all.
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*/
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u8 cur_freq; /* Current frequency (cached, may not == HW) */
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u8 last_freq; /* Last SWREQ frequency */
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u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
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u8 max_freq_softlimit; /* Max frequency permitted by the driver */
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u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
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u8 min_freq; /* AKA RPn. Minimum frequency */
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u8 boost_freq; /* Frequency to request when wait boosting */
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u8 idle_freq; /* Frequency to request when we are idle */
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u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
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u8 rp1_freq; /* "less than" RP0 power/freqency */
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u8 rp0_freq; /* Non-overclocked max frequency. */
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u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */
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int last_adj;
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struct {
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struct mutex mutex;
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enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
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unsigned int interactive;
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u8 up_threshold; /* Current %busy required to uplock */
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u8 down_threshold; /* Current %busy required to downclock */
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} power;
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atomic_t num_waiters;
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atomic_t boosts;
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/* manual wa residency calculations */
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struct intel_rps_ei ei;
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struct intel_ips ips;
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};
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#endif /* INTEL_RPS_TYPES_H */
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