/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __SMU_V12_0_H__
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#define __SMU_V12_0_H__
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#include "amdgpu_smu.h"
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/* MP Apertures */
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#define MP0_Public 0x03800000
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#define MP0_SRAM 0x03900000
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#define MP1_Public 0x03b00000
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#define MP1_SRAM 0x03c00004
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#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
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int smu_v12_0_check_fw_status(struct smu_context *smu);
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int smu_v12_0_check_fw_version(struct smu_context *smu);
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int smu_v12_0_powergate_sdma(struct smu_context *smu, bool gate);
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int smu_v12_0_powergate_vcn(struct smu_context *smu, bool gate);
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int smu_v12_0_powergate_jpeg(struct smu_context *smu, bool gate);
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int smu_v12_0_set_gfx_cgpg(struct smu_context *smu, bool enable);
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uint32_t smu_v12_0_get_gfxoff_status(struct smu_context *smu);
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int smu_v12_0_gfx_off_control(struct smu_context *smu, bool enable);
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int smu_v12_0_fini_smc_tables(struct smu_context *smu);
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int smu_v12_0_set_default_dpm_tables(struct smu_context *smu);
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int smu_v12_0_mode2_reset(struct smu_context *smu);
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int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
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uint32_t min, uint32_t max);
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int smu_v12_0_set_driver_table_location(struct smu_context *smu);
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void smu_v12_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics);
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#endif
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#endif
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