/*
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* Copyright (C) 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _mmhub_9_4_1_OFFSET_HEADER
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#define _mmhub_9_4_1_OFFSET_HEADER
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// addressBlock: mmhub_dagb_dagbdec0
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// base address: 0x68000
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#define mmDAGB0_RDCLI0 0x0000
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#define mmDAGB0_RDCLI0_BASE_IDX 1
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#define mmDAGB0_RDCLI1 0x0001
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#define mmDAGB0_RDCLI1_BASE_IDX 1
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#define mmDAGB0_RDCLI2 0x0002
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#define mmDAGB0_RDCLI2_BASE_IDX 1
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#define mmDAGB0_RDCLI3 0x0003
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#define mmDAGB0_RDCLI3_BASE_IDX 1
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#define mmDAGB0_RDCLI4 0x0004
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#define mmDAGB0_RDCLI4_BASE_IDX 1
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#define mmDAGB0_RDCLI5 0x0005
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#define mmDAGB0_RDCLI5_BASE_IDX 1
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#define mmDAGB0_RDCLI6 0x0006
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#define mmDAGB0_RDCLI6_BASE_IDX 1
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#define mmDAGB0_RDCLI7 0x0007
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#define mmDAGB0_RDCLI7_BASE_IDX 1
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#define mmDAGB0_RDCLI8 0x0008
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#define mmDAGB0_RDCLI8_BASE_IDX 1
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#define mmDAGB0_RDCLI9 0x0009
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#define mmDAGB0_RDCLI9_BASE_IDX 1
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#define mmDAGB0_RDCLI10 0x000a
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#define mmDAGB0_RDCLI10_BASE_IDX 1
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#define mmDAGB0_RDCLI11 0x000b
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#define mmDAGB0_RDCLI11_BASE_IDX 1
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#define mmDAGB0_RDCLI12 0x000c
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#define mmDAGB0_RDCLI12_BASE_IDX 1
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#define mmDAGB0_RDCLI13 0x000d
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#define mmDAGB0_RDCLI13_BASE_IDX 1
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#define mmDAGB0_RDCLI14 0x000e
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#define mmDAGB0_RDCLI14_BASE_IDX 1
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#define mmDAGB0_RDCLI15 0x000f
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#define mmDAGB0_RDCLI15_BASE_IDX 1
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#define mmDAGB0_RD_CNTL 0x0010
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#define mmDAGB0_RD_CNTL_BASE_IDX 1
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#define mmDAGB0_RD_GMI_CNTL 0x0011
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#define mmDAGB0_RD_GMI_CNTL_BASE_IDX 1
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#define mmDAGB0_RD_ADDR_DAGB 0x0012
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#define mmDAGB0_RD_ADDR_DAGB_BASE_IDX 1
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#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST 0x0013
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#define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
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#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 0x0014
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#define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
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#define mmDAGB0_RD_CGTT_CLK_CTRL 0x0015
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#define mmDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0016
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#define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL 0x0017
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#define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0018
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#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0019
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#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x001a
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#define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x001b
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#define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB0_RD_VC0_CNTL 0x001c
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#define mmDAGB0_RD_VC0_CNTL_BASE_IDX 1
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#define mmDAGB0_RD_VC1_CNTL 0x001d
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#define mmDAGB0_RD_VC1_CNTL_BASE_IDX 1
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#define mmDAGB0_RD_VC2_CNTL 0x001e
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#define mmDAGB0_RD_VC2_CNTL_BASE_IDX 1
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#define mmDAGB0_RD_VC3_CNTL 0x001f
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#define mmDAGB0_RD_VC3_CNTL_BASE_IDX 1
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#define mmDAGB0_RD_VC4_CNTL 0x0020
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#define mmDAGB0_RD_VC4_CNTL_BASE_IDX 1
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#define mmDAGB0_RD_VC5_CNTL 0x0021
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#define mmDAGB0_RD_VC5_CNTL_BASE_IDX 1
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#define mmDAGB0_RD_VC6_CNTL 0x0022
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#define mmDAGB0_RD_VC6_CNTL_BASE_IDX 1
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#define mmDAGB0_RD_VC7_CNTL 0x0023
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#define mmDAGB0_RD_VC7_CNTL_BASE_IDX 1
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#define mmDAGB0_RD_CNTL_MISC 0x0024
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#define mmDAGB0_RD_CNTL_MISC_BASE_IDX 1
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#define mmDAGB0_RD_TLB_CREDIT 0x0025
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#define mmDAGB0_RD_TLB_CREDIT_BASE_IDX 1
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#define mmDAGB0_RDCLI_ASK_PENDING 0x0026
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#define mmDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1
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#define mmDAGB0_RDCLI_GO_PENDING 0x0027
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#define mmDAGB0_RDCLI_GO_PENDING_BASE_IDX 1
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#define mmDAGB0_RDCLI_GBLSEND_PENDING 0x0028
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#define mmDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1
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#define mmDAGB0_RDCLI_TLB_PENDING 0x0029
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#define mmDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1
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#define mmDAGB0_RDCLI_OARB_PENDING 0x002a
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#define mmDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1
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#define mmDAGB0_RDCLI_OSD_PENDING 0x002b
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#define mmDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1
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#define mmDAGB0_WRCLI0 0x002c
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#define mmDAGB0_WRCLI0_BASE_IDX 1
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#define mmDAGB0_WRCLI1 0x002d
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#define mmDAGB0_WRCLI1_BASE_IDX 1
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#define mmDAGB0_WRCLI2 0x002e
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#define mmDAGB0_WRCLI2_BASE_IDX 1
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#define mmDAGB0_WRCLI3 0x002f
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#define mmDAGB0_WRCLI3_BASE_IDX 1
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#define mmDAGB0_WRCLI4 0x0030
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#define mmDAGB0_WRCLI4_BASE_IDX 1
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#define mmDAGB0_WRCLI5 0x0031
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#define mmDAGB0_WRCLI5_BASE_IDX 1
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#define mmDAGB0_WRCLI6 0x0032
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#define mmDAGB0_WRCLI6_BASE_IDX 1
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#define mmDAGB0_WRCLI7 0x0033
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#define mmDAGB0_WRCLI7_BASE_IDX 1
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#define mmDAGB0_WRCLI8 0x0034
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#define mmDAGB0_WRCLI8_BASE_IDX 1
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#define mmDAGB0_WRCLI9 0x0035
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#define mmDAGB0_WRCLI9_BASE_IDX 1
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#define mmDAGB0_WRCLI10 0x0036
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#define mmDAGB0_WRCLI10_BASE_IDX 1
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#define mmDAGB0_WRCLI11 0x0037
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#define mmDAGB0_WRCLI11_BASE_IDX 1
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#define mmDAGB0_WRCLI12 0x0038
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#define mmDAGB0_WRCLI12_BASE_IDX 1
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#define mmDAGB0_WRCLI13 0x0039
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#define mmDAGB0_WRCLI13_BASE_IDX 1
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#define mmDAGB0_WRCLI14 0x003a
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#define mmDAGB0_WRCLI14_BASE_IDX 1
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#define mmDAGB0_WRCLI15 0x003b
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#define mmDAGB0_WRCLI15_BASE_IDX 1
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#define mmDAGB0_WR_CNTL 0x003c
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#define mmDAGB0_WR_CNTL_BASE_IDX 1
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#define mmDAGB0_WR_GMI_CNTL 0x003d
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#define mmDAGB0_WR_GMI_CNTL_BASE_IDX 1
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#define mmDAGB0_WR_ADDR_DAGB 0x003e
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#define mmDAGB0_WR_ADDR_DAGB_BASE_IDX 1
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#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST 0x003f
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#define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
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#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 0x0040
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#define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
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#define mmDAGB0_WR_CGTT_CLK_CTRL 0x0041
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#define mmDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0042
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#define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL 0x0043
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#define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0044
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#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0045
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#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0046
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#define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x0047
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#define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB0_WR_DATA_DAGB 0x0048
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#define mmDAGB0_WR_DATA_DAGB_BASE_IDX 1
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#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0049
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#define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x004a
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#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1 0x004b
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#define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x004c
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#define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB0_WR_VC0_CNTL 0x004d
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#define mmDAGB0_WR_VC0_CNTL_BASE_IDX 1
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#define mmDAGB0_WR_VC1_CNTL 0x004e
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#define mmDAGB0_WR_VC1_CNTL_BASE_IDX 1
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#define mmDAGB0_WR_VC2_CNTL 0x004f
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#define mmDAGB0_WR_VC2_CNTL_BASE_IDX 1
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#define mmDAGB0_WR_VC3_CNTL 0x0050
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#define mmDAGB0_WR_VC3_CNTL_BASE_IDX 1
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#define mmDAGB0_WR_VC4_CNTL 0x0051
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#define mmDAGB0_WR_VC4_CNTL_BASE_IDX 1
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#define mmDAGB0_WR_VC5_CNTL 0x0052
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#define mmDAGB0_WR_VC5_CNTL_BASE_IDX 1
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#define mmDAGB0_WR_VC6_CNTL 0x0053
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#define mmDAGB0_WR_VC6_CNTL_BASE_IDX 1
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#define mmDAGB0_WR_VC7_CNTL 0x0054
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#define mmDAGB0_WR_VC7_CNTL_BASE_IDX 1
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#define mmDAGB0_WR_CNTL_MISC 0x0055
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#define mmDAGB0_WR_CNTL_MISC_BASE_IDX 1
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#define mmDAGB0_WR_TLB_CREDIT 0x0056
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#define mmDAGB0_WR_TLB_CREDIT_BASE_IDX 1
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#define mmDAGB0_WR_DATA_CREDIT 0x0057
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#define mmDAGB0_WR_DATA_CREDIT_BASE_IDX 1
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#define mmDAGB0_WR_MISC_CREDIT 0x0058
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#define mmDAGB0_WR_MISC_CREDIT_BASE_IDX 1
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#define mmDAGB0_WRCLI_ASK_PENDING 0x005d
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#define mmDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1
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#define mmDAGB0_WRCLI_GO_PENDING 0x005e
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#define mmDAGB0_WRCLI_GO_PENDING_BASE_IDX 1
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#define mmDAGB0_WRCLI_GBLSEND_PENDING 0x005f
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#define mmDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1
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#define mmDAGB0_WRCLI_TLB_PENDING 0x0060
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#define mmDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1
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#define mmDAGB0_WRCLI_OARB_PENDING 0x0061
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#define mmDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1
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#define mmDAGB0_WRCLI_OSD_PENDING 0x0062
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#define mmDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1
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#define mmDAGB0_WRCLI_DBUS_ASK_PENDING 0x0063
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#define mmDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
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#define mmDAGB0_WRCLI_DBUS_GO_PENDING 0x0064
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#define mmDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
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#define mmDAGB0_DAGB_DLY 0x0065
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#define mmDAGB0_DAGB_DLY_BASE_IDX 1
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#define mmDAGB0_CNTL_MISC 0x0066
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#define mmDAGB0_CNTL_MISC_BASE_IDX 1
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#define mmDAGB0_CNTL_MISC2 0x0067
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#define mmDAGB0_CNTL_MISC2_BASE_IDX 1
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#define mmDAGB0_FIFO_EMPTY 0x0068
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#define mmDAGB0_FIFO_EMPTY_BASE_IDX 1
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#define mmDAGB0_FIFO_FULL 0x0069
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#define mmDAGB0_FIFO_FULL_BASE_IDX 1
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#define mmDAGB0_WR_CREDITS_FULL 0x006a
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#define mmDAGB0_WR_CREDITS_FULL_BASE_IDX 1
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#define mmDAGB0_RD_CREDITS_FULL 0x006b
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#define mmDAGB0_RD_CREDITS_FULL_BASE_IDX 1
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#define mmDAGB0_PERFCOUNTER_LO 0x006c
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#define mmDAGB0_PERFCOUNTER_LO_BASE_IDX 1
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#define mmDAGB0_PERFCOUNTER_HI 0x006d
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#define mmDAGB0_PERFCOUNTER_HI_BASE_IDX 1
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#define mmDAGB0_PERFCOUNTER0_CFG 0x006e
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#define mmDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmDAGB0_PERFCOUNTER1_CFG 0x006f
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#define mmDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmDAGB0_PERFCOUNTER2_CFG 0x0070
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#define mmDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1
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#define mmDAGB0_PERFCOUNTER_RSLT_CNTL 0x0071
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#define mmDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmDAGB0_RESERVE0 0x0072
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#define mmDAGB0_RESERVE0_BASE_IDX 1
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#define mmDAGB0_RESERVE1 0x0073
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#define mmDAGB0_RESERVE1_BASE_IDX 1
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#define mmDAGB0_RESERVE2 0x0074
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#define mmDAGB0_RESERVE2_BASE_IDX 1
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#define mmDAGB0_RESERVE3 0x0075
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#define mmDAGB0_RESERVE3_BASE_IDX 1
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#define mmDAGB0_RESERVE4 0x0076
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#define mmDAGB0_RESERVE4_BASE_IDX 1
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#define mmDAGB0_RESERVE5 0x0077
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#define mmDAGB0_RESERVE5_BASE_IDX 1
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#define mmDAGB0_RESERVE6 0x0078
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#define mmDAGB0_RESERVE6_BASE_IDX 1
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#define mmDAGB0_RESERVE7 0x0079
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#define mmDAGB0_RESERVE7_BASE_IDX 1
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#define mmDAGB0_RESERVE8 0x007a
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#define mmDAGB0_RESERVE8_BASE_IDX 1
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#define mmDAGB0_RESERVE9 0x007b
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#define mmDAGB0_RESERVE9_BASE_IDX 1
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#define mmDAGB0_RESERVE10 0x007c
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#define mmDAGB0_RESERVE10_BASE_IDX 1
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#define mmDAGB0_RESERVE11 0x007d
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#define mmDAGB0_RESERVE11_BASE_IDX 1
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#define mmDAGB0_RESERVE12 0x007e
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#define mmDAGB0_RESERVE12_BASE_IDX 1
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#define mmDAGB0_RESERVE13 0x007f
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#define mmDAGB0_RESERVE13_BASE_IDX 1
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// addressBlock: mmhub_dagb_dagbdec1
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// base address: 0x68200
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#define mmDAGB1_RDCLI0 0x0080
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#define mmDAGB1_RDCLI0_BASE_IDX 1
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#define mmDAGB1_RDCLI1 0x0081
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#define mmDAGB1_RDCLI1_BASE_IDX 1
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#define mmDAGB1_RDCLI2 0x0082
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#define mmDAGB1_RDCLI2_BASE_IDX 1
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#define mmDAGB1_RDCLI3 0x0083
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#define mmDAGB1_RDCLI3_BASE_IDX 1
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#define mmDAGB1_RDCLI4 0x0084
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#define mmDAGB1_RDCLI4_BASE_IDX 1
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#define mmDAGB1_RDCLI5 0x0085
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#define mmDAGB1_RDCLI5_BASE_IDX 1
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#define mmDAGB1_RDCLI6 0x0086
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#define mmDAGB1_RDCLI6_BASE_IDX 1
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#define mmDAGB1_RDCLI7 0x0087
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#define mmDAGB1_RDCLI7_BASE_IDX 1
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#define mmDAGB1_RDCLI8 0x0088
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#define mmDAGB1_RDCLI8_BASE_IDX 1
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#define mmDAGB1_RDCLI9 0x0089
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#define mmDAGB1_RDCLI9_BASE_IDX 1
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#define mmDAGB1_RDCLI10 0x008a
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#define mmDAGB1_RDCLI10_BASE_IDX 1
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#define mmDAGB1_RDCLI11 0x008b
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#define mmDAGB1_RDCLI11_BASE_IDX 1
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#define mmDAGB1_RDCLI12 0x008c
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#define mmDAGB1_RDCLI12_BASE_IDX 1
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#define mmDAGB1_RDCLI13 0x008d
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#define mmDAGB1_RDCLI13_BASE_IDX 1
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#define mmDAGB1_RDCLI14 0x008e
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#define mmDAGB1_RDCLI14_BASE_IDX 1
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#define mmDAGB1_RDCLI15 0x008f
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#define mmDAGB1_RDCLI15_BASE_IDX 1
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#define mmDAGB1_RD_CNTL 0x0090
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#define mmDAGB1_RD_CNTL_BASE_IDX 1
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#define mmDAGB1_RD_GMI_CNTL 0x0091
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#define mmDAGB1_RD_GMI_CNTL_BASE_IDX 1
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#define mmDAGB1_RD_ADDR_DAGB 0x0092
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#define mmDAGB1_RD_ADDR_DAGB_BASE_IDX 1
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#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST 0x0093
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#define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
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#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 0x0094
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#define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
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#define mmDAGB1_RD_CGTT_CLK_CTRL 0x0095
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#define mmDAGB1_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL 0x0096
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#define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL 0x0097
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#define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0 0x0098
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#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0 0x0099
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#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1 0x009a
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#define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1 0x009b
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#define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB1_RD_VC0_CNTL 0x009c
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#define mmDAGB1_RD_VC0_CNTL_BASE_IDX 1
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#define mmDAGB1_RD_VC1_CNTL 0x009d
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#define mmDAGB1_RD_VC1_CNTL_BASE_IDX 1
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#define mmDAGB1_RD_VC2_CNTL 0x009e
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#define mmDAGB1_RD_VC2_CNTL_BASE_IDX 1
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#define mmDAGB1_RD_VC3_CNTL 0x009f
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#define mmDAGB1_RD_VC3_CNTL_BASE_IDX 1
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#define mmDAGB1_RD_VC4_CNTL 0x00a0
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#define mmDAGB1_RD_VC4_CNTL_BASE_IDX 1
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#define mmDAGB1_RD_VC5_CNTL 0x00a1
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#define mmDAGB1_RD_VC5_CNTL_BASE_IDX 1
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#define mmDAGB1_RD_VC6_CNTL 0x00a2
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#define mmDAGB1_RD_VC6_CNTL_BASE_IDX 1
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#define mmDAGB1_RD_VC7_CNTL 0x00a3
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#define mmDAGB1_RD_VC7_CNTL_BASE_IDX 1
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#define mmDAGB1_RD_CNTL_MISC 0x00a4
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#define mmDAGB1_RD_CNTL_MISC_BASE_IDX 1
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#define mmDAGB1_RD_TLB_CREDIT 0x00a5
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#define mmDAGB1_RD_TLB_CREDIT_BASE_IDX 1
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#define mmDAGB1_RDCLI_ASK_PENDING 0x00a6
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#define mmDAGB1_RDCLI_ASK_PENDING_BASE_IDX 1
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#define mmDAGB1_RDCLI_GO_PENDING 0x00a7
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#define mmDAGB1_RDCLI_GO_PENDING_BASE_IDX 1
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#define mmDAGB1_RDCLI_GBLSEND_PENDING 0x00a8
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#define mmDAGB1_RDCLI_GBLSEND_PENDING_BASE_IDX 1
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#define mmDAGB1_RDCLI_TLB_PENDING 0x00a9
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#define mmDAGB1_RDCLI_TLB_PENDING_BASE_IDX 1
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#define mmDAGB1_RDCLI_OARB_PENDING 0x00aa
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#define mmDAGB1_RDCLI_OARB_PENDING_BASE_IDX 1
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#define mmDAGB1_RDCLI_OSD_PENDING 0x00ab
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#define mmDAGB1_RDCLI_OSD_PENDING_BASE_IDX 1
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#define mmDAGB1_WRCLI0 0x00ac
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#define mmDAGB1_WRCLI0_BASE_IDX 1
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#define mmDAGB1_WRCLI1 0x00ad
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#define mmDAGB1_WRCLI1_BASE_IDX 1
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#define mmDAGB1_WRCLI2 0x00ae
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#define mmDAGB1_WRCLI2_BASE_IDX 1
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#define mmDAGB1_WRCLI3 0x00af
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#define mmDAGB1_WRCLI3_BASE_IDX 1
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#define mmDAGB1_WRCLI4 0x00b0
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#define mmDAGB1_WRCLI4_BASE_IDX 1
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#define mmDAGB1_WRCLI5 0x00b1
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#define mmDAGB1_WRCLI5_BASE_IDX 1
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#define mmDAGB1_WRCLI6 0x00b2
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#define mmDAGB1_WRCLI6_BASE_IDX 1
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#define mmDAGB1_WRCLI7 0x00b3
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#define mmDAGB1_WRCLI7_BASE_IDX 1
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#define mmDAGB1_WRCLI8 0x00b4
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#define mmDAGB1_WRCLI8_BASE_IDX 1
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#define mmDAGB1_WRCLI9 0x00b5
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#define mmDAGB1_WRCLI9_BASE_IDX 1
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#define mmDAGB1_WRCLI10 0x00b6
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#define mmDAGB1_WRCLI10_BASE_IDX 1
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#define mmDAGB1_WRCLI11 0x00b7
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#define mmDAGB1_WRCLI11_BASE_IDX 1
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#define mmDAGB1_WRCLI12 0x00b8
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#define mmDAGB1_WRCLI12_BASE_IDX 1
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#define mmDAGB1_WRCLI13 0x00b9
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#define mmDAGB1_WRCLI13_BASE_IDX 1
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#define mmDAGB1_WRCLI14 0x00ba
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#define mmDAGB1_WRCLI14_BASE_IDX 1
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#define mmDAGB1_WRCLI15 0x00bb
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#define mmDAGB1_WRCLI15_BASE_IDX 1
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#define mmDAGB1_WR_CNTL 0x00bc
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#define mmDAGB1_WR_CNTL_BASE_IDX 1
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#define mmDAGB1_WR_GMI_CNTL 0x00bd
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#define mmDAGB1_WR_GMI_CNTL_BASE_IDX 1
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#define mmDAGB1_WR_ADDR_DAGB 0x00be
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#define mmDAGB1_WR_ADDR_DAGB_BASE_IDX 1
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#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST 0x00bf
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#define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
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#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 0x00c0
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#define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
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#define mmDAGB1_WR_CGTT_CLK_CTRL 0x00c1
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#define mmDAGB1_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL 0x00c2
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#define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL 0x00c3
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#define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0 0x00c4
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#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0 0x00c5
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#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1 0x00c6
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#define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1 0x00c7
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#define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB1_WR_DATA_DAGB 0x00c8
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#define mmDAGB1_WR_DATA_DAGB_BASE_IDX 1
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#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0 0x00c9
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#define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0 0x00ca
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#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1 0x00cb
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#define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1 0x00cc
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#define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB1_WR_VC0_CNTL 0x00cd
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#define mmDAGB1_WR_VC0_CNTL_BASE_IDX 1
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#define mmDAGB1_WR_VC1_CNTL 0x00ce
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#define mmDAGB1_WR_VC1_CNTL_BASE_IDX 1
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#define mmDAGB1_WR_VC2_CNTL 0x00cf
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#define mmDAGB1_WR_VC2_CNTL_BASE_IDX 1
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#define mmDAGB1_WR_VC3_CNTL 0x00d0
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#define mmDAGB1_WR_VC3_CNTL_BASE_IDX 1
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#define mmDAGB1_WR_VC4_CNTL 0x00d1
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#define mmDAGB1_WR_VC4_CNTL_BASE_IDX 1
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#define mmDAGB1_WR_VC5_CNTL 0x00d2
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#define mmDAGB1_WR_VC5_CNTL_BASE_IDX 1
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#define mmDAGB1_WR_VC6_CNTL 0x00d3
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#define mmDAGB1_WR_VC6_CNTL_BASE_IDX 1
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#define mmDAGB1_WR_VC7_CNTL 0x00d4
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#define mmDAGB1_WR_VC7_CNTL_BASE_IDX 1
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#define mmDAGB1_WR_CNTL_MISC 0x00d5
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#define mmDAGB1_WR_CNTL_MISC_BASE_IDX 1
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#define mmDAGB1_WR_TLB_CREDIT 0x00d6
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#define mmDAGB1_WR_TLB_CREDIT_BASE_IDX 1
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#define mmDAGB1_WR_DATA_CREDIT 0x00d7
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#define mmDAGB1_WR_DATA_CREDIT_BASE_IDX 1
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#define mmDAGB1_WR_MISC_CREDIT 0x00d8
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#define mmDAGB1_WR_MISC_CREDIT_BASE_IDX 1
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#define mmDAGB1_WRCLI_ASK_PENDING 0x00dd
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#define mmDAGB1_WRCLI_ASK_PENDING_BASE_IDX 1
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#define mmDAGB1_WRCLI_GO_PENDING 0x00de
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#define mmDAGB1_WRCLI_GO_PENDING_BASE_IDX 1
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#define mmDAGB1_WRCLI_GBLSEND_PENDING 0x00df
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#define mmDAGB1_WRCLI_GBLSEND_PENDING_BASE_IDX 1
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#define mmDAGB1_WRCLI_TLB_PENDING 0x00e0
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#define mmDAGB1_WRCLI_TLB_PENDING_BASE_IDX 1
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#define mmDAGB1_WRCLI_OARB_PENDING 0x00e1
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#define mmDAGB1_WRCLI_OARB_PENDING_BASE_IDX 1
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#define mmDAGB1_WRCLI_OSD_PENDING 0x00e2
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#define mmDAGB1_WRCLI_OSD_PENDING_BASE_IDX 1
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#define mmDAGB1_WRCLI_DBUS_ASK_PENDING 0x00e3
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#define mmDAGB1_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
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#define mmDAGB1_WRCLI_DBUS_GO_PENDING 0x00e4
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#define mmDAGB1_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
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#define mmDAGB1_DAGB_DLY 0x00e5
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#define mmDAGB1_DAGB_DLY_BASE_IDX 1
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#define mmDAGB1_CNTL_MISC 0x00e6
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#define mmDAGB1_CNTL_MISC_BASE_IDX 1
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#define mmDAGB1_CNTL_MISC2 0x00e7
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#define mmDAGB1_CNTL_MISC2_BASE_IDX 1
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#define mmDAGB1_FIFO_EMPTY 0x00e8
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#define mmDAGB1_FIFO_EMPTY_BASE_IDX 1
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#define mmDAGB1_FIFO_FULL 0x00e9
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#define mmDAGB1_FIFO_FULL_BASE_IDX 1
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#define mmDAGB1_WR_CREDITS_FULL 0x00ea
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#define mmDAGB1_WR_CREDITS_FULL_BASE_IDX 1
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#define mmDAGB1_RD_CREDITS_FULL 0x00eb
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#define mmDAGB1_RD_CREDITS_FULL_BASE_IDX 1
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#define mmDAGB1_PERFCOUNTER_LO 0x00ec
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#define mmDAGB1_PERFCOUNTER_LO_BASE_IDX 1
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#define mmDAGB1_PERFCOUNTER_HI 0x00ed
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#define mmDAGB1_PERFCOUNTER_HI_BASE_IDX 1
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#define mmDAGB1_PERFCOUNTER0_CFG 0x00ee
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#define mmDAGB1_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmDAGB1_PERFCOUNTER1_CFG 0x00ef
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#define mmDAGB1_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmDAGB1_PERFCOUNTER2_CFG 0x00f0
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#define mmDAGB1_PERFCOUNTER2_CFG_BASE_IDX 1
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#define mmDAGB1_PERFCOUNTER_RSLT_CNTL 0x00f1
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#define mmDAGB1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmDAGB1_RESERVE0 0x00f2
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#define mmDAGB1_RESERVE0_BASE_IDX 1
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#define mmDAGB1_RESERVE1 0x00f3
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#define mmDAGB1_RESERVE1_BASE_IDX 1
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#define mmDAGB1_RESERVE2 0x00f4
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#define mmDAGB1_RESERVE2_BASE_IDX 1
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#define mmDAGB1_RESERVE3 0x00f5
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#define mmDAGB1_RESERVE3_BASE_IDX 1
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#define mmDAGB1_RESERVE4 0x00f6
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#define mmDAGB1_RESERVE4_BASE_IDX 1
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#define mmDAGB1_RESERVE5 0x00f7
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#define mmDAGB1_RESERVE5_BASE_IDX 1
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#define mmDAGB1_RESERVE6 0x00f8
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#define mmDAGB1_RESERVE6_BASE_IDX 1
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#define mmDAGB1_RESERVE7 0x00f9
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#define mmDAGB1_RESERVE7_BASE_IDX 1
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#define mmDAGB1_RESERVE8 0x00fa
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#define mmDAGB1_RESERVE8_BASE_IDX 1
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#define mmDAGB1_RESERVE9 0x00fb
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#define mmDAGB1_RESERVE9_BASE_IDX 1
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#define mmDAGB1_RESERVE10 0x00fc
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#define mmDAGB1_RESERVE10_BASE_IDX 1
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#define mmDAGB1_RESERVE11 0x00fd
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#define mmDAGB1_RESERVE11_BASE_IDX 1
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#define mmDAGB1_RESERVE12 0x00fe
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#define mmDAGB1_RESERVE12_BASE_IDX 1
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#define mmDAGB1_RESERVE13 0x00ff
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#define mmDAGB1_RESERVE13_BASE_IDX 1
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// addressBlock: mmhub_dagb_dagbdec2
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// base address: 0x68400
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#define mmDAGB2_RDCLI0 0x0100
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#define mmDAGB2_RDCLI0_BASE_IDX 1
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#define mmDAGB2_RDCLI1 0x0101
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#define mmDAGB2_RDCLI1_BASE_IDX 1
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#define mmDAGB2_RDCLI2 0x0102
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#define mmDAGB2_RDCLI2_BASE_IDX 1
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#define mmDAGB2_RDCLI3 0x0103
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#define mmDAGB2_RDCLI3_BASE_IDX 1
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#define mmDAGB2_RDCLI4 0x0104
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#define mmDAGB2_RDCLI4_BASE_IDX 1
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#define mmDAGB2_RDCLI5 0x0105
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#define mmDAGB2_RDCLI5_BASE_IDX 1
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#define mmDAGB2_RDCLI6 0x0106
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#define mmDAGB2_RDCLI6_BASE_IDX 1
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#define mmDAGB2_RDCLI7 0x0107
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#define mmDAGB2_RDCLI7_BASE_IDX 1
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#define mmDAGB2_RDCLI8 0x0108
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#define mmDAGB2_RDCLI8_BASE_IDX 1
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#define mmDAGB2_RDCLI9 0x0109
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#define mmDAGB2_RDCLI9_BASE_IDX 1
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#define mmDAGB2_RDCLI10 0x010a
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#define mmDAGB2_RDCLI10_BASE_IDX 1
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#define mmDAGB2_RDCLI11 0x010b
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#define mmDAGB2_RDCLI11_BASE_IDX 1
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#define mmDAGB2_RDCLI12 0x010c
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#define mmDAGB2_RDCLI12_BASE_IDX 1
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#define mmDAGB2_RDCLI13 0x010d
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#define mmDAGB2_RDCLI13_BASE_IDX 1
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#define mmDAGB2_RDCLI14 0x010e
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#define mmDAGB2_RDCLI14_BASE_IDX 1
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#define mmDAGB2_RDCLI15 0x010f
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#define mmDAGB2_RDCLI15_BASE_IDX 1
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#define mmDAGB2_RD_CNTL 0x0110
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#define mmDAGB2_RD_CNTL_BASE_IDX 1
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#define mmDAGB2_RD_GMI_CNTL 0x0111
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#define mmDAGB2_RD_GMI_CNTL_BASE_IDX 1
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#define mmDAGB2_RD_ADDR_DAGB 0x0112
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#define mmDAGB2_RD_ADDR_DAGB_BASE_IDX 1
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#define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST 0x0113
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#define mmDAGB2_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
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#define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 0x0114
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#define mmDAGB2_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
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#define mmDAGB2_RD_CGTT_CLK_CTRL 0x0115
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#define mmDAGB2_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL 0x0116
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#define mmDAGB2_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL 0x0117
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#define mmDAGB2_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0 0x0118
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#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0 0x0119
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#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1 0x011a
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#define mmDAGB2_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1 0x011b
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#define mmDAGB2_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB2_RD_VC0_CNTL 0x011c
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#define mmDAGB2_RD_VC0_CNTL_BASE_IDX 1
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#define mmDAGB2_RD_VC1_CNTL 0x011d
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#define mmDAGB2_RD_VC1_CNTL_BASE_IDX 1
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#define mmDAGB2_RD_VC2_CNTL 0x011e
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#define mmDAGB2_RD_VC2_CNTL_BASE_IDX 1
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#define mmDAGB2_RD_VC3_CNTL 0x011f
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#define mmDAGB2_RD_VC3_CNTL_BASE_IDX 1
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#define mmDAGB2_RD_VC4_CNTL 0x0120
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#define mmDAGB2_RD_VC4_CNTL_BASE_IDX 1
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#define mmDAGB2_RD_VC5_CNTL 0x0121
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#define mmDAGB2_RD_VC5_CNTL_BASE_IDX 1
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#define mmDAGB2_RD_VC6_CNTL 0x0122
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#define mmDAGB2_RD_VC6_CNTL_BASE_IDX 1
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#define mmDAGB2_RD_VC7_CNTL 0x0123
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#define mmDAGB2_RD_VC7_CNTL_BASE_IDX 1
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#define mmDAGB2_RD_CNTL_MISC 0x0124
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#define mmDAGB2_RD_CNTL_MISC_BASE_IDX 1
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#define mmDAGB2_RD_TLB_CREDIT 0x0125
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#define mmDAGB2_RD_TLB_CREDIT_BASE_IDX 1
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#define mmDAGB2_RDCLI_ASK_PENDING 0x0126
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#define mmDAGB2_RDCLI_ASK_PENDING_BASE_IDX 1
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#define mmDAGB2_RDCLI_GO_PENDING 0x0127
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#define mmDAGB2_RDCLI_GO_PENDING_BASE_IDX 1
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#define mmDAGB2_RDCLI_GBLSEND_PENDING 0x0128
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#define mmDAGB2_RDCLI_GBLSEND_PENDING_BASE_IDX 1
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#define mmDAGB2_RDCLI_TLB_PENDING 0x0129
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#define mmDAGB2_RDCLI_TLB_PENDING_BASE_IDX 1
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#define mmDAGB2_RDCLI_OARB_PENDING 0x012a
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#define mmDAGB2_RDCLI_OARB_PENDING_BASE_IDX 1
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#define mmDAGB2_RDCLI_OSD_PENDING 0x012b
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#define mmDAGB2_RDCLI_OSD_PENDING_BASE_IDX 1
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#define mmDAGB2_WRCLI0 0x012c
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#define mmDAGB2_WRCLI0_BASE_IDX 1
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#define mmDAGB2_WRCLI1 0x012d
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#define mmDAGB2_WRCLI1_BASE_IDX 1
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#define mmDAGB2_WRCLI2 0x012e
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#define mmDAGB2_WRCLI2_BASE_IDX 1
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#define mmDAGB2_WRCLI3 0x012f
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#define mmDAGB2_WRCLI3_BASE_IDX 1
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#define mmDAGB2_WRCLI4 0x0130
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#define mmDAGB2_WRCLI4_BASE_IDX 1
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#define mmDAGB2_WRCLI5 0x0131
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#define mmDAGB2_WRCLI5_BASE_IDX 1
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#define mmDAGB2_WRCLI6 0x0132
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#define mmDAGB2_WRCLI6_BASE_IDX 1
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#define mmDAGB2_WRCLI7 0x0133
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#define mmDAGB2_WRCLI7_BASE_IDX 1
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#define mmDAGB2_WRCLI8 0x0134
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#define mmDAGB2_WRCLI8_BASE_IDX 1
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#define mmDAGB2_WRCLI9 0x0135
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#define mmDAGB2_WRCLI9_BASE_IDX 1
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#define mmDAGB2_WRCLI10 0x0136
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#define mmDAGB2_WRCLI10_BASE_IDX 1
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#define mmDAGB2_WRCLI11 0x0137
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#define mmDAGB2_WRCLI11_BASE_IDX 1
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#define mmDAGB2_WRCLI12 0x0138
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#define mmDAGB2_WRCLI12_BASE_IDX 1
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#define mmDAGB2_WRCLI13 0x0139
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#define mmDAGB2_WRCLI13_BASE_IDX 1
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#define mmDAGB2_WRCLI14 0x013a
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#define mmDAGB2_WRCLI14_BASE_IDX 1
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#define mmDAGB2_WRCLI15 0x013b
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#define mmDAGB2_WRCLI15_BASE_IDX 1
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#define mmDAGB2_WR_CNTL 0x013c
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#define mmDAGB2_WR_CNTL_BASE_IDX 1
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#define mmDAGB2_WR_GMI_CNTL 0x013d
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#define mmDAGB2_WR_GMI_CNTL_BASE_IDX 1
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#define mmDAGB2_WR_ADDR_DAGB 0x013e
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#define mmDAGB2_WR_ADDR_DAGB_BASE_IDX 1
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#define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST 0x013f
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#define mmDAGB2_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
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#define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 0x0140
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#define mmDAGB2_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
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#define mmDAGB2_WR_CGTT_CLK_CTRL 0x0141
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#define mmDAGB2_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL 0x0142
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#define mmDAGB2_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL 0x0143
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#define mmDAGB2_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0 0x0144
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#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0 0x0145
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#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1 0x0146
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#define mmDAGB2_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1 0x0147
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#define mmDAGB2_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB2_WR_DATA_DAGB 0x0148
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#define mmDAGB2_WR_DATA_DAGB_BASE_IDX 1
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#define mmDAGB2_WR_DATA_DAGB_MAX_BURST0 0x0149
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#define mmDAGB2_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0 0x014a
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#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB2_WR_DATA_DAGB_MAX_BURST1 0x014b
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#define mmDAGB2_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1 0x014c
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#define mmDAGB2_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB2_WR_VC0_CNTL 0x014d
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#define mmDAGB2_WR_VC0_CNTL_BASE_IDX 1
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#define mmDAGB2_WR_VC1_CNTL 0x014e
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#define mmDAGB2_WR_VC1_CNTL_BASE_IDX 1
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#define mmDAGB2_WR_VC2_CNTL 0x014f
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#define mmDAGB2_WR_VC2_CNTL_BASE_IDX 1
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#define mmDAGB2_WR_VC3_CNTL 0x0150
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#define mmDAGB2_WR_VC3_CNTL_BASE_IDX 1
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#define mmDAGB2_WR_VC4_CNTL 0x0151
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#define mmDAGB2_WR_VC4_CNTL_BASE_IDX 1
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#define mmDAGB2_WR_VC5_CNTL 0x0152
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#define mmDAGB2_WR_VC5_CNTL_BASE_IDX 1
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#define mmDAGB2_WR_VC6_CNTL 0x0153
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#define mmDAGB2_WR_VC6_CNTL_BASE_IDX 1
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#define mmDAGB2_WR_VC7_CNTL 0x0154
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#define mmDAGB2_WR_VC7_CNTL_BASE_IDX 1
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#define mmDAGB2_WR_CNTL_MISC 0x0155
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#define mmDAGB2_WR_CNTL_MISC_BASE_IDX 1
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#define mmDAGB2_WR_TLB_CREDIT 0x0156
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#define mmDAGB2_WR_TLB_CREDIT_BASE_IDX 1
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#define mmDAGB2_WR_DATA_CREDIT 0x0157
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#define mmDAGB2_WR_DATA_CREDIT_BASE_IDX 1
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#define mmDAGB2_WR_MISC_CREDIT 0x0158
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#define mmDAGB2_WR_MISC_CREDIT_BASE_IDX 1
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#define mmDAGB2_WRCLI_ASK_PENDING 0x015d
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#define mmDAGB2_WRCLI_ASK_PENDING_BASE_IDX 1
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#define mmDAGB2_WRCLI_GO_PENDING 0x015e
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#define mmDAGB2_WRCLI_GO_PENDING_BASE_IDX 1
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#define mmDAGB2_WRCLI_GBLSEND_PENDING 0x015f
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#define mmDAGB2_WRCLI_GBLSEND_PENDING_BASE_IDX 1
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#define mmDAGB2_WRCLI_TLB_PENDING 0x0160
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#define mmDAGB2_WRCLI_TLB_PENDING_BASE_IDX 1
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#define mmDAGB2_WRCLI_OARB_PENDING 0x0161
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#define mmDAGB2_WRCLI_OARB_PENDING_BASE_IDX 1
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#define mmDAGB2_WRCLI_OSD_PENDING 0x0162
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#define mmDAGB2_WRCLI_OSD_PENDING_BASE_IDX 1
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#define mmDAGB2_WRCLI_DBUS_ASK_PENDING 0x0163
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#define mmDAGB2_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
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#define mmDAGB2_WRCLI_DBUS_GO_PENDING 0x0164
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#define mmDAGB2_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
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#define mmDAGB2_DAGB_DLY 0x0165
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#define mmDAGB2_DAGB_DLY_BASE_IDX 1
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#define mmDAGB2_CNTL_MISC 0x0166
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#define mmDAGB2_CNTL_MISC_BASE_IDX 1
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#define mmDAGB2_CNTL_MISC2 0x0167
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#define mmDAGB2_CNTL_MISC2_BASE_IDX 1
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#define mmDAGB2_FIFO_EMPTY 0x0168
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#define mmDAGB2_FIFO_EMPTY_BASE_IDX 1
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#define mmDAGB2_FIFO_FULL 0x0169
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#define mmDAGB2_FIFO_FULL_BASE_IDX 1
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#define mmDAGB2_WR_CREDITS_FULL 0x016a
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#define mmDAGB2_WR_CREDITS_FULL_BASE_IDX 1
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#define mmDAGB2_RD_CREDITS_FULL 0x016b
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#define mmDAGB2_RD_CREDITS_FULL_BASE_IDX 1
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#define mmDAGB2_PERFCOUNTER_LO 0x016c
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#define mmDAGB2_PERFCOUNTER_LO_BASE_IDX 1
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#define mmDAGB2_PERFCOUNTER_HI 0x016d
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#define mmDAGB2_PERFCOUNTER_HI_BASE_IDX 1
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#define mmDAGB2_PERFCOUNTER0_CFG 0x016e
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#define mmDAGB2_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmDAGB2_PERFCOUNTER1_CFG 0x016f
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#define mmDAGB2_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmDAGB2_PERFCOUNTER2_CFG 0x0170
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#define mmDAGB2_PERFCOUNTER2_CFG_BASE_IDX 1
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#define mmDAGB2_PERFCOUNTER_RSLT_CNTL 0x0171
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#define mmDAGB2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmDAGB2_RESERVE0 0x0172
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#define mmDAGB2_RESERVE0_BASE_IDX 1
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#define mmDAGB2_RESERVE1 0x0173
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#define mmDAGB2_RESERVE1_BASE_IDX 1
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#define mmDAGB2_RESERVE2 0x0174
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#define mmDAGB2_RESERVE2_BASE_IDX 1
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#define mmDAGB2_RESERVE3 0x0175
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#define mmDAGB2_RESERVE3_BASE_IDX 1
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#define mmDAGB2_RESERVE4 0x0176
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#define mmDAGB2_RESERVE4_BASE_IDX 1
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#define mmDAGB2_RESERVE5 0x0177
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#define mmDAGB2_RESERVE5_BASE_IDX 1
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#define mmDAGB2_RESERVE6 0x0178
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#define mmDAGB2_RESERVE6_BASE_IDX 1
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#define mmDAGB2_RESERVE7 0x0179
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#define mmDAGB2_RESERVE7_BASE_IDX 1
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#define mmDAGB2_RESERVE8 0x017a
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#define mmDAGB2_RESERVE8_BASE_IDX 1
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#define mmDAGB2_RESERVE9 0x017b
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#define mmDAGB2_RESERVE9_BASE_IDX 1
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#define mmDAGB2_RESERVE10 0x017c
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#define mmDAGB2_RESERVE10_BASE_IDX 1
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#define mmDAGB2_RESERVE11 0x017d
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#define mmDAGB2_RESERVE11_BASE_IDX 1
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#define mmDAGB2_RESERVE12 0x017e
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#define mmDAGB2_RESERVE12_BASE_IDX 1
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#define mmDAGB2_RESERVE13 0x017f
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#define mmDAGB2_RESERVE13_BASE_IDX 1
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|
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// addressBlock: mmhub_dagb_dagbdec3
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// base address: 0x68600
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#define mmDAGB3_RDCLI0 0x0180
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#define mmDAGB3_RDCLI0_BASE_IDX 1
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#define mmDAGB3_RDCLI1 0x0181
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#define mmDAGB3_RDCLI1_BASE_IDX 1
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#define mmDAGB3_RDCLI2 0x0182
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#define mmDAGB3_RDCLI2_BASE_IDX 1
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#define mmDAGB3_RDCLI3 0x0183
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#define mmDAGB3_RDCLI3_BASE_IDX 1
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#define mmDAGB3_RDCLI4 0x0184
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#define mmDAGB3_RDCLI4_BASE_IDX 1
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#define mmDAGB3_RDCLI5 0x0185
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#define mmDAGB3_RDCLI5_BASE_IDX 1
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#define mmDAGB3_RDCLI6 0x0186
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#define mmDAGB3_RDCLI6_BASE_IDX 1
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#define mmDAGB3_RDCLI7 0x0187
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#define mmDAGB3_RDCLI7_BASE_IDX 1
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#define mmDAGB3_RDCLI8 0x0188
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#define mmDAGB3_RDCLI8_BASE_IDX 1
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#define mmDAGB3_RDCLI9 0x0189
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#define mmDAGB3_RDCLI9_BASE_IDX 1
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#define mmDAGB3_RDCLI10 0x018a
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#define mmDAGB3_RDCLI10_BASE_IDX 1
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#define mmDAGB3_RDCLI11 0x018b
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#define mmDAGB3_RDCLI11_BASE_IDX 1
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#define mmDAGB3_RDCLI12 0x018c
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#define mmDAGB3_RDCLI12_BASE_IDX 1
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#define mmDAGB3_RDCLI13 0x018d
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#define mmDAGB3_RDCLI13_BASE_IDX 1
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#define mmDAGB3_RDCLI14 0x018e
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#define mmDAGB3_RDCLI14_BASE_IDX 1
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#define mmDAGB3_RDCLI15 0x018f
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#define mmDAGB3_RDCLI15_BASE_IDX 1
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#define mmDAGB3_RD_CNTL 0x0190
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#define mmDAGB3_RD_CNTL_BASE_IDX 1
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#define mmDAGB3_RD_GMI_CNTL 0x0191
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#define mmDAGB3_RD_GMI_CNTL_BASE_IDX 1
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#define mmDAGB3_RD_ADDR_DAGB 0x0192
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#define mmDAGB3_RD_ADDR_DAGB_BASE_IDX 1
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#define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST 0x0193
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#define mmDAGB3_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
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#define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 0x0194
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#define mmDAGB3_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
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#define mmDAGB3_RD_CGTT_CLK_CTRL 0x0195
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#define mmDAGB3_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL 0x0196
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#define mmDAGB3_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL 0x0197
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#define mmDAGB3_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0 0x0198
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#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0 0x0199
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#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1 0x019a
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#define mmDAGB3_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1 0x019b
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#define mmDAGB3_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB3_RD_VC0_CNTL 0x019c
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#define mmDAGB3_RD_VC0_CNTL_BASE_IDX 1
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#define mmDAGB3_RD_VC1_CNTL 0x019d
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#define mmDAGB3_RD_VC1_CNTL_BASE_IDX 1
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#define mmDAGB3_RD_VC2_CNTL 0x019e
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#define mmDAGB3_RD_VC2_CNTL_BASE_IDX 1
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#define mmDAGB3_RD_VC3_CNTL 0x019f
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#define mmDAGB3_RD_VC3_CNTL_BASE_IDX 1
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#define mmDAGB3_RD_VC4_CNTL 0x01a0
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#define mmDAGB3_RD_VC4_CNTL_BASE_IDX 1
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#define mmDAGB3_RD_VC5_CNTL 0x01a1
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#define mmDAGB3_RD_VC5_CNTL_BASE_IDX 1
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#define mmDAGB3_RD_VC6_CNTL 0x01a2
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#define mmDAGB3_RD_VC6_CNTL_BASE_IDX 1
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#define mmDAGB3_RD_VC7_CNTL 0x01a3
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#define mmDAGB3_RD_VC7_CNTL_BASE_IDX 1
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#define mmDAGB3_RD_CNTL_MISC 0x01a4
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#define mmDAGB3_RD_CNTL_MISC_BASE_IDX 1
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#define mmDAGB3_RD_TLB_CREDIT 0x01a5
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#define mmDAGB3_RD_TLB_CREDIT_BASE_IDX 1
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#define mmDAGB3_RDCLI_ASK_PENDING 0x01a6
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#define mmDAGB3_RDCLI_ASK_PENDING_BASE_IDX 1
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#define mmDAGB3_RDCLI_GO_PENDING 0x01a7
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#define mmDAGB3_RDCLI_GO_PENDING_BASE_IDX 1
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#define mmDAGB3_RDCLI_GBLSEND_PENDING 0x01a8
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#define mmDAGB3_RDCLI_GBLSEND_PENDING_BASE_IDX 1
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#define mmDAGB3_RDCLI_TLB_PENDING 0x01a9
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#define mmDAGB3_RDCLI_TLB_PENDING_BASE_IDX 1
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#define mmDAGB3_RDCLI_OARB_PENDING 0x01aa
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#define mmDAGB3_RDCLI_OARB_PENDING_BASE_IDX 1
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#define mmDAGB3_RDCLI_OSD_PENDING 0x01ab
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#define mmDAGB3_RDCLI_OSD_PENDING_BASE_IDX 1
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#define mmDAGB3_WRCLI0 0x01ac
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#define mmDAGB3_WRCLI0_BASE_IDX 1
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#define mmDAGB3_WRCLI1 0x01ad
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#define mmDAGB3_WRCLI1_BASE_IDX 1
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#define mmDAGB3_WRCLI2 0x01ae
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#define mmDAGB3_WRCLI2_BASE_IDX 1
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#define mmDAGB3_WRCLI3 0x01af
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#define mmDAGB3_WRCLI3_BASE_IDX 1
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#define mmDAGB3_WRCLI4 0x01b0
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#define mmDAGB3_WRCLI4_BASE_IDX 1
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#define mmDAGB3_WRCLI5 0x01b1
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#define mmDAGB3_WRCLI5_BASE_IDX 1
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#define mmDAGB3_WRCLI6 0x01b2
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#define mmDAGB3_WRCLI6_BASE_IDX 1
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#define mmDAGB3_WRCLI7 0x01b3
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#define mmDAGB3_WRCLI7_BASE_IDX 1
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#define mmDAGB3_WRCLI8 0x01b4
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#define mmDAGB3_WRCLI8_BASE_IDX 1
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#define mmDAGB3_WRCLI9 0x01b5
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#define mmDAGB3_WRCLI9_BASE_IDX 1
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#define mmDAGB3_WRCLI10 0x01b6
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#define mmDAGB3_WRCLI10_BASE_IDX 1
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#define mmDAGB3_WRCLI11 0x01b7
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#define mmDAGB3_WRCLI11_BASE_IDX 1
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#define mmDAGB3_WRCLI12 0x01b8
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#define mmDAGB3_WRCLI12_BASE_IDX 1
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#define mmDAGB3_WRCLI13 0x01b9
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#define mmDAGB3_WRCLI13_BASE_IDX 1
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#define mmDAGB3_WRCLI14 0x01ba
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#define mmDAGB3_WRCLI14_BASE_IDX 1
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#define mmDAGB3_WRCLI15 0x01bb
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#define mmDAGB3_WRCLI15_BASE_IDX 1
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#define mmDAGB3_WR_CNTL 0x01bc
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#define mmDAGB3_WR_CNTL_BASE_IDX 1
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#define mmDAGB3_WR_GMI_CNTL 0x01bd
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#define mmDAGB3_WR_GMI_CNTL_BASE_IDX 1
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#define mmDAGB3_WR_ADDR_DAGB 0x01be
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#define mmDAGB3_WR_ADDR_DAGB_BASE_IDX 1
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#define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST 0x01bf
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#define mmDAGB3_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
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#define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 0x01c0
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#define mmDAGB3_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
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#define mmDAGB3_WR_CGTT_CLK_CTRL 0x01c1
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#define mmDAGB3_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL 0x01c2
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#define mmDAGB3_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL 0x01c3
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#define mmDAGB3_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0 0x01c4
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#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0 0x01c5
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#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1 0x01c6
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#define mmDAGB3_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1 0x01c7
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#define mmDAGB3_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB3_WR_DATA_DAGB 0x01c8
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#define mmDAGB3_WR_DATA_DAGB_BASE_IDX 1
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#define mmDAGB3_WR_DATA_DAGB_MAX_BURST0 0x01c9
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#define mmDAGB3_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0 0x01ca
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#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB3_WR_DATA_DAGB_MAX_BURST1 0x01cb
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#define mmDAGB3_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1 0x01cc
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#define mmDAGB3_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB3_WR_VC0_CNTL 0x01cd
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#define mmDAGB3_WR_VC0_CNTL_BASE_IDX 1
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#define mmDAGB3_WR_VC1_CNTL 0x01ce
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#define mmDAGB3_WR_VC1_CNTL_BASE_IDX 1
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#define mmDAGB3_WR_VC2_CNTL 0x01cf
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#define mmDAGB3_WR_VC2_CNTL_BASE_IDX 1
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#define mmDAGB3_WR_VC3_CNTL 0x01d0
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#define mmDAGB3_WR_VC3_CNTL_BASE_IDX 1
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#define mmDAGB3_WR_VC4_CNTL 0x01d1
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#define mmDAGB3_WR_VC4_CNTL_BASE_IDX 1
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#define mmDAGB3_WR_VC5_CNTL 0x01d2
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#define mmDAGB3_WR_VC5_CNTL_BASE_IDX 1
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#define mmDAGB3_WR_VC6_CNTL 0x01d3
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#define mmDAGB3_WR_VC6_CNTL_BASE_IDX 1
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#define mmDAGB3_WR_VC7_CNTL 0x01d4
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#define mmDAGB3_WR_VC7_CNTL_BASE_IDX 1
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#define mmDAGB3_WR_CNTL_MISC 0x01d5
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#define mmDAGB3_WR_CNTL_MISC_BASE_IDX 1
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#define mmDAGB3_WR_TLB_CREDIT 0x01d6
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#define mmDAGB3_WR_TLB_CREDIT_BASE_IDX 1
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#define mmDAGB3_WR_DATA_CREDIT 0x01d7
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#define mmDAGB3_WR_DATA_CREDIT_BASE_IDX 1
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#define mmDAGB3_WR_MISC_CREDIT 0x01d8
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#define mmDAGB3_WR_MISC_CREDIT_BASE_IDX 1
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#define mmDAGB3_WRCLI_ASK_PENDING 0x01dd
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#define mmDAGB3_WRCLI_ASK_PENDING_BASE_IDX 1
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#define mmDAGB3_WRCLI_GO_PENDING 0x01de
|
#define mmDAGB3_WRCLI_GO_PENDING_BASE_IDX 1
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#define mmDAGB3_WRCLI_GBLSEND_PENDING 0x01df
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#define mmDAGB3_WRCLI_GBLSEND_PENDING_BASE_IDX 1
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#define mmDAGB3_WRCLI_TLB_PENDING 0x01e0
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#define mmDAGB3_WRCLI_TLB_PENDING_BASE_IDX 1
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#define mmDAGB3_WRCLI_OARB_PENDING 0x01e1
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#define mmDAGB3_WRCLI_OARB_PENDING_BASE_IDX 1
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#define mmDAGB3_WRCLI_OSD_PENDING 0x01e2
|
#define mmDAGB3_WRCLI_OSD_PENDING_BASE_IDX 1
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#define mmDAGB3_WRCLI_DBUS_ASK_PENDING 0x01e3
|
#define mmDAGB3_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
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#define mmDAGB3_WRCLI_DBUS_GO_PENDING 0x01e4
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#define mmDAGB3_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
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#define mmDAGB3_DAGB_DLY 0x01e5
|
#define mmDAGB3_DAGB_DLY_BASE_IDX 1
|
#define mmDAGB3_CNTL_MISC 0x01e6
|
#define mmDAGB3_CNTL_MISC_BASE_IDX 1
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#define mmDAGB3_CNTL_MISC2 0x01e7
|
#define mmDAGB3_CNTL_MISC2_BASE_IDX 1
|
#define mmDAGB3_FIFO_EMPTY 0x01e8
|
#define mmDAGB3_FIFO_EMPTY_BASE_IDX 1
|
#define mmDAGB3_FIFO_FULL 0x01e9
|
#define mmDAGB3_FIFO_FULL_BASE_IDX 1
|
#define mmDAGB3_WR_CREDITS_FULL 0x01ea
|
#define mmDAGB3_WR_CREDITS_FULL_BASE_IDX 1
|
#define mmDAGB3_RD_CREDITS_FULL 0x01eb
|
#define mmDAGB3_RD_CREDITS_FULL_BASE_IDX 1
|
#define mmDAGB3_PERFCOUNTER_LO 0x01ec
|
#define mmDAGB3_PERFCOUNTER_LO_BASE_IDX 1
|
#define mmDAGB3_PERFCOUNTER_HI 0x01ed
|
#define mmDAGB3_PERFCOUNTER_HI_BASE_IDX 1
|
#define mmDAGB3_PERFCOUNTER0_CFG 0x01ee
|
#define mmDAGB3_PERFCOUNTER0_CFG_BASE_IDX 1
|
#define mmDAGB3_PERFCOUNTER1_CFG 0x01ef
|
#define mmDAGB3_PERFCOUNTER1_CFG_BASE_IDX 1
|
#define mmDAGB3_PERFCOUNTER2_CFG 0x01f0
|
#define mmDAGB3_PERFCOUNTER2_CFG_BASE_IDX 1
|
#define mmDAGB3_PERFCOUNTER_RSLT_CNTL 0x01f1
|
#define mmDAGB3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
|
#define mmDAGB3_RESERVE0 0x01f2
|
#define mmDAGB3_RESERVE0_BASE_IDX 1
|
#define mmDAGB3_RESERVE1 0x01f3
|
#define mmDAGB3_RESERVE1_BASE_IDX 1
|
#define mmDAGB3_RESERVE2 0x01f4
|
#define mmDAGB3_RESERVE2_BASE_IDX 1
|
#define mmDAGB3_RESERVE3 0x01f5
|
#define mmDAGB3_RESERVE3_BASE_IDX 1
|
#define mmDAGB3_RESERVE4 0x01f6
|
#define mmDAGB3_RESERVE4_BASE_IDX 1
|
#define mmDAGB3_RESERVE5 0x01f7
|
#define mmDAGB3_RESERVE5_BASE_IDX 1
|
#define mmDAGB3_RESERVE6 0x01f8
|
#define mmDAGB3_RESERVE6_BASE_IDX 1
|
#define mmDAGB3_RESERVE7 0x01f9
|
#define mmDAGB3_RESERVE7_BASE_IDX 1
|
#define mmDAGB3_RESERVE8 0x01fa
|
#define mmDAGB3_RESERVE8_BASE_IDX 1
|
#define mmDAGB3_RESERVE9 0x01fb
|
#define mmDAGB3_RESERVE9_BASE_IDX 1
|
#define mmDAGB3_RESERVE10 0x01fc
|
#define mmDAGB3_RESERVE10_BASE_IDX 1
|
#define mmDAGB3_RESERVE11 0x01fd
|
#define mmDAGB3_RESERVE11_BASE_IDX 1
|
#define mmDAGB3_RESERVE12 0x01fe
|
#define mmDAGB3_RESERVE12_BASE_IDX 1
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#define mmDAGB3_RESERVE13 0x01ff
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#define mmDAGB3_RESERVE13_BASE_IDX 1
|
|
|
// addressBlock: mmhub_dagb_dagbdec4
|
// base address: 0x68800
|
#define mmDAGB4_RDCLI0 0x0200
|
#define mmDAGB4_RDCLI0_BASE_IDX 1
|
#define mmDAGB4_RDCLI1 0x0201
|
#define mmDAGB4_RDCLI1_BASE_IDX 1
|
#define mmDAGB4_RDCLI2 0x0202
|
#define mmDAGB4_RDCLI2_BASE_IDX 1
|
#define mmDAGB4_RDCLI3 0x0203
|
#define mmDAGB4_RDCLI3_BASE_IDX 1
|
#define mmDAGB4_RDCLI4 0x0204
|
#define mmDAGB4_RDCLI4_BASE_IDX 1
|
#define mmDAGB4_RDCLI5 0x0205
|
#define mmDAGB4_RDCLI5_BASE_IDX 1
|
#define mmDAGB4_RDCLI6 0x0206
|
#define mmDAGB4_RDCLI6_BASE_IDX 1
|
#define mmDAGB4_RDCLI7 0x0207
|
#define mmDAGB4_RDCLI7_BASE_IDX 1
|
#define mmDAGB4_RDCLI8 0x0208
|
#define mmDAGB4_RDCLI8_BASE_IDX 1
|
#define mmDAGB4_RDCLI9 0x0209
|
#define mmDAGB4_RDCLI9_BASE_IDX 1
|
#define mmDAGB4_RDCLI10 0x020a
|
#define mmDAGB4_RDCLI10_BASE_IDX 1
|
#define mmDAGB4_RDCLI11 0x020b
|
#define mmDAGB4_RDCLI11_BASE_IDX 1
|
#define mmDAGB4_RDCLI12 0x020c
|
#define mmDAGB4_RDCLI12_BASE_IDX 1
|
#define mmDAGB4_RDCLI13 0x020d
|
#define mmDAGB4_RDCLI13_BASE_IDX 1
|
#define mmDAGB4_RDCLI14 0x020e
|
#define mmDAGB4_RDCLI14_BASE_IDX 1
|
#define mmDAGB4_RDCLI15 0x020f
|
#define mmDAGB4_RDCLI15_BASE_IDX 1
|
#define mmDAGB4_RD_CNTL 0x0210
|
#define mmDAGB4_RD_CNTL_BASE_IDX 1
|
#define mmDAGB4_RD_GMI_CNTL 0x0211
|
#define mmDAGB4_RD_GMI_CNTL_BASE_IDX 1
|
#define mmDAGB4_RD_ADDR_DAGB 0x0212
|
#define mmDAGB4_RD_ADDR_DAGB_BASE_IDX 1
|
#define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST 0x0213
|
#define mmDAGB4_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
|
#define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 0x0214
|
#define mmDAGB4_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
|
#define mmDAGB4_RD_CGTT_CLK_CTRL 0x0215
|
#define mmDAGB4_RD_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL 0x0216
|
#define mmDAGB4_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL 0x0217
|
#define mmDAGB4_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0 0x0218
|
#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
|
#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0 0x0219
|
#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
|
#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1 0x021a
|
#define mmDAGB4_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
|
#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1 0x021b
|
#define mmDAGB4_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
|
#define mmDAGB4_RD_VC0_CNTL 0x021c
|
#define mmDAGB4_RD_VC0_CNTL_BASE_IDX 1
|
#define mmDAGB4_RD_VC1_CNTL 0x021d
|
#define mmDAGB4_RD_VC1_CNTL_BASE_IDX 1
|
#define mmDAGB4_RD_VC2_CNTL 0x021e
|
#define mmDAGB4_RD_VC2_CNTL_BASE_IDX 1
|
#define mmDAGB4_RD_VC3_CNTL 0x021f
|
#define mmDAGB4_RD_VC3_CNTL_BASE_IDX 1
|
#define mmDAGB4_RD_VC4_CNTL 0x0220
|
#define mmDAGB4_RD_VC4_CNTL_BASE_IDX 1
|
#define mmDAGB4_RD_VC5_CNTL 0x0221
|
#define mmDAGB4_RD_VC5_CNTL_BASE_IDX 1
|
#define mmDAGB4_RD_VC6_CNTL 0x0222
|
#define mmDAGB4_RD_VC6_CNTL_BASE_IDX 1
|
#define mmDAGB4_RD_VC7_CNTL 0x0223
|
#define mmDAGB4_RD_VC7_CNTL_BASE_IDX 1
|
#define mmDAGB4_RD_CNTL_MISC 0x0224
|
#define mmDAGB4_RD_CNTL_MISC_BASE_IDX 1
|
#define mmDAGB4_RD_TLB_CREDIT 0x0225
|
#define mmDAGB4_RD_TLB_CREDIT_BASE_IDX 1
|
#define mmDAGB4_RDCLI_ASK_PENDING 0x0226
|
#define mmDAGB4_RDCLI_ASK_PENDING_BASE_IDX 1
|
#define mmDAGB4_RDCLI_GO_PENDING 0x0227
|
#define mmDAGB4_RDCLI_GO_PENDING_BASE_IDX 1
|
#define mmDAGB4_RDCLI_GBLSEND_PENDING 0x0228
|
#define mmDAGB4_RDCLI_GBLSEND_PENDING_BASE_IDX 1
|
#define mmDAGB4_RDCLI_TLB_PENDING 0x0229
|
#define mmDAGB4_RDCLI_TLB_PENDING_BASE_IDX 1
|
#define mmDAGB4_RDCLI_OARB_PENDING 0x022a
|
#define mmDAGB4_RDCLI_OARB_PENDING_BASE_IDX 1
|
#define mmDAGB4_RDCLI_OSD_PENDING 0x022b
|
#define mmDAGB4_RDCLI_OSD_PENDING_BASE_IDX 1
|
#define mmDAGB4_WRCLI0 0x022c
|
#define mmDAGB4_WRCLI0_BASE_IDX 1
|
#define mmDAGB4_WRCLI1 0x022d
|
#define mmDAGB4_WRCLI1_BASE_IDX 1
|
#define mmDAGB4_WRCLI2 0x022e
|
#define mmDAGB4_WRCLI2_BASE_IDX 1
|
#define mmDAGB4_WRCLI3 0x022f
|
#define mmDAGB4_WRCLI3_BASE_IDX 1
|
#define mmDAGB4_WRCLI4 0x0230
|
#define mmDAGB4_WRCLI4_BASE_IDX 1
|
#define mmDAGB4_WRCLI5 0x0231
|
#define mmDAGB4_WRCLI5_BASE_IDX 1
|
#define mmDAGB4_WRCLI6 0x0232
|
#define mmDAGB4_WRCLI6_BASE_IDX 1
|
#define mmDAGB4_WRCLI7 0x0233
|
#define mmDAGB4_WRCLI7_BASE_IDX 1
|
#define mmDAGB4_WRCLI8 0x0234
|
#define mmDAGB4_WRCLI8_BASE_IDX 1
|
#define mmDAGB4_WRCLI9 0x0235
|
#define mmDAGB4_WRCLI9_BASE_IDX 1
|
#define mmDAGB4_WRCLI10 0x0236
|
#define mmDAGB4_WRCLI10_BASE_IDX 1
|
#define mmDAGB4_WRCLI11 0x0237
|
#define mmDAGB4_WRCLI11_BASE_IDX 1
|
#define mmDAGB4_WRCLI12 0x0238
|
#define mmDAGB4_WRCLI12_BASE_IDX 1
|
#define mmDAGB4_WRCLI13 0x0239
|
#define mmDAGB4_WRCLI13_BASE_IDX 1
|
#define mmDAGB4_WRCLI14 0x023a
|
#define mmDAGB4_WRCLI14_BASE_IDX 1
|
#define mmDAGB4_WRCLI15 0x023b
|
#define mmDAGB4_WRCLI15_BASE_IDX 1
|
#define mmDAGB4_WR_CNTL 0x023c
|
#define mmDAGB4_WR_CNTL_BASE_IDX 1
|
#define mmDAGB4_WR_GMI_CNTL 0x023d
|
#define mmDAGB4_WR_GMI_CNTL_BASE_IDX 1
|
#define mmDAGB4_WR_ADDR_DAGB 0x023e
|
#define mmDAGB4_WR_ADDR_DAGB_BASE_IDX 1
|
#define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST 0x023f
|
#define mmDAGB4_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
|
#define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 0x0240
|
#define mmDAGB4_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
|
#define mmDAGB4_WR_CGTT_CLK_CTRL 0x0241
|
#define mmDAGB4_WR_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL 0x0242
|
#define mmDAGB4_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL 0x0243
|
#define mmDAGB4_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0 0x0244
|
#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
|
#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0 0x0245
|
#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
|
#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1 0x0246
|
#define mmDAGB4_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
|
#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1 0x0247
|
#define mmDAGB4_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
|
#define mmDAGB4_WR_DATA_DAGB 0x0248
|
#define mmDAGB4_WR_DATA_DAGB_BASE_IDX 1
|
#define mmDAGB4_WR_DATA_DAGB_MAX_BURST0 0x0249
|
#define mmDAGB4_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
|
#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0 0x024a
|
#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
|
#define mmDAGB4_WR_DATA_DAGB_MAX_BURST1 0x024b
|
#define mmDAGB4_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
|
#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1 0x024c
|
#define mmDAGB4_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
|
#define mmDAGB4_WR_VC0_CNTL 0x024d
|
#define mmDAGB4_WR_VC0_CNTL_BASE_IDX 1
|
#define mmDAGB4_WR_VC1_CNTL 0x024e
|
#define mmDAGB4_WR_VC1_CNTL_BASE_IDX 1
|
#define mmDAGB4_WR_VC2_CNTL 0x024f
|
#define mmDAGB4_WR_VC2_CNTL_BASE_IDX 1
|
#define mmDAGB4_WR_VC3_CNTL 0x0250
|
#define mmDAGB4_WR_VC3_CNTL_BASE_IDX 1
|
#define mmDAGB4_WR_VC4_CNTL 0x0251
|
#define mmDAGB4_WR_VC4_CNTL_BASE_IDX 1
|
#define mmDAGB4_WR_VC5_CNTL 0x0252
|
#define mmDAGB4_WR_VC5_CNTL_BASE_IDX 1
|
#define mmDAGB4_WR_VC6_CNTL 0x0253
|
#define mmDAGB4_WR_VC6_CNTL_BASE_IDX 1
|
#define mmDAGB4_WR_VC7_CNTL 0x0254
|
#define mmDAGB4_WR_VC7_CNTL_BASE_IDX 1
|
#define mmDAGB4_WR_CNTL_MISC 0x0255
|
#define mmDAGB4_WR_CNTL_MISC_BASE_IDX 1
|
#define mmDAGB4_WR_TLB_CREDIT 0x0256
|
#define mmDAGB4_WR_TLB_CREDIT_BASE_IDX 1
|
#define mmDAGB4_WR_DATA_CREDIT 0x0257
|
#define mmDAGB4_WR_DATA_CREDIT_BASE_IDX 1
|
#define mmDAGB4_WR_MISC_CREDIT 0x0258
|
#define mmDAGB4_WR_MISC_CREDIT_BASE_IDX 1
|
#define mmDAGB4_WRCLI_ASK_PENDING 0x025d
|
#define mmDAGB4_WRCLI_ASK_PENDING_BASE_IDX 1
|
#define mmDAGB4_WRCLI_GO_PENDING 0x025e
|
#define mmDAGB4_WRCLI_GO_PENDING_BASE_IDX 1
|
#define mmDAGB4_WRCLI_GBLSEND_PENDING 0x025f
|
#define mmDAGB4_WRCLI_GBLSEND_PENDING_BASE_IDX 1
|
#define mmDAGB4_WRCLI_TLB_PENDING 0x0260
|
#define mmDAGB4_WRCLI_TLB_PENDING_BASE_IDX 1
|
#define mmDAGB4_WRCLI_OARB_PENDING 0x0261
|
#define mmDAGB4_WRCLI_OARB_PENDING_BASE_IDX 1
|
#define mmDAGB4_WRCLI_OSD_PENDING 0x0262
|
#define mmDAGB4_WRCLI_OSD_PENDING_BASE_IDX 1
|
#define mmDAGB4_WRCLI_DBUS_ASK_PENDING 0x0263
|
#define mmDAGB4_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
|
#define mmDAGB4_WRCLI_DBUS_GO_PENDING 0x0264
|
#define mmDAGB4_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
|
#define mmDAGB4_DAGB_DLY 0x0265
|
#define mmDAGB4_DAGB_DLY_BASE_IDX 1
|
#define mmDAGB4_CNTL_MISC 0x0266
|
#define mmDAGB4_CNTL_MISC_BASE_IDX 1
|
#define mmDAGB4_CNTL_MISC2 0x0267
|
#define mmDAGB4_CNTL_MISC2_BASE_IDX 1
|
#define mmDAGB4_FIFO_EMPTY 0x0268
|
#define mmDAGB4_FIFO_EMPTY_BASE_IDX 1
|
#define mmDAGB4_FIFO_FULL 0x0269
|
#define mmDAGB4_FIFO_FULL_BASE_IDX 1
|
#define mmDAGB4_WR_CREDITS_FULL 0x026a
|
#define mmDAGB4_WR_CREDITS_FULL_BASE_IDX 1
|
#define mmDAGB4_RD_CREDITS_FULL 0x026b
|
#define mmDAGB4_RD_CREDITS_FULL_BASE_IDX 1
|
#define mmDAGB4_PERFCOUNTER_LO 0x026c
|
#define mmDAGB4_PERFCOUNTER_LO_BASE_IDX 1
|
#define mmDAGB4_PERFCOUNTER_HI 0x026d
|
#define mmDAGB4_PERFCOUNTER_HI_BASE_IDX 1
|
#define mmDAGB4_PERFCOUNTER0_CFG 0x026e
|
#define mmDAGB4_PERFCOUNTER0_CFG_BASE_IDX 1
|
#define mmDAGB4_PERFCOUNTER1_CFG 0x026f
|
#define mmDAGB4_PERFCOUNTER1_CFG_BASE_IDX 1
|
#define mmDAGB4_PERFCOUNTER2_CFG 0x0270
|
#define mmDAGB4_PERFCOUNTER2_CFG_BASE_IDX 1
|
#define mmDAGB4_PERFCOUNTER_RSLT_CNTL 0x0271
|
#define mmDAGB4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
|
#define mmDAGB4_RESERVE0 0x0272
|
#define mmDAGB4_RESERVE0_BASE_IDX 1
|
#define mmDAGB4_RESERVE1 0x0273
|
#define mmDAGB4_RESERVE1_BASE_IDX 1
|
#define mmDAGB4_RESERVE2 0x0274
|
#define mmDAGB4_RESERVE2_BASE_IDX 1
|
#define mmDAGB4_RESERVE3 0x0275
|
#define mmDAGB4_RESERVE3_BASE_IDX 1
|
#define mmDAGB4_RESERVE4 0x0276
|
#define mmDAGB4_RESERVE4_BASE_IDX 1
|
#define mmDAGB4_RESERVE5 0x0277
|
#define mmDAGB4_RESERVE5_BASE_IDX 1
|
#define mmDAGB4_RESERVE6 0x0278
|
#define mmDAGB4_RESERVE6_BASE_IDX 1
|
#define mmDAGB4_RESERVE7 0x0279
|
#define mmDAGB4_RESERVE7_BASE_IDX 1
|
#define mmDAGB4_RESERVE8 0x027a
|
#define mmDAGB4_RESERVE8_BASE_IDX 1
|
#define mmDAGB4_RESERVE9 0x027b
|
#define mmDAGB4_RESERVE9_BASE_IDX 1
|
#define mmDAGB4_RESERVE10 0x027c
|
#define mmDAGB4_RESERVE10_BASE_IDX 1
|
#define mmDAGB4_RESERVE11 0x027d
|
#define mmDAGB4_RESERVE11_BASE_IDX 1
|
#define mmDAGB4_RESERVE12 0x027e
|
#define mmDAGB4_RESERVE12_BASE_IDX 1
|
#define mmDAGB4_RESERVE13 0x027f
|
#define mmDAGB4_RESERVE13_BASE_IDX 1
|
|
|
// addressBlock: mmhub_ea_mmeadec0
|
// base address: 0x68a00
|
#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0 0x0280
|
#define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1
|
#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1 0x0281
|
#define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1
|
#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0 0x0282
|
#define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1
|
#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1 0x0283
|
#define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1
|
#define mmMMEA0_DRAM_RD_GRP2VC_MAP 0x0284
|
#define mmMMEA0_DRAM_RD_GRP2VC_MAP_BASE_IDX 1
|
#define mmMMEA0_DRAM_WR_GRP2VC_MAP 0x0285
|
#define mmMMEA0_DRAM_WR_GRP2VC_MAP_BASE_IDX 1
|
#define mmMMEA0_DRAM_RD_LAZY 0x0286
|
#define mmMMEA0_DRAM_RD_LAZY_BASE_IDX 1
|
#define mmMMEA0_DRAM_WR_LAZY 0x0287
|
#define mmMMEA0_DRAM_WR_LAZY_BASE_IDX 1
|
#define mmMMEA0_DRAM_RD_CAM_CNTL 0x0288
|
#define mmMMEA0_DRAM_RD_CAM_CNTL_BASE_IDX 1
|
#define mmMMEA0_DRAM_WR_CAM_CNTL 0x0289
|
#define mmMMEA0_DRAM_WR_CAM_CNTL_BASE_IDX 1
|
#define mmMMEA0_DRAM_PAGE_BURST 0x028a
|
#define mmMMEA0_DRAM_PAGE_BURST_BASE_IDX 1
|
#define mmMMEA0_DRAM_RD_PRI_AGE 0x028b
|
#define mmMMEA0_DRAM_RD_PRI_AGE_BASE_IDX 1
|
#define mmMMEA0_DRAM_WR_PRI_AGE 0x028c
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#define mmMMEA0_DRAM_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA0_DRAM_RD_PRI_QUEUING 0x028d
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#define mmMMEA0_DRAM_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA0_DRAM_WR_PRI_QUEUING 0x028e
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#define mmMMEA0_DRAM_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA0_DRAM_RD_PRI_FIXED 0x028f
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#define mmMMEA0_DRAM_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA0_DRAM_WR_PRI_FIXED 0x0290
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#define mmMMEA0_DRAM_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA0_DRAM_RD_PRI_URGENCY 0x0291
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#define mmMMEA0_DRAM_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA0_DRAM_WR_PRI_URGENCY 0x0292
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#define mmMMEA0_DRAM_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1 0x0293
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#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2 0x0294
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#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3 0x0295
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#define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1 0x0296
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#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2 0x0297
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#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3 0x0298
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#define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA0_GMI_RD_CLI2GRP_MAP0 0x0299
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#define mmMMEA0_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA0_GMI_RD_CLI2GRP_MAP1 0x029a
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#define mmMMEA0_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA0_GMI_WR_CLI2GRP_MAP0 0x029b
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#define mmMMEA0_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA0_GMI_WR_CLI2GRP_MAP1 0x029c
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#define mmMMEA0_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA0_GMI_RD_GRP2VC_MAP 0x029d
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#define mmMMEA0_GMI_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA0_GMI_WR_GRP2VC_MAP 0x029e
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#define mmMMEA0_GMI_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA0_GMI_RD_LAZY 0x029f
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#define mmMMEA0_GMI_RD_LAZY_BASE_IDX 1
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#define mmMMEA0_GMI_WR_LAZY 0x02a0
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#define mmMMEA0_GMI_WR_LAZY_BASE_IDX 1
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#define mmMMEA0_GMI_RD_CAM_CNTL 0x02a1
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#define mmMMEA0_GMI_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA0_GMI_WR_CAM_CNTL 0x02a2
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#define mmMMEA0_GMI_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA0_GMI_PAGE_BURST 0x02a3
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#define mmMMEA0_GMI_PAGE_BURST_BASE_IDX 1
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#define mmMMEA0_GMI_RD_PRI_AGE 0x02a4
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#define mmMMEA0_GMI_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA0_GMI_WR_PRI_AGE 0x02a5
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#define mmMMEA0_GMI_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA0_GMI_RD_PRI_QUEUING 0x02a6
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#define mmMMEA0_GMI_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA0_GMI_WR_PRI_QUEUING 0x02a7
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#define mmMMEA0_GMI_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA0_GMI_RD_PRI_FIXED 0x02a8
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#define mmMMEA0_GMI_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA0_GMI_WR_PRI_FIXED 0x02a9
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#define mmMMEA0_GMI_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA0_GMI_RD_PRI_URGENCY 0x02aa
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#define mmMMEA0_GMI_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA0_GMI_WR_PRI_URGENCY 0x02ab
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#define mmMMEA0_GMI_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING 0x02ac
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#define mmMMEA0_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING 0x02ad
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#define mmMMEA0_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA0_GMI_RD_PRI_QUANT_PRI1 0x02ae
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#define mmMMEA0_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA0_GMI_RD_PRI_QUANT_PRI2 0x02af
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#define mmMMEA0_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA0_GMI_RD_PRI_QUANT_PRI3 0x02b0
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#define mmMMEA0_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA0_GMI_WR_PRI_QUANT_PRI1 0x02b1
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#define mmMMEA0_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA0_GMI_WR_PRI_QUANT_PRI2 0x02b2
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#define mmMMEA0_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA0_GMI_WR_PRI_QUANT_PRI3 0x02b3
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#define mmMMEA0_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_BASE_ADDR0 0x02b4
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#define mmMMEA0_ADDRNORM_BASE_ADDR0_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_LIMIT_ADDR0 0x02b5
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#define mmMMEA0_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_BASE_ADDR1 0x02b6
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#define mmMMEA0_ADDRNORM_BASE_ADDR1_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_LIMIT_ADDR1 0x02b7
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#define mmMMEA0_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_OFFSET_ADDR1 0x02b8
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#define mmMMEA0_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_BASE_ADDR2 0x02b9
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#define mmMMEA0_ADDRNORM_BASE_ADDR2_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_LIMIT_ADDR2 0x02ba
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#define mmMMEA0_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_BASE_ADDR3 0x02bb
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#define mmMMEA0_ADDRNORM_BASE_ADDR3_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_LIMIT_ADDR3 0x02bc
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#define mmMMEA0_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_OFFSET_ADDR3 0x02bd
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#define mmMMEA0_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_BASE_ADDR4 0x02be
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#define mmMMEA0_ADDRNORM_BASE_ADDR4_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_LIMIT_ADDR4 0x02bf
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#define mmMMEA0_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_BASE_ADDR5 0x02c0
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#define mmMMEA0_ADDRNORM_BASE_ADDR5_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_LIMIT_ADDR5 0x02c1
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#define mmMMEA0_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1
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#define mmMMEA0_ADDRNORM_OFFSET_ADDR5 0x02c2
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#define mmMMEA0_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1
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#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL 0x02c3
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#define mmMMEA0_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1
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#define mmMMEA0_ADDRNORMGMI_HOLE_CNTL 0x02c4
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#define mmMMEA0_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1
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#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x02c5
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#define mmMMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1
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#define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 0x02c6
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#define mmMMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1
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#define mmMMEA0_ADDRDEC_BANK_CFG 0x02c7
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#define mmMMEA0_ADDRDEC_BANK_CFG_BASE_IDX 1
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#define mmMMEA0_ADDRDEC_MISC_CFG 0x02c8
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#define mmMMEA0_ADDRDEC_MISC_CFG_BASE_IDX 1
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 0x02c9
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 0x02ca
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 0x02cb
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 0x02cc
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 0x02cd
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5 0x02ce
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC 0x02cf
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2 0x02d0
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0 0x02d1
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1 0x02d2
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#define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1
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#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE 0x02d3
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#define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0 0x02d4
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1 0x02d5
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2 0x02d6
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3 0x02d7
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4 0x02d8
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5 0x02d9
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC 0x02da
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2 0x02db
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0 0x02dc
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1 0x02dd
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#define mmMMEA0_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1
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#define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE 0x02de
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#define mmMMEA0_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0 0x02df
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1 0x02e0
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2 0x02e1
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3 0x02e2
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0 0x02e3
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1 0x02e4
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2 0x02e5
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3 0x02e6
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#define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01 0x02e7
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#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23 0x02e8
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#define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01 0x02e9
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#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23 0x02ea
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#define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01 0x02eb
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#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23 0x02ec
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#define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01 0x02ed
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#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23 0x02ee
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#define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01 0x02ef
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#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23 0x02f0
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#define mmMMEA0_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01 0x02f1
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#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23 0x02f2
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#define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01 0x02f3
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#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23 0x02f4
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#define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_RM_SEL_CS01 0x02f5
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#define mmMMEA0_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_RM_SEL_CS23 0x02f6
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#define mmMMEA0_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01 0x02f7
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#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23 0x02f8
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#define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0 0x02f9
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1 0x02fa
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2 0x02fb
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3 0x02fc
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0 0x02fd
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1 0x02fe
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2 0x02ff
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3 0x0300
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#define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01 0x0301
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#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23 0x0302
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#define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01 0x0303
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#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23 0x0304
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#define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01 0x0305
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#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23 0x0306
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#define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01 0x0307
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#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23 0x0308
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#define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01 0x0309
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#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23 0x030a
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#define mmMMEA0_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01 0x030b
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#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23 0x030c
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#define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01 0x030d
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#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23 0x030e
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#define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_RM_SEL_CS01 0x030f
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#define mmMMEA0_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_RM_SEL_CS23 0x0310
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#define mmMMEA0_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01 0x0311
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#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23 0x0312
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#define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0 0x0313
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1 0x0314
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2 0x0315
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3 0x0316
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0 0x0317
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1 0x0318
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2 0x0319
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3 0x031a
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#define mmMMEA0_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01 0x031b
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#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23 0x031c
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#define mmMMEA0_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01 0x031d
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#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23 0x031e
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#define mmMMEA0_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01 0x031f
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#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23 0x0320
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#define mmMMEA0_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01 0x0321
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#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23 0x0322
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#define mmMMEA0_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01 0x0323
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#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23 0x0324
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#define mmMMEA0_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01 0x0325
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#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23 0x0326
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#define mmMMEA0_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01 0x0327
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#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23 0x0328
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#define mmMMEA0_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_RM_SEL_CS01 0x0329
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#define mmMMEA0_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_RM_SEL_CS23 0x032a
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#define mmMMEA0_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01 0x032b
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#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23 0x032c
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#define mmMMEA0_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL 0x032d
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#define mmMMEA0_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL 0x032e
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#define mmMMEA0_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA0_IO_RD_CLI2GRP_MAP0 0x0355
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#define mmMMEA0_IO_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA0_IO_RD_CLI2GRP_MAP1 0x0356
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#define mmMMEA0_IO_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA0_IO_WR_CLI2GRP_MAP0 0x0357
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#define mmMMEA0_IO_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA0_IO_WR_CLI2GRP_MAP1 0x0358
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#define mmMMEA0_IO_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA0_IO_RD_COMBINE_FLUSH 0x0359
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#define mmMMEA0_IO_RD_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA0_IO_WR_COMBINE_FLUSH 0x035a
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#define mmMMEA0_IO_WR_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA0_IO_GROUP_BURST 0x035b
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#define mmMMEA0_IO_GROUP_BURST_BASE_IDX 1
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#define mmMMEA0_IO_RD_PRI_AGE 0x035c
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#define mmMMEA0_IO_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA0_IO_WR_PRI_AGE 0x035d
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#define mmMMEA0_IO_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA0_IO_RD_PRI_QUEUING 0x035e
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#define mmMMEA0_IO_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA0_IO_WR_PRI_QUEUING 0x035f
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#define mmMMEA0_IO_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA0_IO_RD_PRI_FIXED 0x0360
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#define mmMMEA0_IO_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA0_IO_WR_PRI_FIXED 0x0361
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#define mmMMEA0_IO_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA0_IO_RD_PRI_URGENCY 0x0362
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#define mmMMEA0_IO_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA0_IO_WR_PRI_URGENCY 0x0363
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#define mmMMEA0_IO_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING 0x0364
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#define mmMMEA0_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING 0x0365
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#define mmMMEA0_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA0_IO_RD_PRI_QUANT_PRI1 0x0366
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#define mmMMEA0_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA0_IO_RD_PRI_QUANT_PRI2 0x0367
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#define mmMMEA0_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA0_IO_RD_PRI_QUANT_PRI3 0x0368
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#define mmMMEA0_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA0_IO_WR_PRI_QUANT_PRI1 0x0369
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#define mmMMEA0_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA0_IO_WR_PRI_QUANT_PRI2 0x036a
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#define mmMMEA0_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA0_IO_WR_PRI_QUANT_PRI3 0x036b
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#define mmMMEA0_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA0_SDP_ARB_DRAM 0x036c
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#define mmMMEA0_SDP_ARB_DRAM_BASE_IDX 1
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#define mmMMEA0_SDP_ARB_GMI 0x036d
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#define mmMMEA0_SDP_ARB_GMI_BASE_IDX 1
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#define mmMMEA0_SDP_ARB_FINAL 0x036e
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#define mmMMEA0_SDP_ARB_FINAL_BASE_IDX 1
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#define mmMMEA0_SDP_DRAM_PRIORITY 0x036f
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#define mmMMEA0_SDP_DRAM_PRIORITY_BASE_IDX 1
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#define mmMMEA0_SDP_GMI_PRIORITY 0x0370
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#define mmMMEA0_SDP_GMI_PRIORITY_BASE_IDX 1
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#define mmMMEA0_SDP_IO_PRIORITY 0x0371
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#define mmMMEA0_SDP_IO_PRIORITY_BASE_IDX 1
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#define mmMMEA0_SDP_CREDITS 0x0372
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#define mmMMEA0_SDP_CREDITS_BASE_IDX 1
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#define mmMMEA0_SDP_TAG_RESERVE0 0x0373
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#define mmMMEA0_SDP_TAG_RESERVE0_BASE_IDX 1
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#define mmMMEA0_SDP_TAG_RESERVE1 0x0374
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#define mmMMEA0_SDP_TAG_RESERVE1_BASE_IDX 1
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#define mmMMEA0_SDP_VCC_RESERVE0 0x0375
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#define mmMMEA0_SDP_VCC_RESERVE0_BASE_IDX 1
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#define mmMMEA0_SDP_VCC_RESERVE1 0x0376
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#define mmMMEA0_SDP_VCC_RESERVE1_BASE_IDX 1
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#define mmMMEA0_SDP_VCD_RESERVE0 0x0377
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#define mmMMEA0_SDP_VCD_RESERVE0_BASE_IDX 1
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#define mmMMEA0_SDP_VCD_RESERVE1 0x0378
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#define mmMMEA0_SDP_VCD_RESERVE1_BASE_IDX 1
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#define mmMMEA0_SDP_REQ_CNTL 0x0379
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#define mmMMEA0_SDP_REQ_CNTL_BASE_IDX 1
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#define mmMMEA0_MISC 0x037a
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#define mmMMEA0_MISC_BASE_IDX 1
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#define mmMMEA0_LATENCY_SAMPLING 0x037b
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#define mmMMEA0_LATENCY_SAMPLING_BASE_IDX 1
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#define mmMMEA0_PERFCOUNTER_LO 0x037c
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#define mmMMEA0_PERFCOUNTER_LO_BASE_IDX 1
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#define mmMMEA0_PERFCOUNTER_HI 0x037d
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#define mmMMEA0_PERFCOUNTER_HI_BASE_IDX 1
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#define mmMMEA0_PERFCOUNTER0_CFG 0x037e
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#define mmMMEA0_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmMMEA0_PERFCOUNTER1_CFG 0x037f
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#define mmMMEA0_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmMMEA0_PERFCOUNTER_RSLT_CNTL 0x0380
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#define mmMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmMMEA0_EDC_CNT 0x0386
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#define mmMMEA0_EDC_CNT_BASE_IDX 1
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#define mmMMEA0_EDC_CNT2 0x0387
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#define mmMMEA0_EDC_CNT2_BASE_IDX 1
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#define mmMMEA0_DSM_CNTL 0x0388
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#define mmMMEA0_DSM_CNTL_BASE_IDX 1
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#define mmMMEA0_DSM_CNTLA 0x0389
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#define mmMMEA0_DSM_CNTLA_BASE_IDX 1
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#define mmMMEA0_DSM_CNTLB 0x038a
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#define mmMMEA0_DSM_CNTLB_BASE_IDX 1
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#define mmMMEA0_DSM_CNTL2 0x038b
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#define mmMMEA0_DSM_CNTL2_BASE_IDX 1
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#define mmMMEA0_DSM_CNTL2A 0x038c
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#define mmMMEA0_DSM_CNTL2A_BASE_IDX 1
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#define mmMMEA0_DSM_CNTL2B 0x038d
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#define mmMMEA0_DSM_CNTL2B_BASE_IDX 1
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#define mmMMEA0_CGTT_CLK_CTRL 0x038f
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#define mmMMEA0_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmMMEA0_EDC_MODE 0x0390
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#define mmMMEA0_EDC_MODE_BASE_IDX 1
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#define mmMMEA0_ERR_STATUS 0x0391
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#define mmMMEA0_ERR_STATUS_BASE_IDX 1
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#define mmMMEA0_MISC2 0x0392
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#define mmMMEA0_MISC2_BASE_IDX 1
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#define mmMMEA0_ADDRDEC_SELECT 0x0393
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#define mmMMEA0_ADDRDEC_SELECT_BASE_IDX 1
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#define mmMMEA0_EDC_CNT3 0x0394
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#define mmMMEA0_EDC_CNT3_BASE_IDX 1
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// addressBlock: mmhub_ea_mmeadec1
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// base address: 0x68f00
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#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0 0x03c0
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#define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1 0x03c1
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#define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0 0x03c2
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#define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1 0x03c3
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#define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA1_DRAM_RD_GRP2VC_MAP 0x03c4
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#define mmMMEA1_DRAM_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA1_DRAM_WR_GRP2VC_MAP 0x03c5
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#define mmMMEA1_DRAM_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA1_DRAM_RD_LAZY 0x03c6
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#define mmMMEA1_DRAM_RD_LAZY_BASE_IDX 1
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#define mmMMEA1_DRAM_WR_LAZY 0x03c7
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#define mmMMEA1_DRAM_WR_LAZY_BASE_IDX 1
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#define mmMMEA1_DRAM_RD_CAM_CNTL 0x03c8
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#define mmMMEA1_DRAM_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA1_DRAM_WR_CAM_CNTL 0x03c9
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#define mmMMEA1_DRAM_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA1_DRAM_PAGE_BURST 0x03ca
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#define mmMMEA1_DRAM_PAGE_BURST_BASE_IDX 1
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#define mmMMEA1_DRAM_RD_PRI_AGE 0x03cb
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#define mmMMEA1_DRAM_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA1_DRAM_WR_PRI_AGE 0x03cc
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#define mmMMEA1_DRAM_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA1_DRAM_RD_PRI_QUEUING 0x03cd
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#define mmMMEA1_DRAM_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA1_DRAM_WR_PRI_QUEUING 0x03ce
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#define mmMMEA1_DRAM_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA1_DRAM_RD_PRI_FIXED 0x03cf
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#define mmMMEA1_DRAM_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA1_DRAM_WR_PRI_FIXED 0x03d0
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#define mmMMEA1_DRAM_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA1_DRAM_RD_PRI_URGENCY 0x03d1
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#define mmMMEA1_DRAM_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA1_DRAM_WR_PRI_URGENCY 0x03d2
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#define mmMMEA1_DRAM_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1 0x03d3
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#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2 0x03d4
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#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3 0x03d5
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#define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1 0x03d6
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#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2 0x03d7
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#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3 0x03d8
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#define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA1_GMI_RD_CLI2GRP_MAP0 0x03d9
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#define mmMMEA1_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA1_GMI_RD_CLI2GRP_MAP1 0x03da
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#define mmMMEA1_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA1_GMI_WR_CLI2GRP_MAP0 0x03db
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#define mmMMEA1_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA1_GMI_WR_CLI2GRP_MAP1 0x03dc
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#define mmMMEA1_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA1_GMI_RD_GRP2VC_MAP 0x03dd
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#define mmMMEA1_GMI_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA1_GMI_WR_GRP2VC_MAP 0x03de
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#define mmMMEA1_GMI_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA1_GMI_RD_LAZY 0x03df
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#define mmMMEA1_GMI_RD_LAZY_BASE_IDX 1
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#define mmMMEA1_GMI_WR_LAZY 0x03e0
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#define mmMMEA1_GMI_WR_LAZY_BASE_IDX 1
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#define mmMMEA1_GMI_RD_CAM_CNTL 0x03e1
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#define mmMMEA1_GMI_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA1_GMI_WR_CAM_CNTL 0x03e2
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#define mmMMEA1_GMI_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA1_GMI_PAGE_BURST 0x03e3
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#define mmMMEA1_GMI_PAGE_BURST_BASE_IDX 1
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#define mmMMEA1_GMI_RD_PRI_AGE 0x03e4
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#define mmMMEA1_GMI_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA1_GMI_WR_PRI_AGE 0x03e5
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#define mmMMEA1_GMI_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA1_GMI_RD_PRI_QUEUING 0x03e6
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#define mmMMEA1_GMI_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA1_GMI_WR_PRI_QUEUING 0x03e7
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#define mmMMEA1_GMI_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA1_GMI_RD_PRI_FIXED 0x03e8
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#define mmMMEA1_GMI_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA1_GMI_WR_PRI_FIXED 0x03e9
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#define mmMMEA1_GMI_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA1_GMI_RD_PRI_URGENCY 0x03ea
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#define mmMMEA1_GMI_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA1_GMI_WR_PRI_URGENCY 0x03eb
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#define mmMMEA1_GMI_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING 0x03ec
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#define mmMMEA1_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING 0x03ed
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#define mmMMEA1_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA1_GMI_RD_PRI_QUANT_PRI1 0x03ee
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#define mmMMEA1_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA1_GMI_RD_PRI_QUANT_PRI2 0x03ef
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#define mmMMEA1_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA1_GMI_RD_PRI_QUANT_PRI3 0x03f0
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#define mmMMEA1_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA1_GMI_WR_PRI_QUANT_PRI1 0x03f1
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#define mmMMEA1_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA1_GMI_WR_PRI_QUANT_PRI2 0x03f2
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#define mmMMEA1_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA1_GMI_WR_PRI_QUANT_PRI3 0x03f3
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#define mmMMEA1_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_BASE_ADDR0 0x03f4
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#define mmMMEA1_ADDRNORM_BASE_ADDR0_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_LIMIT_ADDR0 0x03f5
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#define mmMMEA1_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_BASE_ADDR1 0x03f6
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#define mmMMEA1_ADDRNORM_BASE_ADDR1_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_LIMIT_ADDR1 0x03f7
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#define mmMMEA1_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_OFFSET_ADDR1 0x03f8
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#define mmMMEA1_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_BASE_ADDR2 0x03f9
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#define mmMMEA1_ADDRNORM_BASE_ADDR2_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_LIMIT_ADDR2 0x03fa
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#define mmMMEA1_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_BASE_ADDR3 0x03fb
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#define mmMMEA1_ADDRNORM_BASE_ADDR3_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_LIMIT_ADDR3 0x03fc
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#define mmMMEA1_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_OFFSET_ADDR3 0x03fd
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#define mmMMEA1_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_BASE_ADDR4 0x03fe
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#define mmMMEA1_ADDRNORM_BASE_ADDR4_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_LIMIT_ADDR4 0x03ff
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#define mmMMEA1_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_BASE_ADDR5 0x0400
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#define mmMMEA1_ADDRNORM_BASE_ADDR5_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_LIMIT_ADDR5 0x0401
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#define mmMMEA1_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1
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#define mmMMEA1_ADDRNORM_OFFSET_ADDR5 0x0402
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#define mmMMEA1_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1
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#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL 0x0403
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#define mmMMEA1_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1
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#define mmMMEA1_ADDRNORMGMI_HOLE_CNTL 0x0404
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#define mmMMEA1_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1
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#define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0405
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#define mmMMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1
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#define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0406
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#define mmMMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1
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#define mmMMEA1_ADDRDEC_BANK_CFG 0x0407
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#define mmMMEA1_ADDRDEC_BANK_CFG_BASE_IDX 1
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#define mmMMEA1_ADDRDEC_MISC_CFG 0x0408
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#define mmMMEA1_ADDRDEC_MISC_CFG_BASE_IDX 1
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 0x0409
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 0x040a
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 0x040b
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 0x040c
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 0x040d
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5 0x040e
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC 0x040f
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2 0x0410
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0 0x0411
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1 0x0412
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#define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1
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#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE 0x0413
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#define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0 0x0414
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1 0x0415
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2 0x0416
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3 0x0417
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4 0x0418
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5 0x0419
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC 0x041a
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2 0x041b
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0 0x041c
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1 0x041d
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#define mmMMEA1_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1
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#define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE 0x041e
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#define mmMMEA1_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0 0x041f
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1 0x0420
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2 0x0421
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3 0x0422
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0 0x0423
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1 0x0424
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2 0x0425
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3 0x0426
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#define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01 0x0427
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#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23 0x0428
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#define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01 0x0429
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#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23 0x042a
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#define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01 0x042b
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#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23 0x042c
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#define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01 0x042d
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#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23 0x042e
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#define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01 0x042f
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#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23 0x0430
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#define mmMMEA1_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01 0x0431
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#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23 0x0432
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#define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01 0x0433
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#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23 0x0434
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#define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_RM_SEL_CS01 0x0435
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#define mmMMEA1_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_RM_SEL_CS23 0x0436
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#define mmMMEA1_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01 0x0437
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#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23 0x0438
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#define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0 0x0439
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1 0x043a
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2 0x043b
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3 0x043c
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0 0x043d
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1 0x043e
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2 0x043f
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3 0x0440
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#define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01 0x0441
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#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23 0x0442
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#define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01 0x0443
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#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23 0x0444
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#define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01 0x0445
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#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23 0x0446
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#define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01 0x0447
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#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23 0x0448
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#define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01 0x0449
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#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23 0x044a
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#define mmMMEA1_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01 0x044b
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#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23 0x044c
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#define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01 0x044d
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#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23 0x044e
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#define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_RM_SEL_CS01 0x044f
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#define mmMMEA1_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_RM_SEL_CS23 0x0450
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#define mmMMEA1_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01 0x0451
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#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23 0x0452
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#define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0 0x0453
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1 0x0454
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2 0x0455
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3 0x0456
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0 0x0457
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1 0x0458
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2 0x0459
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3 0x045a
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#define mmMMEA1_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01 0x045b
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#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23 0x045c
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#define mmMMEA1_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01 0x045d
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#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23 0x045e
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#define mmMMEA1_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01 0x045f
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#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23 0x0460
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#define mmMMEA1_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01 0x0461
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#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23 0x0462
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#define mmMMEA1_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01 0x0463
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#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23 0x0464
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#define mmMMEA1_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01 0x0465
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#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23 0x0466
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#define mmMMEA1_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01 0x0467
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#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23 0x0468
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#define mmMMEA1_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_RM_SEL_CS01 0x0469
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#define mmMMEA1_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_RM_SEL_CS23 0x046a
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#define mmMMEA1_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01 0x046b
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#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23 0x046c
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#define mmMMEA1_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL 0x046d
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#define mmMMEA1_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL 0x046e
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#define mmMMEA1_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA1_IO_RD_CLI2GRP_MAP0 0x0495
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#define mmMMEA1_IO_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA1_IO_RD_CLI2GRP_MAP1 0x0496
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#define mmMMEA1_IO_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA1_IO_WR_CLI2GRP_MAP0 0x0497
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#define mmMMEA1_IO_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA1_IO_WR_CLI2GRP_MAP1 0x0498
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#define mmMMEA1_IO_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA1_IO_RD_COMBINE_FLUSH 0x0499
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#define mmMMEA1_IO_RD_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA1_IO_WR_COMBINE_FLUSH 0x049a
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#define mmMMEA1_IO_WR_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA1_IO_GROUP_BURST 0x049b
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#define mmMMEA1_IO_GROUP_BURST_BASE_IDX 1
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#define mmMMEA1_IO_RD_PRI_AGE 0x049c
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#define mmMMEA1_IO_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA1_IO_WR_PRI_AGE 0x049d
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#define mmMMEA1_IO_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA1_IO_RD_PRI_QUEUING 0x049e
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#define mmMMEA1_IO_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA1_IO_WR_PRI_QUEUING 0x049f
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#define mmMMEA1_IO_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA1_IO_RD_PRI_FIXED 0x04a0
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#define mmMMEA1_IO_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA1_IO_WR_PRI_FIXED 0x04a1
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#define mmMMEA1_IO_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA1_IO_RD_PRI_URGENCY 0x04a2
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#define mmMMEA1_IO_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA1_IO_WR_PRI_URGENCY 0x04a3
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#define mmMMEA1_IO_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA1_IO_RD_PRI_URGENCY_MASKING 0x04a4
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#define mmMMEA1_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA1_IO_WR_PRI_URGENCY_MASKING 0x04a5
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#define mmMMEA1_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA1_IO_RD_PRI_QUANT_PRI1 0x04a6
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#define mmMMEA1_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA1_IO_RD_PRI_QUANT_PRI2 0x04a7
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#define mmMMEA1_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA1_IO_RD_PRI_QUANT_PRI3 0x04a8
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#define mmMMEA1_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA1_IO_WR_PRI_QUANT_PRI1 0x04a9
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#define mmMMEA1_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA1_IO_WR_PRI_QUANT_PRI2 0x04aa
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#define mmMMEA1_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA1_IO_WR_PRI_QUANT_PRI3 0x04ab
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#define mmMMEA1_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA1_SDP_ARB_DRAM 0x04ac
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#define mmMMEA1_SDP_ARB_DRAM_BASE_IDX 1
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#define mmMMEA1_SDP_ARB_GMI 0x04ad
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#define mmMMEA1_SDP_ARB_GMI_BASE_IDX 1
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#define mmMMEA1_SDP_ARB_FINAL 0x04ae
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#define mmMMEA1_SDP_ARB_FINAL_BASE_IDX 1
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#define mmMMEA1_SDP_DRAM_PRIORITY 0x04af
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#define mmMMEA1_SDP_DRAM_PRIORITY_BASE_IDX 1
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#define mmMMEA1_SDP_GMI_PRIORITY 0x04b0
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#define mmMMEA1_SDP_GMI_PRIORITY_BASE_IDX 1
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#define mmMMEA1_SDP_IO_PRIORITY 0x04b1
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#define mmMMEA1_SDP_IO_PRIORITY_BASE_IDX 1
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#define mmMMEA1_SDP_CREDITS 0x04b2
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#define mmMMEA1_SDP_CREDITS_BASE_IDX 1
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#define mmMMEA1_SDP_TAG_RESERVE0 0x04b3
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#define mmMMEA1_SDP_TAG_RESERVE0_BASE_IDX 1
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#define mmMMEA1_SDP_TAG_RESERVE1 0x04b4
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#define mmMMEA1_SDP_TAG_RESERVE1_BASE_IDX 1
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#define mmMMEA1_SDP_VCC_RESERVE0 0x04b5
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#define mmMMEA1_SDP_VCC_RESERVE0_BASE_IDX 1
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#define mmMMEA1_SDP_VCC_RESERVE1 0x04b6
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#define mmMMEA1_SDP_VCC_RESERVE1_BASE_IDX 1
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#define mmMMEA1_SDP_VCD_RESERVE0 0x04b7
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#define mmMMEA1_SDP_VCD_RESERVE0_BASE_IDX 1
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#define mmMMEA1_SDP_VCD_RESERVE1 0x04b8
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#define mmMMEA1_SDP_VCD_RESERVE1_BASE_IDX 1
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#define mmMMEA1_SDP_REQ_CNTL 0x04b9
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#define mmMMEA1_SDP_REQ_CNTL_BASE_IDX 1
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#define mmMMEA1_MISC 0x04ba
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#define mmMMEA1_MISC_BASE_IDX 1
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#define mmMMEA1_LATENCY_SAMPLING 0x04bb
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#define mmMMEA1_LATENCY_SAMPLING_BASE_IDX 1
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#define mmMMEA1_PERFCOUNTER_LO 0x04bc
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#define mmMMEA1_PERFCOUNTER_LO_BASE_IDX 1
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#define mmMMEA1_PERFCOUNTER_HI 0x04bd
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#define mmMMEA1_PERFCOUNTER_HI_BASE_IDX 1
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#define mmMMEA1_PERFCOUNTER0_CFG 0x04be
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#define mmMMEA1_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmMMEA1_PERFCOUNTER1_CFG 0x04bf
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#define mmMMEA1_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmMMEA1_PERFCOUNTER_RSLT_CNTL 0x04c0
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#define mmMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmMMEA1_EDC_CNT 0x04c6
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#define mmMMEA1_EDC_CNT_BASE_IDX 1
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#define mmMMEA1_EDC_CNT2 0x04c7
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#define mmMMEA1_EDC_CNT2_BASE_IDX 1
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#define mmMMEA1_DSM_CNTL 0x04c8
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#define mmMMEA1_DSM_CNTL_BASE_IDX 1
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#define mmMMEA1_DSM_CNTLA 0x04c9
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#define mmMMEA1_DSM_CNTLA_BASE_IDX 1
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#define mmMMEA1_DSM_CNTLB 0x04ca
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#define mmMMEA1_DSM_CNTLB_BASE_IDX 1
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#define mmMMEA1_DSM_CNTL2 0x04cb
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#define mmMMEA1_DSM_CNTL2_BASE_IDX 1
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#define mmMMEA1_DSM_CNTL2A 0x04cc
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#define mmMMEA1_DSM_CNTL2A_BASE_IDX 1
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#define mmMMEA1_DSM_CNTL2B 0x04cd
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#define mmMMEA1_DSM_CNTL2B_BASE_IDX 1
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#define mmMMEA1_CGTT_CLK_CTRL 0x04cf
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#define mmMMEA1_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmMMEA1_EDC_MODE 0x04d0
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#define mmMMEA1_EDC_MODE_BASE_IDX 1
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#define mmMMEA1_ERR_STATUS 0x04d1
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#define mmMMEA1_ERR_STATUS_BASE_IDX 1
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#define mmMMEA1_MISC2 0x04d2
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#define mmMMEA1_MISC2_BASE_IDX 1
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#define mmMMEA1_ADDRDEC_SELECT 0x04d3
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#define mmMMEA1_ADDRDEC_SELECT_BASE_IDX 1
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#define mmMMEA1_EDC_CNT3 0x04d4
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#define mmMMEA1_EDC_CNT3_BASE_IDX 1
|
|
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// addressBlock: mmhub_ea_mmeadec2
|
// base address: 0x69400
|
#define mmMMEA2_DRAM_RD_CLI2GRP_MAP0 0x0500
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#define mmMMEA2_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA2_DRAM_RD_CLI2GRP_MAP1 0x0501
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#define mmMMEA2_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA2_DRAM_WR_CLI2GRP_MAP0 0x0502
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#define mmMMEA2_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA2_DRAM_WR_CLI2GRP_MAP1 0x0503
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#define mmMMEA2_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA2_DRAM_RD_GRP2VC_MAP 0x0504
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#define mmMMEA2_DRAM_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA2_DRAM_WR_GRP2VC_MAP 0x0505
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#define mmMMEA2_DRAM_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA2_DRAM_RD_LAZY 0x0506
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#define mmMMEA2_DRAM_RD_LAZY_BASE_IDX 1
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#define mmMMEA2_DRAM_WR_LAZY 0x0507
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#define mmMMEA2_DRAM_WR_LAZY_BASE_IDX 1
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#define mmMMEA2_DRAM_RD_CAM_CNTL 0x0508
|
#define mmMMEA2_DRAM_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA2_DRAM_WR_CAM_CNTL 0x0509
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#define mmMMEA2_DRAM_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA2_DRAM_PAGE_BURST 0x050a
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#define mmMMEA2_DRAM_PAGE_BURST_BASE_IDX 1
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#define mmMMEA2_DRAM_RD_PRI_AGE 0x050b
|
#define mmMMEA2_DRAM_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA2_DRAM_WR_PRI_AGE 0x050c
|
#define mmMMEA2_DRAM_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA2_DRAM_RD_PRI_QUEUING 0x050d
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#define mmMMEA2_DRAM_RD_PRI_QUEUING_BASE_IDX 1
|
#define mmMMEA2_DRAM_WR_PRI_QUEUING 0x050e
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#define mmMMEA2_DRAM_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA2_DRAM_RD_PRI_FIXED 0x050f
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#define mmMMEA2_DRAM_RD_PRI_FIXED_BASE_IDX 1
|
#define mmMMEA2_DRAM_WR_PRI_FIXED 0x0510
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#define mmMMEA2_DRAM_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA2_DRAM_RD_PRI_URGENCY 0x0511
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#define mmMMEA2_DRAM_RD_PRI_URGENCY_BASE_IDX 1
|
#define mmMMEA2_DRAM_WR_PRI_URGENCY 0x0512
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#define mmMMEA2_DRAM_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1 0x0513
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#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2 0x0514
|
#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1
|
#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3 0x0515
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#define mmMMEA2_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1
|
#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1 0x0516
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#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2 0x0517
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#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3 0x0518
|
#define mmMMEA2_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1
|
#define mmMMEA2_GMI_RD_CLI2GRP_MAP0 0x0519
|
#define mmMMEA2_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1
|
#define mmMMEA2_GMI_RD_CLI2GRP_MAP1 0x051a
|
#define mmMMEA2_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1
|
#define mmMMEA2_GMI_WR_CLI2GRP_MAP0 0x051b
|
#define mmMMEA2_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1
|
#define mmMMEA2_GMI_WR_CLI2GRP_MAP1 0x051c
|
#define mmMMEA2_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA2_GMI_RD_GRP2VC_MAP 0x051d
|
#define mmMMEA2_GMI_RD_GRP2VC_MAP_BASE_IDX 1
|
#define mmMMEA2_GMI_WR_GRP2VC_MAP 0x051e
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#define mmMMEA2_GMI_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA2_GMI_RD_LAZY 0x051f
|
#define mmMMEA2_GMI_RD_LAZY_BASE_IDX 1
|
#define mmMMEA2_GMI_WR_LAZY 0x0520
|
#define mmMMEA2_GMI_WR_LAZY_BASE_IDX 1
|
#define mmMMEA2_GMI_RD_CAM_CNTL 0x0521
|
#define mmMMEA2_GMI_RD_CAM_CNTL_BASE_IDX 1
|
#define mmMMEA2_GMI_WR_CAM_CNTL 0x0522
|
#define mmMMEA2_GMI_WR_CAM_CNTL_BASE_IDX 1
|
#define mmMMEA2_GMI_PAGE_BURST 0x0523
|
#define mmMMEA2_GMI_PAGE_BURST_BASE_IDX 1
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#define mmMMEA2_GMI_RD_PRI_AGE 0x0524
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#define mmMMEA2_GMI_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA2_GMI_WR_PRI_AGE 0x0525
|
#define mmMMEA2_GMI_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA2_GMI_RD_PRI_QUEUING 0x0526
|
#define mmMMEA2_GMI_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA2_GMI_WR_PRI_QUEUING 0x0527
|
#define mmMMEA2_GMI_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA2_GMI_RD_PRI_FIXED 0x0528
|
#define mmMMEA2_GMI_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA2_GMI_WR_PRI_FIXED 0x0529
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#define mmMMEA2_GMI_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA2_GMI_RD_PRI_URGENCY 0x052a
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#define mmMMEA2_GMI_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA2_GMI_WR_PRI_URGENCY 0x052b
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#define mmMMEA2_GMI_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING 0x052c
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#define mmMMEA2_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING 0x052d
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#define mmMMEA2_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA2_GMI_RD_PRI_QUANT_PRI1 0x052e
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#define mmMMEA2_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA2_GMI_RD_PRI_QUANT_PRI2 0x052f
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#define mmMMEA2_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA2_GMI_RD_PRI_QUANT_PRI3 0x0530
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#define mmMMEA2_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA2_GMI_WR_PRI_QUANT_PRI1 0x0531
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#define mmMMEA2_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA2_GMI_WR_PRI_QUANT_PRI2 0x0532
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#define mmMMEA2_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA2_GMI_WR_PRI_QUANT_PRI3 0x0533
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#define mmMMEA2_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA2_ADDRNORM_BASE_ADDR0 0x0534
|
#define mmMMEA2_ADDRNORM_BASE_ADDR0_BASE_IDX 1
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#define mmMMEA2_ADDRNORM_LIMIT_ADDR0 0x0535
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#define mmMMEA2_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1
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#define mmMMEA2_ADDRNORM_BASE_ADDR1 0x0536
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#define mmMMEA2_ADDRNORM_BASE_ADDR1_BASE_IDX 1
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#define mmMMEA2_ADDRNORM_LIMIT_ADDR1 0x0537
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#define mmMMEA2_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1
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#define mmMMEA2_ADDRNORM_OFFSET_ADDR1 0x0538
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#define mmMMEA2_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1
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#define mmMMEA2_ADDRNORM_BASE_ADDR2 0x0539
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#define mmMMEA2_ADDRNORM_BASE_ADDR2_BASE_IDX 1
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#define mmMMEA2_ADDRNORM_LIMIT_ADDR2 0x053a
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#define mmMMEA2_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1
|
#define mmMMEA2_ADDRNORM_BASE_ADDR3 0x053b
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#define mmMMEA2_ADDRNORM_BASE_ADDR3_BASE_IDX 1
|
#define mmMMEA2_ADDRNORM_LIMIT_ADDR3 0x053c
|
#define mmMMEA2_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1
|
#define mmMMEA2_ADDRNORM_OFFSET_ADDR3 0x053d
|
#define mmMMEA2_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1
|
#define mmMMEA2_ADDRNORM_BASE_ADDR4 0x053e
|
#define mmMMEA2_ADDRNORM_BASE_ADDR4_BASE_IDX 1
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#define mmMMEA2_ADDRNORM_LIMIT_ADDR4 0x053f
|
#define mmMMEA2_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1
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#define mmMMEA2_ADDRNORM_BASE_ADDR5 0x0540
|
#define mmMMEA2_ADDRNORM_BASE_ADDR5_BASE_IDX 1
|
#define mmMMEA2_ADDRNORM_LIMIT_ADDR5 0x0541
|
#define mmMMEA2_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1
|
#define mmMMEA2_ADDRNORM_OFFSET_ADDR5 0x0542
|
#define mmMMEA2_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1
|
#define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL 0x0543
|
#define mmMMEA2_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1
|
#define mmMMEA2_ADDRNORMGMI_HOLE_CNTL 0x0544
|
#define mmMMEA2_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1
|
#define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0545
|
#define mmMMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1
|
#define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0546
|
#define mmMMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC_BANK_CFG 0x0547
|
#define mmMMEA2_ADDRDEC_BANK_CFG_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC_MISC_CFG 0x0548
|
#define mmMMEA2_ADDRDEC_MISC_CFG_BASE_IDX 1
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0 0x0549
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1 0x054a
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2 0x054b
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3 0x054c
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4 0x054d
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5 0x054e
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC 0x054f
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2 0x0550
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0 0x0551
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1 0x0552
|
#define mmMMEA2_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1
|
#define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE 0x0553
|
#define mmMMEA2_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0 0x0554
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1 0x0555
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2 0x0556
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3 0x0557
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4 0x0558
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5 0x0559
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC 0x055a
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2 0x055b
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0 0x055c
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1 0x055d
|
#define mmMMEA2_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1
|
#define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE 0x055e
|
#define mmMMEA2_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0 0x055f
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1 0x0560
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2 0x0561
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3 0x0562
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0 0x0563
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1 0x0564
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2 0x0565
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3 0x0566
|
#define mmMMEA2_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01 0x0567
|
#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23 0x0568
|
#define mmMMEA2_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01 0x0569
|
#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23 0x056a
|
#define mmMMEA2_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01 0x056b
|
#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23 0x056c
|
#define mmMMEA2_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01 0x056d
|
#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23 0x056e
|
#define mmMMEA2_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01 0x056f
|
#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23 0x0570
|
#define mmMMEA2_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01 0x0571
|
#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23 0x0572
|
#define mmMMEA2_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01 0x0573
|
#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23 0x0574
|
#define mmMMEA2_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1
|
#define mmMMEA2_ADDRDEC0_RM_SEL_CS01 0x0575
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#define mmMMEA2_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC0_RM_SEL_CS23 0x0576
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#define mmMMEA2_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01 0x0577
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#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23 0x0578
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#define mmMMEA2_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0 0x0579
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1 0x057a
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2 0x057b
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3 0x057c
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0 0x057d
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1 0x057e
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2 0x057f
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3 0x0580
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#define mmMMEA2_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01 0x0581
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#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23 0x0582
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#define mmMMEA2_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01 0x0583
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#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23 0x0584
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#define mmMMEA2_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01 0x0585
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#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23 0x0586
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#define mmMMEA2_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01 0x0587
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#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23 0x0588
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#define mmMMEA2_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01 0x0589
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#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23 0x058a
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#define mmMMEA2_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01 0x058b
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#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23 0x058c
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#define mmMMEA2_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01 0x058d
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#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23 0x058e
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#define mmMMEA2_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_RM_SEL_CS01 0x058f
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#define mmMMEA2_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_RM_SEL_CS23 0x0590
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#define mmMMEA2_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01 0x0591
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#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23 0x0592
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#define mmMMEA2_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0 0x0593
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1 0x0594
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2 0x0595
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3 0x0596
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0 0x0597
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1 0x0598
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2 0x0599
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3 0x059a
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#define mmMMEA2_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01 0x059b
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#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23 0x059c
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#define mmMMEA2_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01 0x059d
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#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23 0x059e
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#define mmMMEA2_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01 0x059f
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#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23 0x05a0
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#define mmMMEA2_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01 0x05a1
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#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23 0x05a2
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#define mmMMEA2_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01 0x05a3
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#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23 0x05a4
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#define mmMMEA2_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01 0x05a5
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#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23 0x05a6
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#define mmMMEA2_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01 0x05a7
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#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23 0x05a8
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#define mmMMEA2_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_RM_SEL_CS01 0x05a9
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#define mmMMEA2_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_RM_SEL_CS23 0x05aa
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#define mmMMEA2_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01 0x05ab
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#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23 0x05ac
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#define mmMMEA2_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL 0x05ad
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#define mmMMEA2_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL 0x05ae
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#define mmMMEA2_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA2_IO_RD_CLI2GRP_MAP0 0x05d5
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#define mmMMEA2_IO_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA2_IO_RD_CLI2GRP_MAP1 0x05d6
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#define mmMMEA2_IO_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA2_IO_WR_CLI2GRP_MAP0 0x05d7
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#define mmMMEA2_IO_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA2_IO_WR_CLI2GRP_MAP1 0x05d8
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#define mmMMEA2_IO_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA2_IO_RD_COMBINE_FLUSH 0x05d9
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#define mmMMEA2_IO_RD_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA2_IO_WR_COMBINE_FLUSH 0x05da
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#define mmMMEA2_IO_WR_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA2_IO_GROUP_BURST 0x05db
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#define mmMMEA2_IO_GROUP_BURST_BASE_IDX 1
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#define mmMMEA2_IO_RD_PRI_AGE 0x05dc
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#define mmMMEA2_IO_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA2_IO_WR_PRI_AGE 0x05dd
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#define mmMMEA2_IO_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA2_IO_RD_PRI_QUEUING 0x05de
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#define mmMMEA2_IO_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA2_IO_WR_PRI_QUEUING 0x05df
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#define mmMMEA2_IO_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA2_IO_RD_PRI_FIXED 0x05e0
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#define mmMMEA2_IO_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA2_IO_WR_PRI_FIXED 0x05e1
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#define mmMMEA2_IO_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA2_IO_RD_PRI_URGENCY 0x05e2
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#define mmMMEA2_IO_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA2_IO_WR_PRI_URGENCY 0x05e3
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#define mmMMEA2_IO_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA2_IO_RD_PRI_URGENCY_MASKING 0x05e4
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#define mmMMEA2_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA2_IO_WR_PRI_URGENCY_MASKING 0x05e5
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#define mmMMEA2_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA2_IO_RD_PRI_QUANT_PRI1 0x05e6
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#define mmMMEA2_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA2_IO_RD_PRI_QUANT_PRI2 0x05e7
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#define mmMMEA2_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA2_IO_RD_PRI_QUANT_PRI3 0x05e8
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#define mmMMEA2_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA2_IO_WR_PRI_QUANT_PRI1 0x05e9
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#define mmMMEA2_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA2_IO_WR_PRI_QUANT_PRI2 0x05ea
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#define mmMMEA2_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA2_IO_WR_PRI_QUANT_PRI3 0x05eb
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#define mmMMEA2_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA2_SDP_ARB_DRAM 0x05ec
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#define mmMMEA2_SDP_ARB_DRAM_BASE_IDX 1
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#define mmMMEA2_SDP_ARB_GMI 0x05ed
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#define mmMMEA2_SDP_ARB_GMI_BASE_IDX 1
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#define mmMMEA2_SDP_ARB_FINAL 0x05ee
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#define mmMMEA2_SDP_ARB_FINAL_BASE_IDX 1
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#define mmMMEA2_SDP_DRAM_PRIORITY 0x05ef
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#define mmMMEA2_SDP_DRAM_PRIORITY_BASE_IDX 1
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#define mmMMEA2_SDP_GMI_PRIORITY 0x05f0
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#define mmMMEA2_SDP_GMI_PRIORITY_BASE_IDX 1
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#define mmMMEA2_SDP_IO_PRIORITY 0x05f1
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#define mmMMEA2_SDP_IO_PRIORITY_BASE_IDX 1
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#define mmMMEA2_SDP_CREDITS 0x05f2
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#define mmMMEA2_SDP_CREDITS_BASE_IDX 1
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#define mmMMEA2_SDP_TAG_RESERVE0 0x05f3
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#define mmMMEA2_SDP_TAG_RESERVE0_BASE_IDX 1
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#define mmMMEA2_SDP_TAG_RESERVE1 0x05f4
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#define mmMMEA2_SDP_TAG_RESERVE1_BASE_IDX 1
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#define mmMMEA2_SDP_VCC_RESERVE0 0x05f5
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#define mmMMEA2_SDP_VCC_RESERVE0_BASE_IDX 1
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#define mmMMEA2_SDP_VCC_RESERVE1 0x05f6
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#define mmMMEA2_SDP_VCC_RESERVE1_BASE_IDX 1
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#define mmMMEA2_SDP_VCD_RESERVE0 0x05f7
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#define mmMMEA2_SDP_VCD_RESERVE0_BASE_IDX 1
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#define mmMMEA2_SDP_VCD_RESERVE1 0x05f8
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#define mmMMEA2_SDP_VCD_RESERVE1_BASE_IDX 1
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#define mmMMEA2_SDP_REQ_CNTL 0x05f9
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#define mmMMEA2_SDP_REQ_CNTL_BASE_IDX 1
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#define mmMMEA2_MISC 0x05fa
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#define mmMMEA2_MISC_BASE_IDX 1
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#define mmMMEA2_LATENCY_SAMPLING 0x05fb
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#define mmMMEA2_LATENCY_SAMPLING_BASE_IDX 1
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#define mmMMEA2_PERFCOUNTER_LO 0x05fc
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#define mmMMEA2_PERFCOUNTER_LO_BASE_IDX 1
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#define mmMMEA2_PERFCOUNTER_HI 0x05fd
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#define mmMMEA2_PERFCOUNTER_HI_BASE_IDX 1
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#define mmMMEA2_PERFCOUNTER0_CFG 0x05fe
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#define mmMMEA2_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmMMEA2_PERFCOUNTER1_CFG 0x05ff
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#define mmMMEA2_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmMMEA2_PERFCOUNTER_RSLT_CNTL 0x0600
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#define mmMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmMMEA2_EDC_CNT 0x0606
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#define mmMMEA2_EDC_CNT_BASE_IDX 1
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#define mmMMEA2_EDC_CNT2 0x0607
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#define mmMMEA2_EDC_CNT2_BASE_IDX 1
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#define mmMMEA2_DSM_CNTL 0x0608
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#define mmMMEA2_DSM_CNTL_BASE_IDX 1
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#define mmMMEA2_DSM_CNTLA 0x0609
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#define mmMMEA2_DSM_CNTLA_BASE_IDX 1
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#define mmMMEA2_DSM_CNTLB 0x060a
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#define mmMMEA2_DSM_CNTLB_BASE_IDX 1
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#define mmMMEA2_DSM_CNTL2 0x060b
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#define mmMMEA2_DSM_CNTL2_BASE_IDX 1
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#define mmMMEA2_DSM_CNTL2A 0x060c
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#define mmMMEA2_DSM_CNTL2A_BASE_IDX 1
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#define mmMMEA2_DSM_CNTL2B 0x060d
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#define mmMMEA2_DSM_CNTL2B_BASE_IDX 1
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#define mmMMEA2_CGTT_CLK_CTRL 0x060f
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#define mmMMEA2_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmMMEA2_EDC_MODE 0x0610
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#define mmMMEA2_EDC_MODE_BASE_IDX 1
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#define mmMMEA2_ERR_STATUS 0x0611
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#define mmMMEA2_ERR_STATUS_BASE_IDX 1
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#define mmMMEA2_MISC2 0x0612
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#define mmMMEA2_MISC2_BASE_IDX 1
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#define mmMMEA2_ADDRDEC_SELECT 0x0613
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#define mmMMEA2_ADDRDEC_SELECT_BASE_IDX 1
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#define mmMMEA2_EDC_CNT3 0x0614
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#define mmMMEA2_EDC_CNT3_BASE_IDX 1
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// addressBlock: mmhub_ea_mmeadec3
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// base address: 0x69900
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#define mmMMEA3_DRAM_RD_CLI2GRP_MAP0 0x0640
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#define mmMMEA3_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA3_DRAM_RD_CLI2GRP_MAP1 0x0641
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#define mmMMEA3_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA3_DRAM_WR_CLI2GRP_MAP0 0x0642
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#define mmMMEA3_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA3_DRAM_WR_CLI2GRP_MAP1 0x0643
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#define mmMMEA3_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA3_DRAM_RD_GRP2VC_MAP 0x0644
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#define mmMMEA3_DRAM_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA3_DRAM_WR_GRP2VC_MAP 0x0645
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#define mmMMEA3_DRAM_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA3_DRAM_RD_LAZY 0x0646
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#define mmMMEA3_DRAM_RD_LAZY_BASE_IDX 1
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#define mmMMEA3_DRAM_WR_LAZY 0x0647
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#define mmMMEA3_DRAM_WR_LAZY_BASE_IDX 1
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#define mmMMEA3_DRAM_RD_CAM_CNTL 0x0648
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#define mmMMEA3_DRAM_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA3_DRAM_WR_CAM_CNTL 0x0649
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#define mmMMEA3_DRAM_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA3_DRAM_PAGE_BURST 0x064a
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#define mmMMEA3_DRAM_PAGE_BURST_BASE_IDX 1
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#define mmMMEA3_DRAM_RD_PRI_AGE 0x064b
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#define mmMMEA3_DRAM_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA3_DRAM_WR_PRI_AGE 0x064c
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#define mmMMEA3_DRAM_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA3_DRAM_RD_PRI_QUEUING 0x064d
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#define mmMMEA3_DRAM_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA3_DRAM_WR_PRI_QUEUING 0x064e
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#define mmMMEA3_DRAM_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA3_DRAM_RD_PRI_FIXED 0x064f
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#define mmMMEA3_DRAM_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA3_DRAM_WR_PRI_FIXED 0x0650
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#define mmMMEA3_DRAM_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA3_DRAM_RD_PRI_URGENCY 0x0651
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#define mmMMEA3_DRAM_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA3_DRAM_WR_PRI_URGENCY 0x0652
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#define mmMMEA3_DRAM_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1 0x0653
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#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2 0x0654
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#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3 0x0655
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#define mmMMEA3_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1 0x0656
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#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2 0x0657
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#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3 0x0658
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#define mmMMEA3_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA3_GMI_RD_CLI2GRP_MAP0 0x0659
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#define mmMMEA3_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA3_GMI_RD_CLI2GRP_MAP1 0x065a
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#define mmMMEA3_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA3_GMI_WR_CLI2GRP_MAP0 0x065b
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#define mmMMEA3_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA3_GMI_WR_CLI2GRP_MAP1 0x065c
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#define mmMMEA3_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA3_GMI_RD_GRP2VC_MAP 0x065d
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#define mmMMEA3_GMI_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA3_GMI_WR_GRP2VC_MAP 0x065e
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#define mmMMEA3_GMI_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA3_GMI_RD_LAZY 0x065f
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#define mmMMEA3_GMI_RD_LAZY_BASE_IDX 1
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#define mmMMEA3_GMI_WR_LAZY 0x0660
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#define mmMMEA3_GMI_WR_LAZY_BASE_IDX 1
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#define mmMMEA3_GMI_RD_CAM_CNTL 0x0661
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#define mmMMEA3_GMI_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA3_GMI_WR_CAM_CNTL 0x0662
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#define mmMMEA3_GMI_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA3_GMI_PAGE_BURST 0x0663
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#define mmMMEA3_GMI_PAGE_BURST_BASE_IDX 1
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#define mmMMEA3_GMI_RD_PRI_AGE 0x0664
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#define mmMMEA3_GMI_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA3_GMI_WR_PRI_AGE 0x0665
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#define mmMMEA3_GMI_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA3_GMI_RD_PRI_QUEUING 0x0666
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#define mmMMEA3_GMI_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA3_GMI_WR_PRI_QUEUING 0x0667
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#define mmMMEA3_GMI_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA3_GMI_RD_PRI_FIXED 0x0668
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#define mmMMEA3_GMI_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA3_GMI_WR_PRI_FIXED 0x0669
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#define mmMMEA3_GMI_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA3_GMI_RD_PRI_URGENCY 0x066a
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#define mmMMEA3_GMI_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA3_GMI_WR_PRI_URGENCY 0x066b
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#define mmMMEA3_GMI_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING 0x066c
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#define mmMMEA3_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING 0x066d
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#define mmMMEA3_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA3_GMI_RD_PRI_QUANT_PRI1 0x066e
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#define mmMMEA3_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA3_GMI_RD_PRI_QUANT_PRI2 0x066f
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#define mmMMEA3_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA3_GMI_RD_PRI_QUANT_PRI3 0x0670
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#define mmMMEA3_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA3_GMI_WR_PRI_QUANT_PRI1 0x0671
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#define mmMMEA3_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA3_GMI_WR_PRI_QUANT_PRI2 0x0672
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#define mmMMEA3_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA3_GMI_WR_PRI_QUANT_PRI3 0x0673
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#define mmMMEA3_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_BASE_ADDR0 0x0674
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#define mmMMEA3_ADDRNORM_BASE_ADDR0_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_LIMIT_ADDR0 0x0675
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#define mmMMEA3_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_BASE_ADDR1 0x0676
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#define mmMMEA3_ADDRNORM_BASE_ADDR1_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_LIMIT_ADDR1 0x0677
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#define mmMMEA3_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_OFFSET_ADDR1 0x0678
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#define mmMMEA3_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_BASE_ADDR2 0x0679
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#define mmMMEA3_ADDRNORM_BASE_ADDR2_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_LIMIT_ADDR2 0x067a
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#define mmMMEA3_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_BASE_ADDR3 0x067b
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#define mmMMEA3_ADDRNORM_BASE_ADDR3_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_LIMIT_ADDR3 0x067c
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#define mmMMEA3_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_OFFSET_ADDR3 0x067d
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#define mmMMEA3_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_BASE_ADDR4 0x067e
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#define mmMMEA3_ADDRNORM_BASE_ADDR4_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_LIMIT_ADDR4 0x067f
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#define mmMMEA3_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_BASE_ADDR5 0x0680
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#define mmMMEA3_ADDRNORM_BASE_ADDR5_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_LIMIT_ADDR5 0x0681
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#define mmMMEA3_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1
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#define mmMMEA3_ADDRNORM_OFFSET_ADDR5 0x0682
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#define mmMMEA3_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1
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#define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL 0x0683
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#define mmMMEA3_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1
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#define mmMMEA3_ADDRNORMGMI_HOLE_CNTL 0x0684
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#define mmMMEA3_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1
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#define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x0685
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#define mmMMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1
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#define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG 0x0686
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#define mmMMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1
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#define mmMMEA3_ADDRDEC_BANK_CFG 0x0687
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#define mmMMEA3_ADDRDEC_BANK_CFG_BASE_IDX 1
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#define mmMMEA3_ADDRDEC_MISC_CFG 0x0688
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#define mmMMEA3_ADDRDEC_MISC_CFG_BASE_IDX 1
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0 0x0689
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1 0x068a
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2 0x068b
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3 0x068c
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4 0x068d
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5 0x068e
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC 0x068f
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2 0x0690
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0 0x0691
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1 0x0692
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#define mmMMEA3_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1
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#define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE 0x0693
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#define mmMMEA3_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0 0x0694
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1 0x0695
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2 0x0696
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3 0x0697
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4 0x0698
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5 0x0699
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC 0x069a
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2 0x069b
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0 0x069c
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1 0x069d
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#define mmMMEA3_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1
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#define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE 0x069e
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#define mmMMEA3_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0 0x069f
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1 0x06a0
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2 0x06a1
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3 0x06a2
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0 0x06a3
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1 0x06a4
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2 0x06a5
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3 0x06a6
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#define mmMMEA3_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01 0x06a7
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#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23 0x06a8
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#define mmMMEA3_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01 0x06a9
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#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23 0x06aa
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#define mmMMEA3_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01 0x06ab
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#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23 0x06ac
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#define mmMMEA3_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01 0x06ad
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#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23 0x06ae
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#define mmMMEA3_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01 0x06af
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#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23 0x06b0
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#define mmMMEA3_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01 0x06b1
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#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23 0x06b2
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#define mmMMEA3_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01 0x06b3
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#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23 0x06b4
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#define mmMMEA3_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_RM_SEL_CS01 0x06b5
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#define mmMMEA3_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_RM_SEL_CS23 0x06b6
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#define mmMMEA3_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01 0x06b7
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#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23 0x06b8
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#define mmMMEA3_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0 0x06b9
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1 0x06ba
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2 0x06bb
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3 0x06bc
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0 0x06bd
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1 0x06be
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2 0x06bf
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3 0x06c0
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#define mmMMEA3_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01 0x06c1
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#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23 0x06c2
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#define mmMMEA3_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01 0x06c3
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#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23 0x06c4
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#define mmMMEA3_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01 0x06c5
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#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23 0x06c6
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#define mmMMEA3_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01 0x06c7
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#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23 0x06c8
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#define mmMMEA3_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01 0x06c9
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#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23 0x06ca
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#define mmMMEA3_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01 0x06cb
|
#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23 0x06cc
|
#define mmMMEA3_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01 0x06cd
|
#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23 0x06ce
|
#define mmMMEA3_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC1_RM_SEL_CS01 0x06cf
|
#define mmMMEA3_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC1_RM_SEL_CS23 0x06d0
|
#define mmMMEA3_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01 0x06d1
|
#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23 0x06d2
|
#define mmMMEA3_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0 0x06d3
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1 0x06d4
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2 0x06d5
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3 0x06d6
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0 0x06d7
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1 0x06d8
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2 0x06d9
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3 0x06da
|
#define mmMMEA3_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01 0x06db
|
#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23 0x06dc
|
#define mmMMEA3_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01 0x06dd
|
#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23 0x06de
|
#define mmMMEA3_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01 0x06df
|
#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23 0x06e0
|
#define mmMMEA3_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01 0x06e1
|
#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23 0x06e2
|
#define mmMMEA3_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01 0x06e3
|
#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23 0x06e4
|
#define mmMMEA3_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01 0x06e5
|
#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23 0x06e6
|
#define mmMMEA3_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01 0x06e7
|
#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23 0x06e8
|
#define mmMMEA3_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1
|
#define mmMMEA3_ADDRDEC2_RM_SEL_CS01 0x06e9
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#define mmMMEA3_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC2_RM_SEL_CS23 0x06ea
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#define mmMMEA3_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01 0x06eb
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#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23 0x06ec
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#define mmMMEA3_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL 0x06ed
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#define mmMMEA3_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL 0x06ee
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#define mmMMEA3_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA3_IO_RD_CLI2GRP_MAP0 0x0715
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#define mmMMEA3_IO_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA3_IO_RD_CLI2GRP_MAP1 0x0716
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#define mmMMEA3_IO_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA3_IO_WR_CLI2GRP_MAP0 0x0717
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#define mmMMEA3_IO_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA3_IO_WR_CLI2GRP_MAP1 0x0718
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#define mmMMEA3_IO_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA3_IO_RD_COMBINE_FLUSH 0x0719
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#define mmMMEA3_IO_RD_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA3_IO_WR_COMBINE_FLUSH 0x071a
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#define mmMMEA3_IO_WR_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA3_IO_GROUP_BURST 0x071b
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#define mmMMEA3_IO_GROUP_BURST_BASE_IDX 1
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#define mmMMEA3_IO_RD_PRI_AGE 0x071c
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#define mmMMEA3_IO_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA3_IO_WR_PRI_AGE 0x071d
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#define mmMMEA3_IO_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA3_IO_RD_PRI_QUEUING 0x071e
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#define mmMMEA3_IO_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA3_IO_WR_PRI_QUEUING 0x071f
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#define mmMMEA3_IO_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA3_IO_RD_PRI_FIXED 0x0720
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#define mmMMEA3_IO_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA3_IO_WR_PRI_FIXED 0x0721
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#define mmMMEA3_IO_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA3_IO_RD_PRI_URGENCY 0x0722
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#define mmMMEA3_IO_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA3_IO_WR_PRI_URGENCY 0x0723
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#define mmMMEA3_IO_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA3_IO_RD_PRI_URGENCY_MASKING 0x0724
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#define mmMMEA3_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA3_IO_WR_PRI_URGENCY_MASKING 0x0725
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#define mmMMEA3_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA3_IO_RD_PRI_QUANT_PRI1 0x0726
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#define mmMMEA3_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA3_IO_RD_PRI_QUANT_PRI2 0x0727
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#define mmMMEA3_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA3_IO_RD_PRI_QUANT_PRI3 0x0728
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#define mmMMEA3_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA3_IO_WR_PRI_QUANT_PRI1 0x0729
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#define mmMMEA3_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA3_IO_WR_PRI_QUANT_PRI2 0x072a
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#define mmMMEA3_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA3_IO_WR_PRI_QUANT_PRI3 0x072b
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#define mmMMEA3_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA3_SDP_ARB_DRAM 0x072c
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#define mmMMEA3_SDP_ARB_DRAM_BASE_IDX 1
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#define mmMMEA3_SDP_ARB_GMI 0x072d
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#define mmMMEA3_SDP_ARB_GMI_BASE_IDX 1
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#define mmMMEA3_SDP_ARB_FINAL 0x072e
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#define mmMMEA3_SDP_ARB_FINAL_BASE_IDX 1
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#define mmMMEA3_SDP_DRAM_PRIORITY 0x072f
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#define mmMMEA3_SDP_DRAM_PRIORITY_BASE_IDX 1
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#define mmMMEA3_SDP_GMI_PRIORITY 0x0730
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#define mmMMEA3_SDP_GMI_PRIORITY_BASE_IDX 1
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#define mmMMEA3_SDP_IO_PRIORITY 0x0731
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#define mmMMEA3_SDP_IO_PRIORITY_BASE_IDX 1
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#define mmMMEA3_SDP_CREDITS 0x0732
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#define mmMMEA3_SDP_CREDITS_BASE_IDX 1
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#define mmMMEA3_SDP_TAG_RESERVE0 0x0733
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#define mmMMEA3_SDP_TAG_RESERVE0_BASE_IDX 1
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#define mmMMEA3_SDP_TAG_RESERVE1 0x0734
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#define mmMMEA3_SDP_TAG_RESERVE1_BASE_IDX 1
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#define mmMMEA3_SDP_VCC_RESERVE0 0x0735
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#define mmMMEA3_SDP_VCC_RESERVE0_BASE_IDX 1
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#define mmMMEA3_SDP_VCC_RESERVE1 0x0736
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#define mmMMEA3_SDP_VCC_RESERVE1_BASE_IDX 1
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#define mmMMEA3_SDP_VCD_RESERVE0 0x0737
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#define mmMMEA3_SDP_VCD_RESERVE0_BASE_IDX 1
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#define mmMMEA3_SDP_VCD_RESERVE1 0x0738
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#define mmMMEA3_SDP_VCD_RESERVE1_BASE_IDX 1
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#define mmMMEA3_SDP_REQ_CNTL 0x0739
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#define mmMMEA3_SDP_REQ_CNTL_BASE_IDX 1
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#define mmMMEA3_MISC 0x073a
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#define mmMMEA3_MISC_BASE_IDX 1
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#define mmMMEA3_LATENCY_SAMPLING 0x073b
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#define mmMMEA3_LATENCY_SAMPLING_BASE_IDX 1
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#define mmMMEA3_PERFCOUNTER_LO 0x073c
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#define mmMMEA3_PERFCOUNTER_LO_BASE_IDX 1
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#define mmMMEA3_PERFCOUNTER_HI 0x073d
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#define mmMMEA3_PERFCOUNTER_HI_BASE_IDX 1
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#define mmMMEA3_PERFCOUNTER0_CFG 0x073e
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#define mmMMEA3_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmMMEA3_PERFCOUNTER1_CFG 0x073f
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#define mmMMEA3_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmMMEA3_PERFCOUNTER_RSLT_CNTL 0x0740
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#define mmMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmMMEA3_EDC_CNT 0x0746
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#define mmMMEA3_EDC_CNT_BASE_IDX 1
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#define mmMMEA3_EDC_CNT2 0x0747
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#define mmMMEA3_EDC_CNT2_BASE_IDX 1
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#define mmMMEA3_DSM_CNTL 0x0748
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#define mmMMEA3_DSM_CNTL_BASE_IDX 1
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#define mmMMEA3_DSM_CNTLA 0x0749
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#define mmMMEA3_DSM_CNTLA_BASE_IDX 1
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#define mmMMEA3_DSM_CNTLB 0x074a
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#define mmMMEA3_DSM_CNTLB_BASE_IDX 1
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#define mmMMEA3_DSM_CNTL2 0x074b
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#define mmMMEA3_DSM_CNTL2_BASE_IDX 1
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#define mmMMEA3_DSM_CNTL2A 0x074c
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#define mmMMEA3_DSM_CNTL2A_BASE_IDX 1
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#define mmMMEA3_DSM_CNTL2B 0x074d
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#define mmMMEA3_DSM_CNTL2B_BASE_IDX 1
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#define mmMMEA3_CGTT_CLK_CTRL 0x074f
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#define mmMMEA3_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmMMEA3_EDC_MODE 0x0750
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#define mmMMEA3_EDC_MODE_BASE_IDX 1
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#define mmMMEA3_ERR_STATUS 0x0751
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#define mmMMEA3_ERR_STATUS_BASE_IDX 1
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#define mmMMEA3_MISC2 0x0752
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#define mmMMEA3_MISC2_BASE_IDX 1
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#define mmMMEA3_ADDRDEC_SELECT 0x0753
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#define mmMMEA3_ADDRDEC_SELECT_BASE_IDX 1
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#define mmMMEA3_EDC_CNT3 0x0754
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#define mmMMEA3_EDC_CNT3_BASE_IDX 1
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// addressBlock: mmhub_ea_mmeadec4
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// base address: 0x69e00
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#define mmMMEA4_DRAM_RD_CLI2GRP_MAP0 0x0780
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#define mmMMEA4_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA4_DRAM_RD_CLI2GRP_MAP1 0x0781
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#define mmMMEA4_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA4_DRAM_WR_CLI2GRP_MAP0 0x0782
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#define mmMMEA4_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA4_DRAM_WR_CLI2GRP_MAP1 0x0783
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#define mmMMEA4_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA4_DRAM_RD_GRP2VC_MAP 0x0784
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#define mmMMEA4_DRAM_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA4_DRAM_WR_GRP2VC_MAP 0x0785
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#define mmMMEA4_DRAM_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA4_DRAM_RD_LAZY 0x0786
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#define mmMMEA4_DRAM_RD_LAZY_BASE_IDX 1
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#define mmMMEA4_DRAM_WR_LAZY 0x0787
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#define mmMMEA4_DRAM_WR_LAZY_BASE_IDX 1
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#define mmMMEA4_DRAM_RD_CAM_CNTL 0x0788
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#define mmMMEA4_DRAM_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA4_DRAM_WR_CAM_CNTL 0x0789
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#define mmMMEA4_DRAM_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA4_DRAM_PAGE_BURST 0x078a
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#define mmMMEA4_DRAM_PAGE_BURST_BASE_IDX 1
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#define mmMMEA4_DRAM_RD_PRI_AGE 0x078b
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#define mmMMEA4_DRAM_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA4_DRAM_WR_PRI_AGE 0x078c
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#define mmMMEA4_DRAM_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA4_DRAM_RD_PRI_QUEUING 0x078d
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#define mmMMEA4_DRAM_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA4_DRAM_WR_PRI_QUEUING 0x078e
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#define mmMMEA4_DRAM_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA4_DRAM_RD_PRI_FIXED 0x078f
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#define mmMMEA4_DRAM_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA4_DRAM_WR_PRI_FIXED 0x0790
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#define mmMMEA4_DRAM_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA4_DRAM_RD_PRI_URGENCY 0x0791
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#define mmMMEA4_DRAM_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA4_DRAM_WR_PRI_URGENCY 0x0792
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#define mmMMEA4_DRAM_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1 0x0793
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#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2 0x0794
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#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3 0x0795
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#define mmMMEA4_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1 0x0796
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#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2 0x0797
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#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3 0x0798
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#define mmMMEA4_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA4_GMI_RD_CLI2GRP_MAP0 0x0799
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#define mmMMEA4_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA4_GMI_RD_CLI2GRP_MAP1 0x079a
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#define mmMMEA4_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA4_GMI_WR_CLI2GRP_MAP0 0x079b
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#define mmMMEA4_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA4_GMI_WR_CLI2GRP_MAP1 0x079c
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#define mmMMEA4_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA4_GMI_RD_GRP2VC_MAP 0x079d
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#define mmMMEA4_GMI_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA4_GMI_WR_GRP2VC_MAP 0x079e
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#define mmMMEA4_GMI_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA4_GMI_RD_LAZY 0x079f
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#define mmMMEA4_GMI_RD_LAZY_BASE_IDX 1
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#define mmMMEA4_GMI_WR_LAZY 0x07a0
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#define mmMMEA4_GMI_WR_LAZY_BASE_IDX 1
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#define mmMMEA4_GMI_RD_CAM_CNTL 0x07a1
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#define mmMMEA4_GMI_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA4_GMI_WR_CAM_CNTL 0x07a2
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#define mmMMEA4_GMI_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA4_GMI_PAGE_BURST 0x07a3
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#define mmMMEA4_GMI_PAGE_BURST_BASE_IDX 1
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#define mmMMEA4_GMI_RD_PRI_AGE 0x07a4
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#define mmMMEA4_GMI_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA4_GMI_WR_PRI_AGE 0x07a5
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#define mmMMEA4_GMI_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA4_GMI_RD_PRI_QUEUING 0x07a6
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#define mmMMEA4_GMI_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA4_GMI_WR_PRI_QUEUING 0x07a7
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#define mmMMEA4_GMI_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA4_GMI_RD_PRI_FIXED 0x07a8
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#define mmMMEA4_GMI_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA4_GMI_WR_PRI_FIXED 0x07a9
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#define mmMMEA4_GMI_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA4_GMI_RD_PRI_URGENCY 0x07aa
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#define mmMMEA4_GMI_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA4_GMI_WR_PRI_URGENCY 0x07ab
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#define mmMMEA4_GMI_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING 0x07ac
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#define mmMMEA4_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING 0x07ad
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#define mmMMEA4_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA4_GMI_RD_PRI_QUANT_PRI1 0x07ae
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#define mmMMEA4_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA4_GMI_RD_PRI_QUANT_PRI2 0x07af
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#define mmMMEA4_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA4_GMI_RD_PRI_QUANT_PRI3 0x07b0
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#define mmMMEA4_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA4_GMI_WR_PRI_QUANT_PRI1 0x07b1
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#define mmMMEA4_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA4_GMI_WR_PRI_QUANT_PRI2 0x07b2
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#define mmMMEA4_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA4_GMI_WR_PRI_QUANT_PRI3 0x07b3
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#define mmMMEA4_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_BASE_ADDR0 0x07b4
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#define mmMMEA4_ADDRNORM_BASE_ADDR0_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_LIMIT_ADDR0 0x07b5
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#define mmMMEA4_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_BASE_ADDR1 0x07b6
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#define mmMMEA4_ADDRNORM_BASE_ADDR1_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_LIMIT_ADDR1 0x07b7
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#define mmMMEA4_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_OFFSET_ADDR1 0x07b8
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#define mmMMEA4_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_BASE_ADDR2 0x07b9
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#define mmMMEA4_ADDRNORM_BASE_ADDR2_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_LIMIT_ADDR2 0x07ba
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#define mmMMEA4_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_BASE_ADDR3 0x07bb
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#define mmMMEA4_ADDRNORM_BASE_ADDR3_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_LIMIT_ADDR3 0x07bc
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#define mmMMEA4_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_OFFSET_ADDR3 0x07bd
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#define mmMMEA4_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_BASE_ADDR4 0x07be
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#define mmMMEA4_ADDRNORM_BASE_ADDR4_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_LIMIT_ADDR4 0x07bf
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#define mmMMEA4_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_BASE_ADDR5 0x07c0
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#define mmMMEA4_ADDRNORM_BASE_ADDR5_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_LIMIT_ADDR5 0x07c1
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#define mmMMEA4_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1
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#define mmMMEA4_ADDRNORM_OFFSET_ADDR5 0x07c2
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#define mmMMEA4_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1
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#define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL 0x07c3
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#define mmMMEA4_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1
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#define mmMMEA4_ADDRNORMGMI_HOLE_CNTL 0x07c4
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#define mmMMEA4_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1
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#define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x07c5
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#define mmMMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1
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#define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG 0x07c6
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#define mmMMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1
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#define mmMMEA4_ADDRDEC_BANK_CFG 0x07c7
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#define mmMMEA4_ADDRDEC_BANK_CFG_BASE_IDX 1
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#define mmMMEA4_ADDRDEC_MISC_CFG 0x07c8
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#define mmMMEA4_ADDRDEC_MISC_CFG_BASE_IDX 1
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0 0x07c9
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1 0x07ca
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2 0x07cb
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3 0x07cc
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4 0x07cd
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5 0x07ce
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC 0x07cf
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2 0x07d0
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0 0x07d1
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1 0x07d2
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#define mmMMEA4_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1
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#define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE 0x07d3
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#define mmMMEA4_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0 0x07d4
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1 0x07d5
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2 0x07d6
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3 0x07d7
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4 0x07d8
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5 0x07d9
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC 0x07da
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2 0x07db
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0 0x07dc
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1 0x07dd
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#define mmMMEA4_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1
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#define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE 0x07de
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#define mmMMEA4_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0 0x07df
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1 0x07e0
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2 0x07e1
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3 0x07e2
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0 0x07e3
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1 0x07e4
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2 0x07e5
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3 0x07e6
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#define mmMMEA4_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01 0x07e7
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#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23 0x07e8
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#define mmMMEA4_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01 0x07e9
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#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23 0x07ea
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#define mmMMEA4_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01 0x07eb
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#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23 0x07ec
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#define mmMMEA4_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01 0x07ed
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#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23 0x07ee
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#define mmMMEA4_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01 0x07ef
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#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23 0x07f0
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#define mmMMEA4_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01 0x07f1
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#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23 0x07f2
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#define mmMMEA4_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01 0x07f3
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#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23 0x07f4
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#define mmMMEA4_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_RM_SEL_CS01 0x07f5
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#define mmMMEA4_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_RM_SEL_CS23 0x07f6
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#define mmMMEA4_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01 0x07f7
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#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23 0x07f8
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#define mmMMEA4_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0 0x07f9
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1 0x07fa
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2 0x07fb
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3 0x07fc
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0 0x07fd
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1 0x07fe
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2 0x07ff
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3 0x0800
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#define mmMMEA4_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01 0x0801
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#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23 0x0802
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#define mmMMEA4_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01 0x0803
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#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23 0x0804
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#define mmMMEA4_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01 0x0805
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#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23 0x0806
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#define mmMMEA4_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01 0x0807
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#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23 0x0808
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#define mmMMEA4_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01 0x0809
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#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23 0x080a
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#define mmMMEA4_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01 0x080b
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#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23 0x080c
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#define mmMMEA4_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01 0x080d
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#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23 0x080e
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#define mmMMEA4_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_RM_SEL_CS01 0x080f
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#define mmMMEA4_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_RM_SEL_CS23 0x0810
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#define mmMMEA4_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01 0x0811
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#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23 0x0812
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#define mmMMEA4_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0 0x0813
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1 0x0814
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2 0x0815
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3 0x0816
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0 0x0817
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1 0x0818
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2 0x0819
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3 0x081a
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#define mmMMEA4_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01 0x081b
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#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23 0x081c
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#define mmMMEA4_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01 0x081d
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#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23 0x081e
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#define mmMMEA4_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01 0x081f
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#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23 0x0820
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#define mmMMEA4_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01 0x0821
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#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23 0x0822
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#define mmMMEA4_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01 0x0823
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#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23 0x0824
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#define mmMMEA4_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01 0x0825
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#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23 0x0826
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#define mmMMEA4_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01 0x0827
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#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23 0x0828
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#define mmMMEA4_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_RM_SEL_CS01 0x0829
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#define mmMMEA4_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_RM_SEL_CS23 0x082a
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#define mmMMEA4_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01 0x082b
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#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23 0x082c
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#define mmMMEA4_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL 0x082d
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#define mmMMEA4_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL 0x082e
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#define mmMMEA4_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA4_IO_RD_CLI2GRP_MAP0 0x0855
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#define mmMMEA4_IO_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA4_IO_RD_CLI2GRP_MAP1 0x0856
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#define mmMMEA4_IO_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA4_IO_WR_CLI2GRP_MAP0 0x0857
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#define mmMMEA4_IO_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA4_IO_WR_CLI2GRP_MAP1 0x0858
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#define mmMMEA4_IO_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA4_IO_RD_COMBINE_FLUSH 0x0859
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#define mmMMEA4_IO_RD_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA4_IO_WR_COMBINE_FLUSH 0x085a
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#define mmMMEA4_IO_WR_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA4_IO_GROUP_BURST 0x085b
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#define mmMMEA4_IO_GROUP_BURST_BASE_IDX 1
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#define mmMMEA4_IO_RD_PRI_AGE 0x085c
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#define mmMMEA4_IO_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA4_IO_WR_PRI_AGE 0x085d
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#define mmMMEA4_IO_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA4_IO_RD_PRI_QUEUING 0x085e
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#define mmMMEA4_IO_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA4_IO_WR_PRI_QUEUING 0x085f
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#define mmMMEA4_IO_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA4_IO_RD_PRI_FIXED 0x0860
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#define mmMMEA4_IO_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA4_IO_WR_PRI_FIXED 0x0861
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#define mmMMEA4_IO_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA4_IO_RD_PRI_URGENCY 0x0862
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#define mmMMEA4_IO_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA4_IO_WR_PRI_URGENCY 0x0863
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#define mmMMEA4_IO_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA4_IO_RD_PRI_URGENCY_MASKING 0x0864
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#define mmMMEA4_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA4_IO_WR_PRI_URGENCY_MASKING 0x0865
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#define mmMMEA4_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA4_IO_RD_PRI_QUANT_PRI1 0x0866
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#define mmMMEA4_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA4_IO_RD_PRI_QUANT_PRI2 0x0867
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#define mmMMEA4_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA4_IO_RD_PRI_QUANT_PRI3 0x0868
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#define mmMMEA4_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA4_IO_WR_PRI_QUANT_PRI1 0x0869
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#define mmMMEA4_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA4_IO_WR_PRI_QUANT_PRI2 0x086a
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#define mmMMEA4_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA4_IO_WR_PRI_QUANT_PRI3 0x086b
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#define mmMMEA4_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA4_SDP_ARB_DRAM 0x086c
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#define mmMMEA4_SDP_ARB_DRAM_BASE_IDX 1
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#define mmMMEA4_SDP_ARB_GMI 0x086d
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#define mmMMEA4_SDP_ARB_GMI_BASE_IDX 1
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#define mmMMEA4_SDP_ARB_FINAL 0x086e
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#define mmMMEA4_SDP_ARB_FINAL_BASE_IDX 1
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#define mmMMEA4_SDP_DRAM_PRIORITY 0x086f
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#define mmMMEA4_SDP_DRAM_PRIORITY_BASE_IDX 1
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#define mmMMEA4_SDP_GMI_PRIORITY 0x0870
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#define mmMMEA4_SDP_GMI_PRIORITY_BASE_IDX 1
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#define mmMMEA4_SDP_IO_PRIORITY 0x0871
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#define mmMMEA4_SDP_IO_PRIORITY_BASE_IDX 1
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#define mmMMEA4_SDP_CREDITS 0x0872
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#define mmMMEA4_SDP_CREDITS_BASE_IDX 1
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#define mmMMEA4_SDP_TAG_RESERVE0 0x0873
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#define mmMMEA4_SDP_TAG_RESERVE0_BASE_IDX 1
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#define mmMMEA4_SDP_TAG_RESERVE1 0x0874
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#define mmMMEA4_SDP_TAG_RESERVE1_BASE_IDX 1
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#define mmMMEA4_SDP_VCC_RESERVE0 0x0875
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#define mmMMEA4_SDP_VCC_RESERVE0_BASE_IDX 1
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#define mmMMEA4_SDP_VCC_RESERVE1 0x0876
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#define mmMMEA4_SDP_VCC_RESERVE1_BASE_IDX 1
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#define mmMMEA4_SDP_VCD_RESERVE0 0x0877
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#define mmMMEA4_SDP_VCD_RESERVE0_BASE_IDX 1
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#define mmMMEA4_SDP_VCD_RESERVE1 0x0878
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#define mmMMEA4_SDP_VCD_RESERVE1_BASE_IDX 1
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#define mmMMEA4_SDP_REQ_CNTL 0x0879
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#define mmMMEA4_SDP_REQ_CNTL_BASE_IDX 1
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#define mmMMEA4_MISC 0x087a
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#define mmMMEA4_MISC_BASE_IDX 1
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#define mmMMEA4_LATENCY_SAMPLING 0x087b
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#define mmMMEA4_LATENCY_SAMPLING_BASE_IDX 1
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#define mmMMEA4_PERFCOUNTER_LO 0x087c
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#define mmMMEA4_PERFCOUNTER_LO_BASE_IDX 1
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#define mmMMEA4_PERFCOUNTER_HI 0x087d
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#define mmMMEA4_PERFCOUNTER_HI_BASE_IDX 1
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#define mmMMEA4_PERFCOUNTER0_CFG 0x087e
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#define mmMMEA4_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmMMEA4_PERFCOUNTER1_CFG 0x087f
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#define mmMMEA4_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmMMEA4_PERFCOUNTER_RSLT_CNTL 0x0880
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#define mmMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmMMEA4_EDC_CNT 0x0886
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#define mmMMEA4_EDC_CNT_BASE_IDX 1
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#define mmMMEA4_EDC_CNT2 0x0887
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#define mmMMEA4_EDC_CNT2_BASE_IDX 1
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#define mmMMEA4_DSM_CNTL 0x0888
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#define mmMMEA4_DSM_CNTL_BASE_IDX 1
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#define mmMMEA4_DSM_CNTLA 0x0889
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#define mmMMEA4_DSM_CNTLA_BASE_IDX 1
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#define mmMMEA4_DSM_CNTLB 0x088a
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#define mmMMEA4_DSM_CNTLB_BASE_IDX 1
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#define mmMMEA4_DSM_CNTL2 0x088b
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#define mmMMEA4_DSM_CNTL2_BASE_IDX 1
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#define mmMMEA4_DSM_CNTL2A 0x088c
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#define mmMMEA4_DSM_CNTL2A_BASE_IDX 1
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#define mmMMEA4_DSM_CNTL2B 0x088d
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#define mmMMEA4_DSM_CNTL2B_BASE_IDX 1
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#define mmMMEA4_CGTT_CLK_CTRL 0x088f
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#define mmMMEA4_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmMMEA4_EDC_MODE 0x0890
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#define mmMMEA4_EDC_MODE_BASE_IDX 1
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#define mmMMEA4_ERR_STATUS 0x0891
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#define mmMMEA4_ERR_STATUS_BASE_IDX 1
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#define mmMMEA4_MISC2 0x0892
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#define mmMMEA4_MISC2_BASE_IDX 1
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#define mmMMEA4_ADDRDEC_SELECT 0x0893
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#define mmMMEA4_ADDRDEC_SELECT_BASE_IDX 1
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#define mmMMEA4_EDC_CNT3 0x0894
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#define mmMMEA4_EDC_CNT3_BASE_IDX 1
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// addressBlock: mmhub_pctldec0
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// base address: 0x6a300
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#define mmPCTL0_CTRL 0x08c0
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#define mmPCTL0_CTRL_BASE_IDX 1
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#define mmPCTL0_MMHUB_DEEPSLEEP_IB 0x08c1
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#define mmPCTL0_MMHUB_DEEPSLEEP_IB_BASE_IDX 1
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#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE 0x08c2
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#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1
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#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x08c3
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#define mmPCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1
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#define mmPCTL0_PG_IGNORE_DEEPSLEEP 0x08c4
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#define mmPCTL0_PG_IGNORE_DEEPSLEEP_BASE_IDX 1
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#define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB 0x08c5
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#define mmPCTL0_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1
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#define mmPCTL0_SLICE0_CFG_DAGB_BUSY 0x08c6
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#define mmPCTL0_SLICE0_CFG_DAGB_BUSY_BASE_IDX 1
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#define mmPCTL0_SLICE0_CFG_DS_ALLOW 0x08c7
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#define mmPCTL0_SLICE0_CFG_DS_ALLOW_BASE_IDX 1
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#define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB 0x08c8
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#define mmPCTL0_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1
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#define mmPCTL0_SLICE1_CFG_DAGB_BUSY 0x08c9
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#define mmPCTL0_SLICE1_CFG_DAGB_BUSY_BASE_IDX 1
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#define mmPCTL0_SLICE1_CFG_DS_ALLOW 0x08ca
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#define mmPCTL0_SLICE1_CFG_DS_ALLOW_BASE_IDX 1
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#define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB 0x08cb
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#define mmPCTL0_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1
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#define mmPCTL0_SLICE2_CFG_DAGB_BUSY 0x08cc
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#define mmPCTL0_SLICE2_CFG_DAGB_BUSY_BASE_IDX 1
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#define mmPCTL0_SLICE2_CFG_DS_ALLOW 0x08cd
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#define mmPCTL0_SLICE2_CFG_DS_ALLOW_BASE_IDX 1
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#define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB 0x08ce
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#define mmPCTL0_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 1
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#define mmPCTL0_SLICE3_CFG_DAGB_BUSY 0x08cf
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#define mmPCTL0_SLICE3_CFG_DAGB_BUSY_BASE_IDX 1
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#define mmPCTL0_SLICE3_CFG_DS_ALLOW 0x08d0
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#define mmPCTL0_SLICE3_CFG_DS_ALLOW_BASE_IDX 1
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#define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB 0x08d1
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#define mmPCTL0_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 1
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#define mmPCTL0_SLICE4_CFG_DAGB_BUSY 0x08d2
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#define mmPCTL0_SLICE4_CFG_DAGB_BUSY_BASE_IDX 1
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#define mmPCTL0_SLICE4_CFG_DS_ALLOW 0x08d3
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#define mmPCTL0_SLICE4_CFG_DS_ALLOW_BASE_IDX 1
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#define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB 0x08d4
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#define mmPCTL0_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 1
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#define mmPCTL0_UTCL2_MISC 0x08d5
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#define mmPCTL0_UTCL2_MISC_BASE_IDX 1
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#define mmPCTL0_SLICE0_MISC 0x08d6
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#define mmPCTL0_SLICE0_MISC_BASE_IDX 1
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#define mmPCTL0_SLICE1_MISC 0x08d7
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#define mmPCTL0_SLICE1_MISC_BASE_IDX 1
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#define mmPCTL0_SLICE2_MISC 0x08d8
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#define mmPCTL0_SLICE2_MISC_BASE_IDX 1
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#define mmPCTL0_SLICE3_MISC 0x08d9
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#define mmPCTL0_SLICE3_MISC_BASE_IDX 1
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#define mmPCTL0_SLICE4_MISC 0x08da
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#define mmPCTL0_SLICE4_MISC_BASE_IDX 1
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#define mmPCTL0_UTCL2_RENG_EXECUTE 0x08db
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#define mmPCTL0_UTCL2_RENG_EXECUTE_BASE_IDX 1
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#define mmPCTL0_SLICE0_RENG_EXECUTE 0x08dc
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#define mmPCTL0_SLICE0_RENG_EXECUTE_BASE_IDX 1
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#define mmPCTL0_SLICE1_RENG_EXECUTE 0x08dd
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#define mmPCTL0_SLICE1_RENG_EXECUTE_BASE_IDX 1
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#define mmPCTL0_SLICE2_RENG_EXECUTE 0x08de
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#define mmPCTL0_SLICE2_RENG_EXECUTE_BASE_IDX 1
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#define mmPCTL0_SLICE3_RENG_EXECUTE 0x08df
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#define mmPCTL0_SLICE3_RENG_EXECUTE_BASE_IDX 1
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#define mmPCTL0_SLICE4_RENG_EXECUTE 0x08e0
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#define mmPCTL0_SLICE4_RENG_EXECUTE_BASE_IDX 1
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#define mmPCTL0_UTCL2_RENG_RAM_INDEX 0x08e1
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#define mmPCTL0_UTCL2_RENG_RAM_INDEX_BASE_IDX 1
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#define mmPCTL0_UTCL2_RENG_RAM_DATA 0x08e2
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#define mmPCTL0_UTCL2_RENG_RAM_DATA_BASE_IDX 1
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#define mmPCTL0_SLICE0_RENG_RAM_INDEX 0x08e3
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#define mmPCTL0_SLICE0_RENG_RAM_INDEX_BASE_IDX 1
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#define mmPCTL0_SLICE0_RENG_RAM_DATA 0x08e4
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#define mmPCTL0_SLICE0_RENG_RAM_DATA_BASE_IDX 1
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#define mmPCTL0_SLICE1_RENG_RAM_INDEX 0x08e5
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#define mmPCTL0_SLICE1_RENG_RAM_INDEX_BASE_IDX 1
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#define mmPCTL0_SLICE1_RENG_RAM_DATA 0x08e6
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#define mmPCTL0_SLICE1_RENG_RAM_DATA_BASE_IDX 1
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#define mmPCTL0_SLICE2_RENG_RAM_INDEX 0x08e7
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#define mmPCTL0_SLICE2_RENG_RAM_INDEX_BASE_IDX 1
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#define mmPCTL0_SLICE2_RENG_RAM_DATA 0x08e8
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#define mmPCTL0_SLICE2_RENG_RAM_DATA_BASE_IDX 1
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#define mmPCTL0_SLICE3_RENG_RAM_INDEX 0x08e9
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#define mmPCTL0_SLICE3_RENG_RAM_INDEX_BASE_IDX 1
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#define mmPCTL0_SLICE3_RENG_RAM_DATA 0x08ea
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#define mmPCTL0_SLICE3_RENG_RAM_DATA_BASE_IDX 1
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#define mmPCTL0_SLICE4_RENG_RAM_INDEX 0x08eb
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#define mmPCTL0_SLICE4_RENG_RAM_INDEX_BASE_IDX 1
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#define mmPCTL0_SLICE4_RENG_RAM_DATA 0x08ec
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#define mmPCTL0_SLICE4_RENG_RAM_DATA_BASE_IDX 1
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x08ed
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x08ee
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x08ef
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x08f0
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x08f1
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x08f2
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x08f3
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#define mmPCTL0_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x08f4
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x08f5
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x08f6
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x08f7
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x08f8
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x08f9
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x08fa
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#define mmPCTL0_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x08fb
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x08fc
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x08fd
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x08fe
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x08ff
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0900
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0901
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#define mmPCTL0_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 0x0902
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 0x0903
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 0x0904
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 0x0905
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 0x0906
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0907
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0908
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#define mmPCTL0_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 0x0909
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 0x090a
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 0x090b
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 0x090c
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 0x090d
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 0x090e
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 0x090f
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#define mmPCTL0_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 0x0910
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 0x0911
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 0x0912
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 0x0913
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 0x0914
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 0x0915
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 0x0916
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#define mmPCTL0_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
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// addressBlock: mmhub_l1tlb_vml1dec
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// base address: 0x6a500
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#define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS 0x0948
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#define mmVML1_0_MC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1
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#define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS 0x0949
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#define mmVML1_0_MC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1
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#define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS 0x094a
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#define mmVML1_0_MC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1
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#define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS 0x094b
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#define mmVML1_0_MC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1
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#define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS 0x094c
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#define mmVML1_0_MC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1
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#define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS 0x094d
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#define mmVML1_0_MC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1
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#define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS 0x094e
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#define mmVML1_0_MC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1
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#define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS 0x094f
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#define mmVML1_0_MC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1
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// addressBlock: mmhub_l1tlb_vml1pldec
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// base address: 0x6a580
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#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG 0x0960
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#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG 0x0961
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#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG 0x0962
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#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1
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#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG 0x0963
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#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1
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#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x0964
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#define mmVML1PL0_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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// addressBlock: mmhub_l1tlb_vml1prdec
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// base address: 0x6a5c0
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#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO 0x0970
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#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1
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#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI 0x0971
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#define mmVML1PR0_MC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1
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// addressBlock: mmhub_utcl2_atcl2dec
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// base address: 0x6a600
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#define mmATCL2_0_ATC_L2_CNTL 0x0980
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#define mmATCL2_0_ATC_L2_CNTL_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_CNTL2 0x0981
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#define mmATCL2_0_ATC_L2_CNTL2_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_CACHE_DATA0 0x0984
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#define mmATCL2_0_ATC_L2_CACHE_DATA0_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_CACHE_DATA1 0x0985
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#define mmATCL2_0_ATC_L2_CACHE_DATA1_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_CACHE_DATA2 0x0986
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#define mmATCL2_0_ATC_L2_CACHE_DATA2_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_CNTL3 0x0987
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#define mmATCL2_0_ATC_L2_CNTL3_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_STATUS 0x0988
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#define mmATCL2_0_ATC_L2_STATUS_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_STATUS2 0x0989
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#define mmATCL2_0_ATC_L2_STATUS2_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_STATUS3 0x098a
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#define mmATCL2_0_ATC_L2_STATUS3_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_MISC_CG 0x098b
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#define mmATCL2_0_ATC_L2_MISC_CG_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_MEM_POWER_LS 0x098c
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#define mmATCL2_0_ATC_L2_MEM_POWER_LS_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL 0x098d
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#define mmATCL2_0_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX 0x098e
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#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX 0x098f
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#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL 0x0990
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#define mmATCL2_0_ATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL 0x0991
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#define mmATCL2_0_ATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_CNTL4 0x0992
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#define mmATCL2_0_ATC_L2_CNTL4_BASE_IDX 1
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#define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES 0x0993
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#define mmATCL2_0_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vml2pfdec
|
// base address: 0x6a700
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#define mmVML2PF0_VM_L2_CNTL 0x09c0
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#define mmVML2PF0_VM_L2_CNTL_BASE_IDX 1
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#define mmVML2PF0_VM_L2_CNTL2 0x09c1
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#define mmVML2PF0_VM_L2_CNTL2_BASE_IDX 1
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#define mmVML2PF0_VM_L2_CNTL3 0x09c2
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#define mmVML2PF0_VM_L2_CNTL3_BASE_IDX 1
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#define mmVML2PF0_VM_L2_STATUS 0x09c3
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#define mmVML2PF0_VM_L2_STATUS_BASE_IDX 1
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#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL 0x09c4
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#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1
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#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32 0x09c5
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#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1
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#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32 0x09c6
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#define mmVML2PF0_VM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL 0x09c7
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2 0x09c8
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3 0x09c9
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4 0x09ca
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS 0x09cb
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32 0x09cc
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32 0x09cd
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x09ce
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x09cf
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#define mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1
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#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x09d1
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#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1
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#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x09d2
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#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1
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#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x09d3
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#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1
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#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x09d4
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#define mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1
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#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x09d5
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#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1
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#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x09d6
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#define mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1
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#define mmVML2PF0_VM_L2_CNTL4 0x09d7
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#define mmVML2PF0_VM_L2_CNTL4_BASE_IDX 1
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#define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES 0x09d8
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#define mmVML2PF0_VM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1
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#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID 0x09d9
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#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1
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#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2 0x09da
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#define mmVML2PF0_VM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1
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#define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL 0x09db
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#define mmVML2PF0_VM_L2_CACHE_PARITY_CNTL_BASE_IDX 1
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#define mmVML2PF0_VM_L2_CGTT_CLK_CTRL 0x09de
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#define mmVML2PF0_VM_L2_CGTT_CLK_CTRL_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vml2vcdec
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// base address: 0x6a800
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#define mmVML2VC0_VM_CONTEXT0_CNTL 0x0a00
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#define mmVML2VC0_VM_CONTEXT0_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT1_CNTL 0x0a01
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#define mmVML2VC0_VM_CONTEXT1_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT2_CNTL 0x0a02
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#define mmVML2VC0_VM_CONTEXT2_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT3_CNTL 0x0a03
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#define mmVML2VC0_VM_CONTEXT3_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT4_CNTL 0x0a04
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#define mmVML2VC0_VM_CONTEXT4_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT5_CNTL 0x0a05
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#define mmVML2VC0_VM_CONTEXT5_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT6_CNTL 0x0a06
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#define mmVML2VC0_VM_CONTEXT6_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT7_CNTL 0x0a07
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#define mmVML2VC0_VM_CONTEXT7_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT8_CNTL 0x0a08
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#define mmVML2VC0_VM_CONTEXT8_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT9_CNTL 0x0a09
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#define mmVML2VC0_VM_CONTEXT9_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT10_CNTL 0x0a0a
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#define mmVML2VC0_VM_CONTEXT10_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT11_CNTL 0x0a0b
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#define mmVML2VC0_VM_CONTEXT11_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT12_CNTL 0x0a0c
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#define mmVML2VC0_VM_CONTEXT12_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT13_CNTL 0x0a0d
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#define mmVML2VC0_VM_CONTEXT13_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT14_CNTL 0x0a0e
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#define mmVML2VC0_VM_CONTEXT14_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT15_CNTL 0x0a0f
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#define mmVML2VC0_VM_CONTEXT15_CNTL_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXTS_DISABLE 0x0a10
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#define mmVML2VC0_VM_CONTEXTS_DISABLE_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG0_SEM 0x0a11
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#define mmVML2VC0_VM_INVALIDATE_ENG0_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG1_SEM 0x0a12
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#define mmVML2VC0_VM_INVALIDATE_ENG1_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG2_SEM 0x0a13
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#define mmVML2VC0_VM_INVALIDATE_ENG2_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG3_SEM 0x0a14
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#define mmVML2VC0_VM_INVALIDATE_ENG3_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG4_SEM 0x0a15
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#define mmVML2VC0_VM_INVALIDATE_ENG4_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG5_SEM 0x0a16
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#define mmVML2VC0_VM_INVALIDATE_ENG5_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG6_SEM 0x0a17
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#define mmVML2VC0_VM_INVALIDATE_ENG6_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG7_SEM 0x0a18
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#define mmVML2VC0_VM_INVALIDATE_ENG7_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG8_SEM 0x0a19
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#define mmVML2VC0_VM_INVALIDATE_ENG8_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG9_SEM 0x0a1a
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#define mmVML2VC0_VM_INVALIDATE_ENG9_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG10_SEM 0x0a1b
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#define mmVML2VC0_VM_INVALIDATE_ENG10_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG11_SEM 0x0a1c
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#define mmVML2VC0_VM_INVALIDATE_ENG11_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG12_SEM 0x0a1d
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#define mmVML2VC0_VM_INVALIDATE_ENG12_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG13_SEM 0x0a1e
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#define mmVML2VC0_VM_INVALIDATE_ENG13_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG14_SEM 0x0a1f
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#define mmVML2VC0_VM_INVALIDATE_ENG14_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG15_SEM 0x0a20
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#define mmVML2VC0_VM_INVALIDATE_ENG15_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG16_SEM 0x0a21
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#define mmVML2VC0_VM_INVALIDATE_ENG16_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG17_SEM 0x0a22
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#define mmVML2VC0_VM_INVALIDATE_ENG17_SEM_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG0_REQ 0x0a23
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#define mmVML2VC0_VM_INVALIDATE_ENG0_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG1_REQ 0x0a24
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#define mmVML2VC0_VM_INVALIDATE_ENG1_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG2_REQ 0x0a25
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#define mmVML2VC0_VM_INVALIDATE_ENG2_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG3_REQ 0x0a26
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#define mmVML2VC0_VM_INVALIDATE_ENG3_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG4_REQ 0x0a27
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#define mmVML2VC0_VM_INVALIDATE_ENG4_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG5_REQ 0x0a28
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#define mmVML2VC0_VM_INVALIDATE_ENG5_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG6_REQ 0x0a29
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#define mmVML2VC0_VM_INVALIDATE_ENG6_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG7_REQ 0x0a2a
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#define mmVML2VC0_VM_INVALIDATE_ENG7_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG8_REQ 0x0a2b
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#define mmVML2VC0_VM_INVALIDATE_ENG8_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG9_REQ 0x0a2c
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#define mmVML2VC0_VM_INVALIDATE_ENG9_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG10_REQ 0x0a2d
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#define mmVML2VC0_VM_INVALIDATE_ENG10_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG11_REQ 0x0a2e
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#define mmVML2VC0_VM_INVALIDATE_ENG11_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG12_REQ 0x0a2f
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#define mmVML2VC0_VM_INVALIDATE_ENG12_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG13_REQ 0x0a30
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#define mmVML2VC0_VM_INVALIDATE_ENG13_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG14_REQ 0x0a31
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#define mmVML2VC0_VM_INVALIDATE_ENG14_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG15_REQ 0x0a32
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#define mmVML2VC0_VM_INVALIDATE_ENG15_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG16_REQ 0x0a33
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#define mmVML2VC0_VM_INVALIDATE_ENG16_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG17_REQ 0x0a34
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#define mmVML2VC0_VM_INVALIDATE_ENG17_REQ_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG0_ACK 0x0a35
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#define mmVML2VC0_VM_INVALIDATE_ENG0_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG1_ACK 0x0a36
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#define mmVML2VC0_VM_INVALIDATE_ENG1_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG2_ACK 0x0a37
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#define mmVML2VC0_VM_INVALIDATE_ENG2_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG3_ACK 0x0a38
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#define mmVML2VC0_VM_INVALIDATE_ENG3_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG4_ACK 0x0a39
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#define mmVML2VC0_VM_INVALIDATE_ENG4_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG5_ACK 0x0a3a
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#define mmVML2VC0_VM_INVALIDATE_ENG5_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG6_ACK 0x0a3b
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#define mmVML2VC0_VM_INVALIDATE_ENG6_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG7_ACK 0x0a3c
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#define mmVML2VC0_VM_INVALIDATE_ENG7_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG8_ACK 0x0a3d
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#define mmVML2VC0_VM_INVALIDATE_ENG8_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG9_ACK 0x0a3e
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#define mmVML2VC0_VM_INVALIDATE_ENG9_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG10_ACK 0x0a3f
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#define mmVML2VC0_VM_INVALIDATE_ENG10_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG11_ACK 0x0a40
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#define mmVML2VC0_VM_INVALIDATE_ENG11_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG12_ACK 0x0a41
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#define mmVML2VC0_VM_INVALIDATE_ENG12_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG13_ACK 0x0a42
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#define mmVML2VC0_VM_INVALIDATE_ENG13_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG14_ACK 0x0a43
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#define mmVML2VC0_VM_INVALIDATE_ENG14_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG15_ACK 0x0a44
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#define mmVML2VC0_VM_INVALIDATE_ENG15_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG16_ACK 0x0a45
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#define mmVML2VC0_VM_INVALIDATE_ENG16_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG17_ACK 0x0a46
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#define mmVML2VC0_VM_INVALIDATE_ENG17_ACK_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0a47
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#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0a48
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#define mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0a49
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#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x0a4a
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#define mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x0a4b
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#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x0a4c
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#define mmVML2VC0_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x0a4d
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#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x0a4e
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#define mmVML2VC0_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x0a4f
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#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0a50
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#define mmVML2VC0_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0a51
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#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0a52
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#define mmVML2VC0_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0a53
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#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0a54
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#define mmVML2VC0_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0a55
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#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0a56
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#define mmVML2VC0_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0a57
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#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0a58
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#define mmVML2VC0_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0a59
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#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x0a5a
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#define mmVML2VC0_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x0a5b
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#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x0a5c
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#define mmVML2VC0_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x0a5d
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#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x0a5e
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#define mmVML2VC0_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x0a5f
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#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x0a60
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#define mmVML2VC0_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x0a61
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#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x0a62
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#define mmVML2VC0_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x0a63
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#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x0a64
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#define mmVML2VC0_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x0a65
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#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x0a66
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#define mmVML2VC0_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0a67
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#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0a68
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#define mmVML2VC0_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x0a69
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#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x0a6a
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#define mmVML2VC0_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x0a6b
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#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x0a6c
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#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0a6d
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#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0a6e
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#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0a6f
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#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0a70
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#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0a71
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#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x0a72
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#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0a73
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#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0a74
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#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x0a75
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#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x0a76
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#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0a77
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#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0a78
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#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x0a79
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#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x0a7a
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#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0a7b
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#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0a7c
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#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x0a7d
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#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0a7e
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#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x0a7f
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#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x0a80
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#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x0a81
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#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x0a82
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#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x0a83
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#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x0a84
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#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x0a85
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#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x0a86
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#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x0a87
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#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x0a88
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#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x0a89
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#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x0a8a
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#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x0a8b
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#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x0a8c
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#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0a8d
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#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0a8e
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#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x0a8f
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#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x0a90
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#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0a91
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#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0a92
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#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0a93
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#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0a94
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#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0a95
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#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x0a96
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#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0a97
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#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0a98
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#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x0a99
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#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x0a9a
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#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0a9b
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#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0a9c
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#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x0a9d
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#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x0a9e
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#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x0a9f
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#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x0aa0
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#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x0aa1
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#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x0aa2
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#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x0aa3
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#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x0aa4
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#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x0aa5
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#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x0aa6
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#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x0aa7
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#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x0aa8
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#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x0aa9
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#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x0aaa
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#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x0aab
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#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x0aac
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#define mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0aad
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#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0aae
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#define mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x0aaf
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#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x0ab0
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#define mmVML2VC0_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0ab1
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#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0ab2
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#define mmVML2VC0_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x0ab3
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#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x0ab4
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#define mmVML2VC0_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0ab5
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#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0ab6
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#define mmVML2VC0_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0ab7
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#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0ab8
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#define mmVML2VC0_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0ab9
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#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x0aba
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#define mmVML2VC0_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0abb
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#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0abc
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#define mmVML2VC0_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x0abd
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#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x0abe
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#define mmVML2VC0_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x0abf
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#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0ac0
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#define mmVML2VC0_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0ac1
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#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0ac2
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#define mmVML2VC0_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0ac3
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#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0ac4
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#define mmVML2VC0_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0ac5
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#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0ac6
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#define mmVML2VC0_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0ac7
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#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0ac8
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#define mmVML2VC0_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0ac9
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#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x0aca
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#define mmVML2VC0_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vmsharedpfdec
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// base address: 0x6ab90
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#define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE 0x0ae4
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#define mmVMSHAREDPF0_MC_VM_NB_MMIOBASE_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT 0x0ae5
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#define mmVMSHAREDPF0_MC_VM_NB_MMIOLIMIT_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL 0x0ae6
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#define mmVMSHAREDPF0_MC_VM_NB_PCI_CTRL_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB 0x0ae7
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#define mmVMSHAREDPF0_MC_VM_NB_PCI_ARB_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1 0x0ae8
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#define mmVMSHAREDPF0_MC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2 0x0ae9
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#define mmVMSHAREDPF0_MC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2 0x0aea
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#define mmVMSHAREDPF0_MC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_FB_OFFSET 0x0aeb
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#define mmVMSHAREDPF0_MC_VM_FB_OFFSET_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0aec
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#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0aed
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#define mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_STEERING 0x0aee
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#define mmVMSHAREDPF0_MC_VM_STEERING_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ 0x0aef
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#define mmVMSHAREDPF0_MC_SHARED_VIRT_RESET_REQ_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_MEM_POWER_LS 0x0af0
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#define mmVMSHAREDPF0_MC_MEM_POWER_LS_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START 0x0af1
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#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END 0x0af2
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#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_APT_CNTL 0x0af3
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#define mmVMSHAREDPF0_MC_VM_APT_CNTL_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START 0x0af4
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#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END 0x0af5
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#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x0af6
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#define mmVMSHAREDPF0_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL 0x0af7
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#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_CNTL_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE 0x0af8
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#define mmVMSHAREDPF0_MC_VM_XGMI_LFB_SIZE_BASE_IDX 1
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#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL 0x0af9
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#define mmVMSHAREDPF0_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vmsharedvcdec
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// base address: 0x6ac00
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#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE 0x0b00
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#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE_BASE_IDX 1
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#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP 0x0b01
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#define mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP_BASE_IDX 1
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#define mmVMSHAREDVC0_MC_VM_AGP_TOP 0x0b02
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#define mmVMSHAREDVC0_MC_VM_AGP_TOP_BASE_IDX 1
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#define mmVMSHAREDVC0_MC_VM_AGP_BOT 0x0b03
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#define mmVMSHAREDVC0_MC_VM_AGP_BOT_BASE_IDX 1
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#define mmVMSHAREDVC0_MC_VM_AGP_BASE 0x0b04
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#define mmVMSHAREDVC0_MC_VM_AGP_BASE_BASE_IDX 1
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#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x0b05
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#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1
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#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0b06
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#define mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1
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#define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL 0x0b07
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#define mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vmsharedhvdec
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// base address: 0x6ac80
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0 0x0b20
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1 0x0b21
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2 0x0b22
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3 0x0b23
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4 0x0b24
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5 0x0b25
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6 0x0b26
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7 0x0b27
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8 0x0b28
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9 0x0b29
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10 0x0b2a
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11 0x0b2b
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12 0x0b2c
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13 0x0b2d
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14 0x0b2e
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15 0x0b2f
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#define mmVMSHAREDHV0_MC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1 0x0b30
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#define mmVMSHAREDHV0_VM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0 0x0b31
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_0_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1 0x0b32
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_1_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2 0x0b33
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_2_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3 0x0b34
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_LO_3_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0 0x0b35
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_0_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1 0x0b36
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_1_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2 0x0b37
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_2_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3 0x0b38
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#define mmVMSHAREDHV0_MC_VM_MARC_BASE_HI_3_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0 0x0b39
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_0_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1 0x0b3a
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_1_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2 0x0b3b
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_2_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3 0x0b3c
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_LO_3_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0 0x0b3d
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_0_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1 0x0b3e
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_1_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2 0x0b3f
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_2_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3 0x0b40
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#define mmVMSHAREDHV0_MC_VM_MARC_RELOC_HI_3_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0 0x0b41
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_0_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1 0x0b42
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_1_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2 0x0b43
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_2_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3 0x0b44
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_LO_3_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0 0x0b45
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_0_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1 0x0b46
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_1_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2 0x0b47
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_2_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3 0x0b48
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#define mmVMSHAREDHV0_MC_VM_MARC_LEN_HI_3_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER 0x0b49
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#define mmVMSHAREDHV0_VM_IOMMU_CONTROL_REGISTER_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0b4a
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#define mmVMSHAREDHV0_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL 0x0b4b
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0 0x0b4c
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1 0x0b4d
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2 0x0b4e
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3 0x0b4f
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4 0x0b50
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5 0x0b51
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6 0x0b52
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7 0x0b53
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8 0x0b54
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9 0x0b55
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10 0x0b56
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11 0x0b57
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12 0x0b58
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13 0x0b59
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14 0x0b5a
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15 0x0b5b
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#define mmVMSHAREDHV0_VM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1
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#define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL 0x0b5c
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#define mmVMSHAREDHV0_UTCL2_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID 0x0b5d
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#define mmVMSHAREDHV0_MC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1
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#define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE 0x0b5e
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#define mmVMSHAREDHV0_MC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1
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// addressBlock: mmhub_utcl2_atcl2pfcntrdec
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// base address: 0x6adc0
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#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO 0x0b70
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#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1
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#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI 0x0b71
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#define mmATCL2PFCNTR0_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1
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// addressBlock: mmhub_utcl2_atcl2pfcntldec
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// base address: 0x6add0
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#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG 0x0b74
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#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG 0x0b75
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#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x0b76
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#define mmATCL2PFCNTL0_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vml2pldec
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// base address: 0x6ae00
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG 0x0b80
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG 0x0b81
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG 0x0b82
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG 0x0b83
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG 0x0b84
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG 0x0b85
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG 0x0b86
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG 0x0b87
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x0b88
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#define mmVML2PL0_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vml2prdec
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// base address: 0x6ae40
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#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO 0x0b90
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#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1
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#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI 0x0b91
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#define mmVML2PR0_MC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1
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// addressBlock: mmhub_dagb_dagbdec5
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// base address: 0x74000
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#define mmDAGB5_RDCLI0 0x3000
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#define mmDAGB5_RDCLI0_BASE_IDX 1
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#define mmDAGB5_RDCLI1 0x3001
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#define mmDAGB5_RDCLI1_BASE_IDX 1
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#define mmDAGB5_RDCLI2 0x3002
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#define mmDAGB5_RDCLI2_BASE_IDX 1
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#define mmDAGB5_RDCLI3 0x3003
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#define mmDAGB5_RDCLI3_BASE_IDX 1
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#define mmDAGB5_RDCLI4 0x3004
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#define mmDAGB5_RDCLI4_BASE_IDX 1
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#define mmDAGB5_RDCLI5 0x3005
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#define mmDAGB5_RDCLI5_BASE_IDX 1
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#define mmDAGB5_RDCLI6 0x3006
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#define mmDAGB5_RDCLI6_BASE_IDX 1
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#define mmDAGB5_RDCLI7 0x3007
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#define mmDAGB5_RDCLI7_BASE_IDX 1
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#define mmDAGB5_RDCLI8 0x3008
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#define mmDAGB5_RDCLI8_BASE_IDX 1
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#define mmDAGB5_RDCLI9 0x3009
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#define mmDAGB5_RDCLI9_BASE_IDX 1
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#define mmDAGB5_RDCLI10 0x300a
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#define mmDAGB5_RDCLI10_BASE_IDX 1
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#define mmDAGB5_RDCLI11 0x300b
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#define mmDAGB5_RDCLI11_BASE_IDX 1
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#define mmDAGB5_RDCLI12 0x300c
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#define mmDAGB5_RDCLI12_BASE_IDX 1
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#define mmDAGB5_RDCLI13 0x300d
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#define mmDAGB5_RDCLI13_BASE_IDX 1
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#define mmDAGB5_RDCLI14 0x300e
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#define mmDAGB5_RDCLI14_BASE_IDX 1
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#define mmDAGB5_RDCLI15 0x300f
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#define mmDAGB5_RDCLI15_BASE_IDX 1
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#define mmDAGB5_RD_CNTL 0x3010
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#define mmDAGB5_RD_CNTL_BASE_IDX 1
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#define mmDAGB5_RD_GMI_CNTL 0x3011
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#define mmDAGB5_RD_GMI_CNTL_BASE_IDX 1
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#define mmDAGB5_RD_ADDR_DAGB 0x3012
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#define mmDAGB5_RD_ADDR_DAGB_BASE_IDX 1
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#define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST 0x3013
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#define mmDAGB5_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
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#define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 0x3014
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#define mmDAGB5_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
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#define mmDAGB5_RD_CGTT_CLK_CTRL 0x3015
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#define mmDAGB5_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL 0x3016
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#define mmDAGB5_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL 0x3017
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#define mmDAGB5_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0 0x3018
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#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0 0x3019
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#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1 0x301a
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#define mmDAGB5_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1 0x301b
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#define mmDAGB5_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB5_RD_VC0_CNTL 0x301c
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#define mmDAGB5_RD_VC0_CNTL_BASE_IDX 1
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#define mmDAGB5_RD_VC1_CNTL 0x301d
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#define mmDAGB5_RD_VC1_CNTL_BASE_IDX 1
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#define mmDAGB5_RD_VC2_CNTL 0x301e
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#define mmDAGB5_RD_VC2_CNTL_BASE_IDX 1
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#define mmDAGB5_RD_VC3_CNTL 0x301f
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#define mmDAGB5_RD_VC3_CNTL_BASE_IDX 1
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#define mmDAGB5_RD_VC4_CNTL 0x3020
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#define mmDAGB5_RD_VC4_CNTL_BASE_IDX 1
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#define mmDAGB5_RD_VC5_CNTL 0x3021
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#define mmDAGB5_RD_VC5_CNTL_BASE_IDX 1
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#define mmDAGB5_RD_VC6_CNTL 0x3022
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#define mmDAGB5_RD_VC6_CNTL_BASE_IDX 1
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#define mmDAGB5_RD_VC7_CNTL 0x3023
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#define mmDAGB5_RD_VC7_CNTL_BASE_IDX 1
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#define mmDAGB5_RD_CNTL_MISC 0x3024
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#define mmDAGB5_RD_CNTL_MISC_BASE_IDX 1
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#define mmDAGB5_RD_TLB_CREDIT 0x3025
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#define mmDAGB5_RD_TLB_CREDIT_BASE_IDX 1
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#define mmDAGB5_RDCLI_ASK_PENDING 0x3026
|
#define mmDAGB5_RDCLI_ASK_PENDING_BASE_IDX 1
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#define mmDAGB5_RDCLI_GO_PENDING 0x3027
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#define mmDAGB5_RDCLI_GO_PENDING_BASE_IDX 1
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#define mmDAGB5_RDCLI_GBLSEND_PENDING 0x3028
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#define mmDAGB5_RDCLI_GBLSEND_PENDING_BASE_IDX 1
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#define mmDAGB5_RDCLI_TLB_PENDING 0x3029
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#define mmDAGB5_RDCLI_TLB_PENDING_BASE_IDX 1
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#define mmDAGB5_RDCLI_OARB_PENDING 0x302a
|
#define mmDAGB5_RDCLI_OARB_PENDING_BASE_IDX 1
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#define mmDAGB5_RDCLI_OSD_PENDING 0x302b
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#define mmDAGB5_RDCLI_OSD_PENDING_BASE_IDX 1
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#define mmDAGB5_WRCLI0 0x302c
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#define mmDAGB5_WRCLI0_BASE_IDX 1
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#define mmDAGB5_WRCLI1 0x302d
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#define mmDAGB5_WRCLI1_BASE_IDX 1
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#define mmDAGB5_WRCLI2 0x302e
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#define mmDAGB5_WRCLI2_BASE_IDX 1
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#define mmDAGB5_WRCLI3 0x302f
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#define mmDAGB5_WRCLI3_BASE_IDX 1
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#define mmDAGB5_WRCLI4 0x3030
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#define mmDAGB5_WRCLI4_BASE_IDX 1
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#define mmDAGB5_WRCLI5 0x3031
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#define mmDAGB5_WRCLI5_BASE_IDX 1
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#define mmDAGB5_WRCLI6 0x3032
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#define mmDAGB5_WRCLI6_BASE_IDX 1
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#define mmDAGB5_WRCLI7 0x3033
|
#define mmDAGB5_WRCLI7_BASE_IDX 1
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#define mmDAGB5_WRCLI8 0x3034
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#define mmDAGB5_WRCLI8_BASE_IDX 1
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#define mmDAGB5_WRCLI9 0x3035
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#define mmDAGB5_WRCLI9_BASE_IDX 1
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#define mmDAGB5_WRCLI10 0x3036
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#define mmDAGB5_WRCLI10_BASE_IDX 1
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#define mmDAGB5_WRCLI11 0x3037
|
#define mmDAGB5_WRCLI11_BASE_IDX 1
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#define mmDAGB5_WRCLI12 0x3038
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#define mmDAGB5_WRCLI12_BASE_IDX 1
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#define mmDAGB5_WRCLI13 0x3039
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#define mmDAGB5_WRCLI13_BASE_IDX 1
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#define mmDAGB5_WRCLI14 0x303a
|
#define mmDAGB5_WRCLI14_BASE_IDX 1
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#define mmDAGB5_WRCLI15 0x303b
|
#define mmDAGB5_WRCLI15_BASE_IDX 1
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#define mmDAGB5_WR_CNTL 0x303c
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#define mmDAGB5_WR_CNTL_BASE_IDX 1
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#define mmDAGB5_WR_GMI_CNTL 0x303d
|
#define mmDAGB5_WR_GMI_CNTL_BASE_IDX 1
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#define mmDAGB5_WR_ADDR_DAGB 0x303e
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#define mmDAGB5_WR_ADDR_DAGB_BASE_IDX 1
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#define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST 0x303f
|
#define mmDAGB5_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
|
#define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 0x3040
|
#define mmDAGB5_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
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#define mmDAGB5_WR_CGTT_CLK_CTRL 0x3041
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#define mmDAGB5_WR_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL 0x3042
|
#define mmDAGB5_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL 0x3043
|
#define mmDAGB5_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0 0x3044
|
#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
|
#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0 0x3045
|
#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
|
#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1 0x3046
|
#define mmDAGB5_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
|
#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1 0x3047
|
#define mmDAGB5_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB5_WR_DATA_DAGB 0x3048
|
#define mmDAGB5_WR_DATA_DAGB_BASE_IDX 1
|
#define mmDAGB5_WR_DATA_DAGB_MAX_BURST0 0x3049
|
#define mmDAGB5_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
|
#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0 0x304a
|
#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
|
#define mmDAGB5_WR_DATA_DAGB_MAX_BURST1 0x304b
|
#define mmDAGB5_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
|
#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1 0x304c
|
#define mmDAGB5_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
|
#define mmDAGB5_WR_VC0_CNTL 0x304d
|
#define mmDAGB5_WR_VC0_CNTL_BASE_IDX 1
|
#define mmDAGB5_WR_VC1_CNTL 0x304e
|
#define mmDAGB5_WR_VC1_CNTL_BASE_IDX 1
|
#define mmDAGB5_WR_VC2_CNTL 0x304f
|
#define mmDAGB5_WR_VC2_CNTL_BASE_IDX 1
|
#define mmDAGB5_WR_VC3_CNTL 0x3050
|
#define mmDAGB5_WR_VC3_CNTL_BASE_IDX 1
|
#define mmDAGB5_WR_VC4_CNTL 0x3051
|
#define mmDAGB5_WR_VC4_CNTL_BASE_IDX 1
|
#define mmDAGB5_WR_VC5_CNTL 0x3052
|
#define mmDAGB5_WR_VC5_CNTL_BASE_IDX 1
|
#define mmDAGB5_WR_VC6_CNTL 0x3053
|
#define mmDAGB5_WR_VC6_CNTL_BASE_IDX 1
|
#define mmDAGB5_WR_VC7_CNTL 0x3054
|
#define mmDAGB5_WR_VC7_CNTL_BASE_IDX 1
|
#define mmDAGB5_WR_CNTL_MISC 0x3055
|
#define mmDAGB5_WR_CNTL_MISC_BASE_IDX 1
|
#define mmDAGB5_WR_TLB_CREDIT 0x3056
|
#define mmDAGB5_WR_TLB_CREDIT_BASE_IDX 1
|
#define mmDAGB5_WR_DATA_CREDIT 0x3057
|
#define mmDAGB5_WR_DATA_CREDIT_BASE_IDX 1
|
#define mmDAGB5_WR_MISC_CREDIT 0x3058
|
#define mmDAGB5_WR_MISC_CREDIT_BASE_IDX 1
|
#define mmDAGB5_WRCLI_ASK_PENDING 0x305d
|
#define mmDAGB5_WRCLI_ASK_PENDING_BASE_IDX 1
|
#define mmDAGB5_WRCLI_GO_PENDING 0x305e
|
#define mmDAGB5_WRCLI_GO_PENDING_BASE_IDX 1
|
#define mmDAGB5_WRCLI_GBLSEND_PENDING 0x305f
|
#define mmDAGB5_WRCLI_GBLSEND_PENDING_BASE_IDX 1
|
#define mmDAGB5_WRCLI_TLB_PENDING 0x3060
|
#define mmDAGB5_WRCLI_TLB_PENDING_BASE_IDX 1
|
#define mmDAGB5_WRCLI_OARB_PENDING 0x3061
|
#define mmDAGB5_WRCLI_OARB_PENDING_BASE_IDX 1
|
#define mmDAGB5_WRCLI_OSD_PENDING 0x3062
|
#define mmDAGB5_WRCLI_OSD_PENDING_BASE_IDX 1
|
#define mmDAGB5_WRCLI_DBUS_ASK_PENDING 0x3063
|
#define mmDAGB5_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
|
#define mmDAGB5_WRCLI_DBUS_GO_PENDING 0x3064
|
#define mmDAGB5_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
|
#define mmDAGB5_DAGB_DLY 0x3065
|
#define mmDAGB5_DAGB_DLY_BASE_IDX 1
|
#define mmDAGB5_CNTL_MISC 0x3066
|
#define mmDAGB5_CNTL_MISC_BASE_IDX 1
|
#define mmDAGB5_CNTL_MISC2 0x3067
|
#define mmDAGB5_CNTL_MISC2_BASE_IDX 1
|
#define mmDAGB5_FIFO_EMPTY 0x3068
|
#define mmDAGB5_FIFO_EMPTY_BASE_IDX 1
|
#define mmDAGB5_FIFO_FULL 0x3069
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#define mmDAGB5_FIFO_FULL_BASE_IDX 1
|
#define mmDAGB5_WR_CREDITS_FULL 0x306a
|
#define mmDAGB5_WR_CREDITS_FULL_BASE_IDX 1
|
#define mmDAGB5_RD_CREDITS_FULL 0x306b
|
#define mmDAGB5_RD_CREDITS_FULL_BASE_IDX 1
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#define mmDAGB5_PERFCOUNTER_LO 0x306c
|
#define mmDAGB5_PERFCOUNTER_LO_BASE_IDX 1
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#define mmDAGB5_PERFCOUNTER_HI 0x306d
|
#define mmDAGB5_PERFCOUNTER_HI_BASE_IDX 1
|
#define mmDAGB5_PERFCOUNTER0_CFG 0x306e
|
#define mmDAGB5_PERFCOUNTER0_CFG_BASE_IDX 1
|
#define mmDAGB5_PERFCOUNTER1_CFG 0x306f
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#define mmDAGB5_PERFCOUNTER1_CFG_BASE_IDX 1
|
#define mmDAGB5_PERFCOUNTER2_CFG 0x3070
|
#define mmDAGB5_PERFCOUNTER2_CFG_BASE_IDX 1
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#define mmDAGB5_PERFCOUNTER_RSLT_CNTL 0x3071
|
#define mmDAGB5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmDAGB5_RESERVE0 0x3072
|
#define mmDAGB5_RESERVE0_BASE_IDX 1
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#define mmDAGB5_RESERVE1 0x3073
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#define mmDAGB5_RESERVE1_BASE_IDX 1
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#define mmDAGB5_RESERVE2 0x3074
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#define mmDAGB5_RESERVE2_BASE_IDX 1
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#define mmDAGB5_RESERVE3 0x3075
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#define mmDAGB5_RESERVE3_BASE_IDX 1
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#define mmDAGB5_RESERVE4 0x3076
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#define mmDAGB5_RESERVE4_BASE_IDX 1
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#define mmDAGB5_RESERVE5 0x3077
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#define mmDAGB5_RESERVE5_BASE_IDX 1
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#define mmDAGB5_RESERVE6 0x3078
|
#define mmDAGB5_RESERVE6_BASE_IDX 1
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#define mmDAGB5_RESERVE7 0x3079
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#define mmDAGB5_RESERVE7_BASE_IDX 1
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#define mmDAGB5_RESERVE8 0x307a
|
#define mmDAGB5_RESERVE8_BASE_IDX 1
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#define mmDAGB5_RESERVE9 0x307b
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#define mmDAGB5_RESERVE9_BASE_IDX 1
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#define mmDAGB5_RESERVE10 0x307c
|
#define mmDAGB5_RESERVE10_BASE_IDX 1
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#define mmDAGB5_RESERVE11 0x307d
|
#define mmDAGB5_RESERVE11_BASE_IDX 1
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#define mmDAGB5_RESERVE12 0x307e
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#define mmDAGB5_RESERVE12_BASE_IDX 1
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#define mmDAGB5_RESERVE13 0x307f
|
#define mmDAGB5_RESERVE13_BASE_IDX 1
|
|
|
// addressBlock: mmhub_dagb_dagbdec6
|
// base address: 0x74200
|
#define mmDAGB6_RDCLI0 0x3080
|
#define mmDAGB6_RDCLI0_BASE_IDX 1
|
#define mmDAGB6_RDCLI1 0x3081
|
#define mmDAGB6_RDCLI1_BASE_IDX 1
|
#define mmDAGB6_RDCLI2 0x3082
|
#define mmDAGB6_RDCLI2_BASE_IDX 1
|
#define mmDAGB6_RDCLI3 0x3083
|
#define mmDAGB6_RDCLI3_BASE_IDX 1
|
#define mmDAGB6_RDCLI4 0x3084
|
#define mmDAGB6_RDCLI4_BASE_IDX 1
|
#define mmDAGB6_RDCLI5 0x3085
|
#define mmDAGB6_RDCLI5_BASE_IDX 1
|
#define mmDAGB6_RDCLI6 0x3086
|
#define mmDAGB6_RDCLI6_BASE_IDX 1
|
#define mmDAGB6_RDCLI7 0x3087
|
#define mmDAGB6_RDCLI7_BASE_IDX 1
|
#define mmDAGB6_RDCLI8 0x3088
|
#define mmDAGB6_RDCLI8_BASE_IDX 1
|
#define mmDAGB6_RDCLI9 0x3089
|
#define mmDAGB6_RDCLI9_BASE_IDX 1
|
#define mmDAGB6_RDCLI10 0x308a
|
#define mmDAGB6_RDCLI10_BASE_IDX 1
|
#define mmDAGB6_RDCLI11 0x308b
|
#define mmDAGB6_RDCLI11_BASE_IDX 1
|
#define mmDAGB6_RDCLI12 0x308c
|
#define mmDAGB6_RDCLI12_BASE_IDX 1
|
#define mmDAGB6_RDCLI13 0x308d
|
#define mmDAGB6_RDCLI13_BASE_IDX 1
|
#define mmDAGB6_RDCLI14 0x308e
|
#define mmDAGB6_RDCLI14_BASE_IDX 1
|
#define mmDAGB6_RDCLI15 0x308f
|
#define mmDAGB6_RDCLI15_BASE_IDX 1
|
#define mmDAGB6_RD_CNTL 0x3090
|
#define mmDAGB6_RD_CNTL_BASE_IDX 1
|
#define mmDAGB6_RD_GMI_CNTL 0x3091
|
#define mmDAGB6_RD_GMI_CNTL_BASE_IDX 1
|
#define mmDAGB6_RD_ADDR_DAGB 0x3092
|
#define mmDAGB6_RD_ADDR_DAGB_BASE_IDX 1
|
#define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST 0x3093
|
#define mmDAGB6_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
|
#define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER 0x3094
|
#define mmDAGB6_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
|
#define mmDAGB6_RD_CGTT_CLK_CTRL 0x3095
|
#define mmDAGB6_RD_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL 0x3096
|
#define mmDAGB6_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL 0x3097
|
#define mmDAGB6_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0 0x3098
|
#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
|
#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0 0x3099
|
#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
|
#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1 0x309a
|
#define mmDAGB6_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
|
#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1 0x309b
|
#define mmDAGB6_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
|
#define mmDAGB6_RD_VC0_CNTL 0x309c
|
#define mmDAGB6_RD_VC0_CNTL_BASE_IDX 1
|
#define mmDAGB6_RD_VC1_CNTL 0x309d
|
#define mmDAGB6_RD_VC1_CNTL_BASE_IDX 1
|
#define mmDAGB6_RD_VC2_CNTL 0x309e
|
#define mmDAGB6_RD_VC2_CNTL_BASE_IDX 1
|
#define mmDAGB6_RD_VC3_CNTL 0x309f
|
#define mmDAGB6_RD_VC3_CNTL_BASE_IDX 1
|
#define mmDAGB6_RD_VC4_CNTL 0x30a0
|
#define mmDAGB6_RD_VC4_CNTL_BASE_IDX 1
|
#define mmDAGB6_RD_VC5_CNTL 0x30a1
|
#define mmDAGB6_RD_VC5_CNTL_BASE_IDX 1
|
#define mmDAGB6_RD_VC6_CNTL 0x30a2
|
#define mmDAGB6_RD_VC6_CNTL_BASE_IDX 1
|
#define mmDAGB6_RD_VC7_CNTL 0x30a3
|
#define mmDAGB6_RD_VC7_CNTL_BASE_IDX 1
|
#define mmDAGB6_RD_CNTL_MISC 0x30a4
|
#define mmDAGB6_RD_CNTL_MISC_BASE_IDX 1
|
#define mmDAGB6_RD_TLB_CREDIT 0x30a5
|
#define mmDAGB6_RD_TLB_CREDIT_BASE_IDX 1
|
#define mmDAGB6_RDCLI_ASK_PENDING 0x30a6
|
#define mmDAGB6_RDCLI_ASK_PENDING_BASE_IDX 1
|
#define mmDAGB6_RDCLI_GO_PENDING 0x30a7
|
#define mmDAGB6_RDCLI_GO_PENDING_BASE_IDX 1
|
#define mmDAGB6_RDCLI_GBLSEND_PENDING 0x30a8
|
#define mmDAGB6_RDCLI_GBLSEND_PENDING_BASE_IDX 1
|
#define mmDAGB6_RDCLI_TLB_PENDING 0x30a9
|
#define mmDAGB6_RDCLI_TLB_PENDING_BASE_IDX 1
|
#define mmDAGB6_RDCLI_OARB_PENDING 0x30aa
|
#define mmDAGB6_RDCLI_OARB_PENDING_BASE_IDX 1
|
#define mmDAGB6_RDCLI_OSD_PENDING 0x30ab
|
#define mmDAGB6_RDCLI_OSD_PENDING_BASE_IDX 1
|
#define mmDAGB6_WRCLI0 0x30ac
|
#define mmDAGB6_WRCLI0_BASE_IDX 1
|
#define mmDAGB6_WRCLI1 0x30ad
|
#define mmDAGB6_WRCLI1_BASE_IDX 1
|
#define mmDAGB6_WRCLI2 0x30ae
|
#define mmDAGB6_WRCLI2_BASE_IDX 1
|
#define mmDAGB6_WRCLI3 0x30af
|
#define mmDAGB6_WRCLI3_BASE_IDX 1
|
#define mmDAGB6_WRCLI4 0x30b0
|
#define mmDAGB6_WRCLI4_BASE_IDX 1
|
#define mmDAGB6_WRCLI5 0x30b1
|
#define mmDAGB6_WRCLI5_BASE_IDX 1
|
#define mmDAGB6_WRCLI6 0x30b2
|
#define mmDAGB6_WRCLI6_BASE_IDX 1
|
#define mmDAGB6_WRCLI7 0x30b3
|
#define mmDAGB6_WRCLI7_BASE_IDX 1
|
#define mmDAGB6_WRCLI8 0x30b4
|
#define mmDAGB6_WRCLI8_BASE_IDX 1
|
#define mmDAGB6_WRCLI9 0x30b5
|
#define mmDAGB6_WRCLI9_BASE_IDX 1
|
#define mmDAGB6_WRCLI10 0x30b6
|
#define mmDAGB6_WRCLI10_BASE_IDX 1
|
#define mmDAGB6_WRCLI11 0x30b7
|
#define mmDAGB6_WRCLI11_BASE_IDX 1
|
#define mmDAGB6_WRCLI12 0x30b8
|
#define mmDAGB6_WRCLI12_BASE_IDX 1
|
#define mmDAGB6_WRCLI13 0x30b9
|
#define mmDAGB6_WRCLI13_BASE_IDX 1
|
#define mmDAGB6_WRCLI14 0x30ba
|
#define mmDAGB6_WRCLI14_BASE_IDX 1
|
#define mmDAGB6_WRCLI15 0x30bb
|
#define mmDAGB6_WRCLI15_BASE_IDX 1
|
#define mmDAGB6_WR_CNTL 0x30bc
|
#define mmDAGB6_WR_CNTL_BASE_IDX 1
|
#define mmDAGB6_WR_GMI_CNTL 0x30bd
|
#define mmDAGB6_WR_GMI_CNTL_BASE_IDX 1
|
#define mmDAGB6_WR_ADDR_DAGB 0x30be
|
#define mmDAGB6_WR_ADDR_DAGB_BASE_IDX 1
|
#define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST 0x30bf
|
#define mmDAGB6_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
|
#define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER 0x30c0
|
#define mmDAGB6_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
|
#define mmDAGB6_WR_CGTT_CLK_CTRL 0x30c1
|
#define mmDAGB6_WR_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL 0x30c2
|
#define mmDAGB6_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL 0x30c3
|
#define mmDAGB6_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
|
#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0 0x30c4
|
#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
|
#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0 0x30c5
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#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1 0x30c6
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#define mmDAGB6_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1 0x30c7
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#define mmDAGB6_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB6_WR_DATA_DAGB 0x30c8
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#define mmDAGB6_WR_DATA_DAGB_BASE_IDX 1
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#define mmDAGB6_WR_DATA_DAGB_MAX_BURST0 0x30c9
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#define mmDAGB6_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0 0x30ca
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#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB6_WR_DATA_DAGB_MAX_BURST1 0x30cb
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#define mmDAGB6_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1 0x30cc
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#define mmDAGB6_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB6_WR_VC0_CNTL 0x30cd
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#define mmDAGB6_WR_VC0_CNTL_BASE_IDX 1
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#define mmDAGB6_WR_VC1_CNTL 0x30ce
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#define mmDAGB6_WR_VC1_CNTL_BASE_IDX 1
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#define mmDAGB6_WR_VC2_CNTL 0x30cf
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#define mmDAGB6_WR_VC2_CNTL_BASE_IDX 1
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#define mmDAGB6_WR_VC3_CNTL 0x30d0
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#define mmDAGB6_WR_VC3_CNTL_BASE_IDX 1
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#define mmDAGB6_WR_VC4_CNTL 0x30d1
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#define mmDAGB6_WR_VC4_CNTL_BASE_IDX 1
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#define mmDAGB6_WR_VC5_CNTL 0x30d2
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#define mmDAGB6_WR_VC5_CNTL_BASE_IDX 1
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#define mmDAGB6_WR_VC6_CNTL 0x30d3
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#define mmDAGB6_WR_VC6_CNTL_BASE_IDX 1
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#define mmDAGB6_WR_VC7_CNTL 0x30d4
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#define mmDAGB6_WR_VC7_CNTL_BASE_IDX 1
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#define mmDAGB6_WR_CNTL_MISC 0x30d5
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#define mmDAGB6_WR_CNTL_MISC_BASE_IDX 1
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#define mmDAGB6_WR_TLB_CREDIT 0x30d6
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#define mmDAGB6_WR_TLB_CREDIT_BASE_IDX 1
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#define mmDAGB6_WR_DATA_CREDIT 0x30d7
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#define mmDAGB6_WR_DATA_CREDIT_BASE_IDX 1
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#define mmDAGB6_WR_MISC_CREDIT 0x30d8
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#define mmDAGB6_WR_MISC_CREDIT_BASE_IDX 1
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#define mmDAGB6_WRCLI_ASK_PENDING 0x30dd
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#define mmDAGB6_WRCLI_ASK_PENDING_BASE_IDX 1
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#define mmDAGB6_WRCLI_GO_PENDING 0x30de
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#define mmDAGB6_WRCLI_GO_PENDING_BASE_IDX 1
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#define mmDAGB6_WRCLI_GBLSEND_PENDING 0x30df
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#define mmDAGB6_WRCLI_GBLSEND_PENDING_BASE_IDX 1
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#define mmDAGB6_WRCLI_TLB_PENDING 0x30e0
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#define mmDAGB6_WRCLI_TLB_PENDING_BASE_IDX 1
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#define mmDAGB6_WRCLI_OARB_PENDING 0x30e1
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#define mmDAGB6_WRCLI_OARB_PENDING_BASE_IDX 1
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#define mmDAGB6_WRCLI_OSD_PENDING 0x30e2
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#define mmDAGB6_WRCLI_OSD_PENDING_BASE_IDX 1
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#define mmDAGB6_WRCLI_DBUS_ASK_PENDING 0x30e3
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#define mmDAGB6_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
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#define mmDAGB6_WRCLI_DBUS_GO_PENDING 0x30e4
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#define mmDAGB6_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
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#define mmDAGB6_DAGB_DLY 0x30e5
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#define mmDAGB6_DAGB_DLY_BASE_IDX 1
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#define mmDAGB6_CNTL_MISC 0x30e6
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#define mmDAGB6_CNTL_MISC_BASE_IDX 1
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#define mmDAGB6_CNTL_MISC2 0x30e7
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#define mmDAGB6_CNTL_MISC2_BASE_IDX 1
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#define mmDAGB6_FIFO_EMPTY 0x30e8
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#define mmDAGB6_FIFO_EMPTY_BASE_IDX 1
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#define mmDAGB6_FIFO_FULL 0x30e9
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#define mmDAGB6_FIFO_FULL_BASE_IDX 1
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#define mmDAGB6_WR_CREDITS_FULL 0x30ea
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#define mmDAGB6_WR_CREDITS_FULL_BASE_IDX 1
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#define mmDAGB6_RD_CREDITS_FULL 0x30eb
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#define mmDAGB6_RD_CREDITS_FULL_BASE_IDX 1
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#define mmDAGB6_PERFCOUNTER_LO 0x30ec
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#define mmDAGB6_PERFCOUNTER_LO_BASE_IDX 1
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#define mmDAGB6_PERFCOUNTER_HI 0x30ed
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#define mmDAGB6_PERFCOUNTER_HI_BASE_IDX 1
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#define mmDAGB6_PERFCOUNTER0_CFG 0x30ee
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#define mmDAGB6_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmDAGB6_PERFCOUNTER1_CFG 0x30ef
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#define mmDAGB6_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmDAGB6_PERFCOUNTER2_CFG 0x30f0
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#define mmDAGB6_PERFCOUNTER2_CFG_BASE_IDX 1
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#define mmDAGB6_PERFCOUNTER_RSLT_CNTL 0x30f1
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#define mmDAGB6_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmDAGB6_RESERVE0 0x30f2
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#define mmDAGB6_RESERVE0_BASE_IDX 1
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#define mmDAGB6_RESERVE1 0x30f3
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#define mmDAGB6_RESERVE1_BASE_IDX 1
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#define mmDAGB6_RESERVE2 0x30f4
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#define mmDAGB6_RESERVE2_BASE_IDX 1
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#define mmDAGB6_RESERVE3 0x30f5
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#define mmDAGB6_RESERVE3_BASE_IDX 1
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#define mmDAGB6_RESERVE4 0x30f6
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#define mmDAGB6_RESERVE4_BASE_IDX 1
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#define mmDAGB6_RESERVE5 0x30f7
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#define mmDAGB6_RESERVE5_BASE_IDX 1
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#define mmDAGB6_RESERVE6 0x30f8
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#define mmDAGB6_RESERVE6_BASE_IDX 1
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#define mmDAGB6_RESERVE7 0x30f9
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#define mmDAGB6_RESERVE7_BASE_IDX 1
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#define mmDAGB6_RESERVE8 0x30fa
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#define mmDAGB6_RESERVE8_BASE_IDX 1
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#define mmDAGB6_RESERVE9 0x30fb
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#define mmDAGB6_RESERVE9_BASE_IDX 1
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#define mmDAGB6_RESERVE10 0x30fc
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#define mmDAGB6_RESERVE10_BASE_IDX 1
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#define mmDAGB6_RESERVE11 0x30fd
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#define mmDAGB6_RESERVE11_BASE_IDX 1
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#define mmDAGB6_RESERVE12 0x30fe
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#define mmDAGB6_RESERVE12_BASE_IDX 1
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#define mmDAGB6_RESERVE13 0x30ff
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#define mmDAGB6_RESERVE13_BASE_IDX 1
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|
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// addressBlock: mmhub_dagb_dagbdec7
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// base address: 0x74400
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#define mmDAGB7_RDCLI0 0x3100
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#define mmDAGB7_RDCLI0_BASE_IDX 1
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#define mmDAGB7_RDCLI1 0x3101
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#define mmDAGB7_RDCLI1_BASE_IDX 1
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#define mmDAGB7_RDCLI2 0x3102
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#define mmDAGB7_RDCLI2_BASE_IDX 1
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#define mmDAGB7_RDCLI3 0x3103
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#define mmDAGB7_RDCLI3_BASE_IDX 1
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#define mmDAGB7_RDCLI4 0x3104
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#define mmDAGB7_RDCLI4_BASE_IDX 1
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#define mmDAGB7_RDCLI5 0x3105
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#define mmDAGB7_RDCLI5_BASE_IDX 1
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#define mmDAGB7_RDCLI6 0x3106
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#define mmDAGB7_RDCLI6_BASE_IDX 1
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#define mmDAGB7_RDCLI7 0x3107
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#define mmDAGB7_RDCLI7_BASE_IDX 1
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#define mmDAGB7_RDCLI8 0x3108
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#define mmDAGB7_RDCLI8_BASE_IDX 1
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#define mmDAGB7_RDCLI9 0x3109
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#define mmDAGB7_RDCLI9_BASE_IDX 1
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#define mmDAGB7_RDCLI10 0x310a
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#define mmDAGB7_RDCLI10_BASE_IDX 1
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#define mmDAGB7_RDCLI11 0x310b
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#define mmDAGB7_RDCLI11_BASE_IDX 1
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#define mmDAGB7_RDCLI12 0x310c
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#define mmDAGB7_RDCLI12_BASE_IDX 1
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#define mmDAGB7_RDCLI13 0x310d
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#define mmDAGB7_RDCLI13_BASE_IDX 1
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#define mmDAGB7_RDCLI14 0x310e
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#define mmDAGB7_RDCLI14_BASE_IDX 1
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#define mmDAGB7_RDCLI15 0x310f
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#define mmDAGB7_RDCLI15_BASE_IDX 1
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#define mmDAGB7_RD_CNTL 0x3110
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#define mmDAGB7_RD_CNTL_BASE_IDX 1
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#define mmDAGB7_RD_GMI_CNTL 0x3111
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#define mmDAGB7_RD_GMI_CNTL_BASE_IDX 1
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#define mmDAGB7_RD_ADDR_DAGB 0x3112
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#define mmDAGB7_RD_ADDR_DAGB_BASE_IDX 1
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#define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST 0x3113
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#define mmDAGB7_RD_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
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#define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER 0x3114
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#define mmDAGB7_RD_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
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#define mmDAGB7_RD_CGTT_CLK_CTRL 0x3115
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#define mmDAGB7_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL 0x3116
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#define mmDAGB7_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL 0x3117
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#define mmDAGB7_ATCVM_RD_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0 0x3118
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#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0 0x3119
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#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1 0x311a
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#define mmDAGB7_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1 0x311b
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#define mmDAGB7_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB7_RD_VC0_CNTL 0x311c
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#define mmDAGB7_RD_VC0_CNTL_BASE_IDX 1
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#define mmDAGB7_RD_VC1_CNTL 0x311d
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#define mmDAGB7_RD_VC1_CNTL_BASE_IDX 1
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#define mmDAGB7_RD_VC2_CNTL 0x311e
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#define mmDAGB7_RD_VC2_CNTL_BASE_IDX 1
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#define mmDAGB7_RD_VC3_CNTL 0x311f
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#define mmDAGB7_RD_VC3_CNTL_BASE_IDX 1
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#define mmDAGB7_RD_VC4_CNTL 0x3120
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#define mmDAGB7_RD_VC4_CNTL_BASE_IDX 1
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#define mmDAGB7_RD_VC5_CNTL 0x3121
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#define mmDAGB7_RD_VC5_CNTL_BASE_IDX 1
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#define mmDAGB7_RD_VC6_CNTL 0x3122
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#define mmDAGB7_RD_VC6_CNTL_BASE_IDX 1
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#define mmDAGB7_RD_VC7_CNTL 0x3123
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#define mmDAGB7_RD_VC7_CNTL_BASE_IDX 1
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#define mmDAGB7_RD_CNTL_MISC 0x3124
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#define mmDAGB7_RD_CNTL_MISC_BASE_IDX 1
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#define mmDAGB7_RD_TLB_CREDIT 0x3125
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#define mmDAGB7_RD_TLB_CREDIT_BASE_IDX 1
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#define mmDAGB7_RDCLI_ASK_PENDING 0x3126
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#define mmDAGB7_RDCLI_ASK_PENDING_BASE_IDX 1
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#define mmDAGB7_RDCLI_GO_PENDING 0x3127
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#define mmDAGB7_RDCLI_GO_PENDING_BASE_IDX 1
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#define mmDAGB7_RDCLI_GBLSEND_PENDING 0x3128
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#define mmDAGB7_RDCLI_GBLSEND_PENDING_BASE_IDX 1
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#define mmDAGB7_RDCLI_TLB_PENDING 0x3129
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#define mmDAGB7_RDCLI_TLB_PENDING_BASE_IDX 1
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#define mmDAGB7_RDCLI_OARB_PENDING 0x312a
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#define mmDAGB7_RDCLI_OARB_PENDING_BASE_IDX 1
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#define mmDAGB7_RDCLI_OSD_PENDING 0x312b
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#define mmDAGB7_RDCLI_OSD_PENDING_BASE_IDX 1
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#define mmDAGB7_WRCLI0 0x312c
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#define mmDAGB7_WRCLI0_BASE_IDX 1
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#define mmDAGB7_WRCLI1 0x312d
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#define mmDAGB7_WRCLI1_BASE_IDX 1
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#define mmDAGB7_WRCLI2 0x312e
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#define mmDAGB7_WRCLI2_BASE_IDX 1
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#define mmDAGB7_WRCLI3 0x312f
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#define mmDAGB7_WRCLI3_BASE_IDX 1
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#define mmDAGB7_WRCLI4 0x3130
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#define mmDAGB7_WRCLI4_BASE_IDX 1
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#define mmDAGB7_WRCLI5 0x3131
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#define mmDAGB7_WRCLI5_BASE_IDX 1
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#define mmDAGB7_WRCLI6 0x3132
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#define mmDAGB7_WRCLI6_BASE_IDX 1
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#define mmDAGB7_WRCLI7 0x3133
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#define mmDAGB7_WRCLI7_BASE_IDX 1
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#define mmDAGB7_WRCLI8 0x3134
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#define mmDAGB7_WRCLI8_BASE_IDX 1
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#define mmDAGB7_WRCLI9 0x3135
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#define mmDAGB7_WRCLI9_BASE_IDX 1
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#define mmDAGB7_WRCLI10 0x3136
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#define mmDAGB7_WRCLI10_BASE_IDX 1
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#define mmDAGB7_WRCLI11 0x3137
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#define mmDAGB7_WRCLI11_BASE_IDX 1
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#define mmDAGB7_WRCLI12 0x3138
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#define mmDAGB7_WRCLI12_BASE_IDX 1
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#define mmDAGB7_WRCLI13 0x3139
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#define mmDAGB7_WRCLI13_BASE_IDX 1
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#define mmDAGB7_WRCLI14 0x313a
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#define mmDAGB7_WRCLI14_BASE_IDX 1
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#define mmDAGB7_WRCLI15 0x313b
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#define mmDAGB7_WRCLI15_BASE_IDX 1
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#define mmDAGB7_WR_CNTL 0x313c
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#define mmDAGB7_WR_CNTL_BASE_IDX 1
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#define mmDAGB7_WR_GMI_CNTL 0x313d
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#define mmDAGB7_WR_GMI_CNTL_BASE_IDX 1
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#define mmDAGB7_WR_ADDR_DAGB 0x313e
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#define mmDAGB7_WR_ADDR_DAGB_BASE_IDX 1
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#define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST 0x313f
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#define mmDAGB7_WR_OUTPUT_DAGB_MAX_BURST_BASE_IDX 1
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#define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER 0x3140
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#define mmDAGB7_WR_OUTPUT_DAGB_LAZY_TIMER_BASE_IDX 1
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#define mmDAGB7_WR_CGTT_CLK_CTRL 0x3141
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#define mmDAGB7_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL 0x3142
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#define mmDAGB7_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL 0x3143
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#define mmDAGB7_ATCVM_WR_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0 0x3144
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#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0 0x3145
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#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1 0x3146
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#define mmDAGB7_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1 0x3147
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#define mmDAGB7_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB7_WR_DATA_DAGB 0x3148
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#define mmDAGB7_WR_DATA_DAGB_BASE_IDX 1
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#define mmDAGB7_WR_DATA_DAGB_MAX_BURST0 0x3149
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#define mmDAGB7_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1
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#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0 0x314a
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#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1
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#define mmDAGB7_WR_DATA_DAGB_MAX_BURST1 0x314b
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#define mmDAGB7_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1
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#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1 0x314c
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#define mmDAGB7_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1
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#define mmDAGB7_WR_VC0_CNTL 0x314d
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#define mmDAGB7_WR_VC0_CNTL_BASE_IDX 1
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#define mmDAGB7_WR_VC1_CNTL 0x314e
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#define mmDAGB7_WR_VC1_CNTL_BASE_IDX 1
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#define mmDAGB7_WR_VC2_CNTL 0x314f
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#define mmDAGB7_WR_VC2_CNTL_BASE_IDX 1
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#define mmDAGB7_WR_VC3_CNTL 0x3150
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#define mmDAGB7_WR_VC3_CNTL_BASE_IDX 1
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#define mmDAGB7_WR_VC4_CNTL 0x3151
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#define mmDAGB7_WR_VC4_CNTL_BASE_IDX 1
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#define mmDAGB7_WR_VC5_CNTL 0x3152
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#define mmDAGB7_WR_VC5_CNTL_BASE_IDX 1
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#define mmDAGB7_WR_VC6_CNTL 0x3153
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#define mmDAGB7_WR_VC6_CNTL_BASE_IDX 1
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#define mmDAGB7_WR_VC7_CNTL 0x3154
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#define mmDAGB7_WR_VC7_CNTL_BASE_IDX 1
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#define mmDAGB7_WR_CNTL_MISC 0x3155
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#define mmDAGB7_WR_CNTL_MISC_BASE_IDX 1
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#define mmDAGB7_WR_TLB_CREDIT 0x3156
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#define mmDAGB7_WR_TLB_CREDIT_BASE_IDX 1
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#define mmDAGB7_WR_DATA_CREDIT 0x3157
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#define mmDAGB7_WR_DATA_CREDIT_BASE_IDX 1
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#define mmDAGB7_WR_MISC_CREDIT 0x3158
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#define mmDAGB7_WR_MISC_CREDIT_BASE_IDX 1
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#define mmDAGB7_WRCLI_ASK_PENDING 0x315d
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#define mmDAGB7_WRCLI_ASK_PENDING_BASE_IDX 1
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#define mmDAGB7_WRCLI_GO_PENDING 0x315e
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#define mmDAGB7_WRCLI_GO_PENDING_BASE_IDX 1
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#define mmDAGB7_WRCLI_GBLSEND_PENDING 0x315f
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#define mmDAGB7_WRCLI_GBLSEND_PENDING_BASE_IDX 1
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#define mmDAGB7_WRCLI_TLB_PENDING 0x3160
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#define mmDAGB7_WRCLI_TLB_PENDING_BASE_IDX 1
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#define mmDAGB7_WRCLI_OARB_PENDING 0x3161
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#define mmDAGB7_WRCLI_OARB_PENDING_BASE_IDX 1
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#define mmDAGB7_WRCLI_OSD_PENDING 0x3162
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#define mmDAGB7_WRCLI_OSD_PENDING_BASE_IDX 1
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#define mmDAGB7_WRCLI_DBUS_ASK_PENDING 0x3163
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#define mmDAGB7_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1
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#define mmDAGB7_WRCLI_DBUS_GO_PENDING 0x3164
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#define mmDAGB7_WRCLI_DBUS_GO_PENDING_BASE_IDX 1
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#define mmDAGB7_DAGB_DLY 0x3165
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#define mmDAGB7_DAGB_DLY_BASE_IDX 1
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#define mmDAGB7_CNTL_MISC 0x3166
|
#define mmDAGB7_CNTL_MISC_BASE_IDX 1
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#define mmDAGB7_CNTL_MISC2 0x3167
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#define mmDAGB7_CNTL_MISC2_BASE_IDX 1
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#define mmDAGB7_FIFO_EMPTY 0x3168
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#define mmDAGB7_FIFO_EMPTY_BASE_IDX 1
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#define mmDAGB7_FIFO_FULL 0x3169
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#define mmDAGB7_FIFO_FULL_BASE_IDX 1
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#define mmDAGB7_WR_CREDITS_FULL 0x316a
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#define mmDAGB7_WR_CREDITS_FULL_BASE_IDX 1
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#define mmDAGB7_RD_CREDITS_FULL 0x316b
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#define mmDAGB7_RD_CREDITS_FULL_BASE_IDX 1
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#define mmDAGB7_PERFCOUNTER_LO 0x316c
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#define mmDAGB7_PERFCOUNTER_LO_BASE_IDX 1
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#define mmDAGB7_PERFCOUNTER_HI 0x316d
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#define mmDAGB7_PERFCOUNTER_HI_BASE_IDX 1
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#define mmDAGB7_PERFCOUNTER0_CFG 0x316e
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#define mmDAGB7_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmDAGB7_PERFCOUNTER1_CFG 0x316f
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#define mmDAGB7_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmDAGB7_PERFCOUNTER2_CFG 0x3170
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#define mmDAGB7_PERFCOUNTER2_CFG_BASE_IDX 1
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#define mmDAGB7_PERFCOUNTER_RSLT_CNTL 0x3171
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#define mmDAGB7_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmDAGB7_RESERVE0 0x3172
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#define mmDAGB7_RESERVE0_BASE_IDX 1
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#define mmDAGB7_RESERVE1 0x3173
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#define mmDAGB7_RESERVE1_BASE_IDX 1
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#define mmDAGB7_RESERVE2 0x3174
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#define mmDAGB7_RESERVE2_BASE_IDX 1
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#define mmDAGB7_RESERVE3 0x3175
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#define mmDAGB7_RESERVE3_BASE_IDX 1
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#define mmDAGB7_RESERVE4 0x3176
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#define mmDAGB7_RESERVE4_BASE_IDX 1
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#define mmDAGB7_RESERVE5 0x3177
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#define mmDAGB7_RESERVE5_BASE_IDX 1
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#define mmDAGB7_RESERVE6 0x3178
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#define mmDAGB7_RESERVE6_BASE_IDX 1
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#define mmDAGB7_RESERVE7 0x3179
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#define mmDAGB7_RESERVE7_BASE_IDX 1
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#define mmDAGB7_RESERVE8 0x317a
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#define mmDAGB7_RESERVE8_BASE_IDX 1
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#define mmDAGB7_RESERVE9 0x317b
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#define mmDAGB7_RESERVE9_BASE_IDX 1
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#define mmDAGB7_RESERVE10 0x317c
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#define mmDAGB7_RESERVE10_BASE_IDX 1
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#define mmDAGB7_RESERVE11 0x317d
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#define mmDAGB7_RESERVE11_BASE_IDX 1
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#define mmDAGB7_RESERVE12 0x317e
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#define mmDAGB7_RESERVE12_BASE_IDX 1
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#define mmDAGB7_RESERVE13 0x317f
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#define mmDAGB7_RESERVE13_BASE_IDX 1
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|
|
// addressBlock: mmhub_ea_mmeadec5
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// base address: 0x74a00
|
#define mmMMEA5_DRAM_RD_CLI2GRP_MAP0 0x3280
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#define mmMMEA5_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA5_DRAM_RD_CLI2GRP_MAP1 0x3281
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#define mmMMEA5_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA5_DRAM_WR_CLI2GRP_MAP0 0x3282
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#define mmMMEA5_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA5_DRAM_WR_CLI2GRP_MAP1 0x3283
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#define mmMMEA5_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA5_DRAM_RD_GRP2VC_MAP 0x3284
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#define mmMMEA5_DRAM_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA5_DRAM_WR_GRP2VC_MAP 0x3285
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#define mmMMEA5_DRAM_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA5_DRAM_RD_LAZY 0x3286
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#define mmMMEA5_DRAM_RD_LAZY_BASE_IDX 1
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#define mmMMEA5_DRAM_WR_LAZY 0x3287
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#define mmMMEA5_DRAM_WR_LAZY_BASE_IDX 1
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#define mmMMEA5_DRAM_RD_CAM_CNTL 0x3288
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#define mmMMEA5_DRAM_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA5_DRAM_WR_CAM_CNTL 0x3289
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#define mmMMEA5_DRAM_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA5_DRAM_PAGE_BURST 0x328a
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#define mmMMEA5_DRAM_PAGE_BURST_BASE_IDX 1
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#define mmMMEA5_DRAM_RD_PRI_AGE 0x328b
|
#define mmMMEA5_DRAM_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA5_DRAM_WR_PRI_AGE 0x328c
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#define mmMMEA5_DRAM_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA5_DRAM_RD_PRI_QUEUING 0x328d
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#define mmMMEA5_DRAM_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA5_DRAM_WR_PRI_QUEUING 0x328e
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#define mmMMEA5_DRAM_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA5_DRAM_RD_PRI_FIXED 0x328f
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#define mmMMEA5_DRAM_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA5_DRAM_WR_PRI_FIXED 0x3290
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#define mmMMEA5_DRAM_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA5_DRAM_RD_PRI_URGENCY 0x3291
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#define mmMMEA5_DRAM_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA5_DRAM_WR_PRI_URGENCY 0x3292
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#define mmMMEA5_DRAM_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1 0x3293
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#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2 0x3294
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#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3 0x3295
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#define mmMMEA5_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1 0x3296
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#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2 0x3297
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#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3 0x3298
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#define mmMMEA5_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA5_GMI_RD_CLI2GRP_MAP0 0x3299
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#define mmMMEA5_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA5_GMI_RD_CLI2GRP_MAP1 0x329a
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#define mmMMEA5_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA5_GMI_WR_CLI2GRP_MAP0 0x329b
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#define mmMMEA5_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA5_GMI_WR_CLI2GRP_MAP1 0x329c
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#define mmMMEA5_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA5_GMI_RD_GRP2VC_MAP 0x329d
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#define mmMMEA5_GMI_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA5_GMI_WR_GRP2VC_MAP 0x329e
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#define mmMMEA5_GMI_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA5_GMI_RD_LAZY 0x329f
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#define mmMMEA5_GMI_RD_LAZY_BASE_IDX 1
|
#define mmMMEA5_GMI_WR_LAZY 0x32a0
|
#define mmMMEA5_GMI_WR_LAZY_BASE_IDX 1
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#define mmMMEA5_GMI_RD_CAM_CNTL 0x32a1
|
#define mmMMEA5_GMI_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA5_GMI_WR_CAM_CNTL 0x32a2
|
#define mmMMEA5_GMI_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA5_GMI_PAGE_BURST 0x32a3
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#define mmMMEA5_GMI_PAGE_BURST_BASE_IDX 1
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#define mmMMEA5_GMI_RD_PRI_AGE 0x32a4
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#define mmMMEA5_GMI_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA5_GMI_WR_PRI_AGE 0x32a5
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#define mmMMEA5_GMI_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA5_GMI_RD_PRI_QUEUING 0x32a6
|
#define mmMMEA5_GMI_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA5_GMI_WR_PRI_QUEUING 0x32a7
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#define mmMMEA5_GMI_WR_PRI_QUEUING_BASE_IDX 1
|
#define mmMMEA5_GMI_RD_PRI_FIXED 0x32a8
|
#define mmMMEA5_GMI_RD_PRI_FIXED_BASE_IDX 1
|
#define mmMMEA5_GMI_WR_PRI_FIXED 0x32a9
|
#define mmMMEA5_GMI_WR_PRI_FIXED_BASE_IDX 1
|
#define mmMMEA5_GMI_RD_PRI_URGENCY 0x32aa
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#define mmMMEA5_GMI_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA5_GMI_WR_PRI_URGENCY 0x32ab
|
#define mmMMEA5_GMI_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING 0x32ac
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#define mmMMEA5_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1
|
#define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING 0x32ad
|
#define mmMMEA5_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA5_GMI_RD_PRI_QUANT_PRI1 0x32ae
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#define mmMMEA5_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA5_GMI_RD_PRI_QUANT_PRI2 0x32af
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#define mmMMEA5_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA5_GMI_RD_PRI_QUANT_PRI3 0x32b0
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#define mmMMEA5_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA5_GMI_WR_PRI_QUANT_PRI1 0x32b1
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#define mmMMEA5_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA5_GMI_WR_PRI_QUANT_PRI2 0x32b2
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#define mmMMEA5_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA5_GMI_WR_PRI_QUANT_PRI3 0x32b3
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#define mmMMEA5_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_BASE_ADDR0 0x32b4
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#define mmMMEA5_ADDRNORM_BASE_ADDR0_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_LIMIT_ADDR0 0x32b5
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#define mmMMEA5_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_BASE_ADDR1 0x32b6
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#define mmMMEA5_ADDRNORM_BASE_ADDR1_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_LIMIT_ADDR1 0x32b7
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#define mmMMEA5_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_OFFSET_ADDR1 0x32b8
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#define mmMMEA5_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_BASE_ADDR2 0x32b9
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#define mmMMEA5_ADDRNORM_BASE_ADDR2_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_LIMIT_ADDR2 0x32ba
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#define mmMMEA5_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_BASE_ADDR3 0x32bb
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#define mmMMEA5_ADDRNORM_BASE_ADDR3_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_LIMIT_ADDR3 0x32bc
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#define mmMMEA5_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_OFFSET_ADDR3 0x32bd
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#define mmMMEA5_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_BASE_ADDR4 0x32be
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#define mmMMEA5_ADDRNORM_BASE_ADDR4_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_LIMIT_ADDR4 0x32bf
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#define mmMMEA5_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_BASE_ADDR5 0x32c0
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#define mmMMEA5_ADDRNORM_BASE_ADDR5_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_LIMIT_ADDR5 0x32c1
|
#define mmMMEA5_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1
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#define mmMMEA5_ADDRNORM_OFFSET_ADDR5 0x32c2
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#define mmMMEA5_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1
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#define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL 0x32c3
|
#define mmMMEA5_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1
|
#define mmMMEA5_ADDRNORMGMI_HOLE_CNTL 0x32c4
|
#define mmMMEA5_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1
|
#define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x32c5
|
#define mmMMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1
|
#define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG 0x32c6
|
#define mmMMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC_BANK_CFG 0x32c7
|
#define mmMMEA5_ADDRDEC_BANK_CFG_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC_MISC_CFG 0x32c8
|
#define mmMMEA5_ADDRDEC_MISC_CFG_BASE_IDX 1
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#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0 0x32c9
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1 0x32ca
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2 0x32cb
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3 0x32cc
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4 0x32cd
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5 0x32ce
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC 0x32cf
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2 0x32d0
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0 0x32d1
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1 0x32d2
|
#define mmMMEA5_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1
|
#define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE 0x32d3
|
#define mmMMEA5_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0 0x32d4
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1 0x32d5
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2 0x32d6
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3 0x32d7
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4 0x32d8
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5 0x32d9
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC 0x32da
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2 0x32db
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0 0x32dc
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1 0x32dd
|
#define mmMMEA5_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1
|
#define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE 0x32de
|
#define mmMMEA5_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0 0x32df
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1 0x32e0
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2 0x32e1
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3 0x32e2
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0 0x32e3
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1 0x32e4
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2 0x32e5
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3 0x32e6
|
#define mmMMEA5_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01 0x32e7
|
#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23 0x32e8
|
#define mmMMEA5_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01 0x32e9
|
#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23 0x32ea
|
#define mmMMEA5_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01 0x32eb
|
#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23 0x32ec
|
#define mmMMEA5_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01 0x32ed
|
#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23 0x32ee
|
#define mmMMEA5_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01 0x32ef
|
#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23 0x32f0
|
#define mmMMEA5_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01 0x32f1
|
#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23 0x32f2
|
#define mmMMEA5_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01 0x32f3
|
#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23 0x32f4
|
#define mmMMEA5_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_RM_SEL_CS01 0x32f5
|
#define mmMMEA5_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_RM_SEL_CS23 0x32f6
|
#define mmMMEA5_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01 0x32f7
|
#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23 0x32f8
|
#define mmMMEA5_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0 0x32f9
|
#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1
|
#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1 0x32fa
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2 0x32fb
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3 0x32fc
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0 0x32fd
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1 0x32fe
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2 0x32ff
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3 0x3300
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#define mmMMEA5_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01 0x3301
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#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23 0x3302
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#define mmMMEA5_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01 0x3303
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#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23 0x3304
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#define mmMMEA5_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01 0x3305
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#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23 0x3306
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#define mmMMEA5_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01 0x3307
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#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23 0x3308
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#define mmMMEA5_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01 0x3309
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#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23 0x330a
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#define mmMMEA5_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01 0x330b
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#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23 0x330c
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#define mmMMEA5_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01 0x330d
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#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23 0x330e
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#define mmMMEA5_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_RM_SEL_CS01 0x330f
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#define mmMMEA5_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_RM_SEL_CS23 0x3310
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#define mmMMEA5_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01 0x3311
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#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23 0x3312
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#define mmMMEA5_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0 0x3313
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1 0x3314
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2 0x3315
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3 0x3316
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0 0x3317
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1 0x3318
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2 0x3319
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3 0x331a
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#define mmMMEA5_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01 0x331b
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#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23 0x331c
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#define mmMMEA5_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01 0x331d
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#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23 0x331e
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#define mmMMEA5_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01 0x331f
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#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23 0x3320
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#define mmMMEA5_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01 0x3321
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#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23 0x3322
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#define mmMMEA5_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01 0x3323
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#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23 0x3324
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#define mmMMEA5_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01 0x3325
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#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23 0x3326
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#define mmMMEA5_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01 0x3327
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#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23 0x3328
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#define mmMMEA5_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_RM_SEL_CS01 0x3329
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#define mmMMEA5_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_RM_SEL_CS23 0x332a
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#define mmMMEA5_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01 0x332b
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#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23 0x332c
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#define mmMMEA5_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL 0x332d
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#define mmMMEA5_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL 0x332e
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#define mmMMEA5_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA5_IO_RD_CLI2GRP_MAP0 0x3355
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#define mmMMEA5_IO_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA5_IO_RD_CLI2GRP_MAP1 0x3356
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#define mmMMEA5_IO_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA5_IO_WR_CLI2GRP_MAP0 0x3357
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#define mmMMEA5_IO_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA5_IO_WR_CLI2GRP_MAP1 0x3358
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#define mmMMEA5_IO_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA5_IO_RD_COMBINE_FLUSH 0x3359
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#define mmMMEA5_IO_RD_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA5_IO_WR_COMBINE_FLUSH 0x335a
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#define mmMMEA5_IO_WR_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA5_IO_GROUP_BURST 0x335b
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#define mmMMEA5_IO_GROUP_BURST_BASE_IDX 1
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#define mmMMEA5_IO_RD_PRI_AGE 0x335c
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#define mmMMEA5_IO_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA5_IO_WR_PRI_AGE 0x335d
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#define mmMMEA5_IO_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA5_IO_RD_PRI_QUEUING 0x335e
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#define mmMMEA5_IO_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA5_IO_WR_PRI_QUEUING 0x335f
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#define mmMMEA5_IO_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA5_IO_RD_PRI_FIXED 0x3360
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#define mmMMEA5_IO_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA5_IO_WR_PRI_FIXED 0x3361
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#define mmMMEA5_IO_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA5_IO_RD_PRI_URGENCY 0x3362
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#define mmMMEA5_IO_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA5_IO_WR_PRI_URGENCY 0x3363
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#define mmMMEA5_IO_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA5_IO_RD_PRI_URGENCY_MASKING 0x3364
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#define mmMMEA5_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA5_IO_WR_PRI_URGENCY_MASKING 0x3365
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#define mmMMEA5_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA5_IO_RD_PRI_QUANT_PRI1 0x3366
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#define mmMMEA5_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA5_IO_RD_PRI_QUANT_PRI2 0x3367
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#define mmMMEA5_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA5_IO_RD_PRI_QUANT_PRI3 0x3368
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#define mmMMEA5_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA5_IO_WR_PRI_QUANT_PRI1 0x3369
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#define mmMMEA5_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA5_IO_WR_PRI_QUANT_PRI2 0x336a
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#define mmMMEA5_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA5_IO_WR_PRI_QUANT_PRI3 0x336b
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#define mmMMEA5_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA5_SDP_ARB_DRAM 0x336c
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#define mmMMEA5_SDP_ARB_DRAM_BASE_IDX 1
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#define mmMMEA5_SDP_ARB_GMI 0x336d
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#define mmMMEA5_SDP_ARB_GMI_BASE_IDX 1
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#define mmMMEA5_SDP_ARB_FINAL 0x336e
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#define mmMMEA5_SDP_ARB_FINAL_BASE_IDX 1
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#define mmMMEA5_SDP_DRAM_PRIORITY 0x336f
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#define mmMMEA5_SDP_DRAM_PRIORITY_BASE_IDX 1
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#define mmMMEA5_SDP_GMI_PRIORITY 0x3370
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#define mmMMEA5_SDP_GMI_PRIORITY_BASE_IDX 1
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#define mmMMEA5_SDP_IO_PRIORITY 0x3371
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#define mmMMEA5_SDP_IO_PRIORITY_BASE_IDX 1
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#define mmMMEA5_SDP_CREDITS 0x3372
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#define mmMMEA5_SDP_CREDITS_BASE_IDX 1
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#define mmMMEA5_SDP_TAG_RESERVE0 0x3373
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#define mmMMEA5_SDP_TAG_RESERVE0_BASE_IDX 1
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#define mmMMEA5_SDP_TAG_RESERVE1 0x3374
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#define mmMMEA5_SDP_TAG_RESERVE1_BASE_IDX 1
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#define mmMMEA5_SDP_VCC_RESERVE0 0x3375
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#define mmMMEA5_SDP_VCC_RESERVE0_BASE_IDX 1
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#define mmMMEA5_SDP_VCC_RESERVE1 0x3376
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#define mmMMEA5_SDP_VCC_RESERVE1_BASE_IDX 1
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#define mmMMEA5_SDP_VCD_RESERVE0 0x3377
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#define mmMMEA5_SDP_VCD_RESERVE0_BASE_IDX 1
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#define mmMMEA5_SDP_VCD_RESERVE1 0x3378
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#define mmMMEA5_SDP_VCD_RESERVE1_BASE_IDX 1
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#define mmMMEA5_SDP_REQ_CNTL 0x3379
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#define mmMMEA5_SDP_REQ_CNTL_BASE_IDX 1
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#define mmMMEA5_MISC 0x337a
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#define mmMMEA5_MISC_BASE_IDX 1
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#define mmMMEA5_LATENCY_SAMPLING 0x337b
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#define mmMMEA5_LATENCY_SAMPLING_BASE_IDX 1
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#define mmMMEA5_PERFCOUNTER_LO 0x337c
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#define mmMMEA5_PERFCOUNTER_LO_BASE_IDX 1
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#define mmMMEA5_PERFCOUNTER_HI 0x337d
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#define mmMMEA5_PERFCOUNTER_HI_BASE_IDX 1
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#define mmMMEA5_PERFCOUNTER0_CFG 0x337e
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#define mmMMEA5_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmMMEA5_PERFCOUNTER1_CFG 0x337f
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#define mmMMEA5_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmMMEA5_PERFCOUNTER_RSLT_CNTL 0x3380
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#define mmMMEA5_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmMMEA5_EDC_CNT 0x3386
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#define mmMMEA5_EDC_CNT_BASE_IDX 1
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#define mmMMEA5_EDC_CNT2 0x3387
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#define mmMMEA5_EDC_CNT2_BASE_IDX 1
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#define mmMMEA5_DSM_CNTL 0x3388
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#define mmMMEA5_DSM_CNTL_BASE_IDX 1
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#define mmMMEA5_DSM_CNTLA 0x3389
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#define mmMMEA5_DSM_CNTLA_BASE_IDX 1
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#define mmMMEA5_DSM_CNTLB 0x338a
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#define mmMMEA5_DSM_CNTLB_BASE_IDX 1
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#define mmMMEA5_DSM_CNTL2 0x338b
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#define mmMMEA5_DSM_CNTL2_BASE_IDX 1
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#define mmMMEA5_DSM_CNTL2A 0x338c
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#define mmMMEA5_DSM_CNTL2A_BASE_IDX 1
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#define mmMMEA5_DSM_CNTL2B 0x338d
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#define mmMMEA5_DSM_CNTL2B_BASE_IDX 1
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#define mmMMEA5_CGTT_CLK_CTRL 0x338f
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#define mmMMEA5_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmMMEA5_EDC_MODE 0x3390
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#define mmMMEA5_EDC_MODE_BASE_IDX 1
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#define mmMMEA5_ERR_STATUS 0x3391
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#define mmMMEA5_ERR_STATUS_BASE_IDX 1
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#define mmMMEA5_MISC2 0x3392
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#define mmMMEA5_MISC2_BASE_IDX 1
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#define mmMMEA5_ADDRDEC_SELECT 0x3393
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#define mmMMEA5_ADDRDEC_SELECT_BASE_IDX 1
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#define mmMMEA5_EDC_CNT3 0x3394
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#define mmMMEA5_EDC_CNT3_BASE_IDX 1
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// addressBlock: mmhub_ea_mmeadec6
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// base address: 0x74f00
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#define mmMMEA6_DRAM_RD_CLI2GRP_MAP0 0x33c0
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#define mmMMEA6_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA6_DRAM_RD_CLI2GRP_MAP1 0x33c1
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#define mmMMEA6_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA6_DRAM_WR_CLI2GRP_MAP0 0x33c2
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#define mmMMEA6_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA6_DRAM_WR_CLI2GRP_MAP1 0x33c3
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#define mmMMEA6_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA6_DRAM_RD_GRP2VC_MAP 0x33c4
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#define mmMMEA6_DRAM_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA6_DRAM_WR_GRP2VC_MAP 0x33c5
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#define mmMMEA6_DRAM_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA6_DRAM_RD_LAZY 0x33c6
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#define mmMMEA6_DRAM_RD_LAZY_BASE_IDX 1
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#define mmMMEA6_DRAM_WR_LAZY 0x33c7
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#define mmMMEA6_DRAM_WR_LAZY_BASE_IDX 1
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#define mmMMEA6_DRAM_RD_CAM_CNTL 0x33c8
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#define mmMMEA6_DRAM_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA6_DRAM_WR_CAM_CNTL 0x33c9
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#define mmMMEA6_DRAM_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA6_DRAM_PAGE_BURST 0x33ca
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#define mmMMEA6_DRAM_PAGE_BURST_BASE_IDX 1
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#define mmMMEA6_DRAM_RD_PRI_AGE 0x33cb
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#define mmMMEA6_DRAM_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA6_DRAM_WR_PRI_AGE 0x33cc
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#define mmMMEA6_DRAM_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA6_DRAM_RD_PRI_QUEUING 0x33cd
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#define mmMMEA6_DRAM_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA6_DRAM_WR_PRI_QUEUING 0x33ce
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#define mmMMEA6_DRAM_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA6_DRAM_RD_PRI_FIXED 0x33cf
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#define mmMMEA6_DRAM_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA6_DRAM_WR_PRI_FIXED 0x33d0
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#define mmMMEA6_DRAM_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA6_DRAM_RD_PRI_URGENCY 0x33d1
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#define mmMMEA6_DRAM_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA6_DRAM_WR_PRI_URGENCY 0x33d2
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#define mmMMEA6_DRAM_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1 0x33d3
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#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2 0x33d4
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#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3 0x33d5
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#define mmMMEA6_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1 0x33d6
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#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2 0x33d7
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#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3 0x33d8
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#define mmMMEA6_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA6_GMI_RD_CLI2GRP_MAP0 0x33d9
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#define mmMMEA6_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA6_GMI_RD_CLI2GRP_MAP1 0x33da
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#define mmMMEA6_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA6_GMI_WR_CLI2GRP_MAP0 0x33db
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#define mmMMEA6_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA6_GMI_WR_CLI2GRP_MAP1 0x33dc
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#define mmMMEA6_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA6_GMI_RD_GRP2VC_MAP 0x33dd
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#define mmMMEA6_GMI_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA6_GMI_WR_GRP2VC_MAP 0x33de
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#define mmMMEA6_GMI_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA6_GMI_RD_LAZY 0x33df
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#define mmMMEA6_GMI_RD_LAZY_BASE_IDX 1
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#define mmMMEA6_GMI_WR_LAZY 0x33e0
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#define mmMMEA6_GMI_WR_LAZY_BASE_IDX 1
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#define mmMMEA6_GMI_RD_CAM_CNTL 0x33e1
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#define mmMMEA6_GMI_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA6_GMI_WR_CAM_CNTL 0x33e2
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#define mmMMEA6_GMI_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA6_GMI_PAGE_BURST 0x33e3
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#define mmMMEA6_GMI_PAGE_BURST_BASE_IDX 1
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#define mmMMEA6_GMI_RD_PRI_AGE 0x33e4
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#define mmMMEA6_GMI_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA6_GMI_WR_PRI_AGE 0x33e5
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#define mmMMEA6_GMI_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA6_GMI_RD_PRI_QUEUING 0x33e6
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#define mmMMEA6_GMI_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA6_GMI_WR_PRI_QUEUING 0x33e7
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#define mmMMEA6_GMI_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA6_GMI_RD_PRI_FIXED 0x33e8
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#define mmMMEA6_GMI_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA6_GMI_WR_PRI_FIXED 0x33e9
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#define mmMMEA6_GMI_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA6_GMI_RD_PRI_URGENCY 0x33ea
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#define mmMMEA6_GMI_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA6_GMI_WR_PRI_URGENCY 0x33eb
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#define mmMMEA6_GMI_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING 0x33ec
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#define mmMMEA6_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING 0x33ed
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#define mmMMEA6_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA6_GMI_RD_PRI_QUANT_PRI1 0x33ee
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#define mmMMEA6_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA6_GMI_RD_PRI_QUANT_PRI2 0x33ef
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#define mmMMEA6_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA6_GMI_RD_PRI_QUANT_PRI3 0x33f0
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#define mmMMEA6_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA6_GMI_WR_PRI_QUANT_PRI1 0x33f1
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#define mmMMEA6_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA6_GMI_WR_PRI_QUANT_PRI2 0x33f2
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#define mmMMEA6_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA6_GMI_WR_PRI_QUANT_PRI3 0x33f3
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#define mmMMEA6_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_BASE_ADDR0 0x33f4
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#define mmMMEA6_ADDRNORM_BASE_ADDR0_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_LIMIT_ADDR0 0x33f5
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#define mmMMEA6_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_BASE_ADDR1 0x33f6
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#define mmMMEA6_ADDRNORM_BASE_ADDR1_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_LIMIT_ADDR1 0x33f7
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#define mmMMEA6_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_OFFSET_ADDR1 0x33f8
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#define mmMMEA6_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_BASE_ADDR2 0x33f9
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#define mmMMEA6_ADDRNORM_BASE_ADDR2_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_LIMIT_ADDR2 0x33fa
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#define mmMMEA6_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_BASE_ADDR3 0x33fb
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#define mmMMEA6_ADDRNORM_BASE_ADDR3_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_LIMIT_ADDR3 0x33fc
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#define mmMMEA6_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_OFFSET_ADDR3 0x33fd
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#define mmMMEA6_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_BASE_ADDR4 0x33fe
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#define mmMMEA6_ADDRNORM_BASE_ADDR4_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_LIMIT_ADDR4 0x33ff
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#define mmMMEA6_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_BASE_ADDR5 0x3400
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#define mmMMEA6_ADDRNORM_BASE_ADDR5_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_LIMIT_ADDR5 0x3401
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#define mmMMEA6_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1
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#define mmMMEA6_ADDRNORM_OFFSET_ADDR5 0x3402
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#define mmMMEA6_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1
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#define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL 0x3403
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#define mmMMEA6_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1
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#define mmMMEA6_ADDRNORMGMI_HOLE_CNTL 0x3404
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#define mmMMEA6_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1
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#define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x3405
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#define mmMMEA6_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1
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#define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG 0x3406
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#define mmMMEA6_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1
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#define mmMMEA6_ADDRDEC_BANK_CFG 0x3407
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#define mmMMEA6_ADDRDEC_BANK_CFG_BASE_IDX 1
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#define mmMMEA6_ADDRDEC_MISC_CFG 0x3408
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#define mmMMEA6_ADDRDEC_MISC_CFG_BASE_IDX 1
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0 0x3409
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1 0x340a
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2 0x340b
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3 0x340c
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4 0x340d
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5 0x340e
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC 0x340f
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2 0x3410
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0 0x3411
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1 0x3412
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#define mmMMEA6_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1
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#define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE 0x3413
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#define mmMMEA6_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0 0x3414
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1 0x3415
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2 0x3416
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3 0x3417
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4 0x3418
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5 0x3419
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC 0x341a
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2 0x341b
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0 0x341c
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1 0x341d
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#define mmMMEA6_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1
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#define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE 0x341e
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#define mmMMEA6_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0 0x341f
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1 0x3420
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2 0x3421
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3 0x3422
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0 0x3423
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1 0x3424
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2 0x3425
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3 0x3426
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#define mmMMEA6_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01 0x3427
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#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23 0x3428
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#define mmMMEA6_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01 0x3429
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#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23 0x342a
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#define mmMMEA6_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01 0x342b
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#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23 0x342c
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#define mmMMEA6_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01 0x342d
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#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23 0x342e
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#define mmMMEA6_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01 0x342f
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#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23 0x3430
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#define mmMMEA6_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01 0x3431
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#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23 0x3432
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#define mmMMEA6_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01 0x3433
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#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23 0x3434
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#define mmMMEA6_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_RM_SEL_CS01 0x3435
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#define mmMMEA6_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_RM_SEL_CS23 0x3436
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#define mmMMEA6_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01 0x3437
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#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23 0x3438
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#define mmMMEA6_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0 0x3439
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1 0x343a
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2 0x343b
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3 0x343c
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0 0x343d
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1 0x343e
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2 0x343f
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3 0x3440
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#define mmMMEA6_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01 0x3441
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#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23 0x3442
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#define mmMMEA6_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01 0x3443
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#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23 0x3444
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#define mmMMEA6_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01 0x3445
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#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23 0x3446
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#define mmMMEA6_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01 0x3447
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#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23 0x3448
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#define mmMMEA6_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01 0x3449
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#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23 0x344a
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#define mmMMEA6_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01 0x344b
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#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23 0x344c
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#define mmMMEA6_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01 0x344d
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#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23 0x344e
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#define mmMMEA6_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_RM_SEL_CS01 0x344f
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#define mmMMEA6_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_RM_SEL_CS23 0x3450
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#define mmMMEA6_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01 0x3451
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#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23 0x3452
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#define mmMMEA6_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0 0x3453
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1 0x3454
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2 0x3455
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3 0x3456
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0 0x3457
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1 0x3458
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2 0x3459
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3 0x345a
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#define mmMMEA6_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01 0x345b
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#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23 0x345c
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#define mmMMEA6_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01 0x345d
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#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23 0x345e
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#define mmMMEA6_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01 0x345f
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#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23 0x3460
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#define mmMMEA6_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01 0x3461
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#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23 0x3462
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#define mmMMEA6_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01 0x3463
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#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23 0x3464
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#define mmMMEA6_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01 0x3465
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#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23 0x3466
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#define mmMMEA6_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01 0x3467
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#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23 0x3468
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#define mmMMEA6_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_RM_SEL_CS01 0x3469
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#define mmMMEA6_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_RM_SEL_CS23 0x346a
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#define mmMMEA6_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01 0x346b
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#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23 0x346c
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#define mmMMEA6_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL 0x346d
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#define mmMMEA6_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL 0x346e
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#define mmMMEA6_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA6_IO_RD_CLI2GRP_MAP0 0x3495
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#define mmMMEA6_IO_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA6_IO_RD_CLI2GRP_MAP1 0x3496
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#define mmMMEA6_IO_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA6_IO_WR_CLI2GRP_MAP0 0x3497
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#define mmMMEA6_IO_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA6_IO_WR_CLI2GRP_MAP1 0x3498
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#define mmMMEA6_IO_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA6_IO_RD_COMBINE_FLUSH 0x3499
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#define mmMMEA6_IO_RD_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA6_IO_WR_COMBINE_FLUSH 0x349a
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#define mmMMEA6_IO_WR_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA6_IO_GROUP_BURST 0x349b
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#define mmMMEA6_IO_GROUP_BURST_BASE_IDX 1
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#define mmMMEA6_IO_RD_PRI_AGE 0x349c
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#define mmMMEA6_IO_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA6_IO_WR_PRI_AGE 0x349d
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#define mmMMEA6_IO_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA6_IO_RD_PRI_QUEUING 0x349e
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#define mmMMEA6_IO_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA6_IO_WR_PRI_QUEUING 0x349f
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#define mmMMEA6_IO_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA6_IO_RD_PRI_FIXED 0x34a0
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#define mmMMEA6_IO_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA6_IO_WR_PRI_FIXED 0x34a1
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#define mmMMEA6_IO_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA6_IO_RD_PRI_URGENCY 0x34a2
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#define mmMMEA6_IO_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA6_IO_WR_PRI_URGENCY 0x34a3
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#define mmMMEA6_IO_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA6_IO_RD_PRI_URGENCY_MASKING 0x34a4
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#define mmMMEA6_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA6_IO_WR_PRI_URGENCY_MASKING 0x34a5
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#define mmMMEA6_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA6_IO_RD_PRI_QUANT_PRI1 0x34a6
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#define mmMMEA6_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA6_IO_RD_PRI_QUANT_PRI2 0x34a7
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#define mmMMEA6_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA6_IO_RD_PRI_QUANT_PRI3 0x34a8
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#define mmMMEA6_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA6_IO_WR_PRI_QUANT_PRI1 0x34a9
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#define mmMMEA6_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA6_IO_WR_PRI_QUANT_PRI2 0x34aa
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#define mmMMEA6_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA6_IO_WR_PRI_QUANT_PRI3 0x34ab
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#define mmMMEA6_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA6_SDP_ARB_DRAM 0x34ac
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#define mmMMEA6_SDP_ARB_DRAM_BASE_IDX 1
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#define mmMMEA6_SDP_ARB_GMI 0x34ad
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#define mmMMEA6_SDP_ARB_GMI_BASE_IDX 1
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#define mmMMEA6_SDP_ARB_FINAL 0x34ae
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#define mmMMEA6_SDP_ARB_FINAL_BASE_IDX 1
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#define mmMMEA6_SDP_DRAM_PRIORITY 0x34af
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#define mmMMEA6_SDP_DRAM_PRIORITY_BASE_IDX 1
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#define mmMMEA6_SDP_GMI_PRIORITY 0x34b0
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#define mmMMEA6_SDP_GMI_PRIORITY_BASE_IDX 1
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#define mmMMEA6_SDP_IO_PRIORITY 0x34b1
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#define mmMMEA6_SDP_IO_PRIORITY_BASE_IDX 1
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#define mmMMEA6_SDP_CREDITS 0x34b2
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#define mmMMEA6_SDP_CREDITS_BASE_IDX 1
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#define mmMMEA6_SDP_TAG_RESERVE0 0x34b3
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#define mmMMEA6_SDP_TAG_RESERVE0_BASE_IDX 1
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#define mmMMEA6_SDP_TAG_RESERVE1 0x34b4
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#define mmMMEA6_SDP_TAG_RESERVE1_BASE_IDX 1
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#define mmMMEA6_SDP_VCC_RESERVE0 0x34b5
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#define mmMMEA6_SDP_VCC_RESERVE0_BASE_IDX 1
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#define mmMMEA6_SDP_VCC_RESERVE1 0x34b6
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#define mmMMEA6_SDP_VCC_RESERVE1_BASE_IDX 1
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#define mmMMEA6_SDP_VCD_RESERVE0 0x34b7
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#define mmMMEA6_SDP_VCD_RESERVE0_BASE_IDX 1
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#define mmMMEA6_SDP_VCD_RESERVE1 0x34b8
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#define mmMMEA6_SDP_VCD_RESERVE1_BASE_IDX 1
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#define mmMMEA6_SDP_REQ_CNTL 0x34b9
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#define mmMMEA6_SDP_REQ_CNTL_BASE_IDX 1
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#define mmMMEA6_MISC 0x34ba
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#define mmMMEA6_MISC_BASE_IDX 1
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#define mmMMEA6_LATENCY_SAMPLING 0x34bb
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#define mmMMEA6_LATENCY_SAMPLING_BASE_IDX 1
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#define mmMMEA6_PERFCOUNTER_LO 0x34bc
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#define mmMMEA6_PERFCOUNTER_LO_BASE_IDX 1
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#define mmMMEA6_PERFCOUNTER_HI 0x34bd
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#define mmMMEA6_PERFCOUNTER_HI_BASE_IDX 1
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#define mmMMEA6_PERFCOUNTER0_CFG 0x34be
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#define mmMMEA6_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmMMEA6_PERFCOUNTER1_CFG 0x34bf
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#define mmMMEA6_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmMMEA6_PERFCOUNTER_RSLT_CNTL 0x34c0
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#define mmMMEA6_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmMMEA6_EDC_CNT 0x34c6
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#define mmMMEA6_EDC_CNT_BASE_IDX 1
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#define mmMMEA6_EDC_CNT2 0x34c7
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#define mmMMEA6_EDC_CNT2_BASE_IDX 1
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#define mmMMEA6_DSM_CNTL 0x34c8
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#define mmMMEA6_DSM_CNTL_BASE_IDX 1
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#define mmMMEA6_DSM_CNTLA 0x34c9
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#define mmMMEA6_DSM_CNTLA_BASE_IDX 1
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#define mmMMEA6_DSM_CNTLB 0x34ca
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#define mmMMEA6_DSM_CNTLB_BASE_IDX 1
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#define mmMMEA6_DSM_CNTL2 0x34cb
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#define mmMMEA6_DSM_CNTL2_BASE_IDX 1
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#define mmMMEA6_DSM_CNTL2A 0x34cc
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#define mmMMEA6_DSM_CNTL2A_BASE_IDX 1
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#define mmMMEA6_DSM_CNTL2B 0x34cd
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#define mmMMEA6_DSM_CNTL2B_BASE_IDX 1
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#define mmMMEA6_CGTT_CLK_CTRL 0x34cf
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#define mmMMEA6_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmMMEA6_EDC_MODE 0x34d0
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#define mmMMEA6_EDC_MODE_BASE_IDX 1
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#define mmMMEA6_ERR_STATUS 0x34d1
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#define mmMMEA6_ERR_STATUS_BASE_IDX 1
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#define mmMMEA6_MISC2 0x34d2
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#define mmMMEA6_MISC2_BASE_IDX 1
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#define mmMMEA6_ADDRDEC_SELECT 0x34d3
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#define mmMMEA6_ADDRDEC_SELECT_BASE_IDX 1
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#define mmMMEA6_EDC_CNT3 0x34d4
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#define mmMMEA6_EDC_CNT3_BASE_IDX 1
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|
|
// addressBlock: mmhub_ea_mmeadec7
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// base address: 0x75400
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#define mmMMEA7_DRAM_RD_CLI2GRP_MAP0 0x3500
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#define mmMMEA7_DRAM_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA7_DRAM_RD_CLI2GRP_MAP1 0x3501
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#define mmMMEA7_DRAM_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA7_DRAM_WR_CLI2GRP_MAP0 0x3502
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#define mmMMEA7_DRAM_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA7_DRAM_WR_CLI2GRP_MAP1 0x3503
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#define mmMMEA7_DRAM_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA7_DRAM_RD_GRP2VC_MAP 0x3504
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#define mmMMEA7_DRAM_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA7_DRAM_WR_GRP2VC_MAP 0x3505
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#define mmMMEA7_DRAM_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA7_DRAM_RD_LAZY 0x3506
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#define mmMMEA7_DRAM_RD_LAZY_BASE_IDX 1
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#define mmMMEA7_DRAM_WR_LAZY 0x3507
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#define mmMMEA7_DRAM_WR_LAZY_BASE_IDX 1
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#define mmMMEA7_DRAM_RD_CAM_CNTL 0x3508
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#define mmMMEA7_DRAM_RD_CAM_CNTL_BASE_IDX 1
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#define mmMMEA7_DRAM_WR_CAM_CNTL 0x3509
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#define mmMMEA7_DRAM_WR_CAM_CNTL_BASE_IDX 1
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#define mmMMEA7_DRAM_PAGE_BURST 0x350a
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#define mmMMEA7_DRAM_PAGE_BURST_BASE_IDX 1
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#define mmMMEA7_DRAM_RD_PRI_AGE 0x350b
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#define mmMMEA7_DRAM_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA7_DRAM_WR_PRI_AGE 0x350c
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#define mmMMEA7_DRAM_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA7_DRAM_RD_PRI_QUEUING 0x350d
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#define mmMMEA7_DRAM_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA7_DRAM_WR_PRI_QUEUING 0x350e
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#define mmMMEA7_DRAM_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA7_DRAM_RD_PRI_FIXED 0x350f
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#define mmMMEA7_DRAM_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA7_DRAM_WR_PRI_FIXED 0x3510
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#define mmMMEA7_DRAM_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA7_DRAM_RD_PRI_URGENCY 0x3511
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#define mmMMEA7_DRAM_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA7_DRAM_WR_PRI_URGENCY 0x3512
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#define mmMMEA7_DRAM_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1 0x3513
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#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2 0x3514
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#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3 0x3515
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#define mmMMEA7_DRAM_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1 0x3516
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#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2 0x3517
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#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3 0x3518
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#define mmMMEA7_DRAM_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA7_GMI_RD_CLI2GRP_MAP0 0x3519
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#define mmMMEA7_GMI_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA7_GMI_RD_CLI2GRP_MAP1 0x351a
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#define mmMMEA7_GMI_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA7_GMI_WR_CLI2GRP_MAP0 0x351b
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#define mmMMEA7_GMI_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA7_GMI_WR_CLI2GRP_MAP1 0x351c
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#define mmMMEA7_GMI_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA7_GMI_RD_GRP2VC_MAP 0x351d
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#define mmMMEA7_GMI_RD_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA7_GMI_WR_GRP2VC_MAP 0x351e
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#define mmMMEA7_GMI_WR_GRP2VC_MAP_BASE_IDX 1
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#define mmMMEA7_GMI_RD_LAZY 0x351f
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#define mmMMEA7_GMI_RD_LAZY_BASE_IDX 1
|
#define mmMMEA7_GMI_WR_LAZY 0x3520
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#define mmMMEA7_GMI_WR_LAZY_BASE_IDX 1
|
#define mmMMEA7_GMI_RD_CAM_CNTL 0x3521
|
#define mmMMEA7_GMI_RD_CAM_CNTL_BASE_IDX 1
|
#define mmMMEA7_GMI_WR_CAM_CNTL 0x3522
|
#define mmMMEA7_GMI_WR_CAM_CNTL_BASE_IDX 1
|
#define mmMMEA7_GMI_PAGE_BURST 0x3523
|
#define mmMMEA7_GMI_PAGE_BURST_BASE_IDX 1
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#define mmMMEA7_GMI_RD_PRI_AGE 0x3524
|
#define mmMMEA7_GMI_RD_PRI_AGE_BASE_IDX 1
|
#define mmMMEA7_GMI_WR_PRI_AGE 0x3525
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#define mmMMEA7_GMI_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA7_GMI_RD_PRI_QUEUING 0x3526
|
#define mmMMEA7_GMI_RD_PRI_QUEUING_BASE_IDX 1
|
#define mmMMEA7_GMI_WR_PRI_QUEUING 0x3527
|
#define mmMMEA7_GMI_WR_PRI_QUEUING_BASE_IDX 1
|
#define mmMMEA7_GMI_RD_PRI_FIXED 0x3528
|
#define mmMMEA7_GMI_RD_PRI_FIXED_BASE_IDX 1
|
#define mmMMEA7_GMI_WR_PRI_FIXED 0x3529
|
#define mmMMEA7_GMI_WR_PRI_FIXED_BASE_IDX 1
|
#define mmMMEA7_GMI_RD_PRI_URGENCY 0x352a
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#define mmMMEA7_GMI_RD_PRI_URGENCY_BASE_IDX 1
|
#define mmMMEA7_GMI_WR_PRI_URGENCY 0x352b
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#define mmMMEA7_GMI_WR_PRI_URGENCY_BASE_IDX 1
|
#define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING 0x352c
|
#define mmMMEA7_GMI_RD_PRI_URGENCY_MASKING_BASE_IDX 1
|
#define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING 0x352d
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#define mmMMEA7_GMI_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA7_GMI_RD_PRI_QUANT_PRI1 0x352e
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#define mmMMEA7_GMI_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA7_GMI_RD_PRI_QUANT_PRI2 0x352f
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#define mmMMEA7_GMI_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA7_GMI_RD_PRI_QUANT_PRI3 0x3530
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#define mmMMEA7_GMI_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA7_GMI_WR_PRI_QUANT_PRI1 0x3531
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#define mmMMEA7_GMI_WR_PRI_QUANT_PRI1_BASE_IDX 1
|
#define mmMMEA7_GMI_WR_PRI_QUANT_PRI2 0x3532
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#define mmMMEA7_GMI_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA7_GMI_WR_PRI_QUANT_PRI3 0x3533
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#define mmMMEA7_GMI_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA7_ADDRNORM_BASE_ADDR0 0x3534
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#define mmMMEA7_ADDRNORM_BASE_ADDR0_BASE_IDX 1
|
#define mmMMEA7_ADDRNORM_LIMIT_ADDR0 0x3535
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#define mmMMEA7_ADDRNORM_LIMIT_ADDR0_BASE_IDX 1
|
#define mmMMEA7_ADDRNORM_BASE_ADDR1 0x3536
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#define mmMMEA7_ADDRNORM_BASE_ADDR1_BASE_IDX 1
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#define mmMMEA7_ADDRNORM_LIMIT_ADDR1 0x3537
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#define mmMMEA7_ADDRNORM_LIMIT_ADDR1_BASE_IDX 1
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#define mmMMEA7_ADDRNORM_OFFSET_ADDR1 0x3538
|
#define mmMMEA7_ADDRNORM_OFFSET_ADDR1_BASE_IDX 1
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#define mmMMEA7_ADDRNORM_BASE_ADDR2 0x3539
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#define mmMMEA7_ADDRNORM_BASE_ADDR2_BASE_IDX 1
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#define mmMMEA7_ADDRNORM_LIMIT_ADDR2 0x353a
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#define mmMMEA7_ADDRNORM_LIMIT_ADDR2_BASE_IDX 1
|
#define mmMMEA7_ADDRNORM_BASE_ADDR3 0x353b
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#define mmMMEA7_ADDRNORM_BASE_ADDR3_BASE_IDX 1
|
#define mmMMEA7_ADDRNORM_LIMIT_ADDR3 0x353c
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#define mmMMEA7_ADDRNORM_LIMIT_ADDR3_BASE_IDX 1
|
#define mmMMEA7_ADDRNORM_OFFSET_ADDR3 0x353d
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#define mmMMEA7_ADDRNORM_OFFSET_ADDR3_BASE_IDX 1
|
#define mmMMEA7_ADDRNORM_BASE_ADDR4 0x353e
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#define mmMMEA7_ADDRNORM_BASE_ADDR4_BASE_IDX 1
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#define mmMMEA7_ADDRNORM_LIMIT_ADDR4 0x353f
|
#define mmMMEA7_ADDRNORM_LIMIT_ADDR4_BASE_IDX 1
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#define mmMMEA7_ADDRNORM_BASE_ADDR5 0x3540
|
#define mmMMEA7_ADDRNORM_BASE_ADDR5_BASE_IDX 1
|
#define mmMMEA7_ADDRNORM_LIMIT_ADDR5 0x3541
|
#define mmMMEA7_ADDRNORM_LIMIT_ADDR5_BASE_IDX 1
|
#define mmMMEA7_ADDRNORM_OFFSET_ADDR5 0x3542
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#define mmMMEA7_ADDRNORM_OFFSET_ADDR5_BASE_IDX 1
|
#define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL 0x3543
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#define mmMMEA7_ADDRNORMDRAM_HOLE_CNTL_BASE_IDX 1
|
#define mmMMEA7_ADDRNORMGMI_HOLE_CNTL 0x3544
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#define mmMMEA7_ADDRNORMGMI_HOLE_CNTL_BASE_IDX 1
|
#define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG 0x3545
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#define mmMMEA7_ADDRNORMDRAM_NP2_CHANNEL_CFG_BASE_IDX 1
|
#define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG 0x3546
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#define mmMMEA7_ADDRNORMGMI_NP2_CHANNEL_CFG_BASE_IDX 1
|
#define mmMMEA7_ADDRDEC_BANK_CFG 0x3547
|
#define mmMMEA7_ADDRDEC_BANK_CFG_BASE_IDX 1
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#define mmMMEA7_ADDRDEC_MISC_CFG 0x3548
|
#define mmMMEA7_ADDRDEC_MISC_CFG_BASE_IDX 1
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#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0 0x3549
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK0_BASE_IDX 1
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#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1 0x354a
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK1_BASE_IDX 1
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2 0x354b
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK2_BASE_IDX 1
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3 0x354c
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4 0x354d
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK4_BASE_IDX 1
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5 0x354e
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_BANK5_BASE_IDX 1
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC 0x354f
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC_BASE_IDX 1
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2 0x3550
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_PC2_BASE_IDX 1
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0 0x3551
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS0_BASE_IDX 1
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1 0x3552
|
#define mmMMEA7_ADDRDECDRAM_ADDR_HASH_CS1_BASE_IDX 1
|
#define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE 0x3553
|
#define mmMMEA7_ADDRDECDRAM_HARVEST_ENABLE_BASE_IDX 1
|
#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0 0x3554
|
#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK0_BASE_IDX 1
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1 0x3555
|
#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK1_BASE_IDX 1
|
#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2 0x3556
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK2_BASE_IDX 1
|
#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3 0x3557
|
#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK3_BASE_IDX 1
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4 0x3558
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK4_BASE_IDX 1
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5 0x3559
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_BANK5_BASE_IDX 1
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC 0x355a
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC_BASE_IDX 1
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2 0x355b
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_PC2_BASE_IDX 1
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0 0x355c
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS0_BASE_IDX 1
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1 0x355d
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#define mmMMEA7_ADDRDECGMI_ADDR_HASH_CS1_BASE_IDX 1
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#define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE 0x355e
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#define mmMMEA7_ADDRDECGMI_HARVEST_ENABLE_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0 0x355f
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1 0x3560
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2 0x3561
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3 0x3562
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0 0x3563
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1 0x3564
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2 0x3565
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3 0x3566
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#define mmMMEA7_ADDRDEC0_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01 0x3567
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#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23 0x3568
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#define mmMMEA7_ADDRDEC0_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01 0x3569
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#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23 0x356a
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#define mmMMEA7_ADDRDEC0_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01 0x356b
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#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23 0x356c
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#define mmMMEA7_ADDRDEC0_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01 0x356d
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#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23 0x356e
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#define mmMMEA7_ADDRDEC0_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01 0x356f
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#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23 0x3570
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#define mmMMEA7_ADDRDEC0_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01 0x3571
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#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23 0x3572
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#define mmMMEA7_ADDRDEC0_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01 0x3573
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#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23 0x3574
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#define mmMMEA7_ADDRDEC0_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_RM_SEL_CS01 0x3575
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#define mmMMEA7_ADDRDEC0_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_RM_SEL_CS23 0x3576
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#define mmMMEA7_ADDRDEC0_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01 0x3577
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#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23 0x3578
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#define mmMMEA7_ADDRDEC0_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0 0x3579
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1 0x357a
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2 0x357b
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3 0x357c
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0 0x357d
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1 0x357e
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2 0x357f
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3 0x3580
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#define mmMMEA7_ADDRDEC1_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01 0x3581
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#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23 0x3582
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#define mmMMEA7_ADDRDEC1_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01 0x3583
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#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23 0x3584
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#define mmMMEA7_ADDRDEC1_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01 0x3585
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#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23 0x3586
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#define mmMMEA7_ADDRDEC1_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01 0x3587
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#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23 0x3588
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#define mmMMEA7_ADDRDEC1_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01 0x3589
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#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23 0x358a
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#define mmMMEA7_ADDRDEC1_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01 0x358b
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#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23 0x358c
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#define mmMMEA7_ADDRDEC1_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01 0x358d
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#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23 0x358e
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#define mmMMEA7_ADDRDEC1_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_RM_SEL_CS01 0x358f
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#define mmMMEA7_ADDRDEC1_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_RM_SEL_CS23 0x3590
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#define mmMMEA7_ADDRDEC1_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01 0x3591
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#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23 0x3592
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#define mmMMEA7_ADDRDEC1_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0 0x3593
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS0_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1 0x3594
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS1_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2 0x3595
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS2_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3 0x3596
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_CS3_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0 0x3597
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS0_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1 0x3598
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS1_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2 0x3599
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS2_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3 0x359a
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#define mmMMEA7_ADDRDEC2_BASE_ADDR_SECCS3_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01 0x359b
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#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23 0x359c
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#define mmMMEA7_ADDRDEC2_ADDR_MASK_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01 0x359d
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#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23 0x359e
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#define mmMMEA7_ADDRDEC2_ADDR_MASK_SECCS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01 0x359f
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#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23 0x35a0
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#define mmMMEA7_ADDRDEC2_ADDR_CFG_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01 0x35a1
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#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23 0x35a2
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#define mmMMEA7_ADDRDEC2_ADDR_SEL_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01 0x35a3
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#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23 0x35a4
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#define mmMMEA7_ADDRDEC2_ADDR_SEL2_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01 0x35a5
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#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23 0x35a6
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#define mmMMEA7_ADDRDEC2_COL_SEL_LO_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01 0x35a7
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#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23 0x35a8
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#define mmMMEA7_ADDRDEC2_COL_SEL_HI_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_RM_SEL_CS01 0x35a9
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#define mmMMEA7_ADDRDEC2_RM_SEL_CS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_RM_SEL_CS23 0x35aa
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#define mmMMEA7_ADDRDEC2_RM_SEL_CS23_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01 0x35ab
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#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS01_BASE_IDX 1
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#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23 0x35ac
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#define mmMMEA7_ADDRDEC2_RM_SEL_SECCS23_BASE_IDX 1
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#define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL 0x35ad
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#define mmMMEA7_ADDRNORMDRAM_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL 0x35ae
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#define mmMMEA7_ADDRNORMGMI_GLOBAL_CNTL_BASE_IDX 1
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#define mmMMEA7_IO_RD_CLI2GRP_MAP0 0x35d5
|
#define mmMMEA7_IO_RD_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA7_IO_RD_CLI2GRP_MAP1 0x35d6
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#define mmMMEA7_IO_RD_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA7_IO_WR_CLI2GRP_MAP0 0x35d7
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#define mmMMEA7_IO_WR_CLI2GRP_MAP0_BASE_IDX 1
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#define mmMMEA7_IO_WR_CLI2GRP_MAP1 0x35d8
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#define mmMMEA7_IO_WR_CLI2GRP_MAP1_BASE_IDX 1
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#define mmMMEA7_IO_RD_COMBINE_FLUSH 0x35d9
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#define mmMMEA7_IO_RD_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA7_IO_WR_COMBINE_FLUSH 0x35da
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#define mmMMEA7_IO_WR_COMBINE_FLUSH_BASE_IDX 1
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#define mmMMEA7_IO_GROUP_BURST 0x35db
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#define mmMMEA7_IO_GROUP_BURST_BASE_IDX 1
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#define mmMMEA7_IO_RD_PRI_AGE 0x35dc
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#define mmMMEA7_IO_RD_PRI_AGE_BASE_IDX 1
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#define mmMMEA7_IO_WR_PRI_AGE 0x35dd
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#define mmMMEA7_IO_WR_PRI_AGE_BASE_IDX 1
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#define mmMMEA7_IO_RD_PRI_QUEUING 0x35de
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#define mmMMEA7_IO_RD_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA7_IO_WR_PRI_QUEUING 0x35df
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#define mmMMEA7_IO_WR_PRI_QUEUING_BASE_IDX 1
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#define mmMMEA7_IO_RD_PRI_FIXED 0x35e0
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#define mmMMEA7_IO_RD_PRI_FIXED_BASE_IDX 1
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#define mmMMEA7_IO_WR_PRI_FIXED 0x35e1
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#define mmMMEA7_IO_WR_PRI_FIXED_BASE_IDX 1
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#define mmMMEA7_IO_RD_PRI_URGENCY 0x35e2
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#define mmMMEA7_IO_RD_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA7_IO_WR_PRI_URGENCY 0x35e3
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#define mmMMEA7_IO_WR_PRI_URGENCY_BASE_IDX 1
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#define mmMMEA7_IO_RD_PRI_URGENCY_MASKING 0x35e4
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#define mmMMEA7_IO_RD_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA7_IO_WR_PRI_URGENCY_MASKING 0x35e5
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#define mmMMEA7_IO_WR_PRI_URGENCY_MASKING_BASE_IDX 1
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#define mmMMEA7_IO_RD_PRI_QUANT_PRI1 0x35e6
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#define mmMMEA7_IO_RD_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA7_IO_RD_PRI_QUANT_PRI2 0x35e7
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#define mmMMEA7_IO_RD_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA7_IO_RD_PRI_QUANT_PRI3 0x35e8
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#define mmMMEA7_IO_RD_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA7_IO_WR_PRI_QUANT_PRI1 0x35e9
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#define mmMMEA7_IO_WR_PRI_QUANT_PRI1_BASE_IDX 1
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#define mmMMEA7_IO_WR_PRI_QUANT_PRI2 0x35ea
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#define mmMMEA7_IO_WR_PRI_QUANT_PRI2_BASE_IDX 1
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#define mmMMEA7_IO_WR_PRI_QUANT_PRI3 0x35eb
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#define mmMMEA7_IO_WR_PRI_QUANT_PRI3_BASE_IDX 1
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#define mmMMEA7_SDP_ARB_DRAM 0x35ec
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#define mmMMEA7_SDP_ARB_DRAM_BASE_IDX 1
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#define mmMMEA7_SDP_ARB_GMI 0x35ed
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#define mmMMEA7_SDP_ARB_GMI_BASE_IDX 1
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#define mmMMEA7_SDP_ARB_FINAL 0x35ee
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#define mmMMEA7_SDP_ARB_FINAL_BASE_IDX 1
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#define mmMMEA7_SDP_DRAM_PRIORITY 0x35ef
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#define mmMMEA7_SDP_DRAM_PRIORITY_BASE_IDX 1
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#define mmMMEA7_SDP_GMI_PRIORITY 0x35f0
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#define mmMMEA7_SDP_GMI_PRIORITY_BASE_IDX 1
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#define mmMMEA7_SDP_IO_PRIORITY 0x35f1
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#define mmMMEA7_SDP_IO_PRIORITY_BASE_IDX 1
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#define mmMMEA7_SDP_CREDITS 0x35f2
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#define mmMMEA7_SDP_CREDITS_BASE_IDX 1
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#define mmMMEA7_SDP_TAG_RESERVE0 0x35f3
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#define mmMMEA7_SDP_TAG_RESERVE0_BASE_IDX 1
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#define mmMMEA7_SDP_TAG_RESERVE1 0x35f4
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#define mmMMEA7_SDP_TAG_RESERVE1_BASE_IDX 1
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#define mmMMEA7_SDP_VCC_RESERVE0 0x35f5
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#define mmMMEA7_SDP_VCC_RESERVE0_BASE_IDX 1
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#define mmMMEA7_SDP_VCC_RESERVE1 0x35f6
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#define mmMMEA7_SDP_VCC_RESERVE1_BASE_IDX 1
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#define mmMMEA7_SDP_VCD_RESERVE0 0x35f7
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#define mmMMEA7_SDP_VCD_RESERVE0_BASE_IDX 1
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#define mmMMEA7_SDP_VCD_RESERVE1 0x35f8
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#define mmMMEA7_SDP_VCD_RESERVE1_BASE_IDX 1
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#define mmMMEA7_SDP_REQ_CNTL 0x35f9
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#define mmMMEA7_SDP_REQ_CNTL_BASE_IDX 1
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#define mmMMEA7_MISC 0x35fa
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#define mmMMEA7_MISC_BASE_IDX 1
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#define mmMMEA7_LATENCY_SAMPLING 0x35fb
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#define mmMMEA7_LATENCY_SAMPLING_BASE_IDX 1
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#define mmMMEA7_PERFCOUNTER_LO 0x35fc
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#define mmMMEA7_PERFCOUNTER_LO_BASE_IDX 1
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#define mmMMEA7_PERFCOUNTER_HI 0x35fd
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#define mmMMEA7_PERFCOUNTER_HI_BASE_IDX 1
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#define mmMMEA7_PERFCOUNTER0_CFG 0x35fe
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#define mmMMEA7_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmMMEA7_PERFCOUNTER1_CFG 0x35ff
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#define mmMMEA7_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmMMEA7_PERFCOUNTER_RSLT_CNTL 0x3600
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#define mmMMEA7_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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#define mmMMEA7_EDC_CNT 0x3606
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#define mmMMEA7_EDC_CNT_BASE_IDX 1
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#define mmMMEA7_EDC_CNT2 0x3607
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#define mmMMEA7_EDC_CNT2_BASE_IDX 1
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#define mmMMEA7_DSM_CNTL 0x3608
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#define mmMMEA7_DSM_CNTL_BASE_IDX 1
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#define mmMMEA7_DSM_CNTLA 0x3609
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#define mmMMEA7_DSM_CNTLA_BASE_IDX 1
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#define mmMMEA7_DSM_CNTLB 0x360a
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#define mmMMEA7_DSM_CNTLB_BASE_IDX 1
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#define mmMMEA7_DSM_CNTL2 0x360b
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#define mmMMEA7_DSM_CNTL2_BASE_IDX 1
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#define mmMMEA7_DSM_CNTL2A 0x360c
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#define mmMMEA7_DSM_CNTL2A_BASE_IDX 1
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#define mmMMEA7_DSM_CNTL2B 0x360d
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#define mmMMEA7_DSM_CNTL2B_BASE_IDX 1
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#define mmMMEA7_CGTT_CLK_CTRL 0x360f
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#define mmMMEA7_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmMMEA7_EDC_MODE 0x3610
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#define mmMMEA7_EDC_MODE_BASE_IDX 1
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#define mmMMEA7_ERR_STATUS 0x3611
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#define mmMMEA7_ERR_STATUS_BASE_IDX 1
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#define mmMMEA7_MISC2 0x3612
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#define mmMMEA7_MISC2_BASE_IDX 1
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#define mmMMEA7_ADDRDEC_SELECT 0x3613
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#define mmMMEA7_ADDRDEC_SELECT_BASE_IDX 1
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#define mmMMEA7_EDC_CNT3 0x3614
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#define mmMMEA7_EDC_CNT3_BASE_IDX 1
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// addressBlock: mmhub_pctldec1
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// base address: 0x76300
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#define mmPCTL1_CTRL 0x38c0
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#define mmPCTL1_CTRL_BASE_IDX 1
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#define mmPCTL1_MMHUB_DEEPSLEEP_IB 0x38c1
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#define mmPCTL1_MMHUB_DEEPSLEEP_IB_BASE_IDX 1
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#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE 0x38c2
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#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1
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#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x38c3
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#define mmPCTL1_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1
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#define mmPCTL1_PG_IGNORE_DEEPSLEEP 0x38c4
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#define mmPCTL1_PG_IGNORE_DEEPSLEEP_BASE_IDX 1
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#define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB 0x38c5
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#define mmPCTL1_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1
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#define mmPCTL1_SLICE0_CFG_DAGB_BUSY 0x38c6
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#define mmPCTL1_SLICE0_CFG_DAGB_BUSY_BASE_IDX 1
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#define mmPCTL1_SLICE0_CFG_DS_ALLOW 0x38c7
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#define mmPCTL1_SLICE0_CFG_DS_ALLOW_BASE_IDX 1
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#define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB 0x38c8
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#define mmPCTL1_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1
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#define mmPCTL1_SLICE1_CFG_DAGB_BUSY 0x38c9
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#define mmPCTL1_SLICE1_CFG_DAGB_BUSY_BASE_IDX 1
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#define mmPCTL1_SLICE1_CFG_DS_ALLOW 0x38ca
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#define mmPCTL1_SLICE1_CFG_DS_ALLOW_BASE_IDX 1
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#define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB 0x38cb
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#define mmPCTL1_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1
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#define mmPCTL1_SLICE2_CFG_DAGB_BUSY 0x38cc
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#define mmPCTL1_SLICE2_CFG_DAGB_BUSY_BASE_IDX 1
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#define mmPCTL1_SLICE2_CFG_DS_ALLOW 0x38cd
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#define mmPCTL1_SLICE2_CFG_DS_ALLOW_BASE_IDX 1
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#define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB 0x38ce
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#define mmPCTL1_SLICE2_CFG_DS_ALLOW_IB_BASE_IDX 1
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#define mmPCTL1_SLICE3_CFG_DAGB_BUSY 0x38cf
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#define mmPCTL1_SLICE3_CFG_DAGB_BUSY_BASE_IDX 1
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#define mmPCTL1_SLICE3_CFG_DS_ALLOW 0x38d0
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#define mmPCTL1_SLICE3_CFG_DS_ALLOW_BASE_IDX 1
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#define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB 0x38d1
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#define mmPCTL1_SLICE3_CFG_DS_ALLOW_IB_BASE_IDX 1
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#define mmPCTL1_SLICE4_CFG_DAGB_BUSY 0x38d2
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#define mmPCTL1_SLICE4_CFG_DAGB_BUSY_BASE_IDX 1
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#define mmPCTL1_SLICE4_CFG_DS_ALLOW 0x38d3
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#define mmPCTL1_SLICE4_CFG_DS_ALLOW_BASE_IDX 1
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#define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB 0x38d4
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#define mmPCTL1_SLICE4_CFG_DS_ALLOW_IB_BASE_IDX 1
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#define mmPCTL1_UTCL2_MISC 0x38d5
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#define mmPCTL1_UTCL2_MISC_BASE_IDX 1
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#define mmPCTL1_SLICE0_MISC 0x38d6
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#define mmPCTL1_SLICE0_MISC_BASE_IDX 1
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#define mmPCTL1_SLICE1_MISC 0x38d7
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#define mmPCTL1_SLICE1_MISC_BASE_IDX 1
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#define mmPCTL1_SLICE2_MISC 0x38d8
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#define mmPCTL1_SLICE2_MISC_BASE_IDX 1
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#define mmPCTL1_SLICE3_MISC 0x38d9
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#define mmPCTL1_SLICE3_MISC_BASE_IDX 1
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#define mmPCTL1_SLICE4_MISC 0x38da
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#define mmPCTL1_SLICE4_MISC_BASE_IDX 1
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#define mmPCTL1_UTCL2_RENG_EXECUTE 0x38db
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#define mmPCTL1_UTCL2_RENG_EXECUTE_BASE_IDX 1
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#define mmPCTL1_SLICE0_RENG_EXECUTE 0x38dc
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#define mmPCTL1_SLICE0_RENG_EXECUTE_BASE_IDX 1
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#define mmPCTL1_SLICE1_RENG_EXECUTE 0x38dd
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#define mmPCTL1_SLICE1_RENG_EXECUTE_BASE_IDX 1
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#define mmPCTL1_SLICE2_RENG_EXECUTE 0x38de
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#define mmPCTL1_SLICE2_RENG_EXECUTE_BASE_IDX 1
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#define mmPCTL1_SLICE3_RENG_EXECUTE 0x38df
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#define mmPCTL1_SLICE3_RENG_EXECUTE_BASE_IDX 1
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#define mmPCTL1_SLICE4_RENG_EXECUTE 0x38e0
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#define mmPCTL1_SLICE4_RENG_EXECUTE_BASE_IDX 1
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#define mmPCTL1_UTCL2_RENG_RAM_INDEX 0x38e1
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#define mmPCTL1_UTCL2_RENG_RAM_INDEX_BASE_IDX 1
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#define mmPCTL1_UTCL2_RENG_RAM_DATA 0x38e2
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#define mmPCTL1_UTCL2_RENG_RAM_DATA_BASE_IDX 1
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#define mmPCTL1_SLICE0_RENG_RAM_INDEX 0x38e3
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#define mmPCTL1_SLICE0_RENG_RAM_INDEX_BASE_IDX 1
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#define mmPCTL1_SLICE0_RENG_RAM_DATA 0x38e4
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#define mmPCTL1_SLICE0_RENG_RAM_DATA_BASE_IDX 1
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#define mmPCTL1_SLICE1_RENG_RAM_INDEX 0x38e5
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#define mmPCTL1_SLICE1_RENG_RAM_INDEX_BASE_IDX 1
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#define mmPCTL1_SLICE1_RENG_RAM_DATA 0x38e6
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#define mmPCTL1_SLICE1_RENG_RAM_DATA_BASE_IDX 1
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#define mmPCTL1_SLICE2_RENG_RAM_INDEX 0x38e7
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#define mmPCTL1_SLICE2_RENG_RAM_INDEX_BASE_IDX 1
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#define mmPCTL1_SLICE2_RENG_RAM_DATA 0x38e8
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#define mmPCTL1_SLICE2_RENG_RAM_DATA_BASE_IDX 1
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#define mmPCTL1_SLICE3_RENG_RAM_INDEX 0x38e9
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#define mmPCTL1_SLICE3_RENG_RAM_INDEX_BASE_IDX 1
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#define mmPCTL1_SLICE3_RENG_RAM_DATA 0x38ea
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#define mmPCTL1_SLICE3_RENG_RAM_DATA_BASE_IDX 1
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#define mmPCTL1_SLICE4_RENG_RAM_INDEX 0x38eb
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#define mmPCTL1_SLICE4_RENG_RAM_INDEX_BASE_IDX 1
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#define mmPCTL1_SLICE4_RENG_RAM_DATA 0x38ec
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#define mmPCTL1_SLICE4_RENG_RAM_DATA_BASE_IDX 1
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x38ed
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x38ee
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x38ef
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x38f0
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x38f1
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x38f2
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x38f3
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#define mmPCTL1_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x38f4
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x38f5
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x38f6
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x38f7
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x38f8
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x38f9
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x38fa
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#define mmPCTL1_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x38fb
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x38fc
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x38fd
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x38fe
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x38ff
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x3900
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x3901
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#define mmPCTL1_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0 0x3902
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1 0x3903
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2 0x3904
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3 0x3905
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4 0x3906
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x3907
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x3908
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#define mmPCTL1_SLICE2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0 0x3909
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1 0x390a
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2 0x390b
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3 0x390c
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4 0x390d
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0 0x390e
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1 0x390f
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#define mmPCTL1_SLICE3_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0 0x3910
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1 0x3911
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2 0x3912
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3 0x3913
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4 0x3914
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0 0x3915
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1 0x3916
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#define mmPCTL1_SLICE4_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1
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// addressBlock: mmhub_l1tlb_vml1dec:1
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// base address: 0x76500
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#define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS 0x3948
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#define mmVML1_1_MC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1
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#define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS 0x3949
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#define mmVML1_1_MC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1
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#define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS 0x394a
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#define mmVML1_1_MC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1
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#define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS 0x394b
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#define mmVML1_1_MC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1
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#define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS 0x394c
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#define mmVML1_1_MC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1
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#define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS 0x394d
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#define mmVML1_1_MC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1
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#define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS 0x394e
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#define mmVML1_1_MC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1
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#define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS 0x394f
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#define mmVML1_1_MC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1
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// addressBlock: mmhub_l1tlb_vml1pldec:1
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// base address: 0x76580
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#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG 0x3960
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#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG 0x3961
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#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG 0x3962
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#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1
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#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG 0x3963
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#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1
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#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x3964
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#define mmVML1PL1_MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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// addressBlock: mmhub_l1tlb_vml1prdec:1
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// base address: 0x765c0
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#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO 0x3970
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#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1
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#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI 0x3971
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#define mmVML1PR1_MC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1
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// addressBlock: mmhub_utcl2_atcl2dec:1
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// base address: 0x76600
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#define mmATCL2_1_ATC_L2_CNTL 0x3980
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#define mmATCL2_1_ATC_L2_CNTL_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_CNTL2 0x3981
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#define mmATCL2_1_ATC_L2_CNTL2_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_CACHE_DATA0 0x3984
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#define mmATCL2_1_ATC_L2_CACHE_DATA0_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_CACHE_DATA1 0x3985
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#define mmATCL2_1_ATC_L2_CACHE_DATA1_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_CACHE_DATA2 0x3986
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#define mmATCL2_1_ATC_L2_CACHE_DATA2_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_CNTL3 0x3987
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#define mmATCL2_1_ATC_L2_CNTL3_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_STATUS 0x3988
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#define mmATCL2_1_ATC_L2_STATUS_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_STATUS2 0x3989
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#define mmATCL2_1_ATC_L2_STATUS2_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_STATUS3 0x398a
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#define mmATCL2_1_ATC_L2_STATUS3_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_MISC_CG 0x398b
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#define mmATCL2_1_ATC_L2_MISC_CG_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_MEM_POWER_LS 0x398c
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#define mmATCL2_1_ATC_L2_MEM_POWER_LS_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL 0x398d
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#define mmATCL2_1_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX 0x398e
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#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_INDEX_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX 0x398f
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#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_INDEX_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL 0x3990
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#define mmATCL2_1_ATC_L2_CACHE_4K_DSM_CNTL_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL 0x3991
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#define mmATCL2_1_ATC_L2_CACHE_2M_DSM_CNTL_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_CNTL4 0x3992
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#define mmATCL2_1_ATC_L2_CNTL4_BASE_IDX 1
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#define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES 0x3993
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#define mmATCL2_1_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vml2pfdec:1
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// base address: 0x76700
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#define mmVML2PF1_VM_L2_CNTL 0x39c0
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#define mmVML2PF1_VM_L2_CNTL_BASE_IDX 1
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#define mmVML2PF1_VM_L2_CNTL2 0x39c1
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#define mmVML2PF1_VM_L2_CNTL2_BASE_IDX 1
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#define mmVML2PF1_VM_L2_CNTL3 0x39c2
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#define mmVML2PF1_VM_L2_CNTL3_BASE_IDX 1
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#define mmVML2PF1_VM_L2_STATUS 0x39c3
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#define mmVML2PF1_VM_L2_STATUS_BASE_IDX 1
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#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL 0x39c4
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#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1
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#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32 0x39c5
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#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1
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#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32 0x39c6
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#define mmVML2PF1_VM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL 0x39c7
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2 0x39c8
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3 0x39c9
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4 0x39ca
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS 0x39cb
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32 0x39cc
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32 0x39cd
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x39ce
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x39cf
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#define mmVML2PF1_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1
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#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x39d1
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#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1
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#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x39d2
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#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1
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#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x39d3
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#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1
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#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x39d4
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#define mmVML2PF1_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1
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#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x39d5
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#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1
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#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x39d6
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#define mmVML2PF1_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1
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#define mmVML2PF1_VM_L2_CNTL4 0x39d7
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#define mmVML2PF1_VM_L2_CNTL4_BASE_IDX 1
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#define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES 0x39d8
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#define mmVML2PF1_VM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1
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#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID 0x39d9
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#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1
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#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2 0x39da
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#define mmVML2PF1_VM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1
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#define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL 0x39db
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#define mmVML2PF1_VM_L2_CACHE_PARITY_CNTL_BASE_IDX 1
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#define mmVML2PF1_VM_L2_CGTT_CLK_CTRL 0x39de
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#define mmVML2PF1_VM_L2_CGTT_CLK_CTRL_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vml2vcdec:1
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// base address: 0x76800
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#define mmVML2VC1_VM_CONTEXT0_CNTL 0x3a00
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#define mmVML2VC1_VM_CONTEXT0_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT1_CNTL 0x3a01
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#define mmVML2VC1_VM_CONTEXT1_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT2_CNTL 0x3a02
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#define mmVML2VC1_VM_CONTEXT2_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT3_CNTL 0x3a03
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#define mmVML2VC1_VM_CONTEXT3_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT4_CNTL 0x3a04
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#define mmVML2VC1_VM_CONTEXT4_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT5_CNTL 0x3a05
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#define mmVML2VC1_VM_CONTEXT5_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT6_CNTL 0x3a06
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#define mmVML2VC1_VM_CONTEXT6_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT7_CNTL 0x3a07
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#define mmVML2VC1_VM_CONTEXT7_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT8_CNTL 0x3a08
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#define mmVML2VC1_VM_CONTEXT8_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT9_CNTL 0x3a09
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#define mmVML2VC1_VM_CONTEXT9_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT10_CNTL 0x3a0a
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#define mmVML2VC1_VM_CONTEXT10_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT11_CNTL 0x3a0b
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#define mmVML2VC1_VM_CONTEXT11_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT12_CNTL 0x3a0c
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#define mmVML2VC1_VM_CONTEXT12_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT13_CNTL 0x3a0d
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#define mmVML2VC1_VM_CONTEXT13_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT14_CNTL 0x3a0e
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#define mmVML2VC1_VM_CONTEXT14_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT15_CNTL 0x3a0f
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#define mmVML2VC1_VM_CONTEXT15_CNTL_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXTS_DISABLE 0x3a10
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#define mmVML2VC1_VM_CONTEXTS_DISABLE_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG0_SEM 0x3a11
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#define mmVML2VC1_VM_INVALIDATE_ENG0_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG1_SEM 0x3a12
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#define mmVML2VC1_VM_INVALIDATE_ENG1_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG2_SEM 0x3a13
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#define mmVML2VC1_VM_INVALIDATE_ENG2_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG3_SEM 0x3a14
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#define mmVML2VC1_VM_INVALIDATE_ENG3_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG4_SEM 0x3a15
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#define mmVML2VC1_VM_INVALIDATE_ENG4_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG5_SEM 0x3a16
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#define mmVML2VC1_VM_INVALIDATE_ENG5_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG6_SEM 0x3a17
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#define mmVML2VC1_VM_INVALIDATE_ENG6_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG7_SEM 0x3a18
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#define mmVML2VC1_VM_INVALIDATE_ENG7_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG8_SEM 0x3a19
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#define mmVML2VC1_VM_INVALIDATE_ENG8_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG9_SEM 0x3a1a
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#define mmVML2VC1_VM_INVALIDATE_ENG9_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG10_SEM 0x3a1b
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#define mmVML2VC1_VM_INVALIDATE_ENG10_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG11_SEM 0x3a1c
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#define mmVML2VC1_VM_INVALIDATE_ENG11_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG12_SEM 0x3a1d
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#define mmVML2VC1_VM_INVALIDATE_ENG12_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG13_SEM 0x3a1e
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#define mmVML2VC1_VM_INVALIDATE_ENG13_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG14_SEM 0x3a1f
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#define mmVML2VC1_VM_INVALIDATE_ENG14_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG15_SEM 0x3a20
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#define mmVML2VC1_VM_INVALIDATE_ENG15_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG16_SEM 0x3a21
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#define mmVML2VC1_VM_INVALIDATE_ENG16_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG17_SEM 0x3a22
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#define mmVML2VC1_VM_INVALIDATE_ENG17_SEM_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG0_REQ 0x3a23
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#define mmVML2VC1_VM_INVALIDATE_ENG0_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG1_REQ 0x3a24
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#define mmVML2VC1_VM_INVALIDATE_ENG1_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG2_REQ 0x3a25
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#define mmVML2VC1_VM_INVALIDATE_ENG2_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG3_REQ 0x3a26
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#define mmVML2VC1_VM_INVALIDATE_ENG3_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG4_REQ 0x3a27
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#define mmVML2VC1_VM_INVALIDATE_ENG4_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG5_REQ 0x3a28
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#define mmVML2VC1_VM_INVALIDATE_ENG5_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG6_REQ 0x3a29
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#define mmVML2VC1_VM_INVALIDATE_ENG6_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG7_REQ 0x3a2a
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#define mmVML2VC1_VM_INVALIDATE_ENG7_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG8_REQ 0x3a2b
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#define mmVML2VC1_VM_INVALIDATE_ENG8_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG9_REQ 0x3a2c
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#define mmVML2VC1_VM_INVALIDATE_ENG9_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG10_REQ 0x3a2d
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#define mmVML2VC1_VM_INVALIDATE_ENG10_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG11_REQ 0x3a2e
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#define mmVML2VC1_VM_INVALIDATE_ENG11_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG12_REQ 0x3a2f
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#define mmVML2VC1_VM_INVALIDATE_ENG12_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG13_REQ 0x3a30
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#define mmVML2VC1_VM_INVALIDATE_ENG13_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG14_REQ 0x3a31
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#define mmVML2VC1_VM_INVALIDATE_ENG14_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG15_REQ 0x3a32
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#define mmVML2VC1_VM_INVALIDATE_ENG15_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG16_REQ 0x3a33
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#define mmVML2VC1_VM_INVALIDATE_ENG16_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG17_REQ 0x3a34
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#define mmVML2VC1_VM_INVALIDATE_ENG17_REQ_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG0_ACK 0x3a35
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#define mmVML2VC1_VM_INVALIDATE_ENG0_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG1_ACK 0x3a36
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#define mmVML2VC1_VM_INVALIDATE_ENG1_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG2_ACK 0x3a37
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#define mmVML2VC1_VM_INVALIDATE_ENG2_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG3_ACK 0x3a38
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#define mmVML2VC1_VM_INVALIDATE_ENG3_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG4_ACK 0x3a39
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#define mmVML2VC1_VM_INVALIDATE_ENG4_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG5_ACK 0x3a3a
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#define mmVML2VC1_VM_INVALIDATE_ENG5_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG6_ACK 0x3a3b
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#define mmVML2VC1_VM_INVALIDATE_ENG6_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG7_ACK 0x3a3c
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#define mmVML2VC1_VM_INVALIDATE_ENG7_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG8_ACK 0x3a3d
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#define mmVML2VC1_VM_INVALIDATE_ENG8_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG9_ACK 0x3a3e
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#define mmVML2VC1_VM_INVALIDATE_ENG9_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG10_ACK 0x3a3f
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#define mmVML2VC1_VM_INVALIDATE_ENG10_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG11_ACK 0x3a40
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#define mmVML2VC1_VM_INVALIDATE_ENG11_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG12_ACK 0x3a41
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#define mmVML2VC1_VM_INVALIDATE_ENG12_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG13_ACK 0x3a42
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#define mmVML2VC1_VM_INVALIDATE_ENG13_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG14_ACK 0x3a43
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#define mmVML2VC1_VM_INVALIDATE_ENG14_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG15_ACK 0x3a44
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#define mmVML2VC1_VM_INVALIDATE_ENG15_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG16_ACK 0x3a45
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#define mmVML2VC1_VM_INVALIDATE_ENG16_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG17_ACK 0x3a46
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#define mmVML2VC1_VM_INVALIDATE_ENG17_ACK_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x3a47
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#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x3a48
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#define mmVML2VC1_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x3a49
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#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x3a4a
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#define mmVML2VC1_VM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x3a4b
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#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x3a4c
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#define mmVML2VC1_VM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x3a4d
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#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x3a4e
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#define mmVML2VC1_VM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x3a4f
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#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x3a50
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#define mmVML2VC1_VM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x3a51
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#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x3a52
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#define mmVML2VC1_VM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x3a53
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#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x3a54
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#define mmVML2VC1_VM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x3a55
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#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x3a56
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#define mmVML2VC1_VM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x3a57
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#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x3a58
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#define mmVML2VC1_VM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x3a59
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#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x3a5a
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#define mmVML2VC1_VM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x3a5b
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#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x3a5c
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#define mmVML2VC1_VM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x3a5d
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#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x3a5e
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#define mmVML2VC1_VM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x3a5f
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#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x3a60
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#define mmVML2VC1_VM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x3a61
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#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x3a62
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#define mmVML2VC1_VM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x3a63
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#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x3a64
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#define mmVML2VC1_VM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x3a65
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#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x3a66
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#define mmVML2VC1_VM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x3a67
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#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x3a68
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#define mmVML2VC1_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x3a69
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#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x3a6a
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#define mmVML2VC1_VM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x3a6b
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#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x3a6c
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#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x3a6d
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#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x3a6e
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#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x3a6f
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#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x3a70
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#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x3a71
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#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x3a72
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#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x3a73
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#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x3a74
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#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x3a75
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#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x3a76
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#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x3a77
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#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x3a78
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#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x3a79
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#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x3a7a
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#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x3a7b
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#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x3a7c
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#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x3a7d
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#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x3a7e
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#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x3a7f
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#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x3a80
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#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x3a81
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#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x3a82
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#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x3a83
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#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x3a84
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#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x3a85
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#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x3a86
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#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x3a87
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#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x3a88
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#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x3a89
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#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x3a8a
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#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x3a8b
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#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x3a8c
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#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x3a8d
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#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x3a8e
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#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x3a8f
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#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x3a90
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#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x3a91
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#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x3a92
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#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x3a93
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#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x3a94
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#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x3a95
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#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x3a96
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#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x3a97
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#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x3a98
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#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x3a99
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#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x3a9a
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#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x3a9b
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#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x3a9c
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#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x3a9d
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#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x3a9e
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#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x3a9f
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#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x3aa0
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#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x3aa1
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#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x3aa2
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#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x3aa3
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#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x3aa4
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#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x3aa5
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#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x3aa6
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#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x3aa7
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#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x3aa8
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#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x3aa9
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#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x3aaa
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#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x3aab
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#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x3aac
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#define mmVML2VC1_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x3aad
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#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x3aae
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#define mmVML2VC1_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x3aaf
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#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x3ab0
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#define mmVML2VC1_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x3ab1
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#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x3ab2
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#define mmVML2VC1_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x3ab3
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#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x3ab4
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#define mmVML2VC1_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x3ab5
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#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x3ab6
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#define mmVML2VC1_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x3ab7
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#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x3ab8
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#define mmVML2VC1_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x3ab9
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#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x3aba
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#define mmVML2VC1_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x3abb
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#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x3abc
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#define mmVML2VC1_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x3abd
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#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x3abe
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#define mmVML2VC1_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x3abf
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#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x3ac0
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#define mmVML2VC1_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x3ac1
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#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x3ac2
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#define mmVML2VC1_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x3ac3
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#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x3ac4
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#define mmVML2VC1_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x3ac5
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#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x3ac6
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#define mmVML2VC1_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x3ac7
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#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x3ac8
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#define mmVML2VC1_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x3ac9
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#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1
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#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x3aca
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#define mmVML2VC1_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vmsharedpfdec:1
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// base address: 0x76b90
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#define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE 0x3ae4
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#define mmVMSHAREDPF1_MC_VM_NB_MMIOBASE_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT 0x3ae5
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#define mmVMSHAREDPF1_MC_VM_NB_MMIOLIMIT_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL 0x3ae6
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#define mmVMSHAREDPF1_MC_VM_NB_PCI_CTRL_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB 0x3ae7
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#define mmVMSHAREDPF1_MC_VM_NB_PCI_ARB_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1 0x3ae8
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#define mmVMSHAREDPF1_MC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2 0x3ae9
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#define mmVMSHAREDPF1_MC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2 0x3aea
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#define mmVMSHAREDPF1_MC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_FB_OFFSET 0x3aeb
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#define mmVMSHAREDPF1_MC_VM_FB_OFFSET_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x3aec
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#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x3aed
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#define mmVMSHAREDPF1_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_STEERING 0x3aee
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#define mmVMSHAREDPF1_MC_VM_STEERING_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ 0x3aef
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#define mmVMSHAREDPF1_MC_SHARED_VIRT_RESET_REQ_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_MEM_POWER_LS 0x3af0
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#define mmVMSHAREDPF1_MC_MEM_POWER_LS_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START 0x3af1
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#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END 0x3af2
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#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_APT_CNTL 0x3af3
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#define mmVMSHAREDPF1_MC_VM_APT_CNTL_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START 0x3af4
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#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END 0x3af5
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#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x3af6
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#define mmVMSHAREDPF1_MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL 0x3af7
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#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_CNTL_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE 0x3af8
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#define mmVMSHAREDPF1_MC_VM_XGMI_LFB_SIZE_BASE_IDX 1
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#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL 0x3af9
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#define mmVMSHAREDPF1_MC_VM_CACHEABLE_DRAM_CNTL_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vmsharedvcdec:1
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// base address: 0x76c00
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#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE 0x3b00
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#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_BASE_BASE_IDX 1
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#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP 0x3b01
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#define mmVMSHAREDVC1_MC_VM_FB_LOCATION_TOP_BASE_IDX 1
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#define mmVMSHAREDVC1_MC_VM_AGP_TOP 0x3b02
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#define mmVMSHAREDVC1_MC_VM_AGP_TOP_BASE_IDX 1
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#define mmVMSHAREDVC1_MC_VM_AGP_BOT 0x3b03
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#define mmVMSHAREDVC1_MC_VM_AGP_BOT_BASE_IDX 1
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#define mmVMSHAREDVC1_MC_VM_AGP_BASE 0x3b04
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#define mmVMSHAREDVC1_MC_VM_AGP_BASE_BASE_IDX 1
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#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x3b05
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#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1
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#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x3b06
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#define mmVMSHAREDVC1_MC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1
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#define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL 0x3b07
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#define mmVMSHAREDVC1_MC_VM_MX_L1_TLB_CNTL_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vmsharedhvdec:1
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// base address: 0x76c80
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0 0x3b20
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF0_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1 0x3b21
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF1_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2 0x3b22
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF2_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3 0x3b23
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF3_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4 0x3b24
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF4_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5 0x3b25
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF5_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6 0x3b26
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF6_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7 0x3b27
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF7_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8 0x3b28
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF8_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9 0x3b29
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF9_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10 0x3b2a
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF10_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11 0x3b2b
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF11_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12 0x3b2c
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF12_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13 0x3b2d
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF13_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14 0x3b2e
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF14_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15 0x3b2f
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#define mmVMSHAREDHV1_MC_VM_FB_SIZE_OFFSET_VF15_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1 0x3b30
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#define mmVMSHAREDHV1_VM_IOMMU_MMIO_CNTRL_1_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0 0x3b31
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_0_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1 0x3b32
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_1_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2 0x3b33
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_2_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3 0x3b34
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_LO_3_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0 0x3b35
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_0_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1 0x3b36
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_1_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2 0x3b37
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_2_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3 0x3b38
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#define mmVMSHAREDHV1_MC_VM_MARC_BASE_HI_3_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0 0x3b39
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_0_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1 0x3b3a
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_1_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2 0x3b3b
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_2_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3 0x3b3c
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_LO_3_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0 0x3b3d
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_0_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1 0x3b3e
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_1_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2 0x3b3f
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_2_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3 0x3b40
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#define mmVMSHAREDHV1_MC_VM_MARC_RELOC_HI_3_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0 0x3b41
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_0_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1 0x3b42
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_1_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2 0x3b43
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_2_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3 0x3b44
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_LO_3_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0 0x3b45
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_0_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1 0x3b46
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_1_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2 0x3b47
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_2_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3 0x3b48
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#define mmVMSHAREDHV1_MC_VM_MARC_LEN_HI_3_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER 0x3b49
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#define mmVMSHAREDHV1_VM_IOMMU_CONTROL_REGISTER_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x3b4a
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#define mmVMSHAREDHV1_VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL 0x3b4b
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0 0x3b4c
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_0_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1 0x3b4d
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_1_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2 0x3b4e
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_2_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3 0x3b4f
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_3_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4 0x3b50
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_4_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5 0x3b51
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_5_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6 0x3b52
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_6_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7 0x3b53
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_7_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8 0x3b54
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_8_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9 0x3b55
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_9_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10 0x3b56
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_10_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11 0x3b57
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_11_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12 0x3b58
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_12_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13 0x3b59
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_13_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14 0x3b5a
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_14_BASE_IDX 1
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15 0x3b5b
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#define mmVMSHAREDHV1_VM_PCIE_ATS_CNTL_VF_15_BASE_IDX 1
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#define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL 0x3b5c
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#define mmVMSHAREDHV1_UTCL2_CGTT_CLK_CTRL_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID 0x3b5d
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#define mmVMSHAREDHV1_MC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1
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#define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE 0x3b5e
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#define mmVMSHAREDHV1_MC_VM_XGMI_GPUIOV_ENABLE_BASE_IDX 1
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// addressBlock: mmhub_utcl2_atcl2pfcntrdec:1
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// base address: 0x76dc0
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#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO 0x3b70
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#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1
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#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI 0x3b71
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#define mmATCL2PFCNTR1_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1
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// addressBlock: mmhub_utcl2_atcl2pfcntldec:1
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// base address: 0x76dd0
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#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG 0x3b74
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#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG 0x3b75
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#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x3b76
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#define mmATCL2PFCNTL1_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vml2pldec:1
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// base address: 0x76e00
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG 0x3b80
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG 0x3b81
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG 0x3b82
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG 0x3b83
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG 0x3b84
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG 0x3b85
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG 0x3b86
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG 0x3b87
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x3b88
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#define mmVML2PL1_MC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1
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// addressBlock: mmhub_utcl2_vml2prdec:1
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// base address: 0x76e40
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#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO 0x3b90
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#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1
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#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI 0x3b91
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#define mmVML2PR1_MC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1
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#endif
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