/*
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* Copyright (C) 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _df_3_6_SH_MASK_HEADER
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#define _df_3_6_SH_MASK_HEADER
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/* FabricConfigAccessControl */
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#define FabricConfigAccessControl__CfgRegInstAccEn__SHIFT 0x0
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#define FabricConfigAccessControl__CfgRegInstAccRegLock__SHIFT 0x1
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#define FabricConfigAccessControl__CfgRegInstID__SHIFT 0x10
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#define FabricConfigAccessControl__CfgRegInstAccEn_MASK 0x00000001L
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#define FabricConfigAccessControl__CfgRegInstAccRegLock_MASK 0x00000002L
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#define FabricConfigAccessControl__CfgRegInstID_MASK 0x00FF0000L
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/* DF_PIE_AON0_DfGlobalClkGater */
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#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode__SHIFT 0x0
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#define DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK 0x0000000FL
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/* DF_CS_UMC_AON0_DfGlobalCtrl */
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#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl64K__SHIFT 0x14
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#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl2M__SHIFT 0x15
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#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl1G__SHIFT 0x16
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#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl64K_MASK 0x00100000L
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#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl2M_MASK 0x00200000L
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#define DF_CS_UMC_AON0_DfGlobalCtrl__GlbHashIntlvCtl1G_MASK 0x00400000L
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/* DF_CS_AON0_DramBaseAddress0 */
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#define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal__SHIFT 0x0
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#define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn__SHIFT 0x1
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#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT 0x2
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#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel__SHIFT 0x9
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#define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr__SHIFT 0xc
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#define DF_CS_UMC_AON0_DramBaseAddress0__AddrRngVal_MASK 0x00000001L
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#define DF_CS_UMC_AON0_DramBaseAddress0__LgcyMmioHoleEn_MASK 0x00000002L
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#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK 0x0000003CL
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#define DF_CS_UMC_AON0_DramBaseAddress0__IntLvAddrSel_MASK 0x00000E00L
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#define DF_CS_UMC_AON0_DramBaseAddress0__DramBaseAddr_MASK 0xFFFFF000L
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//DF_CS_UMC_AON0_DramLimitAddress0
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#define DF_CS_UMC_AON0_DramLimitAddress0__DstFabricID__SHIFT 0x0
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#define DF_CS_UMC_AON0_DramLimitAddress0__AllowReqIO__SHIFT 0xa
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#define DF_CS_UMC_AON0_DramLimitAddress0__DramLimitAddr__SHIFT 0xc
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#define DF_CS_UMC_AON0_DramLimitAddress0__DstFabricID_MASK 0x000003FFL
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#define DF_CS_UMC_AON0_DramLimitAddress0__AllowReqIO_MASK 0x00000400L
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#define DF_CS_UMC_AON0_DramLimitAddress0__DramLimitAddr_MASK 0xFFFFF000L
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#endif
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