#ifndef _dcn_3_0_0_OFFSET_HEADER
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#define _dcn_3_0_0_OFFSET_HEADER
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// addressBlock: dce_dc_mmhubbub_vga_dispdec
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// base address: 0x0
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#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
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#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
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#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
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#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
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#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
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#define mmVGA_RENDER_CONTROL 0x0000
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#define mmVGA_RENDER_CONTROL_BASE_IDX 1
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#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
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#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
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#define mmVGA_MODE_CONTROL 0x0002
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#define mmVGA_MODE_CONTROL_BASE_IDX 1
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#define mmVGA_SURFACE_PITCH_SELECT 0x0003
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#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
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#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
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#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
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#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
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#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
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#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
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#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
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#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
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#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
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#define mmVGA_HDP_CONTROL 0x000a
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#define mmVGA_HDP_CONTROL_BASE_IDX 1
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#define mmVGA_CACHE_CONTROL 0x000b
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#define mmVGA_CACHE_CONTROL_BASE_IDX 1
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#define mmD1VGA_CONTROL 0x000c
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#define mmD1VGA_CONTROL_BASE_IDX 1
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#define mmD2VGA_CONTROL 0x000e
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#define mmD2VGA_CONTROL_BASE_IDX 1
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#define mmVGA_STATUS 0x0010
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#define mmVGA_STATUS_BASE_IDX 1
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#define mmVGA_INTERRUPT_CONTROL 0x0011
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#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
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#define mmVGA_STATUS_CLEAR 0x0012
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#define mmVGA_STATUS_CLEAR_BASE_IDX 1
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#define mmVGA_INTERRUPT_STATUS 0x0013
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#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
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#define mmVGA_MAIN_CONTROL 0x0014
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#define mmVGA_MAIN_CONTROL_BASE_IDX 1
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#define mmVGA_TEST_CONTROL 0x0015
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#define mmVGA_TEST_CONTROL_BASE_IDX 1
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#define mmVGA_QOS_CTRL 0x0018
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#define mmVGA_QOS_CTRL_BASE_IDX 1
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#define mmCRTC8_IDX 0x002d
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#define mmCRTC8_IDX_BASE_IDX 1
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#define mmCRTC8_DATA 0x002d
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#define mmCRTC8_DATA_BASE_IDX 1
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#define mmGENFC_WT 0x002e
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#define mmGENFC_WT_BASE_IDX 1
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#define mmGENS1 0x002e
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#define mmGENS1_BASE_IDX 1
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#define mmATTRDW 0x0030
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#define mmATTRDW_BASE_IDX 1
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#define mmATTRX 0x0030
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#define mmATTRX_BASE_IDX 1
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#define mmATTRDR 0x0030
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#define mmATTRDR_BASE_IDX 1
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#define mmGENMO_WT 0x0030
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#define mmGENMO_WT_BASE_IDX 1
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#define mmGENS0 0x0030
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#define mmGENS0_BASE_IDX 1
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#define mmGENENB 0x0030
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#define mmGENENB_BASE_IDX 1
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#define mmSEQ8_IDX 0x0031
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#define mmSEQ8_IDX_BASE_IDX 1
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#define mmSEQ8_DATA 0x0031
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#define mmSEQ8_DATA_BASE_IDX 1
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#define mmDAC_MASK 0x0031
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#define mmDAC_MASK_BASE_IDX 1
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#define mmDAC_R_INDEX 0x0031
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#define mmDAC_R_INDEX_BASE_IDX 1
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#define mmDAC_W_INDEX 0x0032
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#define mmDAC_W_INDEX_BASE_IDX 1
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#define mmDAC_DATA 0x0032
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#define mmDAC_DATA_BASE_IDX 1
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#define mmGENFC_RD 0x0032
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#define mmGENFC_RD_BASE_IDX 1
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#define mmGENMO_RD 0x0033
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#define mmGENMO_RD_BASE_IDX 1
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#define mmGRPH8_IDX 0x0033
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#define mmGRPH8_IDX_BASE_IDX 1
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#define mmGRPH8_DATA 0x0033
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#define mmGRPH8_DATA_BASE_IDX 1
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#define mmCRTC8_IDX_1 0x0035
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#define mmCRTC8_IDX_1_BASE_IDX 1
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#define mmCRTC8_DATA_1 0x0035
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#define mmCRTC8_DATA_1_BASE_IDX 1
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#define mmGENFC_WT_1 0x0036
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#define mmGENFC_WT_1_BASE_IDX 1
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#define mmGENS1_1 0x0036
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#define mmGENS1_1_BASE_IDX 1
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#define mmD3VGA_CONTROL 0x0038
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#define mmD3VGA_CONTROL_BASE_IDX 1
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#define mmD4VGA_CONTROL 0x0039
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#define mmD4VGA_CONTROL_BASE_IDX 1
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#define mmD5VGA_CONTROL 0x003a
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#define mmD5VGA_CONTROL_BASE_IDX 1
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#define mmD6VGA_CONTROL 0x003b
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#define mmD6VGA_CONTROL_BASE_IDX 1
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#define mmVGA_SOURCE_SELECT 0x003c
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#define mmVGA_SOURCE_SELECT_BASE_IDX 1
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// addressBlock: dce_dc_dccg_dccg_dispdec
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// base address: 0x0
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#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
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#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
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#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
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#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
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#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmDP_DTO_DBUF_EN 0x0044
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#define mmDP_DTO_DBUF_EN_BASE_IDX 1
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#define mmDSCCLK3_DTO_PARAM 0x0045
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#define mmDSCCLK3_DTO_PARAM_BASE_IDX 1
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#define mmDSCCLK4_DTO_PARAM 0x0046
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#define mmDSCCLK4_DTO_PARAM_BASE_IDX 1
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#define mmDSCCLK5_DTO_PARAM 0x0047
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#define mmDSCCLK5_DTO_PARAM_BASE_IDX 1
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#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
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#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
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#define mmREFCLK_CNTL 0x0049
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#define mmREFCLK_CNTL_BASE_IDX 1
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#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
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#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
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#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
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#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmDCCG_PERFMON_CNTL2 0x004e
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#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
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#define mmDCCG_DS_DTO_INCR 0x0053
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#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
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#define mmDCCG_DS_DTO_MODULO 0x0054
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#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
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#define mmDCCG_DS_CNTL 0x0055
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#define mmDCCG_DS_CNTL_BASE_IDX 1
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#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
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#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
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#define mmDPREFCLK_CNTL 0x0058
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#define mmDPREFCLK_CNTL_BASE_IDX 1
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#define mmDCE_VERSION 0x005e
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#define mmDCE_VERSION_BASE_IDX 1
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#define mmDCCG_GTC_CNTL 0x0060
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#define mmDCCG_GTC_CNTL_BASE_IDX 1
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#define mmDCCG_GTC_DTO_INCR 0x0061
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#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
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#define mmDCCG_GTC_DTO_MODULO 0x0062
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#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
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#define mmDCCG_GTC_CURRENT 0x0063
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#define mmDCCG_GTC_CURRENT_BASE_IDX 1
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#define mmDSCCLK0_DTO_PARAM 0x006c
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#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1
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#define mmDSCCLK1_DTO_PARAM 0x006d
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#define mmDSCCLK1_DTO_PARAM_BASE_IDX 1
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#define mmDSCCLK2_DTO_PARAM 0x006e
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#define mmDSCCLK2_DTO_PARAM_BASE_IDX 1
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#define mmMILLISECOND_TIME_BASE_DIV 0x0070
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#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
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#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
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#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
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#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
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#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
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#define mmDCCG_PERFMON_CNTL 0x0073
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#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
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#define mmDCCG_GATE_DISABLE_CNTL 0x0074
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#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
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#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
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#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
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#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076
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#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
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#define mmDCCG_CAC_STATUS 0x0077
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#define mmDCCG_CAC_STATUS_BASE_IDX 1
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#define mmMICROSECOND_TIME_BASE_DIV 0x007b
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#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
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#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
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#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
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#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
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#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
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#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
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#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
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#define mmDCCG_DISP_CNTL_REG 0x007f
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#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
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#define mmOTG0_PIXEL_RATE_CNTL 0x0080
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#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmDP_DTO0_PHASE 0x0081
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#define mmDP_DTO0_PHASE_BASE_IDX 1
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#define mmDP_DTO0_MODULO 0x0082
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#define mmDP_DTO0_MODULO_BASE_IDX 1
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#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083
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#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmOTG1_PIXEL_RATE_CNTL 0x0084
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#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmDP_DTO1_PHASE 0x0085
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#define mmDP_DTO1_PHASE_BASE_IDX 1
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#define mmDP_DTO1_MODULO 0x0086
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#define mmDP_DTO1_MODULO_BASE_IDX 1
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#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087
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#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmOTG2_PIXEL_RATE_CNTL 0x0088
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#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmDP_DTO2_PHASE 0x0089
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#define mmDP_DTO2_PHASE_BASE_IDX 1
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#define mmDP_DTO2_MODULO 0x008a
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#define mmDP_DTO2_MODULO_BASE_IDX 1
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#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b
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#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmOTG3_PIXEL_RATE_CNTL 0x008c
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#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmDP_DTO3_PHASE 0x008d
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#define mmDP_DTO3_PHASE_BASE_IDX 1
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#define mmDP_DTO3_MODULO 0x008e
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#define mmDP_DTO3_MODULO_BASE_IDX 1
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#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f
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#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmOTG4_PIXEL_RATE_CNTL 0x0090
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#define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmDP_DTO4_PHASE 0x0091
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#define mmDP_DTO4_PHASE_BASE_IDX 1
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#define mmDP_DTO4_MODULO 0x0092
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#define mmDP_DTO4_MODULO_BASE_IDX 1
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#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093
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#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmOTG5_PIXEL_RATE_CNTL 0x0094
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#define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmDP_DTO5_PHASE 0x0095
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#define mmDP_DTO5_PHASE_BASE_IDX 1
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#define mmDP_DTO5_MODULO 0x0096
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#define mmDP_DTO5_MODULO_BASE_IDX 1
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#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097
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#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
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#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098
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#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
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#define mmDPPCLK0_DTO_PARAM 0x0099
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#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1
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#define mmDPPCLK1_DTO_PARAM 0x009a
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#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1
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#define mmDPPCLK2_DTO_PARAM 0x009b
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#define mmDPPCLK2_DTO_PARAM_BASE_IDX 1
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#define mmDPPCLK3_DTO_PARAM 0x009c
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#define mmDPPCLK3_DTO_PARAM_BASE_IDX 1
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#define mmDPPCLK4_DTO_PARAM 0x009d
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#define mmDPPCLK4_DTO_PARAM_BASE_IDX 1
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#define mmDPPCLK5_DTO_PARAM 0x009e
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#define mmDPPCLK5_DTO_PARAM_BASE_IDX 1
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#define mmDCCG_CAC_STATUS2 0x009f
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#define mmDCCG_CAC_STATUS2_BASE_IDX 1
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#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
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#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
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#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
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#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
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#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
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#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
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#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
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#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
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#define mmSYMCLKE_CLOCK_ENABLE 0x00a4
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#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
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#define mmSYMCLKF_CLOCK_ENABLE 0x00a5
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#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
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#define mmDCCG_SOFT_RESET 0x00a6
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#define mmDCCG_SOFT_RESET_BASE_IDX 1
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#define mmDSCCLK_DTO_CTRL 0x00a7
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#define mmDSCCLK_DTO_CTRL_BASE_IDX 1
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#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
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#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
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#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
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#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
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#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
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#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
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#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
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#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
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#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
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#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
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#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0
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#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1
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#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1
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#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1
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#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2
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#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1
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#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3
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#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1
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#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4
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#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1
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#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5
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#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1
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#define mmDPPCLK_DTO_CTRL 0x00b6
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#define mmDPPCLK_DTO_CTRL_BASE_IDX 1
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#define mmDCCG_VSYNC_CNT_CTRL 0x00b8
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#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1
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#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9
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#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1
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#define mmFORCE_SYMCLK_DISABLE 0x00ba
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#define mmFORCE_SYMCLK_DISABLE_BASE_IDX 1
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#define mmPHYASYMCLK_CLOCK_CNTL 0x0052
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#define mmPHYASYMCLK_CLOCK_CNTL_BASE_IDX 2
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#define mmPHYBSYMCLK_CLOCK_CNTL 0x0053
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#define mmPHYBSYMCLK_CLOCK_CNTL_BASE_IDX 2
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#define mmPHYCSYMCLK_CLOCK_CNTL 0x0054
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#define mmPHYCSYMCLK_CLOCK_CNTL_BASE_IDX 2
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#define mmPHYDSYMCLK_CLOCK_CNTL 0x0055
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#define mmPHYDSYMCLK_CLOCK_CNTL_BASE_IDX 2
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#define mmPHYESYMCLK_CLOCK_CNTL 0x0056
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#define mmPHYESYMCLK_CLOCK_CNTL_BASE_IDX 2
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#define mmPHYFSYMCLK_CLOCK_CNTL 0x0057
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#define mmPHYFSYMCLK_CLOCK_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
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// base address: 0x0
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#define mmDENTIST_DISPCLK_CNTL 0x0064
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#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
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// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
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// base address: 0x0
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#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000
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#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001
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#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002
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#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON0_PERFMON_CNTL 0x0003
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#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004
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#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005
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#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006
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#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON0_PERFMON_HI 0x0007
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#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON0_PERFMON_LOW 0x0008
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#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
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// base address: 0x30
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#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c
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#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d
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#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e
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#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON1_PERFMON_CNTL 0x000f
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#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010
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#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011
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#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012
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#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON1_PERFMON_HI 0x0013
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#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON1_PERFMON_LOW 0x0014
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#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dmu_dc_pg_dispdec
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// base address: 0x0
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#define mmDOMAIN0_PG_CONFIG 0x0080
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#define mmDOMAIN0_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN0_PG_STATUS 0x0081
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#define mmDOMAIN0_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN1_PG_CONFIG 0x0082
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#define mmDOMAIN1_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN1_PG_STATUS 0x0083
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#define mmDOMAIN1_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN2_PG_CONFIG 0x0084
|
#define mmDOMAIN2_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN2_PG_STATUS 0x0085
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#define mmDOMAIN2_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN3_PG_CONFIG 0x0086
|
#define mmDOMAIN3_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN3_PG_STATUS 0x0087
|
#define mmDOMAIN3_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN4_PG_CONFIG 0x0088
|
#define mmDOMAIN4_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN4_PG_STATUS 0x0089
|
#define mmDOMAIN4_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN5_PG_CONFIG 0x008a
|
#define mmDOMAIN5_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN5_PG_STATUS 0x008b
|
#define mmDOMAIN5_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN6_PG_CONFIG 0x008c
|
#define mmDOMAIN6_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN6_PG_STATUS 0x008d
|
#define mmDOMAIN6_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN7_PG_CONFIG 0x008e
|
#define mmDOMAIN7_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN7_PG_STATUS 0x008f
|
#define mmDOMAIN7_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN8_PG_CONFIG 0x0090
|
#define mmDOMAIN8_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN8_PG_STATUS 0x0091
|
#define mmDOMAIN8_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN9_PG_CONFIG 0x0092
|
#define mmDOMAIN9_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN9_PG_STATUS 0x0093
|
#define mmDOMAIN9_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN10_PG_CONFIG 0x0094
|
#define mmDOMAIN10_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN10_PG_STATUS 0x0095
|
#define mmDOMAIN10_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN11_PG_CONFIG 0x0096
|
#define mmDOMAIN11_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN11_PG_STATUS 0x0097
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#define mmDOMAIN11_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN16_PG_CONFIG 0x00a1
|
#define mmDOMAIN16_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN16_PG_STATUS 0x00a2
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#define mmDOMAIN16_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN17_PG_CONFIG 0x00a3
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#define mmDOMAIN17_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN17_PG_STATUS 0x00a4
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#define mmDOMAIN17_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN18_PG_CONFIG 0x00a5
|
#define mmDOMAIN18_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN18_PG_STATUS 0x00a6
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#define mmDOMAIN18_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN19_PG_CONFIG 0x00a7
|
#define mmDOMAIN19_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN19_PG_STATUS 0x00a8
|
#define mmDOMAIN19_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN20_PG_CONFIG 0x00a9
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#define mmDOMAIN20_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN20_PG_STATUS 0x00aa
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#define mmDOMAIN20_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN21_PG_CONFIG 0x00ab
|
#define mmDOMAIN21_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN21_PG_STATUS 0x00ac
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#define mmDOMAIN21_PG_STATUS_BASE_IDX 2
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#define mmDCPG_INTERRUPT_STATUS 0x00ad
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#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDCPG_INTERRUPT_STATUS_2 0x00ae
|
#define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX 2
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#define mmDCPG_INTERRUPT_CONTROL_1 0x00af
|
#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2
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#define mmDCPG_INTERRUPT_CONTROL_2 0x00b0
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#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2
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#define mmDCPG_INTERRUPT_CONTROL_3 0x00b1
|
#define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2
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#define mmDC_IP_REQUEST_CNTL 0x00b2
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#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
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|
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// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x2f8
|
#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be
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#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf
|
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0
|
#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_CNTL 0x00c1
|
#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2
|
#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3
|
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4
|
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_HI 0x00c5
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#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_LOW 0x00c6
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#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
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|
|
// addressBlock: dce_dc_dmu_dmu_misc_dispdec
|
// base address: 0x0
|
#define mmCC_DC_PIPE_DIS 0x00ca
|
#define mmCC_DC_PIPE_DIS_BASE_IDX 2
|
#define mmDMU_CLK_CNTL 0x00cb
|
#define mmDMU_CLK_CNTL_BASE_IDX 2
|
#define mmDMU_MEM_PWR_CNTL 0x00cc
|
#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2
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#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd
|
#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmSMU_INTERRUPT_CONTROL 0x00ce
|
#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDMU_MISC_ALLOW_DS_FORCE 0x00d6
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#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dmu_dmcu_dispdec
|
// base address: 0x0
|
#define mmDMCU_CTRL 0x00da
|
#define mmDMCU_CTRL_BASE_IDX 2
|
#define mmDMCU_STATUS 0x00db
|
#define mmDMCU_STATUS_BASE_IDX 2
|
#define mmDMCU_PC_START_ADDR 0x00dc
|
#define mmDMCU_PC_START_ADDR_BASE_IDX 2
|
#define mmDMCU_FW_START_ADDR 0x00dd
|
#define mmDMCU_FW_START_ADDR_BASE_IDX 2
|
#define mmDMCU_FW_END_ADDR 0x00de
|
#define mmDMCU_FW_END_ADDR_BASE_IDX 2
|
#define mmDMCU_FW_ISR_START_ADDR 0x00df
|
#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
|
#define mmDMCU_FW_CS_HI 0x00e0
|
#define mmDMCU_FW_CS_HI_BASE_IDX 2
|
#define mmDMCU_FW_CS_LO 0x00e1
|
#define mmDMCU_FW_CS_LO_BASE_IDX 2
|
#define mmDMCU_RAM_ACCESS_CTRL 0x00e2
|
#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
|
#define mmDMCU_ERAM_WR_CTRL 0x00e3
|
#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
|
#define mmDMCU_ERAM_WR_DATA 0x00e4
|
#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
|
#define mmDMCU_ERAM_RD_CTRL 0x00e5
|
#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
|
#define mmDMCU_ERAM_RD_DATA 0x00e6
|
#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
|
#define mmDMCU_IRAM_WR_CTRL 0x00e7
|
#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
|
#define mmDMCU_IRAM_WR_DATA 0x00e8
|
#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
|
#define mmDMCU_IRAM_RD_CTRL 0x00e9
|
#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
|
#define mmDMCU_IRAM_RD_DATA 0x00ea
|
#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
|
#define mmDMCU_EVENT_TRIGGER 0x00eb
|
#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
|
#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec
|
#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
|
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed
|
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_STATUS 0x00ee
|
#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_STATUS_1 0x00ef
|
#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0
|
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
|
#define mmDC_DMCU_SCRATCH 0x00f5
|
#define mmDC_DMCU_SCRATCH_BASE_IDX 2
|
#define mmDMCU_INT_CNT 0x00f6
|
#define mmDMCU_INT_CNT_BASE_IDX 2
|
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7
|
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
|
#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8
|
#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
|
#define mmMASTER_COMM_DATA_REG1 0x00f9
|
#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
|
#define mmMASTER_COMM_DATA_REG2 0x00fa
|
#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
|
#define mmMASTER_COMM_DATA_REG3 0x00fb
|
#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
|
#define mmMASTER_COMM_CMD_REG 0x00fc
|
#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
|
#define mmMASTER_COMM_CNTL_REG 0x00fd
|
#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
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#define mmSLAVE_COMM_DATA_REG1 0x00fe
|
#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
|
#define mmSLAVE_COMM_DATA_REG2 0x00ff
|
#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
|
#define mmSLAVE_COMM_DATA_REG3 0x0100
|
#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
|
#define mmSLAVE_COMM_CMD_REG 0x0101
|
#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
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#define mmSLAVE_COMM_CNTL_REG 0x0102
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#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
|
#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114
|
#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
|
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115
|
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
|
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116
|
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119
|
#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2
|
#define mmDMCU_INT_CNT_CONTINUE 0x011c
|
#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_STATUS_2 0x011e
|
#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2
|
#define mmDMCU_INT_CNT_CONT2 0x0120
|
#define mmDMCU_INT_CNT_CONT2_BASE_IDX 2
|
#define mmDMCU_INT_CNT_CONT3 0x0121
|
#define mmDMCU_INT_CNT_CONT3_BASE_IDX 2
|
#define mmDMCU_INT_CNT_CONT4 0x0122
|
#define mmDMCU_INT_CNT_CONT4_BASE_IDX 2
|
#define mmDMCU_INT_CNT_CONT5 0x0123
|
#define mmDMCU_INT_CNT_CONT5_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dmu_ihc_dispdec
|
// base address: 0x0
|
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126
|
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127
|
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2
|
#define mmDC_GPU_TIMER_READ 0x0128
|
#define mmDC_GPU_TIMER_READ_BASE_IDX 2
|
#define mmDC_GPU_TIMER_READ_CNTL 0x0129
|
#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS 0x012a
|
#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141
|
#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142
|
#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143
|
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144
|
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE23 0x0145
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE24 0x0146
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE25 0x0147
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE25_BASE_IDX 2
|
#define mmDCCG_INTERRUPT_DEST 0x0148
|
#define mmDCCG_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDMU_INTERRUPT_DEST 0x0149
|
#define mmDMU_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDMU_INTERRUPT_DEST2 0x014a
|
#define mmDMU_INTERRUPT_DEST2_BASE_IDX 2
|
#define mmDCPG_INTERRUPT_DEST 0x014b
|
#define mmDCPG_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDCPG_INTERRUPT_DEST2 0x014c
|
#define mmDCPG_INTERRUPT_DEST2_BASE_IDX 2
|
#define mmMMHUBBUB_INTERRUPT_DEST 0x014d
|
#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2
|
#define mmWB_INTERRUPT_DEST 0x014e
|
#define mmWB_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDCHUB_INTERRUPT_DEST 0x014f
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#define mmDCHUB_INTERRUPT_DEST_BASE_IDX 2
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#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x0150
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#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
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#define mmDCHUB_INTERRUPT_DEST2 0x0151
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#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX 2
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#define mmDPP_PERFCOUNTER_INTERRUPT_DEST 0x0152
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#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
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#define mmMPC_INTERRUPT_DEST 0x0153
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#define mmMPC_INTERRUPT_DEST_BASE_IDX 2
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#define mmOPP_INTERRUPT_DEST 0x0154
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#define mmOPP_INTERRUPT_DEST_BASE_IDX 2
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#define mmOPTC_INTERRUPT_DEST 0x0155
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#define mmOPTC_INTERRUPT_DEST_BASE_IDX 2
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#define mmOTG0_INTERRUPT_DEST 0x0156
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#define mmOTG0_INTERRUPT_DEST_BASE_IDX 2
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#define mmOTG1_INTERRUPT_DEST 0x0157
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#define mmOTG1_INTERRUPT_DEST_BASE_IDX 2
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#define mmOTG2_INTERRUPT_DEST 0x0158
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#define mmOTG2_INTERRUPT_DEST_BASE_IDX 2
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#define mmOTG3_INTERRUPT_DEST 0x0159
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#define mmOTG3_INTERRUPT_DEST_BASE_IDX 2
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#define mmOTG4_INTERRUPT_DEST 0x015a
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#define mmOTG4_INTERRUPT_DEST_BASE_IDX 2
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#define mmOTG5_INTERRUPT_DEST 0x015b
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#define mmOTG5_INTERRUPT_DEST_BASE_IDX 2
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#define mmDIG_INTERRUPT_DEST 0x015c
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#define mmDIG_INTERRUPT_DEST_BASE_IDX 2
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#define mmI2C_DDC_HPD_INTERRUPT_DEST 0x015d
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#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2
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#define mmDIO_INTERRUPT_DEST 0x015f
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#define mmDIO_INTERRUPT_DEST_BASE_IDX 2
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#define mmDCIO_INTERRUPT_DEST 0x0160
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#define mmDCIO_INTERRUPT_DEST_BASE_IDX 2
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#define mmHPD_INTERRUPT_DEST 0x0161
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#define mmHPD_INTERRUPT_DEST_BASE_IDX 2
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#define mmAZ_INTERRUPT_DEST 0x0162
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#define mmAZ_INTERRUPT_DEST_BASE_IDX 2
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#define mmAUX_INTERRUPT_DEST 0x0163
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#define mmAUX_INTERRUPT_DEST_BASE_IDX 2
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#define mmDSC_INTERRUPT_DEST 0x0164
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#define mmDSC_INTERRUPT_DEST_BASE_IDX 2
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// addressBlock: dce_dc_dmu_fgsec_dispdec
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// base address: 0x0
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#define mmDMCUB_RBBMIF_SEC_CNTL 0x017a
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#define mmDMCUB_RBBMIF_SEC_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dmu_rbbmif_dispdec
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// base address: 0x0
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#define mmRBBMIF_TIMEOUT 0x017f
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#define mmRBBMIF_TIMEOUT_BASE_IDX 2
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#define mmRBBMIF_STATUS 0x0180
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#define mmRBBMIF_STATUS_BASE_IDX 2
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#define mmRBBMIF_STATUS_2 0x0181
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#define mmRBBMIF_STATUS_2_BASE_IDX 2
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#define mmRBBMIF_INT_STATUS 0x0182
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#define mmRBBMIF_INT_STATUS_BASE_IDX 2
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#define mmRBBMIF_TIMEOUT_DIS 0x0183
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#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
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#define mmRBBMIF_TIMEOUT_DIS_2 0x0184
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#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2
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#define mmRBBMIF_STATUS_FLAG 0x0185
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#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
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// addressBlock: dce_dc_dmu_dmcub_dispdec
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// base address: 0x0
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#define mmDMCUB_REGION0_OFFSET 0x018e
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#define mmDMCUB_REGION0_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION0_OFFSET_HIGH 0x018f
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#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION1_OFFSET 0x0190
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#define mmDMCUB_REGION1_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION1_OFFSET_HIGH 0x0191
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#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION2_OFFSET 0x0192
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#define mmDMCUB_REGION2_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION2_OFFSET_HIGH 0x0193
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#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION4_OFFSET 0x0196
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#define mmDMCUB_REGION4_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION4_OFFSET_HIGH 0x0197
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#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION5_OFFSET 0x0198
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#define mmDMCUB_REGION5_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION5_OFFSET_HIGH 0x0199
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#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION6_OFFSET 0x019a
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#define mmDMCUB_REGION6_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION6_OFFSET_HIGH 0x019b
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#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION7_OFFSET 0x019c
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#define mmDMCUB_REGION7_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION7_OFFSET_HIGH 0x019d
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#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION0_TOP_ADDRESS 0x019e
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#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION1_TOP_ADDRESS 0x019f
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#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION2_TOP_ADDRESS 0x01a0
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#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION4_TOP_ADDRESS 0x01a1
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#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION5_TOP_ADDRESS 0x01a2
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#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION6_TOP_ADDRESS 0x01a3
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#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION7_TOP_ADDRESS 0x01a4
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#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW0_BASE_ADDRESS 0x01a5
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#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW1_BASE_ADDRESS 0x01a6
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#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW2_BASE_ADDRESS 0x01a7
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#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW3_BASE_ADDRESS 0x01a8
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#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW4_BASE_ADDRESS 0x01a9
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#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW5_BASE_ADDRESS 0x01aa
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#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW6_BASE_ADDRESS 0x01ab
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#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW7_BASE_ADDRESS 0x01ac
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#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW0_TOP_ADDRESS 0x01ad
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#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW1_TOP_ADDRESS 0x01ae
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#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW2_TOP_ADDRESS 0x01af
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#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW3_TOP_ADDRESS 0x01b0
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#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW4_TOP_ADDRESS 0x01b1
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#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW5_TOP_ADDRESS 0x01b2
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#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW6_TOP_ADDRESS 0x01b3
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#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW7_TOP_ADDRESS 0x01b4
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#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2
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#define mmDMCUB_REGION3_CW0_OFFSET 0x01b5
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#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION3_CW0_OFFSET_HIGH 0x01b6
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#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION3_CW1_OFFSET 0x01b7
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#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION3_CW1_OFFSET_HIGH 0x01b8
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#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION3_CW2_OFFSET 0x01b9
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#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION3_CW2_OFFSET_HIGH 0x01ba
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#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION3_CW3_OFFSET 0x01bb
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#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION3_CW3_OFFSET_HIGH 0x01bc
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#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION3_CW4_OFFSET 0x01bd
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#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION3_CW4_OFFSET_HIGH 0x01be
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#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION3_CW5_OFFSET 0x01bf
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#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION3_CW5_OFFSET_HIGH 0x01c0
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#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION3_CW6_OFFSET 0x01c1
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#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION3_CW6_OFFSET_HIGH 0x01c2
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#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_REGION3_CW7_OFFSET 0x01c3
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#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2
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#define mmDMCUB_REGION3_CW7_OFFSET_HIGH 0x01c4
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#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2
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#define mmDMCUB_INTERRUPT_ENABLE 0x01c5
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#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX 2
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#define mmDMCUB_INTERRUPT_ACK 0x01c6
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#define mmDMCUB_INTERRUPT_ACK_BASE_IDX 2
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#define mmDMCUB_INTERRUPT_STATUS 0x01c7
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#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDMCUB_INTERRUPT_TYPE 0x01c8
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#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX 2
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#define mmDMCUB_EXT_INTERRUPT_STATUS 0x01c9
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#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDMCUB_EXT_INTERRUPT_CTXID 0x01ca
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#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2
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#define mmDMCUB_EXT_INTERRUPT_ACK 0x01cb
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#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2
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#define mmDMCUB_INST_FETCH_FAULT_ADDR 0x01cc
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#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2
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#define mmDMCUB_DATA_WRITE_FAULT_ADDR 0x01cd
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#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2
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#define mmDMCUB_SEC_CNTL 0x01ce
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#define mmDMCUB_SEC_CNTL_BASE_IDX 2
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#define mmDMCUB_MEM_CNTL 0x01cf
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#define mmDMCUB_MEM_CNTL_BASE_IDX 2
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#define mmDMCUB_INBOX0_BASE_ADDRESS 0x01d0
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#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2
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#define mmDMCUB_INBOX0_SIZE 0x01d1
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#define mmDMCUB_INBOX0_SIZE_BASE_IDX 2
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#define mmDMCUB_INBOX0_WPTR 0x01d2
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#define mmDMCUB_INBOX0_WPTR_BASE_IDX 2
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#define mmDMCUB_INBOX0_RPTR 0x01d3
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#define mmDMCUB_INBOX0_RPTR_BASE_IDX 2
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#define mmDMCUB_INBOX1_BASE_ADDRESS 0x01d4
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#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2
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#define mmDMCUB_INBOX1_SIZE 0x01d5
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#define mmDMCUB_INBOX1_SIZE_BASE_IDX 2
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#define mmDMCUB_INBOX1_WPTR 0x01d6
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#define mmDMCUB_INBOX1_WPTR_BASE_IDX 2
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#define mmDMCUB_INBOX1_RPTR 0x01d7
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#define mmDMCUB_INBOX1_RPTR_BASE_IDX 2
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#define mmDMCUB_OUTBOX0_BASE_ADDRESS 0x01d8
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#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2
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#define mmDMCUB_OUTBOX0_SIZE 0x01d9
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#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX 2
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#define mmDMCUB_OUTBOX0_WPTR 0x01da
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#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX 2
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#define mmDMCUB_OUTBOX0_RPTR 0x01db
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#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX 2
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#define mmDMCUB_OUTBOX1_BASE_ADDRESS 0x01dc
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#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2
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#define mmDMCUB_OUTBOX1_SIZE 0x01dd
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#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX 2
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#define mmDMCUB_OUTBOX1_WPTR 0x01de
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#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX 2
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#define mmDMCUB_OUTBOX1_RPTR 0x01df
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#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX 2
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#define mmDMCUB_TIMER_TRIGGER0 0x01e0
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#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX 2
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#define mmDMCUB_TIMER_TRIGGER1 0x01e1
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#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX 2
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#define mmDMCUB_TIMER_WINDOW 0x01e2
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#define mmDMCUB_TIMER_WINDOW_BASE_IDX 2
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#define mmDMCUB_SCRATCH0 0x01e3
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#define mmDMCUB_SCRATCH0_BASE_IDX 2
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#define mmDMCUB_SCRATCH1 0x01e4
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#define mmDMCUB_SCRATCH1_BASE_IDX 2
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#define mmDMCUB_SCRATCH2 0x01e5
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#define mmDMCUB_SCRATCH2_BASE_IDX 2
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#define mmDMCUB_SCRATCH3 0x01e6
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#define mmDMCUB_SCRATCH3_BASE_IDX 2
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#define mmDMCUB_SCRATCH4 0x01e7
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#define mmDMCUB_SCRATCH4_BASE_IDX 2
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#define mmDMCUB_SCRATCH5 0x01e8
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#define mmDMCUB_SCRATCH5_BASE_IDX 2
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#define mmDMCUB_SCRATCH6 0x01e9
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#define mmDMCUB_SCRATCH6_BASE_IDX 2
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#define mmDMCUB_SCRATCH7 0x01ea
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#define mmDMCUB_SCRATCH7_BASE_IDX 2
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#define mmDMCUB_SCRATCH8 0x01eb
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#define mmDMCUB_SCRATCH8_BASE_IDX 2
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#define mmDMCUB_SCRATCH9 0x01ec
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#define mmDMCUB_SCRATCH9_BASE_IDX 2
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#define mmDMCUB_SCRATCH10 0x01ed
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#define mmDMCUB_SCRATCH10_BASE_IDX 2
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#define mmDMCUB_SCRATCH11 0x01ee
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#define mmDMCUB_SCRATCH11_BASE_IDX 2
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#define mmDMCUB_SCRATCH12 0x01ef
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#define mmDMCUB_SCRATCH12_BASE_IDX 2
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#define mmDMCUB_SCRATCH13 0x01f0
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#define mmDMCUB_SCRATCH13_BASE_IDX 2
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#define mmDMCUB_SCRATCH14 0x01f1
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#define mmDMCUB_SCRATCH14_BASE_IDX 2
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#define mmDMCUB_SCRATCH15 0x01f2
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#define mmDMCUB_SCRATCH15_BASE_IDX 2
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#define mmDMCUB_CNTL 0x01f6
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#define mmDMCUB_CNTL_BASE_IDX 2
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#define mmDMCUB_GPINT_DATAIN0 0x01f7
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#define mmDMCUB_GPINT_DATAIN0_BASE_IDX 2
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#define mmDMCUB_GPINT_DATAIN1 0x01f8
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#define mmDMCUB_GPINT_DATAIN1_BASE_IDX 2
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#define mmDMCUB_GPINT_DATAOUT 0x01f9
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#define mmDMCUB_GPINT_DATAOUT_BASE_IDX 2
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#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x01fa
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#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2
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#define mmDMCUB_LS_WAKE_INT_ENABLE 0x01fb
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#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2
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#define mmDMCUB_MEM_PWR_CNTL 0x01fc
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#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX 2
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#define mmDMCUB_TIMER_CURRENT 0x01fd
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#define mmDMCUB_TIMER_CURRENT_BASE_IDX 2
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#define mmDMCUB_PROC_ID 0x01ff
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#define mmDMCUB_PROC_ID_BASE_IDX 2
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// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
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// base address: 0x0
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#define mmMCIF_WB_BUFMGR_SW_CONTROL 0x0272
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#define mmMCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
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#define mmMCIF_WB_BUFMGR_STATUS 0x0274
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#define mmMCIF_WB_BUFMGR_STATUS_BASE_IDX 2
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#define mmMCIF_WB_BUF_PITCH 0x0275
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#define mmMCIF_WB_BUF_PITCH_BASE_IDX 2
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#define mmMCIF_WB_BUF_1_STATUS 0x0276
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#define mmMCIF_WB_BUF_1_STATUS_BASE_IDX 2
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#define mmMCIF_WB_BUF_1_STATUS2 0x0277
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#define mmMCIF_WB_BUF_1_STATUS2_BASE_IDX 2
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#define mmMCIF_WB_BUF_2_STATUS 0x0278
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#define mmMCIF_WB_BUF_2_STATUS_BASE_IDX 2
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#define mmMCIF_WB_BUF_2_STATUS2 0x0279
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#define mmMCIF_WB_BUF_2_STATUS2_BASE_IDX 2
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#define mmMCIF_WB_BUF_3_STATUS 0x027a
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#define mmMCIF_WB_BUF_3_STATUS_BASE_IDX 2
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#define mmMCIF_WB_BUF_3_STATUS2 0x027b
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#define mmMCIF_WB_BUF_3_STATUS2_BASE_IDX 2
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#define mmMCIF_WB_BUF_4_STATUS 0x027c
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#define mmMCIF_WB_BUF_4_STATUS_BASE_IDX 2
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#define mmMCIF_WB_BUF_4_STATUS2 0x027d
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#define mmMCIF_WB_BUF_4_STATUS2_BASE_IDX 2
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#define mmMCIF_WB_ARBITRATION_CONTROL 0x027e
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#define mmMCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
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#define mmMCIF_WB_SCLK_CHANGE 0x027f
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#define mmMCIF_WB_SCLK_CHANGE_BASE_IDX 2
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#define mmMCIF_WB_BUF_1_ADDR_Y 0x0282
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#define mmMCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB_BUF_1_ADDR_C 0x0284
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#define mmMCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB_BUF_2_ADDR_Y 0x0286
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#define mmMCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB_BUF_2_ADDR_C 0x0288
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#define mmMCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB_BUF_3_ADDR_Y 0x028a
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#define mmMCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB_BUF_3_ADDR_C 0x028c
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#define mmMCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB_BUF_4_ADDR_Y 0x028e
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#define mmMCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB_BUF_4_ADDR_C 0x0290
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#define mmMCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB_BUFMGR_VCE_CONTROL 0x0292
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#define mmMCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
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#define mmMCIF_WB_NB_PSTATE_CONTROL 0x0293
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#define mmMCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
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#define mmMCIF_WB_CLOCK_GATER_CONTROL 0x0294
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#define mmMCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
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#define mmMCIF_WB_SELF_REFRESH_CONTROL 0x0296
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#define mmMCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
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#define mmMULTI_LEVEL_QOS_CTRL 0x0297
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#define mmMULTI_LEVEL_QOS_CTRL_BASE_IDX 2
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#define mmMCIF_WB_BUF_LUMA_SIZE 0x0299
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#define mmMCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
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#define mmMCIF_WB_BUF_CHROMA_SIZE 0x029a
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#define mmMCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
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#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH 0x029b
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#define mmMCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
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#define mmMCIF_WB_BUF_1_ADDR_C_HIGH 0x029c
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#define mmMCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
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#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH 0x029d
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#define mmMCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
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#define mmMCIF_WB_BUF_2_ADDR_C_HIGH 0x029e
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#define mmMCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
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#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH 0x029f
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#define mmMCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
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#define mmMCIF_WB_BUF_3_ADDR_C_HIGH 0x02a0
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#define mmMCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
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#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH 0x02a1
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#define mmMCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
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#define mmMCIF_WB_BUF_4_ADDR_C_HIGH 0x02a2
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#define mmMCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
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#define mmMCIF_WB_BUF_1_RESOLUTION 0x02a3
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#define mmMCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
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#define mmMCIF_WB_BUF_2_RESOLUTION 0x02a4
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#define mmMCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
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#define mmMCIF_WB_BUF_3_RESOLUTION 0x02a5
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#define mmMCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
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#define mmMCIF_WB_BUF_4_RESOLUTION 0x02a6
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#define mmMCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
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#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI 0x02a7
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#define mmMCIF_WB_DRAM_SPEED_CHANGE_DURATION_VBI_BASE_IDX 2
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#define mmMCIF_WB_VMID_CONTROL 0x02a8
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#define mmMCIF_WB_VMID_CONTROL_BASE_IDX 2
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#define mmMCIF_WB_MIN_TTO 0x02a9
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#define mmMCIF_WB_MIN_TTO_BASE_IDX 2
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// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
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// base address: 0x0
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#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02aa
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#define mmMCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
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#define mmMCIF_WB_WATERMARK 0x02ab
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#define mmMCIF_WB_WATERMARK_BASE_IDX 2
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#define mmMMHUBBUB_WARMUP_CONFIG 0x02ac
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#define mmMMHUBBUB_WARMUP_CONFIG_BASE_IDX 2
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#define mmMMHUBBUB_WARMUP_CONTROL_STATUS 0x02ad
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#define mmMMHUBBUB_WARMUP_CONTROL_STATUS_BASE_IDX 2
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#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW 0x02ae
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#define mmMMHUBBUB_WARMUP_BASE_ADDR_LOW_BASE_IDX 2
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#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH 0x02af
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#define mmMMHUBBUB_WARMUP_BASE_ADDR_HIGH_BASE_IDX 2
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#define mmMMHUBBUB_WARMUP_ADDR_REGION 0x02b0
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#define mmMMHUBBUB_WARMUP_ADDR_REGION_BASE_IDX 2
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#define mmMMHUBBUB_MIN_TTO 0x02b1
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#define mmMMHUBBUB_MIN_TTO_BASE_IDX 2
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#define mmWBIF_SMU_WM_CONTROL 0x0333
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#define mmWBIF_SMU_WM_CONTROL_BASE_IDX 2
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#define mmWBIF0_MISC_CTRL 0x0334
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#define mmWBIF0_MISC_CTRL_BASE_IDX 2
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#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335
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#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336
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#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmVGA_SRC_SPLIT_CNTL 0x033d
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#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2
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#define mmMMHUBBUB_MEM_PWR_STATUS 0x033e
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#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2
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#define mmMMHUBBUB_MEM_PWR_CNTL 0x033f
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#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2
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#define mmMMHUBBUB_CLOCK_CNTL 0x0340
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#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2
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#define mmMMHUBBUB_SOFT_RESET 0x0341
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#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2
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#define mmDMU_IF_ERR_STATUS 0x0345
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#define mmDMU_IF_ERR_STATUS_BASE_IDX 2
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#define mmMMHUBBUB_CLIENT_UNIT_ID 0x0346
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#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2
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#define mmMMHUBBUB_WARMUP_VMID_CONTROL 0x0348
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#define mmMMHUBBUB_WARMUP_VMID_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
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// base address: 0x0
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#define mmMCIF_CONTROL 0x034a
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#define mmMCIF_CONTROL_BASE_IDX 2
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#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b
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#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
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#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e
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#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f
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#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350
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#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
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// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
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// base address: 0xd48
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#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x0352
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#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x0353
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#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x0354
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#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON3_PERFMON_CNTL 0x0355
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#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON3_PERFMON_CNTL2 0x0356
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#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x0357
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#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0358
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#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON3_PERFMON_HI 0x0359
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#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON3_PERFMON_LOW 0x035a
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#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream0_dispdec
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// base address: 0x0
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#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e
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#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f
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#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream1_dispdec
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// base address: 0x8
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#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360
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#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361
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#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream2_dispdec
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// base address: 0x10
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#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362
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#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363
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#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream3_dispdec
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// base address: 0x18
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#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364
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#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365
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#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream4_dispdec
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// base address: 0x20
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#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366
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#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367
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#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream5_dispdec
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// base address: 0x28
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#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368
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#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369
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#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream6_dispdec
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// base address: 0x30
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#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a
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#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b
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#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream7_dispdec
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// base address: 0x38
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#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c
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#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d
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#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_az_misc_dispdec
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// base address: 0x0
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#define mmAZ_CLOCK_CNTL 0x0372
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#define mmAZ_CLOCK_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
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// base address: 0xde8
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#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x037a
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#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x037b
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#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x037c
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#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_CNTL 0x037d
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#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_CNTL2 0x037e
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#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x037f
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#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0380
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#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_HI 0x0381
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#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_LOW 0x0382
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#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
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// base address: 0x0
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#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386
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#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387
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#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
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// base address: 0x18
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#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c
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#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d
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#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
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// base address: 0x30
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#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392
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#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393
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#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
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// base address: 0x48
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#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398
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#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399
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#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
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// base address: 0x60
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#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e
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#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f
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#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
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// base address: 0x78
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#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4
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#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5
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#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
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// base address: 0x90
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#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa
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#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab
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#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
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// base address: 0xa8
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#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0
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#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1
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#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0controller_dispdec
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// base address: 0x0
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#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2
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#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
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#define mmAZALIA_AUDIO_DTO 0x03c3
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#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
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#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4
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#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
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#define mmAZALIA_SOCCLK_CONTROL 0x03c5
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#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
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#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6
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#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
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#define mmAZALIA_DATA_DMA_CONTROL 0x03c7
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#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
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#define mmAZALIA_BDL_DMA_CONTROL 0x03c8
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#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
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#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9
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#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
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#define mmAZALIA_CORB_DMA_CONTROL 0x03ca
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#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
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#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1
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#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
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#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2
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#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
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#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3
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#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
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#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4
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#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
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#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5
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#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
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#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6
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#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9
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#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da
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#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db
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#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc
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#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd
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#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de
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#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df
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#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0
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#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1
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#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2
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#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
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#define mmAZALIA_CRC0_CONTROL0 0x03e3
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#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
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#define mmAZALIA_CRC0_CONTROL1 0x03e4
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#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
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#define mmAZALIA_CRC0_CONTROL2 0x03e5
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#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
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#define mmAZALIA_CRC0_CONTROL3 0x03e6
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#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
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#define mmAZALIA_CRC0_RESULT 0x03e7
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#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
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#define mmAZALIA_CRC1_CONTROL0 0x03e8
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#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
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#define mmAZALIA_CRC1_CONTROL1 0x03e9
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#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
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#define mmAZALIA_CRC1_CONTROL2 0x03ea
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#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
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#define mmAZALIA_CRC1_CONTROL3 0x03eb
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#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
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#define mmAZALIA_CRC1_RESULT 0x03ec
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#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
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#define mmAZALIA_MEM_PWR_CTRL 0x03ee
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#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
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#define mmAZALIA_MEM_PWR_STATUS 0x03ef
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#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0root_dispdec
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// base address: 0x0
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#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406
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#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407
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#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408
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#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409
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#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
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#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412
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#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
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#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413
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#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415
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#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416
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#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417
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#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418
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#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419
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#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a
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#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b
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#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
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#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c
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#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
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#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d
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#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream8_dispdec
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// base address: 0x320
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#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426
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#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427
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#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream9_dispdec
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// base address: 0x328
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#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428
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#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429
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#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream10_dispdec
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// base address: 0x330
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#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a
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#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b
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#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream11_dispdec
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// base address: 0x338
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#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c
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#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d
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#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream12_dispdec
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// base address: 0x340
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#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e
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#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f
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#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream13_dispdec
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// base address: 0x348
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#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430
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#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431
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#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream14_dispdec
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// base address: 0x350
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#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432
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#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433
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#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream15_dispdec
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// base address: 0x358
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#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434
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#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435
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#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
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// base address: 0x0
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#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a
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#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b
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#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
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// base address: 0x10
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#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e
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#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f
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#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
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// base address: 0x20
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#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442
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#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443
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#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
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// base address: 0x30
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#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446
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#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447
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#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
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// base address: 0x40
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#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a
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#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b
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#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
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// base address: 0x50
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#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e
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#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f
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#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
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// base address: 0x60
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#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452
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#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453
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#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
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// base address: 0x70
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#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456
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#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457
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#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
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// base address: 0x0
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#define mmDCHUBBUB_SDPIF_CFG0 0x048f
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#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2
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#define mmVM_REQUEST_PHYSICAL 0x0490
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#define mmVM_REQUEST_PHYSICAL_BASE_IDX 2
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#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491
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#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2
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#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492
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#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2
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#define mmDCN_VM_FB_LOCATION_BASE 0x0493
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#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX 2
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#define mmDCN_VM_FB_LOCATION_TOP 0x0494
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#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX 2
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#define mmDCN_VM_FB_OFFSET 0x0495
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#define mmDCN_VM_FB_OFFSET_BASE_IDX 2
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#define mmDCN_VM_AGP_BOT 0x0496
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#define mmDCN_VM_AGP_BOT_BASE_IDX 2
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#define mmDCN_VM_AGP_TOP 0x0497
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#define mmDCN_VM_AGP_TOP_BASE_IDX 2
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#define mmDCN_VM_AGP_BASE 0x0498
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#define mmDCN_VM_AGP_BASE_BASE_IDX 2
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#define mmDCN_VM_LOCAL_HBM_ADDRESS_START 0x0499
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#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2
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#define mmDCN_VM_LOCAL_HBM_ADDRESS_END 0x049a
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#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2
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#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x049b
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#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04ba
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#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04bb
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#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_CFG1 0x04bf
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#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_CFG2 0x04c0
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#define mmDCHUBBUB_SDPIF_CFG2_BASE_IDX 2
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// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
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// base address: 0x0
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#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf
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#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0
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#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1
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#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3
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#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4
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#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5
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#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6
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#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7
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#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8
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#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9
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#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da
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#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db
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#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc
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#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd
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#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de
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#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df
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#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG8_0 0x04e0
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#define mmDCHUBBUB_RET_PATH_DCC_CFG8_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG8_1 0x04e1
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#define mmDCHUBBUB_RET_PATH_DCC_CFG8_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG9_0 0x04e2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG9_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG9_1 0x04e3
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#define mmDCHUBBUB_RET_PATH_DCC_CFG9_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG10_0 0x04e4
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#define mmDCHUBBUB_RET_PATH_DCC_CFG10_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG10_1 0x04e5
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#define mmDCHUBBUB_RET_PATH_DCC_CFG10_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG11_0 0x04e6
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#define mmDCHUBBUB_RET_PATH_DCC_CFG11_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG11_1 0x04e7
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#define mmDCHUBBUB_RET_PATH_DCC_CFG11_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef
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#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0
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#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCHUBBUB_CRC_CTRL 0x04f1
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#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2
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#define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2
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#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2
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#define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3
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#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2
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#define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4
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#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2
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#define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5
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#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2
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// addressBlock: dce_dc_dchubbub_hubbub_dispdec
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// base address: 0x0
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#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505
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#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2
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#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506
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#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2
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#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507
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#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2
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#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508
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#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2
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#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A 0x050a
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#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2
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#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B 0x050f
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#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2
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#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C 0x0514
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#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2
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#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D 0x0519
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#define mmDCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2
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#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d
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#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2
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#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e
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#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2
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#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f
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#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2
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#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520
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#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2
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#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521
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#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2
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#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522
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#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2
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#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523
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#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2
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#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524
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#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2
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#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525
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#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2
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#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526
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#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2
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#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527
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#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2
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#define mmVTG0_CONTROL 0x0528
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#define mmVTG0_CONTROL_BASE_IDX 2
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#define mmVTG1_CONTROL 0x0529
|
#define mmVTG1_CONTROL_BASE_IDX 2
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#define mmVTG2_CONTROL 0x052a
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#define mmVTG2_CONTROL_BASE_IDX 2
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#define mmVTG3_CONTROL 0x052b
|
#define mmVTG3_CONTROL_BASE_IDX 2
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#define mmVTG4_CONTROL 0x052c
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#define mmVTG4_CONTROL_BASE_IDX 2
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#define mmVTG5_CONTROL 0x052d
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#define mmVTG5_CONTROL_BASE_IDX 2
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#define mmDCHUBBUB_SOFT_RESET 0x052e
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#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2
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#define mmDCHUBBUB_CLOCK_CNTL 0x052f
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#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2
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#define mmDCFCLK_CNTL 0x0530
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#define mmDCFCLK_CNTL_BASE_IDX 2
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#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531
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#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2
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#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532
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#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2
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#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533
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#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2
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#define mmDCHUBBUB_CTRL_STATUS 0x0534
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#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2
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#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a
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#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2
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#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b
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#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2
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#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c
|
#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d
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#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2
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#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e
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#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2
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#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A 0x053f
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#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_A_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A 0x0540
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#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_A_BASE_IDX 2
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#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B 0x0541
|
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_B_BASE_IDX 2
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#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B 0x0542
|
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_B_BASE_IDX 2
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#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C 0x0543
|
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_C_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C 0x0544
|
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_C_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D 0x0545
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#define mmDCHUBBUB_ARB_FRAC_URG_BW_NOM_D_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D 0x0546
|
#define mmDCHUBBUB_ARB_FRAC_URG_BW_FLIP_D_BASE_IDX 2
|
#define mmFMON_CTRL 0x0548
|
#define mmFMON_CTRL_BASE_IDX 2
|
#define mmFMON_CTRL_1 0x0548
|
#define mmFMON_CTRL_1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x1534
|
#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x054d
|
#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x054e
|
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x054f
|
#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFMON_CNTL 0x0550
|
#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFMON_CNTL2 0x0551
|
#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0552
|
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0553
|
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFMON_HI 0x0554
|
#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFMON_LOW 0x0555
|
#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
|
// base address: 0x0
|
#define mmDCN_VM_CONTEXT0_CNTL 0x0559
|
#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_CNTL 0x0560
|
#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_CNTL 0x0567
|
#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
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#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c
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#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d
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#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_CNTL 0x056e
|
#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570
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#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571
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#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572
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#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_CNTL 0x0575
|
#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_CNTL 0x057c
|
#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_CNTL 0x0583
|
#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_CNTL 0x058a
|
#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_CNTL 0x0591
|
#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_CNTL 0x0598
|
#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_CNTL 0x059f
|
#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_CNTL 0x05a6
|
#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_CNTL 0x05ad
|
#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_CNTL 0x05b4
|
#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_CNTL 0x05bb
|
#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_CNTL 0x05c2
|
#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_DEFAULT_ADDR_MSB 0x05c9
|
#define mmDCN_VM_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmDCN_VM_DEFAULT_ADDR_LSB 0x05ca
|
#define mmDCN_VM_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmDCN_VM_FAULT_CNTL 0x05cb
|
#define mmDCN_VM_FAULT_CNTL_BASE_IDX 2
|
#define mmDCN_VM_FAULT_STATUS 0x05cc
|
#define mmDCN_VM_FAULT_STATUS_BASE_IDX 2
|
#define mmDCN_VM_FAULT_ADDR_MSB 0x05cd
|
#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2
|
#define mmDCN_VM_FAULT_ADDR_LSB 0x05ce
|
#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
|
// base address: 0x0
|
#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5
|
#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2
|
#define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6
|
#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2
|
#define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7
|
#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1
|
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
|
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2
|
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
|
#define mmHUBP0_DCHUBP_CNTL 0x05f3
|
#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2
|
#define mmHUBP0_HUBP_CLK_CNTL 0x05f4
|
#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2
|
#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x05f5
|
#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2
|
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb
|
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
|
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc
|
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
|
#define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6
|
#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
|
#define mmHUBP0_HUBPREQ_DEBUG 0x05f7
|
#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
|
// base address: 0x0
|
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607
|
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608
|
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
|
#define mmHUBPREQ0_VMID_SETTINGS_0 0x0609
|
#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a
|
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b
|
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c
|
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620
|
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x0629
|
#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062a
|
#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062b
|
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062c
|
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x062d
|
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x062e
|
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x062f
|
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0630
|
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0631
|
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0632
|
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0633
|
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL 0x0634
|
#define mmHUBPREQ0_DCN_DMDATA_VM_CNTL_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0635
|
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0636
|
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0643
|
#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
|
#define mmHUBPREQ0_BLANK_OFFSET_0 0x0644
|
#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2
|
#define mmHUBPREQ0_BLANK_OFFSET_1 0x0645
|
#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2
|
#define mmHUBPREQ0_DST_DIMENSIONS 0x0646
|
#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2
|
#define mmHUBPREQ0_DST_AFTER_SCALER 0x0647
|
#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2
|
#define mmHUBPREQ0_PREFETCH_SETTINGS 0x0648
|
#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x0649
|
#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064a
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064b
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064c
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064d
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x064e
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ0_FLIP_PARAMETERS_0 0x064f
|
#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ0_FLIP_PARAMETERS_1 0x0650
|
#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0651
|
#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_0 0x0652
|
#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_1 0x0653
|
#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_2 0x0654
|
#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_3 0x0655
|
#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_4 0x0656
|
#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_5 0x0657
|
#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_6 0x0658
|
#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_7 0x0659
|
#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2
|
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065a
|
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2
|
#define mmHUBPREQ0_PER_LINE_DELIVERY 0x065b
|
#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2
|
#define mmHUBPREQ0_CURSOR_SETTINGS 0x065c
|
#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065d
|
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
|
#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x065e
|
#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
|
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x065f
|
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0660
|
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_5 0x0663
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_5_BASE_IDX 2
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_6 0x0664
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_6_BASE_IDX 2
|
#define mmHUBPREQ0_FLIP_PARAMETERS_3 0x0665
|
#define mmHUBPREQ0_FLIP_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ0_FLIP_PARAMETERS_4 0x0666
|
#define mmHUBPREQ0_FLIP_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ0_FLIP_PARAMETERS_5 0x0667
|
#define mmHUBPREQ0_FLIP_PARAMETERS_5_BASE_IDX 2
|
#define mmHUBPREQ0_FLIP_PARAMETERS_6 0x0668
|
#define mmHUBPREQ0_FLIP_PARAMETERS_6_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
|
// base address: 0x0
|
#define mmHUBPRET0_HUBPRET_CONTROL 0x066c
|
#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d
|
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e
|
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f
|
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670
|
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_READ_LINE0 0x0671
|
#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_READ_LINE1 0x0672
|
#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_INTERRUPT 0x0673
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#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2
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#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674
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#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
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#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675
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#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
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// base address: 0x0
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#define mmCURSOR0_0_CURSOR_CONTROL 0x0678
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#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2
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#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679
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#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a
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#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_0_CURSOR_SIZE 0x067b
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#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2
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#define mmCURSOR0_0_CURSOR_POSITION 0x067c
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#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2
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#define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d
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#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2
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#define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e
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#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2
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#define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f
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#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2
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#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680
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#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681
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#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682
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#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683
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#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2
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#define mmCURSOR0_0_DMDATA_CNTL 0x0684
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#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2
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#define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685
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#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2
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#define mmCURSOR0_0_DMDATA_STATUS 0x0686
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#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2
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#define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687
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#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2
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#define mmCURSOR0_0_DMDATA_SW_DATA 0x0688
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#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x1a74
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#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x069d
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#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x069e
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#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x069f
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#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_CNTL 0x06a0
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#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_CNTL2 0x06a1
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#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x06a2
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#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x06a3
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#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_HI 0x06a4
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#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_LOW 0x06a5
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#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
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// base address: 0x370
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#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1
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#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2
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#define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2
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#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2
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#define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3
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#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd
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#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
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#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce
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#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
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#define mmHUBP1_DCHUBP_CNTL 0x06cf
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#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2
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#define mmHUBP1_HUBP_CLK_CNTL 0x06d0
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#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2
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#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x06d1
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#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2
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#define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2
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#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define mmHUBP1_HUBPREQ_DEBUG 0x06d3
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#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2
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#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7
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#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
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#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8
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#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
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// base address: 0x370
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#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3
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#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4
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#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
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#define mmHUBPREQ1_VMID_SETTINGS_0 0x06e5
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#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6
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#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7
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#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8
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#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc
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#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0705
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#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2
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#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0706
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#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2
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#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0707
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#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
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#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0708
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#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0709
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#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070a
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#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070b
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#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070c
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#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x070d
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#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x070e
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#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x070f
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#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL 0x0710
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#define mmHUBPREQ1_DCN_DMDATA_VM_CNTL_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0711
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0712
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x071f
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#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
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#define mmHUBPREQ1_BLANK_OFFSET_0 0x0720
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#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2
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#define mmHUBPREQ1_BLANK_OFFSET_1 0x0721
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#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2
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#define mmHUBPREQ1_DST_DIMENSIONS 0x0722
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#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2
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#define mmHUBPREQ1_DST_AFTER_SCALER 0x0723
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#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2
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#define mmHUBPREQ1_PREFETCH_SETTINGS 0x0724
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#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2
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#define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0725
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#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2
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#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0726
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#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0727
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#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0728
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#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0729
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#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072a
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#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072b
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#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ1_FLIP_PARAMETERS_1 0x072c
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#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072d
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#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_0 0x072e
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#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_1 0x072f
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#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0730
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#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0731
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#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0732
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#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_5 0x0733
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#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_6 0x0734
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#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_7 0x0735
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#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2
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#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0736
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#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2
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#define mmHUBPREQ1_PER_LINE_DELIVERY 0x0737
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#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2
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#define mmHUBPREQ1_CURSOR_SETTINGS 0x0738
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#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2
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#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0739
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#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
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#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073a
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#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
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#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073b
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#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073c
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#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPREQ1_VBLANK_PARAMETERS_5 0x073f
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#define mmHUBPREQ1_VBLANK_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ1_VBLANK_PARAMETERS_6 0x0740
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#define mmHUBPREQ1_VBLANK_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ1_FLIP_PARAMETERS_3 0x0741
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#define mmHUBPREQ1_FLIP_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ1_FLIP_PARAMETERS_4 0x0742
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#define mmHUBPREQ1_FLIP_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ1_FLIP_PARAMETERS_5 0x0743
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#define mmHUBPREQ1_FLIP_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ1_FLIP_PARAMETERS_6 0x0744
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#define mmHUBPREQ1_FLIP_PARAMETERS_6_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
|
// base address: 0x370
|
#define mmHUBPRET1_HUBPRET_CONTROL 0x0748
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#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749
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#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a
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#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b
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#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c
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#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_READ_LINE0 0x074d
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#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_READ_LINE1 0x074e
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#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_INTERRUPT 0x074f
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#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750
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#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751
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#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
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// base address: 0x370
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#define mmCURSOR0_1_CURSOR_CONTROL 0x0754
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#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2
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#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755
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#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756
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#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_1_CURSOR_SIZE 0x0757
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#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2
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#define mmCURSOR0_1_CURSOR_POSITION 0x0758
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#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2
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#define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759
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#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2
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#define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a
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#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2
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#define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b
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#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2
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#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c
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#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d
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#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e
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#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f
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#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2
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#define mmCURSOR0_1_DMDATA_CNTL 0x0760
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#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2
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#define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761
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#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2
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#define mmCURSOR0_1_DMDATA_STATUS 0x0762
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#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2
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#define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763
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#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2
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#define mmCURSOR0_1_DMDATA_SW_DATA 0x0764
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#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x1de4
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#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x0779
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#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x077a
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#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x077b
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#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON7_PERFMON_CNTL 0x077c
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#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON7_PERFMON_CNTL2 0x077d
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#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x077e
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#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x077f
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#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON7_PERFMON_HI 0x0780
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#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON7_PERFMON_LOW 0x0781
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#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
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// base address: 0x6e0
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#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x079d
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#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2
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#define mmHUBP2_DCSURF_ADDR_CONFIG 0x079e
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#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2
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#define mmHUBP2_DCSURF_TILING_CONFIG 0x079f
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#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9
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#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
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#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa
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#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
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#define mmHUBP2_DCHUBP_CNTL 0x07ab
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#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2
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#define mmHUBP2_HUBP_CLK_CNTL 0x07ac
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#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2
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#define mmHUBP2_DCHUBP_VMPG_CONFIG 0x07ad
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#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2
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#define mmHUBP2_HUBPREQ_DEBUG_DB 0x07ae
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#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define mmHUBP2_HUBPREQ_DEBUG 0x07af
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#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2
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#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3
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#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
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#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4
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#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
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// base address: 0x6e0
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#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf
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#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0
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#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
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#define mmHUBPREQ2_VMID_SETTINGS_0 0x07c1
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#define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2
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#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3
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#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4
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#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8
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#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x07e1
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#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2
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#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x07e2
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#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2
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#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e3
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#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
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#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e4
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#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e5
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#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e6
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#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07e7
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#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07e8
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#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07e9
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#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ea
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#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07eb
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#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ2_DCN_DMDATA_VM_CNTL 0x07ec
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#define mmHUBPREQ2_DCN_DMDATA_VM_CNTL_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ed
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07ee
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fb
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#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
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#define mmHUBPREQ2_BLANK_OFFSET_0 0x07fc
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#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2
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#define mmHUBPREQ2_BLANK_OFFSET_1 0x07fd
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#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2
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#define mmHUBPREQ2_DST_DIMENSIONS 0x07fe
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#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2
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#define mmHUBPREQ2_DST_AFTER_SCALER 0x07ff
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#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2
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#define mmHUBPREQ2_PREFETCH_SETTINGS 0x0800
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#define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2
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#define mmHUBPREQ2_PREFETCH_SETTINGS_C 0x0801
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#define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2
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#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0802
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#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0803
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#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0804
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#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0805
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#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0806
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#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ2_FLIP_PARAMETERS_0 0x0807
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#define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ2_FLIP_PARAMETERS_1 0x0808
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#define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ2_FLIP_PARAMETERS_2 0x0809
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#define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_0 0x080a
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#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_1 0x080b
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#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_2 0x080c
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#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_3 0x080d
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#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_4 0x080e
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#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_5 0x080f
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#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_6 0x0810
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#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0811
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#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2
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#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0812
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#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2
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#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0813
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#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2
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#define mmHUBPREQ2_CURSOR_SETTINGS 0x0814
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#define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2
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#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0815
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#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
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#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0816
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#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
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#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0817
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#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0818
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#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPREQ2_VBLANK_PARAMETERS_5 0x081b
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#define mmHUBPREQ2_VBLANK_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ2_VBLANK_PARAMETERS_6 0x081c
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#define mmHUBPREQ2_VBLANK_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ2_FLIP_PARAMETERS_3 0x081d
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#define mmHUBPREQ2_FLIP_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ2_FLIP_PARAMETERS_4 0x081e
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#define mmHUBPREQ2_FLIP_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ2_FLIP_PARAMETERS_5 0x081f
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#define mmHUBPREQ2_FLIP_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ2_FLIP_PARAMETERS_6 0x0820
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#define mmHUBPREQ2_FLIP_PARAMETERS_6_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
|
// base address: 0x6e0
|
#define mmHUBPRET2_HUBPRET_CONTROL 0x0824
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#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825
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#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826
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#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827
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#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828
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#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_READ_LINE0 0x0829
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#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_READ_LINE1 0x082a
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#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_INTERRUPT 0x082b
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#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c
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#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d
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#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
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// base address: 0x6e0
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#define mmCURSOR0_2_CURSOR_CONTROL 0x0830
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#define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2
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#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831
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#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832
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#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_2_CURSOR_SIZE 0x0833
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#define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX 2
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#define mmCURSOR0_2_CURSOR_POSITION 0x0834
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#define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX 2
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#define mmCURSOR0_2_CURSOR_HOT_SPOT 0x0835
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#define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2
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#define mmCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836
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#define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2
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#define mmCURSOR0_2_CURSOR_DST_OFFSET 0x0837
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#define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2
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#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838
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#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839
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#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a
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#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b
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#define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2
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#define mmCURSOR0_2_DMDATA_CNTL 0x083c
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#define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX 2
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#define mmCURSOR0_2_DMDATA_QOS_CNTL 0x083d
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#define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2
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#define mmCURSOR0_2_DMDATA_STATUS 0x083e
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#define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX 2
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#define mmCURSOR0_2_DMDATA_SW_CNTL 0x083f
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#define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2
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#define mmCURSOR0_2_DMDATA_SW_DATA 0x0840
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#define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x2154
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#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0855
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#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x0856
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#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x0857
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#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_CNTL 0x0858
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#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_CNTL2 0x0859
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#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x085a
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#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x085b
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#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_HI 0x085c
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#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_LOW 0x085d
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#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
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// base address: 0xa50
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#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x0879
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#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2
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#define mmHUBP3_DCSURF_ADDR_CONFIG 0x087a
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#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2
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#define mmHUBP3_DCSURF_TILING_CONFIG 0x087b
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#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885
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#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
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#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886
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#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
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#define mmHUBP3_DCHUBP_CNTL 0x0887
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#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2
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#define mmHUBP3_HUBP_CLK_CNTL 0x0888
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#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2
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#define mmHUBP3_DCHUBP_VMPG_CONFIG 0x0889
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#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2
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#define mmHUBP3_HUBPREQ_DEBUG_DB 0x088a
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#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define mmHUBP3_HUBPREQ_DEBUG 0x088b
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#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2
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#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f
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#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
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#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890
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#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
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// base address: 0xa50
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#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b
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#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c
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#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
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#define mmHUBPREQ3_VMID_SETTINGS_0 0x089d
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#define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae
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#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af
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#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0
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#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4
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#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x08bd
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#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2
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#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x08be
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#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2
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#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08bf
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#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
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#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c0
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#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c1
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#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c2
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#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c3
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#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c4
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#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c5
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#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c6
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#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08c7
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#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ3_DCN_DMDATA_VM_CNTL 0x08c8
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#define mmHUBPREQ3_DCN_DMDATA_VM_CNTL_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08c9
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08ca
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d7
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#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
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#define mmHUBPREQ3_BLANK_OFFSET_0 0x08d8
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#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2
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#define mmHUBPREQ3_BLANK_OFFSET_1 0x08d9
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#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2
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#define mmHUBPREQ3_DST_DIMENSIONS 0x08da
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#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2
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#define mmHUBPREQ3_DST_AFTER_SCALER 0x08db
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#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2
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#define mmHUBPREQ3_PREFETCH_SETTINGS 0x08dc
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#define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2
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#define mmHUBPREQ3_PREFETCH_SETTINGS_C 0x08dd
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#define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x08de
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#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x08df
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#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x08e0
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#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x08e1
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#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x08e2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ3_FLIP_PARAMETERS_0 0x08e3
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#define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ3_FLIP_PARAMETERS_1 0x08e4
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#define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ3_FLIP_PARAMETERS_2 0x08e5
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#define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_0 0x08e6
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#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_1 0x08e7
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#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_2 0x08e8
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#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_3 0x08e9
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#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_4 0x08ea
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#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_5 0x08eb
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#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_6 0x08ec
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#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_7 0x08ed
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#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2
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#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08ee
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#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2
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#define mmHUBPREQ3_PER_LINE_DELIVERY 0x08ef
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#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2
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#define mmHUBPREQ3_CURSOR_SETTINGS 0x08f0
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#define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2
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#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f1
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#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
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#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f2
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#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
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#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f3
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#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f4
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#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_5 0x08f7
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#define mmHUBPREQ3_VBLANK_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_6 0x08f8
|
#define mmHUBPREQ3_VBLANK_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ3_FLIP_PARAMETERS_3 0x08f9
|
#define mmHUBPREQ3_FLIP_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ3_FLIP_PARAMETERS_4 0x08fa
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#define mmHUBPREQ3_FLIP_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ3_FLIP_PARAMETERS_5 0x08fb
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#define mmHUBPREQ3_FLIP_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ3_FLIP_PARAMETERS_6 0x08fc
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#define mmHUBPREQ3_FLIP_PARAMETERS_6_BASE_IDX 2
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|
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// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
|
// base address: 0xa50
|
#define mmHUBPRET3_HUBPRET_CONTROL 0x0900
|
#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2
|
#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901
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#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902
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#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903
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#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904
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#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0905
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#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0906
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#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0907
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#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908
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#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909
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#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
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// base address: 0xa50
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#define mmCURSOR0_3_CURSOR_CONTROL 0x090c
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#define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2
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#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d
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#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e
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#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_3_CURSOR_SIZE 0x090f
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#define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX 2
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#define mmCURSOR0_3_CURSOR_POSITION 0x0910
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#define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX 2
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#define mmCURSOR0_3_CURSOR_HOT_SPOT 0x0911
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#define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2
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#define mmCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912
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#define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2
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#define mmCURSOR0_3_CURSOR_DST_OFFSET 0x0913
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#define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2
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#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914
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#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915
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#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916
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#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917
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#define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2
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#define mmCURSOR0_3_DMDATA_CNTL 0x0918
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#define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX 2
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#define mmCURSOR0_3_DMDATA_QOS_CNTL 0x0919
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#define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2
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#define mmCURSOR0_3_DMDATA_STATUS 0x091a
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#define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX 2
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#define mmCURSOR0_3_DMDATA_SW_CNTL 0x091b
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#define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2
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#define mmCURSOR0_3_DMDATA_SW_DATA 0x091c
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#define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x24c4
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#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0931
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#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0932
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#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0933
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#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_CNTL 0x0934
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#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_CNTL2 0x0935
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#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x0936
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#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x0937
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#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_HI 0x0938
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#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_LOW 0x0939
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#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp4_dispdec_hubp_dispdec
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// base address: 0xdc0
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#define mmHUBP4_DCSURF_SURFACE_CONFIG 0x0955
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#define mmHUBP4_DCSURF_SURFACE_CONFIG_BASE_IDX 2
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#define mmHUBP4_DCSURF_ADDR_CONFIG 0x0956
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#define mmHUBP4_DCSURF_ADDR_CONFIG_BASE_IDX 2
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#define mmHUBP4_DCSURF_TILING_CONFIG 0x0957
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#define mmHUBP4_DCSURF_TILING_CONFIG_BASE_IDX 2
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#define mmHUBP4_DCSURF_PRI_VIEWPORT_START 0x0959
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#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION 0x095a
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#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C 0x095b
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#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x095c
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#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP4_DCSURF_SEC_VIEWPORT_START 0x095d
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#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION 0x095e
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#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C 0x095f
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#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0960
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#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG 0x0961
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#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
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#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C 0x0962
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#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
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#define mmHUBP4_DCHUBP_CNTL 0x0963
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#define mmHUBP4_DCHUBP_CNTL_BASE_IDX 2
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#define mmHUBP4_HUBP_CLK_CNTL 0x0964
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#define mmHUBP4_HUBP_CLK_CNTL_BASE_IDX 2
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#define mmHUBP4_DCHUBP_VMPG_CONFIG 0x0965
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#define mmHUBP4_DCHUBP_VMPG_CONFIG_BASE_IDX 2
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#define mmHUBP4_HUBPREQ_DEBUG_DB 0x0966
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#define mmHUBP4_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define mmHUBP4_HUBPREQ_DEBUG 0x0967
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#define mmHUBP4_HUBPREQ_DEBUG_BASE_IDX 2
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#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x096b
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#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
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#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x096c
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#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp4_dispdec_hubpreq_dispdec
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// base address: 0xdc0
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#define mmHUBPREQ4_DCSURF_SURFACE_PITCH 0x0977
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#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C 0x0978
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#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
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#define mmHUBPREQ4_VMID_SETTINGS_0 0x0979
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#define mmHUBPREQ4_VMID_SETTINGS_0_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS 0x097a
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#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x097b
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#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x097c
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#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x097d
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#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS 0x097e
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#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x097f
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#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0980
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#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0981
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#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0982
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#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0983
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#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0984
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#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0985
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#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0986
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#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0987
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#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0988
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#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0989
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#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SURFACE_CONTROL 0x098a
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#define mmHUBPREQ4_DCSURF_SURFACE_CONTROL_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_FLIP_CONTROL 0x098b
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#define mmHUBPREQ4_DCSURF_FLIP_CONTROL_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_FLIP_CONTROL2 0x098c
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#define mmHUBPREQ4_DCSURF_FLIP_CONTROL2_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT 0x0990
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#define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SURFACE_INUSE 0x0991
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#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH 0x0992
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#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C 0x0993
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#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C 0x0994
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#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE 0x0995
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#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0996
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#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0997
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#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0998
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#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ4_DCN_EXPANSION_MODE 0x0999
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#define mmHUBPREQ4_DCN_EXPANSION_MODE_BASE_IDX 2
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#define mmHUBPREQ4_DCN_TTU_QOS_WM 0x099a
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#define mmHUBPREQ4_DCN_TTU_QOS_WM_BASE_IDX 2
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#define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL 0x099b
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#define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
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#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0 0x099c
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#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1 0x099d
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#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0 0x099e
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#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1 0x099f
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#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0 0x09a0
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#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1 0x09a1
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#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0 0x09a2
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#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1 0x09a3
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#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ4_DCN_DMDATA_VM_CNTL 0x09a4
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#define mmHUBPREQ4_DCN_DMDATA_VM_CNTL_BASE_IDX 2
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#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x09a5
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#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
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#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x09a6
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#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
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#define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL 0x09b3
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#define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
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#define mmHUBPREQ4_BLANK_OFFSET_0 0x09b4
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#define mmHUBPREQ4_BLANK_OFFSET_0_BASE_IDX 2
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#define mmHUBPREQ4_BLANK_OFFSET_1 0x09b5
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#define mmHUBPREQ4_BLANK_OFFSET_1_BASE_IDX 2
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#define mmHUBPREQ4_DST_DIMENSIONS 0x09b6
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#define mmHUBPREQ4_DST_DIMENSIONS_BASE_IDX 2
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#define mmHUBPREQ4_DST_AFTER_SCALER 0x09b7
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#define mmHUBPREQ4_DST_AFTER_SCALER_BASE_IDX 2
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#define mmHUBPREQ4_PREFETCH_SETTINGS 0x09b8
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#define mmHUBPREQ4_PREFETCH_SETTINGS_BASE_IDX 2
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#define mmHUBPREQ4_PREFETCH_SETTINGS_C 0x09b9
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#define mmHUBPREQ4_PREFETCH_SETTINGS_C_BASE_IDX 2
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#define mmHUBPREQ4_VBLANK_PARAMETERS_0 0x09ba
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#define mmHUBPREQ4_VBLANK_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ4_VBLANK_PARAMETERS_1 0x09bb
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#define mmHUBPREQ4_VBLANK_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ4_VBLANK_PARAMETERS_2 0x09bc
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#define mmHUBPREQ4_VBLANK_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ4_VBLANK_PARAMETERS_3 0x09bd
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#define mmHUBPREQ4_VBLANK_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ4_VBLANK_PARAMETERS_4 0x09be
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#define mmHUBPREQ4_VBLANK_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ4_FLIP_PARAMETERS_0 0x09bf
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#define mmHUBPREQ4_FLIP_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ4_FLIP_PARAMETERS_1 0x09c0
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#define mmHUBPREQ4_FLIP_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ4_FLIP_PARAMETERS_2 0x09c1
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#define mmHUBPREQ4_FLIP_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ4_NOM_PARAMETERS_0 0x09c2
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#define mmHUBPREQ4_NOM_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ4_NOM_PARAMETERS_1 0x09c3
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#define mmHUBPREQ4_NOM_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ4_NOM_PARAMETERS_2 0x09c4
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#define mmHUBPREQ4_NOM_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ4_NOM_PARAMETERS_3 0x09c5
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#define mmHUBPREQ4_NOM_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ4_NOM_PARAMETERS_4 0x09c6
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#define mmHUBPREQ4_NOM_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ4_NOM_PARAMETERS_5 0x09c7
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#define mmHUBPREQ4_NOM_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ4_NOM_PARAMETERS_6 0x09c8
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#define mmHUBPREQ4_NOM_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ4_NOM_PARAMETERS_7 0x09c9
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#define mmHUBPREQ4_NOM_PARAMETERS_7_BASE_IDX 2
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#define mmHUBPREQ4_PER_LINE_DELIVERY_PRE 0x09ca
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#define mmHUBPREQ4_PER_LINE_DELIVERY_PRE_BASE_IDX 2
|
#define mmHUBPREQ4_PER_LINE_DELIVERY 0x09cb
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#define mmHUBPREQ4_PER_LINE_DELIVERY_BASE_IDX 2
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#define mmHUBPREQ4_CURSOR_SETTINGS 0x09cc
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#define mmHUBPREQ4_CURSOR_SETTINGS_BASE_IDX 2
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#define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ 0x09cd
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#define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
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#define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT 0x09ce
|
#define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
|
#define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL 0x09cf
|
#define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS 0x09d0
|
#define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_5 0x09d3
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ4_VBLANK_PARAMETERS_6 0x09d4
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_6_BASE_IDX 2
|
#define mmHUBPREQ4_FLIP_PARAMETERS_3 0x09d5
|
#define mmHUBPREQ4_FLIP_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ4_FLIP_PARAMETERS_4 0x09d6
|
#define mmHUBPREQ4_FLIP_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ4_FLIP_PARAMETERS_5 0x09d7
|
#define mmHUBPREQ4_FLIP_PARAMETERS_5_BASE_IDX 2
|
#define mmHUBPREQ4_FLIP_PARAMETERS_6 0x09d8
|
#define mmHUBPREQ4_FLIP_PARAMETERS_6_BASE_IDX 2
|
|
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// addressBlock: dce_dc_dcbubp4_dispdec_hubpret_dispdec
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// base address: 0xdc0
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#define mmHUBPRET4_HUBPRET_CONTROL 0x09dc
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#define mmHUBPRET4_HUBPRET_CONTROL_BASE_IDX 2
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#define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL 0x09dd
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#define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS 0x09de
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#define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0 0x09df
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#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
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#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1 0x09e0
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#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
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#define mmHUBPRET4_HUBPRET_READ_LINE0 0x09e1
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#define mmHUBPRET4_HUBPRET_READ_LINE0_BASE_IDX 2
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#define mmHUBPRET4_HUBPRET_READ_LINE1 0x09e2
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#define mmHUBPRET4_HUBPRET_READ_LINE1_BASE_IDX 2
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#define mmHUBPRET4_HUBPRET_INTERRUPT 0x09e3
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#define mmHUBPRET4_HUBPRET_INTERRUPT_BASE_IDX 2
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#define mmHUBPRET4_HUBPRET_READ_LINE_VALUE 0x09e4
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#define mmHUBPRET4_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
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#define mmHUBPRET4_HUBPRET_READ_LINE_STATUS 0x09e5
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#define mmHUBPRET4_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp4_dispdec_cursor0_dispdec
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// base address: 0xdc0
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#define mmCURSOR0_4_CURSOR_CONTROL 0x09e8
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#define mmCURSOR0_4_CURSOR_CONTROL_BASE_IDX 2
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#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS 0x09e9
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#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH 0x09ea
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#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_4_CURSOR_SIZE 0x09eb
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#define mmCURSOR0_4_CURSOR_SIZE_BASE_IDX 2
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#define mmCURSOR0_4_CURSOR_POSITION 0x09ec
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#define mmCURSOR0_4_CURSOR_POSITION_BASE_IDX 2
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#define mmCURSOR0_4_CURSOR_HOT_SPOT 0x09ed
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#define mmCURSOR0_4_CURSOR_HOT_SPOT_BASE_IDX 2
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#define mmCURSOR0_4_CURSOR_STEREO_CONTROL 0x09ee
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#define mmCURSOR0_4_CURSOR_STEREO_CONTROL_BASE_IDX 2
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#define mmCURSOR0_4_CURSOR_DST_OFFSET 0x09ef
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#define mmCURSOR0_4_CURSOR_DST_OFFSET_BASE_IDX 2
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#define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL 0x09f0
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#define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS 0x09f1
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#define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCURSOR0_4_DMDATA_ADDRESS_HIGH 0x09f2
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#define mmCURSOR0_4_DMDATA_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_4_DMDATA_ADDRESS_LOW 0x09f3
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#define mmCURSOR0_4_DMDATA_ADDRESS_LOW_BASE_IDX 2
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#define mmCURSOR0_4_DMDATA_CNTL 0x09f4
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#define mmCURSOR0_4_DMDATA_CNTL_BASE_IDX 2
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#define mmCURSOR0_4_DMDATA_QOS_CNTL 0x09f5
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#define mmCURSOR0_4_DMDATA_QOS_CNTL_BASE_IDX 2
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#define mmCURSOR0_4_DMDATA_STATUS 0x09f6
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#define mmCURSOR0_4_DMDATA_STATUS_BASE_IDX 2
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#define mmCURSOR0_4_DMDATA_SW_CNTL 0x09f7
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#define mmCURSOR0_4_DMDATA_SW_CNTL_BASE_IDX 2
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#define mmCURSOR0_4_DMDATA_SW_DATA 0x09f8
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#define mmCURSOR0_4_DMDATA_SW_DATA_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp4_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x2834
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#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0a0d
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#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x0a0e
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#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x0a0f
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#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_CNTL 0x0a10
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#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_CNTL2 0x0a11
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#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0a12
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#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x0a13
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#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_HI 0x0a14
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#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_LOW 0x0a15
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#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp5_dispdec_hubp_dispdec
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// base address: 0x1130
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#define mmHUBP5_DCSURF_SURFACE_CONFIG 0x0a31
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#define mmHUBP5_DCSURF_SURFACE_CONFIG_BASE_IDX 2
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#define mmHUBP5_DCSURF_ADDR_CONFIG 0x0a32
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#define mmHUBP5_DCSURF_ADDR_CONFIG_BASE_IDX 2
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#define mmHUBP5_DCSURF_TILING_CONFIG 0x0a33
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#define mmHUBP5_DCSURF_TILING_CONFIG_BASE_IDX 2
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#define mmHUBP5_DCSURF_PRI_VIEWPORT_START 0x0a35
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#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION 0x0a36
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#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C 0x0a37
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#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0a38
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#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP5_DCSURF_SEC_VIEWPORT_START 0x0a39
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#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION 0x0a3a
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#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C 0x0a3b
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#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0a3c
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#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG 0x0a3d
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#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
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#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C 0x0a3e
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#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
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#define mmHUBP5_DCHUBP_CNTL 0x0a3f
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#define mmHUBP5_DCHUBP_CNTL_BASE_IDX 2
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#define mmHUBP5_HUBP_CLK_CNTL 0x0a40
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#define mmHUBP5_HUBP_CLK_CNTL_BASE_IDX 2
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#define mmHUBP5_DCHUBP_VMPG_CONFIG 0x0a41
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#define mmHUBP5_DCHUBP_VMPG_CONFIG_BASE_IDX 2
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#define mmHUBP5_HUBPREQ_DEBUG_DB 0x0a42
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#define mmHUBP5_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define mmHUBP5_HUBPREQ_DEBUG 0x0a43
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#define mmHUBP5_HUBPREQ_DEBUG_BASE_IDX 2
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#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0a47
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#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
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#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0a48
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#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp5_dispdec_hubpreq_dispdec
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// base address: 0x1130
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#define mmHUBPREQ5_DCSURF_SURFACE_PITCH 0x0a53
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#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C 0x0a54
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#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
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#define mmHUBPREQ5_VMID_SETTINGS_0 0x0a55
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#define mmHUBPREQ5_VMID_SETTINGS_0_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0a56
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#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0a57
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#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0a58
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#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0a59
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#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0a5a
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#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0a5b
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#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0a5c
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#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0a5d
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#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0a5e
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#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0a5f
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#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0a60
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#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0a61
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#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0a62
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#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0a63
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#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0a64
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#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0a65
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#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SURFACE_CONTROL 0x0a66
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#define mmHUBPREQ5_DCSURF_SURFACE_CONTROL_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_FLIP_CONTROL 0x0a67
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#define mmHUBPREQ5_DCSURF_FLIP_CONTROL_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_FLIP_CONTROL2 0x0a68
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#define mmHUBPREQ5_DCSURF_FLIP_CONTROL2_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT 0x0a6c
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#define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SURFACE_INUSE 0x0a6d
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#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH 0x0a6e
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#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C 0x0a6f
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#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C 0x0a70
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#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE 0x0a71
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#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0a72
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#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0a73
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#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0a74
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#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ5_DCN_EXPANSION_MODE 0x0a75
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#define mmHUBPREQ5_DCN_EXPANSION_MODE_BASE_IDX 2
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#define mmHUBPREQ5_DCN_TTU_QOS_WM 0x0a76
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#define mmHUBPREQ5_DCN_TTU_QOS_WM_BASE_IDX 2
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#define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL 0x0a77
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#define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
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#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0 0x0a78
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#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1 0x0a79
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#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0 0x0a7a
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#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1 0x0a7b
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#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0 0x0a7c
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#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1 0x0a7d
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#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0 0x0a7e
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#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1 0x0a7f
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#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ5_DCN_DMDATA_VM_CNTL 0x0a80
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#define mmHUBPREQ5_DCN_DMDATA_VM_CNTL_BASE_IDX 2
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#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0a81
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#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
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#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0a82
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#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
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#define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL 0x0a8f
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#define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
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#define mmHUBPREQ5_BLANK_OFFSET_0 0x0a90
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#define mmHUBPREQ5_BLANK_OFFSET_0_BASE_IDX 2
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#define mmHUBPREQ5_BLANK_OFFSET_1 0x0a91
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#define mmHUBPREQ5_BLANK_OFFSET_1_BASE_IDX 2
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#define mmHUBPREQ5_DST_DIMENSIONS 0x0a92
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#define mmHUBPREQ5_DST_DIMENSIONS_BASE_IDX 2
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#define mmHUBPREQ5_DST_AFTER_SCALER 0x0a93
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#define mmHUBPREQ5_DST_AFTER_SCALER_BASE_IDX 2
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#define mmHUBPREQ5_PREFETCH_SETTINGS 0x0a94
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#define mmHUBPREQ5_PREFETCH_SETTINGS_BASE_IDX 2
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#define mmHUBPREQ5_PREFETCH_SETTINGS_C 0x0a95
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#define mmHUBPREQ5_PREFETCH_SETTINGS_C_BASE_IDX 2
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#define mmHUBPREQ5_VBLANK_PARAMETERS_0 0x0a96
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#define mmHUBPREQ5_VBLANK_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ5_VBLANK_PARAMETERS_1 0x0a97
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#define mmHUBPREQ5_VBLANK_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ5_VBLANK_PARAMETERS_2 0x0a98
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#define mmHUBPREQ5_VBLANK_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ5_VBLANK_PARAMETERS_3 0x0a99
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#define mmHUBPREQ5_VBLANK_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ5_VBLANK_PARAMETERS_4 0x0a9a
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#define mmHUBPREQ5_VBLANK_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ5_FLIP_PARAMETERS_0 0x0a9b
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#define mmHUBPREQ5_FLIP_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ5_FLIP_PARAMETERS_1 0x0a9c
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#define mmHUBPREQ5_FLIP_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ5_FLIP_PARAMETERS_2 0x0a9d
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#define mmHUBPREQ5_FLIP_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ5_NOM_PARAMETERS_0 0x0a9e
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#define mmHUBPREQ5_NOM_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ5_NOM_PARAMETERS_1 0x0a9f
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#define mmHUBPREQ5_NOM_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ5_NOM_PARAMETERS_2 0x0aa0
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#define mmHUBPREQ5_NOM_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ5_NOM_PARAMETERS_3 0x0aa1
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#define mmHUBPREQ5_NOM_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ5_NOM_PARAMETERS_4 0x0aa2
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#define mmHUBPREQ5_NOM_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ5_NOM_PARAMETERS_5 0x0aa3
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#define mmHUBPREQ5_NOM_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ5_NOM_PARAMETERS_6 0x0aa4
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#define mmHUBPREQ5_NOM_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ5_NOM_PARAMETERS_7 0x0aa5
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#define mmHUBPREQ5_NOM_PARAMETERS_7_BASE_IDX 2
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#define mmHUBPREQ5_PER_LINE_DELIVERY_PRE 0x0aa6
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#define mmHUBPREQ5_PER_LINE_DELIVERY_PRE_BASE_IDX 2
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#define mmHUBPREQ5_PER_LINE_DELIVERY 0x0aa7
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#define mmHUBPREQ5_PER_LINE_DELIVERY_BASE_IDX 2
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#define mmHUBPREQ5_CURSOR_SETTINGS 0x0aa8
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#define mmHUBPREQ5_CURSOR_SETTINGS_BASE_IDX 2
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#define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ 0x0aa9
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#define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
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#define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT 0x0aaa
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#define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
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#define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL 0x0aab
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#define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS 0x0aac
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#define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPREQ5_VBLANK_PARAMETERS_5 0x0aaf
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#define mmHUBPREQ5_VBLANK_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ5_VBLANK_PARAMETERS_6 0x0ab0
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#define mmHUBPREQ5_VBLANK_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ5_FLIP_PARAMETERS_3 0x0ab1
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#define mmHUBPREQ5_FLIP_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ5_FLIP_PARAMETERS_4 0x0ab2
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#define mmHUBPREQ5_FLIP_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ5_FLIP_PARAMETERS_5 0x0ab3
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#define mmHUBPREQ5_FLIP_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ5_FLIP_PARAMETERS_6 0x0ab4
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#define mmHUBPREQ5_FLIP_PARAMETERS_6_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp5_dispdec_hubpret_dispdec
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// base address: 0x1130
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#define mmHUBPRET5_HUBPRET_CONTROL 0x0ab8
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#define mmHUBPRET5_HUBPRET_CONTROL_BASE_IDX 2
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#define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL 0x0ab9
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#define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS 0x0aba
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#define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0 0x0abb
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#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
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#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1 0x0abc
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#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
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#define mmHUBPRET5_HUBPRET_READ_LINE0 0x0abd
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#define mmHUBPRET5_HUBPRET_READ_LINE0_BASE_IDX 2
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#define mmHUBPRET5_HUBPRET_READ_LINE1 0x0abe
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#define mmHUBPRET5_HUBPRET_READ_LINE1_BASE_IDX 2
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#define mmHUBPRET5_HUBPRET_INTERRUPT 0x0abf
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#define mmHUBPRET5_HUBPRET_INTERRUPT_BASE_IDX 2
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#define mmHUBPRET5_HUBPRET_READ_LINE_VALUE 0x0ac0
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#define mmHUBPRET5_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
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#define mmHUBPRET5_HUBPRET_READ_LINE_STATUS 0x0ac1
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#define mmHUBPRET5_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp5_dispdec_cursor0_dispdec
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// base address: 0x1130
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#define mmCURSOR0_5_CURSOR_CONTROL 0x0ac4
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#define mmCURSOR0_5_CURSOR_CONTROL_BASE_IDX 2
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#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS 0x0ac5
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#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH 0x0ac6
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#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_5_CURSOR_SIZE 0x0ac7
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#define mmCURSOR0_5_CURSOR_SIZE_BASE_IDX 2
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#define mmCURSOR0_5_CURSOR_POSITION 0x0ac8
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#define mmCURSOR0_5_CURSOR_POSITION_BASE_IDX 2
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#define mmCURSOR0_5_CURSOR_HOT_SPOT 0x0ac9
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#define mmCURSOR0_5_CURSOR_HOT_SPOT_BASE_IDX 2
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#define mmCURSOR0_5_CURSOR_STEREO_CONTROL 0x0aca
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#define mmCURSOR0_5_CURSOR_STEREO_CONTROL_BASE_IDX 2
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#define mmCURSOR0_5_CURSOR_DST_OFFSET 0x0acb
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#define mmCURSOR0_5_CURSOR_DST_OFFSET_BASE_IDX 2
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#define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL 0x0acc
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#define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS 0x0acd
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#define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCURSOR0_5_DMDATA_ADDRESS_HIGH 0x0ace
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#define mmCURSOR0_5_DMDATA_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_5_DMDATA_ADDRESS_LOW 0x0acf
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#define mmCURSOR0_5_DMDATA_ADDRESS_LOW_BASE_IDX 2
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#define mmCURSOR0_5_DMDATA_CNTL 0x0ad0
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#define mmCURSOR0_5_DMDATA_CNTL_BASE_IDX 2
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#define mmCURSOR0_5_DMDATA_QOS_CNTL 0x0ad1
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#define mmCURSOR0_5_DMDATA_QOS_CNTL_BASE_IDX 2
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#define mmCURSOR0_5_DMDATA_STATUS 0x0ad2
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#define mmCURSOR0_5_DMDATA_STATUS_BASE_IDX 2
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#define mmCURSOR0_5_DMDATA_SW_CNTL 0x0ad3
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#define mmCURSOR0_5_DMDATA_SW_CNTL_BASE_IDX 2
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#define mmCURSOR0_5_DMDATA_SW_DATA 0x0ad4
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#define mmCURSOR0_5_DMDATA_SW_DATA_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp5_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x2ba4
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#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x0ae9
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#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x0aea
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#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x0aeb
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#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_CNTL 0x0aec
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#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_CNTL2 0x0aed
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#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0aee
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#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0aef
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#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_HI 0x0af0
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#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_LOW 0x0af1
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#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
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// base address: 0x0
|
#define mmDPP_TOP0_DPP_CONTROL 0x0cc5
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#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2
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#define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6
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#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2
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#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7
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#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2
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#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8
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#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2
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#define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9
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#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2
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#define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca
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#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
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// base address: 0x0
|
#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf
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#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
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#define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0
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#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1
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#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2
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#define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2
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#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2
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#define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3
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#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2
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#define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4
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#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2
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#define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5
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#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2
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#define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6
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#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2
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#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7
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#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8
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#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2
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#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9
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#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2
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#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda
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#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2
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#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb
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#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2
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#define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd
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#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_DEALPHA 0x0cde
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#define mmCNVC_CFG0_PRE_DEALPHA_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_MODE 0x0cdf
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#define mmCNVC_CFG0_PRE_CSC_MODE_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_C11_C12 0x0ce0
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#define mmCNVC_CFG0_PRE_CSC_C11_C12_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_C13_C14 0x0ce1
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#define mmCNVC_CFG0_PRE_CSC_C13_C14_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_C21_C22 0x0ce2
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#define mmCNVC_CFG0_PRE_CSC_C21_C22_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_C23_C24 0x0ce3
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#define mmCNVC_CFG0_PRE_CSC_C23_C24_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_C31_C32 0x0ce4
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#define mmCNVC_CFG0_PRE_CSC_C31_C32_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_C33_C34 0x0ce5
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#define mmCNVC_CFG0_PRE_CSC_C33_C34_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_B_C11_C12 0x0ce6
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#define mmCNVC_CFG0_PRE_CSC_B_C11_C12_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_B_C13_C14 0x0ce7
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#define mmCNVC_CFG0_PRE_CSC_B_C13_C14_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_B_C21_C22 0x0ce8
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#define mmCNVC_CFG0_PRE_CSC_B_C21_C22_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_B_C23_C24 0x0ce9
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#define mmCNVC_CFG0_PRE_CSC_B_C23_C24_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_B_C31_C32 0x0cea
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#define mmCNVC_CFG0_PRE_CSC_B_C31_C32_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_CSC_B_C33_C34 0x0ceb
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#define mmCNVC_CFG0_PRE_CSC_B_C33_C34_BASE_IDX 2
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#define mmCNVC_CFG0_CNVC_COEF_FORMAT 0x0cec
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#define mmCNVC_CFG0_CNVC_COEF_FORMAT_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_DEGAM 0x0ced
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#define mmCNVC_CFG0_PRE_DEGAM_BASE_IDX 2
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#define mmCNVC_CFG0_PRE_REALPHA 0x0cee
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#define mmCNVC_CFG0_PRE_REALPHA_BASE_IDX 2
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// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
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// base address: 0x0
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#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0cf1
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#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2
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#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0cf2
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#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2
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#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0cf3
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#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2
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#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0cf4
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#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
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// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
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// base address: 0x0
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#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cf9
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#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
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#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0cfa
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#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmDSCL0_SCL_MODE 0x0cfb
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#define mmDSCL0_SCL_MODE_BASE_IDX 2
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#define mmDSCL0_SCL_TAP_CONTROL 0x0cfc
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#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmDSCL0_DSCL_CONTROL 0x0cfd
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#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2
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#define mmDSCL0_DSCL_2TAP_CONTROL 0x0cfe
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#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2
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#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cff
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#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0d00
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#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0d01
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#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d02
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#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0d03
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#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0d04
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#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0d05
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#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0d06
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#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d07
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#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0d08
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#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0d09
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#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
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#define mmDSCL0_SCL_BLACK_COLOR 0x0d0a
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#define mmDSCL0_SCL_BLACK_COLOR_BASE_IDX 2
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#define mmDSCL0_DSCL_UPDATE 0x0d0b
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#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2
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#define mmDSCL0_DSCL_AUTOCAL 0x0d0c
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#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2
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#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d0d
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#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d0e
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#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmDSCL0_OTG_H_BLANK 0x0d0f
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#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2
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#define mmDSCL0_OTG_V_BLANK 0x0d10
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#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2
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#define mmDSCL0_RECOUT_START 0x0d11
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#define mmDSCL0_RECOUT_START_BASE_IDX 2
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#define mmDSCL0_RECOUT_SIZE 0x0d12
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#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2
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#define mmDSCL0_MPC_SIZE 0x0d13
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#define mmDSCL0_MPC_SIZE_BASE_IDX 2
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#define mmDSCL0_LB_DATA_FORMAT 0x0d14
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#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2
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#define mmDSCL0_LB_MEMORY_CTRL 0x0d15
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#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2
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#define mmDSCL0_LB_V_COUNTER 0x0d16
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#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2
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#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d17
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#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d18
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#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDSCL0_OBUF_CONTROL 0x0d19
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#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2
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#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d1a
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#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2
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// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
|
// base address: 0x0
|
#define mmCM0_CM_CONTROL 0x0d20
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#define mmCM0_CM_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_POST_CSC_CONTROL 0x0d21
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#define mmCM0_CM_POST_CSC_CONTROL_BASE_IDX 2
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#define mmCM0_CM_POST_CSC_C11_C12 0x0d22
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#define mmCM0_CM_POST_CSC_C11_C12_BASE_IDX 2
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#define mmCM0_CM_POST_CSC_C13_C14 0x0d23
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#define mmCM0_CM_POST_CSC_C13_C14_BASE_IDX 2
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#define mmCM0_CM_POST_CSC_C21_C22 0x0d24
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#define mmCM0_CM_POST_CSC_C21_C22_BASE_IDX 2
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#define mmCM0_CM_POST_CSC_C23_C24 0x0d25
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#define mmCM0_CM_POST_CSC_C23_C24_BASE_IDX 2
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#define mmCM0_CM_POST_CSC_C31_C32 0x0d26
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#define mmCM0_CM_POST_CSC_C31_C32_BASE_IDX 2
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#define mmCM0_CM_POST_CSC_C33_C34 0x0d27
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#define mmCM0_CM_POST_CSC_C33_C34_BASE_IDX 2
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#define mmCM0_CM_POST_CSC_B_C11_C12 0x0d28
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#define mmCM0_CM_POST_CSC_B_C11_C12_BASE_IDX 2
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#define mmCM0_CM_POST_CSC_B_C13_C14 0x0d29
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#define mmCM0_CM_POST_CSC_B_C13_C14_BASE_IDX 2
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#define mmCM0_CM_POST_CSC_B_C21_C22 0x0d2a
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#define mmCM0_CM_POST_CSC_B_C21_C22_BASE_IDX 2
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#define mmCM0_CM_POST_CSC_B_C23_C24 0x0d2b
|
#define mmCM0_CM_POST_CSC_B_C23_C24_BASE_IDX 2
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#define mmCM0_CM_POST_CSC_B_C31_C32 0x0d2c
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#define mmCM0_CM_POST_CSC_B_C31_C32_BASE_IDX 2
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#define mmCM0_CM_POST_CSC_B_C33_C34 0x0d2d
|
#define mmCM0_CM_POST_CSC_B_C33_C34_BASE_IDX 2
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#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d2e
|
#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d2f
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#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d30
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#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d31
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#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d32
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#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d33
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#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d34
|
#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d35
|
#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
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#define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d36
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#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d37
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#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d38
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#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d39
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#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
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#define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d3a
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#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
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#define mmCM0_CM_BIAS_CR_R 0x0d3b
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#define mmCM0_CM_BIAS_CR_R_BASE_IDX 2
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#define mmCM0_CM_BIAS_Y_G_CB_B 0x0d3c
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#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_CONTROL 0x0d3d
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#define mmCM0_CM_GAMCOR_CONTROL_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_LUT_INDEX 0x0d3e
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#define mmCM0_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_LUT_DATA 0x0d3f
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#define mmCM0_CM_GAMCOR_LUT_DATA_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_LUT_CONTROL 0x0d40
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#define mmCM0_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B 0x0d41
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#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G 0x0d42
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#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R 0x0d43
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#define mmCM0_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0d44
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#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0d45
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#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0d46
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#define mmCM0_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0d47
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#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0d48
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#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0d49
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#define mmCM0_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B 0x0d4a
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#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B 0x0d4b
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#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G 0x0d4c
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#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G 0x0d4d
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#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R 0x0d4e
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#define mmCM0_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R 0x0d4f
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#define mmCM0_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B 0x0d50
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#define mmCM0_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G 0x0d51
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#define mmCM0_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R 0x0d52
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#define mmCM0_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1 0x0d53
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#define mmCM0_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3 0x0d54
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#define mmCM0_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5 0x0d55
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#define mmCM0_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7 0x0d56
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#define mmCM0_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9 0x0d57
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#define mmCM0_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11 0x0d58
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#define mmCM0_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13 0x0d59
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#define mmCM0_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15 0x0d5a
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#define mmCM0_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17 0x0d5b
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#define mmCM0_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19 0x0d5c
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#define mmCM0_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21 0x0d5d
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#define mmCM0_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23 0x0d5e
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#define mmCM0_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25 0x0d5f
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#define mmCM0_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27 0x0d60
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#define mmCM0_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29 0x0d61
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#define mmCM0_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31 0x0d62
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#define mmCM0_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33 0x0d63
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#define mmCM0_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B 0x0d64
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#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G 0x0d65
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#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R 0x0d66
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#define mmCM0_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0d67
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#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0d68
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#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0d69
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#define mmCM0_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0d6a
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#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0d6b
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#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0d6c
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#define mmCM0_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B 0x0d6d
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#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B 0x0d6e
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#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G 0x0d6f
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#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G 0x0d70
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#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R 0x0d71
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#define mmCM0_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R 0x0d72
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#define mmCM0_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B 0x0d73
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#define mmCM0_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G 0x0d74
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#define mmCM0_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R 0x0d75
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#define mmCM0_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1 0x0d76
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#define mmCM0_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3 0x0d77
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#define mmCM0_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5 0x0d78
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#define mmCM0_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7 0x0d79
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#define mmCM0_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9 0x0d7a
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#define mmCM0_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11 0x0d7b
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#define mmCM0_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13 0x0d7c
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#define mmCM0_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15 0x0d7d
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#define mmCM0_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17 0x0d7e
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#define mmCM0_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19 0x0d7f
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#define mmCM0_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21 0x0d80
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#define mmCM0_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23 0x0d81
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#define mmCM0_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25 0x0d82
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#define mmCM0_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27 0x0d83
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#define mmCM0_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29 0x0d84
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#define mmCM0_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31 0x0d85
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#define mmCM0_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33 0x0d86
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#define mmCM0_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_CONTROL 0x0d87
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#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d88
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#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d89
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#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_LUT_CONTROL 0x0d8a
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#define mmCM0_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d8b
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#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d8c
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#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d8d
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#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0d8e
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#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0d8f
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#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0d90
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#define mmCM0_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0d91
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#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0d92
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#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0d93
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#define mmCM0_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d94
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#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d95
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#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d96
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#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d97
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#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d98
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#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d99
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#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B 0x0d9a
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#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G 0x0d9b
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#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R 0x0d9c
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#define mmCM0_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d9d
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d9e
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d9f
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0da0
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0da1
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0da2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0da3
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0da4
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0da5
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0da6
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0da7
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0da8
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0da9
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0daa
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0dab
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0dac
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0dad
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#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0dae
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#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0daf
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#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0db0
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#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0db1
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#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0db2
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#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0db3
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#define mmCM0_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0db4
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#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0db5
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#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0db6
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#define mmCM0_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0db7
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#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0db8
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#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0db9
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#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0dba
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#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0dbb
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#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0dbc
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#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B 0x0dbd
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#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G 0x0dbe
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#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R 0x0dbf
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#define mmCM0_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0dc0
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0dc1
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0dc2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0dc3
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0dc4
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0dc5
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0dc6
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0dc7
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0dc8
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0dc9
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0dca
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0dcb
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0dcc
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0dcd
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0dce
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0dcf
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0dd0
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#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM0_CM_HDR_MULT_COEF 0x0dd1
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#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2
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#define mmCM0_CM_MEM_PWR_CTRL 0x0dd2
|
#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCM0_CM_MEM_PWR_STATUS 0x0dd3
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#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCM0_CM_DEALPHA 0x0dd5
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#define mmCM0_CM_DEALPHA_BASE_IDX 2
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#define mmCM0_CM_COEF_FORMAT 0x0dd6
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#define mmCM0_CM_COEF_FORMAT_BASE_IDX 2
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#define mmCM0_CM_SHAPER_CONTROL 0x0dd7
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#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_OFFSET_R 0x0dd8
|
#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2
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#define mmCM0_CM_SHAPER_OFFSET_G 0x0dd9
|
#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2
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#define mmCM0_CM_SHAPER_OFFSET_B 0x0dda
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#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2
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#define mmCM0_CM_SHAPER_SCALE_R 0x0ddb
|
#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2
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#define mmCM0_CM_SHAPER_SCALE_G_B 0x0ddc
|
#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2
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#define mmCM0_CM_SHAPER_LUT_INDEX 0x0ddd
|
#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_LUT_DATA 0x0dde
|
#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0ddf
|
#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0de0
|
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0de1
|
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0de2
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#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0de3
|
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0de4
|
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0de5
|
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0de6
|
#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0de7
|
#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0de8
|
#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0de9
|
#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dea
|
#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0deb
|
#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dec
|
#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0ded
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#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dee
|
#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0def
|
#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0df0
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#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0df1
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#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0df2
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#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0df3
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#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0df4
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#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0df5
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#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0df6
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#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0df7
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#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0df8
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#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0df9
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#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dfa
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#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dfb
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#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dfc
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#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dfd
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#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dfe
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#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dff
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#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0e00
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#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0e01
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#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0e02
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#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0e03
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#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0e04
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#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0e05
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#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0e06
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#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0e07
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#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0e08
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#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0e09
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#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0e0a
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#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0e0b
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#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0e0c
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#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0e0d
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#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM0_CM_MEM_PWR_CTRL2 0x0e0e
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#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmCM0_CM_MEM_PWR_STATUS2 0x0e0f
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#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2
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#define mmCM0_CM_3DLUT_MODE 0x0e10
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#define mmCM0_CM_3DLUT_MODE_BASE_IDX 2
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#define mmCM0_CM_3DLUT_INDEX 0x0e11
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#define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2
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#define mmCM0_CM_3DLUT_DATA 0x0e12
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#define mmCM0_CM_3DLUT_DATA_BASE_IDX 2
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#define mmCM0_CM_3DLUT_DATA_30BIT 0x0e13
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#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2
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#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0e14
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#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
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#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0e15
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#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
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#define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0e16
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#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
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#define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0e17
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#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
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#define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0e18
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#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
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// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x3890
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#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0e24
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#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0e25
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#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0e26
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#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON12_PERFMON_CNTL 0x0e27
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#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON12_PERFMON_CNTL2 0x0e28
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#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0e29
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#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0e2a
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#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON12_PERFMON_HI 0x0e2b
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#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON12_PERFMON_LOW 0x0e2c
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#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
|
// base address: 0x5ac
|
#define mmDPP_TOP1_DPP_CONTROL 0x0e30
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#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2
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#define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31
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#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2
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#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32
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#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2
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#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33
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#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2
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#define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34
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#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2
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#define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35
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#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
|
// base address: 0x5ac
|
#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a
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#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
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#define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b
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#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c
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#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2
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#define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d
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#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2
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#define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e
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#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2
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#define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f
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#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2
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#define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40
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#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2
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#define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41
|
#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2
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#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42
|
#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43
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#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2
|
#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44
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#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2
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#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45
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#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2
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#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46
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#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2
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#define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48
|
#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2
|
#define mmCNVC_CFG1_PRE_DEALPHA 0x0e49
|
#define mmCNVC_CFG1_PRE_DEALPHA_BASE_IDX 2
|
#define mmCNVC_CFG1_PRE_CSC_MODE 0x0e4a
|
#define mmCNVC_CFG1_PRE_CSC_MODE_BASE_IDX 2
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#define mmCNVC_CFG1_PRE_CSC_C11_C12 0x0e4b
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#define mmCNVC_CFG1_PRE_CSC_C11_C12_BASE_IDX 2
|
#define mmCNVC_CFG1_PRE_CSC_C13_C14 0x0e4c
|
#define mmCNVC_CFG1_PRE_CSC_C13_C14_BASE_IDX 2
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#define mmCNVC_CFG1_PRE_CSC_C21_C22 0x0e4d
|
#define mmCNVC_CFG1_PRE_CSC_C21_C22_BASE_IDX 2
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#define mmCNVC_CFG1_PRE_CSC_C23_C24 0x0e4e
|
#define mmCNVC_CFG1_PRE_CSC_C23_C24_BASE_IDX 2
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#define mmCNVC_CFG1_PRE_CSC_C31_C32 0x0e4f
|
#define mmCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX 2
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#define mmCNVC_CFG1_PRE_CSC_C33_C34 0x0e50
|
#define mmCNVC_CFG1_PRE_CSC_C33_C34_BASE_IDX 2
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#define mmCNVC_CFG1_PRE_CSC_B_C11_C12 0x0e51
|
#define mmCNVC_CFG1_PRE_CSC_B_C11_C12_BASE_IDX 2
|
#define mmCNVC_CFG1_PRE_CSC_B_C13_C14 0x0e52
|
#define mmCNVC_CFG1_PRE_CSC_B_C13_C14_BASE_IDX 2
|
#define mmCNVC_CFG1_PRE_CSC_B_C21_C22 0x0e53
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#define mmCNVC_CFG1_PRE_CSC_B_C21_C22_BASE_IDX 2
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#define mmCNVC_CFG1_PRE_CSC_B_C23_C24 0x0e54
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#define mmCNVC_CFG1_PRE_CSC_B_C23_C24_BASE_IDX 2
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#define mmCNVC_CFG1_PRE_CSC_B_C31_C32 0x0e55
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#define mmCNVC_CFG1_PRE_CSC_B_C31_C32_BASE_IDX 2
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#define mmCNVC_CFG1_PRE_CSC_B_C33_C34 0x0e56
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#define mmCNVC_CFG1_PRE_CSC_B_C33_C34_BASE_IDX 2
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#define mmCNVC_CFG1_CNVC_COEF_FORMAT 0x0e57
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#define mmCNVC_CFG1_CNVC_COEF_FORMAT_BASE_IDX 2
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#define mmCNVC_CFG1_PRE_DEGAM 0x0e58
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#define mmCNVC_CFG1_PRE_DEGAM_BASE_IDX 2
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#define mmCNVC_CFG1_PRE_REALPHA 0x0e59
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#define mmCNVC_CFG1_PRE_REALPHA_BASE_IDX 2
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// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
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// base address: 0x5ac
|
#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e5c
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#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2
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#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e5d
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#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2
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#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e5e
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#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2
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#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e5f
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#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
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// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
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// base address: 0x5ac
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#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e64
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#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
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#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e65
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#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmDSCL1_SCL_MODE 0x0e66
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#define mmDSCL1_SCL_MODE_BASE_IDX 2
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#define mmDSCL1_SCL_TAP_CONTROL 0x0e67
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#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmDSCL1_DSCL_CONTROL 0x0e68
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#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2
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#define mmDSCL1_DSCL_2TAP_CONTROL 0x0e69
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#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2
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#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e6a
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#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e6b
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#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e6c
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#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e6d
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#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e6e
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#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e6f
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#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e70
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#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e71
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#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e72
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#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e73
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#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e74
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#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
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#define mmDSCL1_SCL_BLACK_COLOR 0x0e75
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#define mmDSCL1_SCL_BLACK_COLOR_BASE_IDX 2
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#define mmDSCL1_DSCL_UPDATE 0x0e76
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#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2
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#define mmDSCL1_DSCL_AUTOCAL 0x0e77
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#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2
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#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e78
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#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e79
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#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmDSCL1_OTG_H_BLANK 0x0e7a
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#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2
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#define mmDSCL1_OTG_V_BLANK 0x0e7b
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#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2
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#define mmDSCL1_RECOUT_START 0x0e7c
|
#define mmDSCL1_RECOUT_START_BASE_IDX 2
|
#define mmDSCL1_RECOUT_SIZE 0x0e7d
|
#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2
|
#define mmDSCL1_MPC_SIZE 0x0e7e
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#define mmDSCL1_MPC_SIZE_BASE_IDX 2
|
#define mmDSCL1_LB_DATA_FORMAT 0x0e7f
|
#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2
|
#define mmDSCL1_LB_MEMORY_CTRL 0x0e80
|
#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2
|
#define mmDSCL1_LB_V_COUNTER 0x0e81
|
#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2
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#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e82
|
#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e83
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#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDSCL1_OBUF_CONTROL 0x0e84
|
#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2
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#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e85
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#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2
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// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
|
// base address: 0x5ac
|
#define mmCM1_CM_CONTROL 0x0e8b
|
#define mmCM1_CM_CONTROL_BASE_IDX 2
|
#define mmCM1_CM_POST_CSC_CONTROL 0x0e8c
|
#define mmCM1_CM_POST_CSC_CONTROL_BASE_IDX 2
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#define mmCM1_CM_POST_CSC_C11_C12 0x0e8d
|
#define mmCM1_CM_POST_CSC_C11_C12_BASE_IDX 2
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#define mmCM1_CM_POST_CSC_C13_C14 0x0e8e
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#define mmCM1_CM_POST_CSC_C13_C14_BASE_IDX 2
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#define mmCM1_CM_POST_CSC_C21_C22 0x0e8f
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#define mmCM1_CM_POST_CSC_C21_C22_BASE_IDX 2
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#define mmCM1_CM_POST_CSC_C23_C24 0x0e90
|
#define mmCM1_CM_POST_CSC_C23_C24_BASE_IDX 2
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#define mmCM1_CM_POST_CSC_C31_C32 0x0e91
|
#define mmCM1_CM_POST_CSC_C31_C32_BASE_IDX 2
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#define mmCM1_CM_POST_CSC_C33_C34 0x0e92
|
#define mmCM1_CM_POST_CSC_C33_C34_BASE_IDX 2
|
#define mmCM1_CM_POST_CSC_B_C11_C12 0x0e93
|
#define mmCM1_CM_POST_CSC_B_C11_C12_BASE_IDX 2
|
#define mmCM1_CM_POST_CSC_B_C13_C14 0x0e94
|
#define mmCM1_CM_POST_CSC_B_C13_C14_BASE_IDX 2
|
#define mmCM1_CM_POST_CSC_B_C21_C22 0x0e95
|
#define mmCM1_CM_POST_CSC_B_C21_C22_BASE_IDX 2
|
#define mmCM1_CM_POST_CSC_B_C23_C24 0x0e96
|
#define mmCM1_CM_POST_CSC_B_C23_C24_BASE_IDX 2
|
#define mmCM1_CM_POST_CSC_B_C31_C32 0x0e97
|
#define mmCM1_CM_POST_CSC_B_C31_C32_BASE_IDX 2
|
#define mmCM1_CM_POST_CSC_B_C33_C34 0x0e98
|
#define mmCM1_CM_POST_CSC_B_C33_C34_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e99
|
#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e9a
|
#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e9b
|
#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e9c
|
#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e9d
|
#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e9e
|
#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e9f
|
#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0ea0
|
#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0ea1
|
#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0ea2
|
#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0ea3
|
#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0ea4
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#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
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#define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0ea5
|
#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
|
#define mmCM1_CM_BIAS_CR_R 0x0ea6
|
#define mmCM1_CM_BIAS_CR_R_BASE_IDX 2
|
#define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea7
|
#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_CONTROL 0x0ea8
|
#define mmCM1_CM_GAMCOR_CONTROL_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_LUT_INDEX 0x0ea9
|
#define mmCM1_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_LUT_DATA 0x0eaa
|
#define mmCM1_CM_GAMCOR_LUT_DATA_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_LUT_CONTROL 0x0eab
|
#define mmCM1_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B 0x0eac
|
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G 0x0ead
|
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R 0x0eae
|
#define mmCM1_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x0eaf
|
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x0eb0
|
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x0eb1
|
#define mmCM1_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x0eb2
|
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x0eb3
|
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x0eb4
|
#define mmCM1_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B 0x0eb5
|
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B 0x0eb6
|
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G 0x0eb7
|
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G 0x0eb8
|
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R 0x0eb9
|
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R 0x0eba
|
#define mmCM1_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B 0x0ebb
|
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G 0x0ebc
|
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R 0x0ebd
|
#define mmCM1_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1 0x0ebe
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3 0x0ebf
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5 0x0ec0
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7 0x0ec1
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9 0x0ec2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11 0x0ec3
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13 0x0ec4
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15 0x0ec5
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17 0x0ec6
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19 0x0ec7
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21 0x0ec8
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23 0x0ec9
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25 0x0eca
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27 0x0ecb
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29 0x0ecc
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31 0x0ecd
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33 0x0ece
|
#define mmCM1_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B 0x0ecf
|
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G 0x0ed0
|
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R 0x0ed1
|
#define mmCM1_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x0ed2
|
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x0ed3
|
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x0ed4
|
#define mmCM1_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x0ed5
|
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x0ed6
|
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x0ed7
|
#define mmCM1_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B 0x0ed8
|
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B 0x0ed9
|
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G 0x0eda
|
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G 0x0edb
|
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R 0x0edc
|
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R 0x0edd
|
#define mmCM1_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B 0x0ede
|
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G 0x0edf
|
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R 0x0ee0
|
#define mmCM1_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1 0x0ee1
|
#define mmCM1_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3 0x0ee2
|
#define mmCM1_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5 0x0ee3
|
#define mmCM1_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7 0x0ee4
|
#define mmCM1_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9 0x0ee5
|
#define mmCM1_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11 0x0ee6
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#define mmCM1_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13 0x0ee7
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#define mmCM1_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15 0x0ee8
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#define mmCM1_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17 0x0ee9
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#define mmCM1_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19 0x0eea
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#define mmCM1_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21 0x0eeb
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#define mmCM1_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23 0x0eec
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#define mmCM1_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25 0x0eed
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#define mmCM1_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27 0x0eee
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#define mmCM1_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29 0x0eef
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#define mmCM1_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31 0x0ef0
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#define mmCM1_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33 0x0ef1
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#define mmCM1_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_CONTROL 0x0ef2
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#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ef3
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#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ef4
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#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_LUT_CONTROL 0x0ef5
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#define mmCM1_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ef6
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#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ef7
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#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ef8
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#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x0ef9
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#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x0efa
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#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x0efb
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#define mmCM1_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x0efc
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#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x0efd
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#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x0efe
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#define mmCM1_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0eff
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#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0f00
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#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0f01
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#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0f02
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#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0f03
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#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0f04
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#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B 0x0f05
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#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G 0x0f06
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#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R 0x0f07
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#define mmCM1_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0f08
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0f09
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0f0a
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0f0b
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0f0c
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0f0d
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0f0e
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0f0f
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0f10
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0f11
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0f12
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0f13
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0f14
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0f15
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0f16
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0f17
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0f18
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#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0f19
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#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0f1a
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#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0f1b
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#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x0f1c
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#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x0f1d
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#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x0f1e
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#define mmCM1_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x0f1f
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#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x0f20
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#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x0f21
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#define mmCM1_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0f22
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#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0f23
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#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0f24
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#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0f25
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#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0f26
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#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0f27
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#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B 0x0f28
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#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G 0x0f29
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#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R 0x0f2a
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#define mmCM1_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0f2b
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0f2c
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0f2d
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0f2e
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0f2f
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f30
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f31
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f32
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f33
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f34
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f35
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f36
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f37
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f38
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f39
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f3a
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f3b
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#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM1_CM_HDR_MULT_COEF 0x0f3c
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#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2
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#define mmCM1_CM_MEM_PWR_CTRL 0x0f3d
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#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCM1_CM_MEM_PWR_STATUS 0x0f3e
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#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCM1_CM_DEALPHA 0x0f40
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#define mmCM1_CM_DEALPHA_BASE_IDX 2
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#define mmCM1_CM_COEF_FORMAT 0x0f41
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#define mmCM1_CM_COEF_FORMAT_BASE_IDX 2
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#define mmCM1_CM_SHAPER_CONTROL 0x0f42
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#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2
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#define mmCM1_CM_SHAPER_OFFSET_R 0x0f43
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#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2
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#define mmCM1_CM_SHAPER_OFFSET_G 0x0f44
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#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2
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#define mmCM1_CM_SHAPER_OFFSET_B 0x0f45
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#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2
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#define mmCM1_CM_SHAPER_SCALE_R 0x0f46
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#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2
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#define mmCM1_CM_SHAPER_SCALE_G_B 0x0f47
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#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2
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#define mmCM1_CM_SHAPER_LUT_INDEX 0x0f48
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#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2
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#define mmCM1_CM_SHAPER_LUT_DATA 0x0f49
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#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2
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#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f4a
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#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f4b
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#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f4c
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#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f4d
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#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f4e
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#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f4f
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#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f50
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#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f51
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#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f52
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#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f53
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#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f54
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#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f55
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#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f56
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#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f57
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#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f58
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#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f59
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#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f5a
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#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f5b
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#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f5c
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#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f5d
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#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f5e
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#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f5f
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#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f60
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#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f61
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#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f62
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#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f63
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#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f64
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#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f65
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#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f66
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#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f67
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#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f68
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#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f69
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#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f6a
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#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f6b
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#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f6c
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#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f6d
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#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f6e
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#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f6f
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#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f70
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#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f71
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#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f72
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#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f73
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#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f74
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#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f75
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#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f76
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#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f77
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#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f78
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#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM1_CM_MEM_PWR_CTRL2 0x0f79
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#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmCM1_CM_MEM_PWR_STATUS2 0x0f7a
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#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2
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#define mmCM1_CM_3DLUT_MODE 0x0f7b
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#define mmCM1_CM_3DLUT_MODE_BASE_IDX 2
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#define mmCM1_CM_3DLUT_INDEX 0x0f7c
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#define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2
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#define mmCM1_CM_3DLUT_DATA 0x0f7d
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#define mmCM1_CM_3DLUT_DATA_BASE_IDX 2
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#define mmCM1_CM_3DLUT_DATA_30BIT 0x0f7e
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#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2
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#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f7f
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#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
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#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f80
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#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
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#define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f81
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#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
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#define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f82
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#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
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#define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f83
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#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
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// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x3e3c
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#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x0f8f
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#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x0f90
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#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x0f91
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#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_CNTL 0x0f92
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#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_CNTL2 0x0f93
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#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0f94
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#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0f95
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#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_HI 0x0f96
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#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_LOW 0x0f97
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#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
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// base address: 0xb58
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#define mmDPP_TOP2_DPP_CONTROL 0x0f9b
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#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2
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#define mmDPP_TOP2_DPP_SOFT_RESET 0x0f9c
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#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2
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#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d
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#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2
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#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e
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#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2
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#define mmDPP_TOP2_DPP_CRC_CTRL 0x0f9f
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#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2
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#define mmDPP_TOP2_HOST_READ_CONTROL 0x0fa0
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#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
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// base address: 0xb58
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#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5
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#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
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#define mmCNVC_CFG2_FORMAT_CONTROL 0x0fa6
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#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7
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#define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2
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#define mmCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8
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#define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2
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#define mmCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9
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#define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2
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#define mmCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa
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#define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2
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#define mmCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab
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#define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2
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#define mmCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac
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#define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2
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#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad
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#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae
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#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2
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#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0faf
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#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2
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#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0
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#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2
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#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1
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#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2
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#define mmCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3
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#define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_DEALPHA 0x0fb4
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#define mmCNVC_CFG2_PRE_DEALPHA_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_MODE 0x0fb5
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#define mmCNVC_CFG2_PRE_CSC_MODE_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_C11_C12 0x0fb6
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#define mmCNVC_CFG2_PRE_CSC_C11_C12_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_C13_C14 0x0fb7
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#define mmCNVC_CFG2_PRE_CSC_C13_C14_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_C21_C22 0x0fb8
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#define mmCNVC_CFG2_PRE_CSC_C21_C22_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_C23_C24 0x0fb9
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#define mmCNVC_CFG2_PRE_CSC_C23_C24_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_C31_C32 0x0fba
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#define mmCNVC_CFG2_PRE_CSC_C31_C32_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_C33_C34 0x0fbb
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#define mmCNVC_CFG2_PRE_CSC_C33_C34_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_B_C11_C12 0x0fbc
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#define mmCNVC_CFG2_PRE_CSC_B_C11_C12_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_B_C13_C14 0x0fbd
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#define mmCNVC_CFG2_PRE_CSC_B_C13_C14_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_B_C21_C22 0x0fbe
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#define mmCNVC_CFG2_PRE_CSC_B_C21_C22_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_B_C23_C24 0x0fbf
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#define mmCNVC_CFG2_PRE_CSC_B_C23_C24_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_B_C31_C32 0x0fc0
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#define mmCNVC_CFG2_PRE_CSC_B_C31_C32_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_CSC_B_C33_C34 0x0fc1
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#define mmCNVC_CFG2_PRE_CSC_B_C33_C34_BASE_IDX 2
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#define mmCNVC_CFG2_CNVC_COEF_FORMAT 0x0fc2
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#define mmCNVC_CFG2_CNVC_COEF_FORMAT_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_DEGAM 0x0fc3
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#define mmCNVC_CFG2_PRE_DEGAM_BASE_IDX 2
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#define mmCNVC_CFG2_PRE_REALPHA 0x0fc4
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#define mmCNVC_CFG2_PRE_REALPHA_BASE_IDX 2
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// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
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// base address: 0xb58
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#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0fc7
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#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2
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#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0fc8
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#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2
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#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0fc9
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#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2
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#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fca
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#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
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// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
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// base address: 0xb58
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#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fcf
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#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
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#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fd0
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#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmDSCL2_SCL_MODE 0x0fd1
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#define mmDSCL2_SCL_MODE_BASE_IDX 2
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#define mmDSCL2_SCL_TAP_CONTROL 0x0fd2
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#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmDSCL2_DSCL_CONTROL 0x0fd3
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#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2
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#define mmDSCL2_DSCL_2TAP_CONTROL 0x0fd4
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#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2
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#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fd5
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#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fd6
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#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0fd7
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#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fd8
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#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fd9
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#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fda
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#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0fdb
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#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fdc
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#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fdd
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#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0fde
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#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fdf
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#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
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#define mmDSCL2_SCL_BLACK_COLOR 0x0fe0
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#define mmDSCL2_SCL_BLACK_COLOR_BASE_IDX 2
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#define mmDSCL2_DSCL_UPDATE 0x0fe1
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#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2
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#define mmDSCL2_DSCL_AUTOCAL 0x0fe2
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#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2
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#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fe3
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#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fe4
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#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmDSCL2_OTG_H_BLANK 0x0fe5
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#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2
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#define mmDSCL2_OTG_V_BLANK 0x0fe6
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#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2
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#define mmDSCL2_RECOUT_START 0x0fe7
|
#define mmDSCL2_RECOUT_START_BASE_IDX 2
|
#define mmDSCL2_RECOUT_SIZE 0x0fe8
|
#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2
|
#define mmDSCL2_MPC_SIZE 0x0fe9
|
#define mmDSCL2_MPC_SIZE_BASE_IDX 2
|
#define mmDSCL2_LB_DATA_FORMAT 0x0fea
|
#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2
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#define mmDSCL2_LB_MEMORY_CTRL 0x0feb
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#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2
|
#define mmDSCL2_LB_V_COUNTER 0x0fec
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#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2
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#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0fed
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#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0fee
|
#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDSCL2_OBUF_CONTROL 0x0fef
|
#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2
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#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0ff0
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#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2
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// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
|
// base address: 0xb58
|
#define mmCM2_CM_CONTROL 0x0ff6
|
#define mmCM2_CM_CONTROL_BASE_IDX 2
|
#define mmCM2_CM_POST_CSC_CONTROL 0x0ff7
|
#define mmCM2_CM_POST_CSC_CONTROL_BASE_IDX 2
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#define mmCM2_CM_POST_CSC_C11_C12 0x0ff8
|
#define mmCM2_CM_POST_CSC_C11_C12_BASE_IDX 2
|
#define mmCM2_CM_POST_CSC_C13_C14 0x0ff9
|
#define mmCM2_CM_POST_CSC_C13_C14_BASE_IDX 2
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#define mmCM2_CM_POST_CSC_C21_C22 0x0ffa
|
#define mmCM2_CM_POST_CSC_C21_C22_BASE_IDX 2
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#define mmCM2_CM_POST_CSC_C23_C24 0x0ffb
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#define mmCM2_CM_POST_CSC_C23_C24_BASE_IDX 2
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#define mmCM2_CM_POST_CSC_C31_C32 0x0ffc
|
#define mmCM2_CM_POST_CSC_C31_C32_BASE_IDX 2
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#define mmCM2_CM_POST_CSC_C33_C34 0x0ffd
|
#define mmCM2_CM_POST_CSC_C33_C34_BASE_IDX 2
|
#define mmCM2_CM_POST_CSC_B_C11_C12 0x0ffe
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#define mmCM2_CM_POST_CSC_B_C11_C12_BASE_IDX 2
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#define mmCM2_CM_POST_CSC_B_C13_C14 0x0fff
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#define mmCM2_CM_POST_CSC_B_C13_C14_BASE_IDX 2
|
#define mmCM2_CM_POST_CSC_B_C21_C22 0x1000
|
#define mmCM2_CM_POST_CSC_B_C21_C22_BASE_IDX 2
|
#define mmCM2_CM_POST_CSC_B_C23_C24 0x1001
|
#define mmCM2_CM_POST_CSC_B_C23_C24_BASE_IDX 2
|
#define mmCM2_CM_POST_CSC_B_C31_C32 0x1002
|
#define mmCM2_CM_POST_CSC_B_C31_C32_BASE_IDX 2
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#define mmCM2_CM_POST_CSC_B_C33_C34 0x1003
|
#define mmCM2_CM_POST_CSC_B_C33_C34_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x1004
|
#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x1005
|
#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x1006
|
#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x1007
|
#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x1008
|
#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x1009
|
#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x100a
|
#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_B_C11_C12 0x100b
|
#define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_B_C13_C14 0x100c
|
#define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_B_C21_C22 0x100d
|
#define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_B_C23_C24 0x100e
|
#define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_B_C31_C32 0x100f
|
#define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_B_C33_C34 0x1010
|
#define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
|
#define mmCM2_CM_BIAS_CR_R 0x1011
|
#define mmCM2_CM_BIAS_CR_R_BASE_IDX 2
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#define mmCM2_CM_BIAS_Y_G_CB_B 0x1012
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#define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_CONTROL 0x1013
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#define mmCM2_CM_GAMCOR_CONTROL_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_LUT_INDEX 0x1014
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#define mmCM2_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_LUT_DATA 0x1015
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#define mmCM2_CM_GAMCOR_LUT_DATA_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_LUT_CONTROL 0x1016
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#define mmCM2_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B 0x1017
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#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G 0x1018
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#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R 0x1019
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#define mmCM2_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x101a
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#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x101b
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#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x101c
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#define mmCM2_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x101d
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#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x101e
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#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x101f
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#define mmCM2_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B 0x1020
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#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B 0x1021
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#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G 0x1022
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#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G 0x1023
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#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R 0x1024
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#define mmCM2_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R 0x1025
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#define mmCM2_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_OFFSET_B 0x1026
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#define mmCM2_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_OFFSET_G 0x1027
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#define mmCM2_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_OFFSET_R 0x1028
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#define mmCM2_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_0_1 0x1029
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#define mmCM2_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_2_3 0x102a
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#define mmCM2_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_4_5 0x102b
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#define mmCM2_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_6_7 0x102c
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#define mmCM2_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_8_9 0x102d
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#define mmCM2_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_10_11 0x102e
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#define mmCM2_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_12_13 0x102f
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#define mmCM2_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_14_15 0x1030
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#define mmCM2_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_16_17 0x1031
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#define mmCM2_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_18_19 0x1032
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#define mmCM2_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_20_21 0x1033
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#define mmCM2_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_22_23 0x1034
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#define mmCM2_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_24_25 0x1035
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#define mmCM2_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_26_27 0x1036
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#define mmCM2_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_28_29 0x1037
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#define mmCM2_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_30_31 0x1038
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#define mmCM2_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMA_REGION_32_33 0x1039
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#define mmCM2_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B 0x103a
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#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G 0x103b
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#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R 0x103c
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#define mmCM2_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x103d
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#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x103e
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#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x103f
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#define mmCM2_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1040
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#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1041
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#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1042
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#define mmCM2_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B 0x1043
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#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B 0x1044
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#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G 0x1045
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#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G 0x1046
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#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R 0x1047
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#define mmCM2_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R 0x1048
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#define mmCM2_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_OFFSET_B 0x1049
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#define mmCM2_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_OFFSET_G 0x104a
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#define mmCM2_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_OFFSET_R 0x104b
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#define mmCM2_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_0_1 0x104c
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#define mmCM2_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_2_3 0x104d
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#define mmCM2_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_4_5 0x104e
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#define mmCM2_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_6_7 0x104f
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#define mmCM2_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_8_9 0x1050
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#define mmCM2_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_10_11 0x1051
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#define mmCM2_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_12_13 0x1052
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#define mmCM2_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_14_15 0x1053
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#define mmCM2_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_16_17 0x1054
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#define mmCM2_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_18_19 0x1055
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#define mmCM2_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_20_21 0x1056
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#define mmCM2_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_22_23 0x1057
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#define mmCM2_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_24_25 0x1058
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#define mmCM2_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_26_27 0x1059
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#define mmCM2_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_28_29 0x105a
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#define mmCM2_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_30_31 0x105b
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#define mmCM2_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM2_CM_GAMCOR_RAMB_REGION_32_33 0x105c
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#define mmCM2_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_CONTROL 0x105d
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#define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_LUT_INDEX 0x105e
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#define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_LUT_DATA 0x105f
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#define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_LUT_CONTROL 0x1060
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#define mmCM2_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x1061
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#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x1062
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#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x1063
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#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x1064
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#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x1065
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#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x1066
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#define mmCM2_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x1067
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#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x1068
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#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x1069
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#define mmCM2_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x106a
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#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x106b
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#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x106c
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#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x106d
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#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x106e
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#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x106f
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#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B 0x1070
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#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G 0x1071
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#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R 0x1072
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#define mmCM2_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1073
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x1074
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x1075
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x1076
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x1077
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x1078
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x1079
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x107a
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x107b
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x107c
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x107d
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x107e
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x107f
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1080
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1081
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1082
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1083
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#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x1084
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#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x1085
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#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x1086
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#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x1087
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#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x1088
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#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x1089
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#define mmCM2_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x108a
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#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x108b
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#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x108c
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#define mmCM2_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x108d
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#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x108e
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#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x108f
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#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1090
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#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1091
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#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1092
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#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B 0x1093
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#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G 0x1094
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#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R 0x1095
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#define mmCM2_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1096
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1097
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1098
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1099
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x109a
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x109b
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x109c
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x109d
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x109e
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x109f
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x10a0
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x10a1
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x10a2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x10a3
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x10a4
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x10a5
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x10a6
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#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM2_CM_HDR_MULT_COEF 0x10a7
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#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2
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#define mmCM2_CM_MEM_PWR_CTRL 0x10a8
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#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCM2_CM_MEM_PWR_STATUS 0x10a9
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#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCM2_CM_DEALPHA 0x10ab
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#define mmCM2_CM_DEALPHA_BASE_IDX 2
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#define mmCM2_CM_COEF_FORMAT 0x10ac
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#define mmCM2_CM_COEF_FORMAT_BASE_IDX 2
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#define mmCM2_CM_SHAPER_CONTROL 0x10ad
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#define mmCM2_CM_SHAPER_CONTROL_BASE_IDX 2
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#define mmCM2_CM_SHAPER_OFFSET_R 0x10ae
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#define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2
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#define mmCM2_CM_SHAPER_OFFSET_G 0x10af
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#define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2
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#define mmCM2_CM_SHAPER_OFFSET_B 0x10b0
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#define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2
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#define mmCM2_CM_SHAPER_SCALE_R 0x10b1
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#define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX 2
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#define mmCM2_CM_SHAPER_SCALE_G_B 0x10b2
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#define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2
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#define mmCM2_CM_SHAPER_LUT_INDEX 0x10b3
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#define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2
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#define mmCM2_CM_SHAPER_LUT_DATA 0x10b4
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#define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2
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#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x10b5
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#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B 0x10b6
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#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G 0x10b7
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#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R 0x10b8
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#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B 0x10b9
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#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G 0x10ba
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#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R 0x10bb
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#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_0_1 0x10bc
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#define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_2_3 0x10bd
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#define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_4_5 0x10be
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#define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_6_7 0x10bf
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#define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_8_9 0x10c0
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#define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_10_11 0x10c1
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#define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_12_13 0x10c2
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#define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_14_15 0x10c3
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#define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_16_17 0x10c4
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#define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_18_19 0x10c5
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#define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_20_21 0x10c6
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#define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_22_23 0x10c7
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#define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_24_25 0x10c8
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#define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_26_27 0x10c9
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#define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_28_29 0x10ca
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#define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_30_31 0x10cb
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#define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMA_REGION_32_33 0x10cc
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#define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B 0x10cd
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#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G 0x10ce
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#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R 0x10cf
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#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10d0
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#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10d1
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#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10d2
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#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_0_1 0x10d3
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#define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_2_3 0x10d4
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#define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_4_5 0x10d5
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#define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_6_7 0x10d6
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#define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_8_9 0x10d7
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#define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_10_11 0x10d8
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#define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_12_13 0x10d9
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#define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_14_15 0x10da
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#define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_16_17 0x10db
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#define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_18_19 0x10dc
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#define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_20_21 0x10dd
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#define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_22_23 0x10de
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#define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_24_25 0x10df
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#define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_26_27 0x10e0
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#define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_28_29 0x10e1
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#define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_30_31 0x10e2
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#define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM2_CM_SHAPER_RAMB_REGION_32_33 0x10e3
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#define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM2_CM_MEM_PWR_CTRL2 0x10e4
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#define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmCM2_CM_MEM_PWR_STATUS2 0x10e5
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#define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2
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#define mmCM2_CM_3DLUT_MODE 0x10e6
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#define mmCM2_CM_3DLUT_MODE_BASE_IDX 2
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#define mmCM2_CM_3DLUT_INDEX 0x10e7
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#define mmCM2_CM_3DLUT_INDEX_BASE_IDX 2
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#define mmCM2_CM_3DLUT_DATA 0x10e8
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#define mmCM2_CM_3DLUT_DATA_BASE_IDX 2
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#define mmCM2_CM_3DLUT_DATA_30BIT 0x10e9
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#define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2
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#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ea
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#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
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#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10eb
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#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
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#define mmCM2_CM_3DLUT_OUT_OFFSET_R 0x10ec
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#define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
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#define mmCM2_CM_3DLUT_OUT_OFFSET_G 0x10ed
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#define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
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#define mmCM2_CM_3DLUT_OUT_OFFSET_B 0x10ee
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#define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
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// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x43e8
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#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x10fa
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#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x10fb
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#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x10fc
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#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON14_PERFMON_CNTL 0x10fd
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#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON14_PERFMON_CNTL2 0x10fe
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#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x10ff
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#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x1100
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#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON14_PERFMON_HI 0x1101
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#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON14_PERFMON_LOW 0x1102
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#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
|
// base address: 0x1104
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#define mmDPP_TOP3_DPP_CONTROL 0x1106
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#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2
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#define mmDPP_TOP3_DPP_SOFT_RESET 0x1107
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#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2
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#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x1108
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#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2
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#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x1109
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#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2
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#define mmDPP_TOP3_DPP_CRC_CTRL 0x110a
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#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2
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#define mmDPP_TOP3_HOST_READ_CONTROL 0x110b
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#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
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// base address: 0x1104
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#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110
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#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
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#define mmCNVC_CFG3_FORMAT_CONTROL 0x1111
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#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG3_FCNV_FP_BIAS_R 0x1112
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#define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2
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#define mmCNVC_CFG3_FCNV_FP_BIAS_G 0x1113
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#define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2
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#define mmCNVC_CFG3_FCNV_FP_BIAS_B 0x1114
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#define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2
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#define mmCNVC_CFG3_FCNV_FP_SCALE_R 0x1115
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#define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2
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#define mmCNVC_CFG3_FCNV_FP_SCALE_G 0x1116
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#define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2
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#define mmCNVC_CFG3_FCNV_FP_SCALE_B 0x1117
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#define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2
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#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118
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#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119
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#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2
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#define mmCNVC_CFG3_COLOR_KEYER_RED 0x111a
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#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2
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#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x111b
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#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2
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#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x111c
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#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2
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#define mmCNVC_CFG3_ALPHA_2BIT_LUT 0x111e
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#define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_DEALPHA 0x111f
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#define mmCNVC_CFG3_PRE_DEALPHA_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_MODE 0x1120
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#define mmCNVC_CFG3_PRE_CSC_MODE_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_C11_C12 0x1121
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#define mmCNVC_CFG3_PRE_CSC_C11_C12_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_C13_C14 0x1122
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#define mmCNVC_CFG3_PRE_CSC_C13_C14_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_C21_C22 0x1123
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#define mmCNVC_CFG3_PRE_CSC_C21_C22_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_C23_C24 0x1124
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#define mmCNVC_CFG3_PRE_CSC_C23_C24_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_C31_C32 0x1125
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#define mmCNVC_CFG3_PRE_CSC_C31_C32_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_C33_C34 0x1126
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#define mmCNVC_CFG3_PRE_CSC_C33_C34_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_B_C11_C12 0x1127
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#define mmCNVC_CFG3_PRE_CSC_B_C11_C12_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_B_C13_C14 0x1128
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#define mmCNVC_CFG3_PRE_CSC_B_C13_C14_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_B_C21_C22 0x1129
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#define mmCNVC_CFG3_PRE_CSC_B_C21_C22_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_B_C23_C24 0x112a
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#define mmCNVC_CFG3_PRE_CSC_B_C23_C24_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_B_C31_C32 0x112b
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#define mmCNVC_CFG3_PRE_CSC_B_C31_C32_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_CSC_B_C33_C34 0x112c
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#define mmCNVC_CFG3_PRE_CSC_B_C33_C34_BASE_IDX 2
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#define mmCNVC_CFG3_CNVC_COEF_FORMAT 0x112d
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#define mmCNVC_CFG3_CNVC_COEF_FORMAT_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_DEGAM 0x112e
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#define mmCNVC_CFG3_PRE_DEGAM_BASE_IDX 2
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#define mmCNVC_CFG3_PRE_REALPHA 0x112f
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#define mmCNVC_CFG3_PRE_REALPHA_BASE_IDX 2
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// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
|
// base address: 0x1104
|
#define mmCNVC_CUR3_CURSOR0_CONTROL 0x1132
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#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2
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#define mmCNVC_CUR3_CURSOR0_COLOR0 0x1133
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#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2
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#define mmCNVC_CUR3_CURSOR0_COLOR1 0x1134
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#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2
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#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1135
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#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
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// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
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// base address: 0x1104
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#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x113a
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#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
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#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x113b
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#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmDSCL3_SCL_MODE 0x113c
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#define mmDSCL3_SCL_MODE_BASE_IDX 2
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#define mmDSCL3_SCL_TAP_CONTROL 0x113d
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#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmDSCL3_DSCL_CONTROL 0x113e
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#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2
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#define mmDSCL3_DSCL_2TAP_CONTROL 0x113f
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#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2
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#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1140
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#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1141
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#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x1142
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#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1143
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#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x1144
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#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1145
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#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL3_SCL_VERT_FILTER_INIT 0x1146
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#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1147
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#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1148
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#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x1149
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#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x114a
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#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
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#define mmDSCL3_SCL_BLACK_COLOR 0x114b
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#define mmDSCL3_SCL_BLACK_COLOR_BASE_IDX 2
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#define mmDSCL3_DSCL_UPDATE 0x114c
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#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2
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#define mmDSCL3_DSCL_AUTOCAL 0x114d
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#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2
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#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x114e
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#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x114f
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#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmDSCL3_OTG_H_BLANK 0x1150
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#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2
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#define mmDSCL3_OTG_V_BLANK 0x1151
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#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2
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#define mmDSCL3_RECOUT_START 0x1152
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#define mmDSCL3_RECOUT_START_BASE_IDX 2
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#define mmDSCL3_RECOUT_SIZE 0x1153
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#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2
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#define mmDSCL3_MPC_SIZE 0x1154
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#define mmDSCL3_MPC_SIZE_BASE_IDX 2
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#define mmDSCL3_LB_DATA_FORMAT 0x1155
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#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2
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#define mmDSCL3_LB_MEMORY_CTRL 0x1156
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#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2
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#define mmDSCL3_LB_V_COUNTER 0x1157
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#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2
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#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x1158
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#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x1159
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#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDSCL3_OBUF_CONTROL 0x115a
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#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2
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#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x115b
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#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2
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// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
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// base address: 0x1104
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#define mmCM3_CM_CONTROL 0x1161
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#define mmCM3_CM_CONTROL_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_CONTROL 0x1162
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#define mmCM3_CM_POST_CSC_CONTROL_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_C11_C12 0x1163
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#define mmCM3_CM_POST_CSC_C11_C12_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_C13_C14 0x1164
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#define mmCM3_CM_POST_CSC_C13_C14_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_C21_C22 0x1165
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#define mmCM3_CM_POST_CSC_C21_C22_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_C23_C24 0x1166
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#define mmCM3_CM_POST_CSC_C23_C24_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_C31_C32 0x1167
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#define mmCM3_CM_POST_CSC_C31_C32_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_C33_C34 0x1168
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#define mmCM3_CM_POST_CSC_C33_C34_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_B_C11_C12 0x1169
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#define mmCM3_CM_POST_CSC_B_C11_C12_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_B_C13_C14 0x116a
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#define mmCM3_CM_POST_CSC_B_C13_C14_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_B_C21_C22 0x116b
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#define mmCM3_CM_POST_CSC_B_C21_C22_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_B_C23_C24 0x116c
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#define mmCM3_CM_POST_CSC_B_C23_C24_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_B_C31_C32 0x116d
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#define mmCM3_CM_POST_CSC_B_C31_C32_BASE_IDX 2
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#define mmCM3_CM_POST_CSC_B_C33_C34 0x116e
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#define mmCM3_CM_POST_CSC_B_C33_C34_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x116f
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#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x1170
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#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x1171
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#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x1172
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#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x1173
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#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x1174
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#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x1175
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#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_B_C11_C12 0x1176
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#define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_B_C13_C14 0x1177
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#define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_B_C21_C22 0x1178
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#define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_B_C23_C24 0x1179
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#define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_B_C31_C32 0x117a
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#define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_B_C33_C34 0x117b
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#define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
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#define mmCM3_CM_BIAS_CR_R 0x117c
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#define mmCM3_CM_BIAS_CR_R_BASE_IDX 2
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#define mmCM3_CM_BIAS_Y_G_CB_B 0x117d
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#define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_CONTROL 0x117e
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#define mmCM3_CM_GAMCOR_CONTROL_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_LUT_INDEX 0x117f
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#define mmCM3_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_LUT_DATA 0x1180
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#define mmCM3_CM_GAMCOR_LUT_DATA_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_LUT_CONTROL 0x1181
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#define mmCM3_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B 0x1182
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#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G 0x1183
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#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R 0x1184
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#define mmCM3_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1185
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#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1186
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#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1187
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#define mmCM3_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x1188
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#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x1189
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#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x118a
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#define mmCM3_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B 0x118b
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#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B 0x118c
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#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G 0x118d
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#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G 0x118e
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#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R 0x118f
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#define mmCM3_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R 0x1190
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#define mmCM3_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_OFFSET_B 0x1191
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#define mmCM3_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_OFFSET_G 0x1192
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#define mmCM3_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_OFFSET_R 0x1193
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#define mmCM3_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_0_1 0x1194
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#define mmCM3_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_2_3 0x1195
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#define mmCM3_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_4_5 0x1196
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#define mmCM3_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_6_7 0x1197
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#define mmCM3_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_8_9 0x1198
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#define mmCM3_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_10_11 0x1199
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#define mmCM3_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_12_13 0x119a
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#define mmCM3_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_14_15 0x119b
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#define mmCM3_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_16_17 0x119c
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#define mmCM3_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_18_19 0x119d
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#define mmCM3_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_20_21 0x119e
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#define mmCM3_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_22_23 0x119f
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#define mmCM3_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_24_25 0x11a0
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#define mmCM3_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_26_27 0x11a1
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#define mmCM3_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_28_29 0x11a2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_30_31 0x11a3
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#define mmCM3_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMA_REGION_32_33 0x11a4
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#define mmCM3_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B 0x11a5
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#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G 0x11a6
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#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R 0x11a7
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#define mmCM3_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x11a8
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#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x11a9
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#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x11aa
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#define mmCM3_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x11ab
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#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x11ac
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#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x11ad
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#define mmCM3_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B 0x11ae
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#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B 0x11af
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#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G 0x11b0
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#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G 0x11b1
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#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R 0x11b2
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#define mmCM3_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R 0x11b3
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#define mmCM3_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_OFFSET_B 0x11b4
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#define mmCM3_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_OFFSET_G 0x11b5
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#define mmCM3_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_OFFSET_R 0x11b6
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#define mmCM3_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_0_1 0x11b7
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#define mmCM3_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_2_3 0x11b8
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#define mmCM3_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_4_5 0x11b9
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#define mmCM3_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_6_7 0x11ba
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#define mmCM3_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_8_9 0x11bb
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#define mmCM3_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_10_11 0x11bc
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#define mmCM3_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_12_13 0x11bd
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#define mmCM3_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_14_15 0x11be
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#define mmCM3_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_16_17 0x11bf
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#define mmCM3_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_18_19 0x11c0
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#define mmCM3_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_20_21 0x11c1
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#define mmCM3_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_22_23 0x11c2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_24_25 0x11c3
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#define mmCM3_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_26_27 0x11c4
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#define mmCM3_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_28_29 0x11c5
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#define mmCM3_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_30_31 0x11c6
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#define mmCM3_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM3_CM_GAMCOR_RAMB_REGION_32_33 0x11c7
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#define mmCM3_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_CONTROL 0x11c8
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#define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_LUT_INDEX 0x11c9
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#define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_LUT_DATA 0x11ca
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#define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_LUT_CONTROL 0x11cb
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#define mmCM3_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11cc
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#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11cd
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#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11ce
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#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x11cf
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#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x11d0
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#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x11d1
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#define mmCM3_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x11d2
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#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x11d3
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#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x11d4
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#define mmCM3_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11d5
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#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11d6
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#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11d7
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#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11d8
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#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11d9
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#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11da
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#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B 0x11db
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#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G 0x11dc
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#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R 0x11dd
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#define mmCM3_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11de
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11df
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11e0
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11e1
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11e2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11e3
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11e4
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11e5
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11e6
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11e7
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11e8
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11e9
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11ea
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11eb
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11ec
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11ed
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11ee
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#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11ef
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#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11f0
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#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11f1
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#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x11f2
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#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x11f3
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#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x11f4
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#define mmCM3_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x11f5
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#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x11f6
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#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x11f7
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#define mmCM3_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11f8
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#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11f9
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#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11fa
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#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11fb
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#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11fc
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#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11fd
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#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B 0x11fe
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#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G 0x11ff
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#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R 0x1200
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#define mmCM3_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x1201
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x1202
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x1203
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x1204
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x1205
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x1206
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x1207
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x1208
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x1209
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x120a
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x120b
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x120c
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x120d
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x120e
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x120f
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x1210
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x1211
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#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM3_CM_HDR_MULT_COEF 0x1212
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#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2
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#define mmCM3_CM_MEM_PWR_CTRL 0x1213
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#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCM3_CM_MEM_PWR_STATUS 0x1214
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#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCM3_CM_DEALPHA 0x1216
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#define mmCM3_CM_DEALPHA_BASE_IDX 2
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#define mmCM3_CM_COEF_FORMAT 0x1217
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#define mmCM3_CM_COEF_FORMAT_BASE_IDX 2
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#define mmCM3_CM_SHAPER_CONTROL 0x1218
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#define mmCM3_CM_SHAPER_CONTROL_BASE_IDX 2
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#define mmCM3_CM_SHAPER_OFFSET_R 0x1219
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#define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2
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#define mmCM3_CM_SHAPER_OFFSET_G 0x121a
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#define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2
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#define mmCM3_CM_SHAPER_OFFSET_B 0x121b
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#define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2
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#define mmCM3_CM_SHAPER_SCALE_R 0x121c
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#define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX 2
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#define mmCM3_CM_SHAPER_SCALE_G_B 0x121d
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#define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2
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#define mmCM3_CM_SHAPER_LUT_INDEX 0x121e
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#define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2
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#define mmCM3_CM_SHAPER_LUT_DATA 0x121f
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#define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2
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#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x1220
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#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B 0x1221
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#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G 0x1222
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#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R 0x1223
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#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B 0x1224
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#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G 0x1225
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#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R 0x1226
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#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_0_1 0x1227
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#define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_2_3 0x1228
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#define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_4_5 0x1229
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#define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_6_7 0x122a
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#define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_8_9 0x122b
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#define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_10_11 0x122c
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#define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_12_13 0x122d
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#define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_14_15 0x122e
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#define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_16_17 0x122f
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#define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_18_19 0x1230
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#define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_20_21 0x1231
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#define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_22_23 0x1232
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#define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_24_25 0x1233
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#define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_26_27 0x1234
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#define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_28_29 0x1235
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#define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_30_31 0x1236
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#define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMA_REGION_32_33 0x1237
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#define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1238
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#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1239
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#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R 0x123a
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#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B 0x123b
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#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G 0x123c
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#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R 0x123d
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#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_0_1 0x123e
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#define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_2_3 0x123f
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#define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_4_5 0x1240
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#define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_6_7 0x1241
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#define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_8_9 0x1242
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#define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_10_11 0x1243
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#define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_12_13 0x1244
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#define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_14_15 0x1245
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#define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_16_17 0x1246
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#define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_18_19 0x1247
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#define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_20_21 0x1248
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#define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_22_23 0x1249
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#define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_24_25 0x124a
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#define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_26_27 0x124b
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#define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_28_29 0x124c
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#define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_30_31 0x124d
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#define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM3_CM_SHAPER_RAMB_REGION_32_33 0x124e
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#define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM3_CM_MEM_PWR_CTRL2 0x124f
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#define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmCM3_CM_MEM_PWR_STATUS2 0x1250
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#define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2
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#define mmCM3_CM_3DLUT_MODE 0x1251
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#define mmCM3_CM_3DLUT_MODE_BASE_IDX 2
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#define mmCM3_CM_3DLUT_INDEX 0x1252
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#define mmCM3_CM_3DLUT_INDEX_BASE_IDX 2
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#define mmCM3_CM_3DLUT_DATA 0x1253
|
#define mmCM3_CM_3DLUT_DATA_BASE_IDX 2
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#define mmCM3_CM_3DLUT_DATA_30BIT 0x1254
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#define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2
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#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1255
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#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
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#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1256
|
#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
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#define mmCM3_CM_3DLUT_OUT_OFFSET_R 0x1257
|
#define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
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#define mmCM3_CM_3DLUT_OUT_OFFSET_G 0x1258
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#define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
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#define mmCM3_CM_3DLUT_OUT_OFFSET_B 0x1259
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#define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
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// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x4994
|
#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x1265
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#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x1266
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#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x1267
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#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON15_PERFMON_CNTL 0x1268
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#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON15_PERFMON_CNTL2 0x1269
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#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x126a
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#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x126b
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#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON15_PERFMON_HI 0x126c
|
#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON15_PERFMON_LOW 0x126d
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#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2
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|
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// addressBlock: dce_dc_dpp4_dispdec_dpp_top_dispdec
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// base address: 0x16b0
|
#define mmDPP_TOP4_DPP_CONTROL 0x1271
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#define mmDPP_TOP4_DPP_CONTROL_BASE_IDX 2
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#define mmDPP_TOP4_DPP_SOFT_RESET 0x1272
|
#define mmDPP_TOP4_DPP_SOFT_RESET_BASE_IDX 2
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#define mmDPP_TOP4_DPP_CRC_VAL_R_G 0x1273
|
#define mmDPP_TOP4_DPP_CRC_VAL_R_G_BASE_IDX 2
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#define mmDPP_TOP4_DPP_CRC_VAL_B_A 0x1274
|
#define mmDPP_TOP4_DPP_CRC_VAL_B_A_BASE_IDX 2
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#define mmDPP_TOP4_DPP_CRC_CTRL 0x1275
|
#define mmDPP_TOP4_DPP_CRC_CTRL_BASE_IDX 2
|
#define mmDPP_TOP4_HOST_READ_CONTROL 0x1276
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#define mmDPP_TOP4_HOST_READ_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dpp4_dispdec_cnvc_cfg_dispdec
|
// base address: 0x16b0
|
#define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT 0x127b
|
#define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
|
#define mmCNVC_CFG4_FORMAT_CONTROL 0x127c
|
#define mmCNVC_CFG4_FORMAT_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG4_FCNV_FP_BIAS_R 0x127d
|
#define mmCNVC_CFG4_FCNV_FP_BIAS_R_BASE_IDX 2
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#define mmCNVC_CFG4_FCNV_FP_BIAS_G 0x127e
|
#define mmCNVC_CFG4_FCNV_FP_BIAS_G_BASE_IDX 2
|
#define mmCNVC_CFG4_FCNV_FP_BIAS_B 0x127f
|
#define mmCNVC_CFG4_FCNV_FP_BIAS_B_BASE_IDX 2
|
#define mmCNVC_CFG4_FCNV_FP_SCALE_R 0x1280
|
#define mmCNVC_CFG4_FCNV_FP_SCALE_R_BASE_IDX 2
|
#define mmCNVC_CFG4_FCNV_FP_SCALE_G 0x1281
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#define mmCNVC_CFG4_FCNV_FP_SCALE_G_BASE_IDX 2
|
#define mmCNVC_CFG4_FCNV_FP_SCALE_B 0x1282
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#define mmCNVC_CFG4_FCNV_FP_SCALE_B_BASE_IDX 2
|
#define mmCNVC_CFG4_COLOR_KEYER_CONTROL 0x1283
|
#define mmCNVC_CFG4_COLOR_KEYER_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG4_COLOR_KEYER_ALPHA 0x1284
|
#define mmCNVC_CFG4_COLOR_KEYER_ALPHA_BASE_IDX 2
|
#define mmCNVC_CFG4_COLOR_KEYER_RED 0x1285
|
#define mmCNVC_CFG4_COLOR_KEYER_RED_BASE_IDX 2
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#define mmCNVC_CFG4_COLOR_KEYER_GREEN 0x1286
|
#define mmCNVC_CFG4_COLOR_KEYER_GREEN_BASE_IDX 2
|
#define mmCNVC_CFG4_COLOR_KEYER_BLUE 0x1287
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#define mmCNVC_CFG4_COLOR_KEYER_BLUE_BASE_IDX 2
|
#define mmCNVC_CFG4_ALPHA_2BIT_LUT 0x1289
|
#define mmCNVC_CFG4_ALPHA_2BIT_LUT_BASE_IDX 2
|
#define mmCNVC_CFG4_PRE_DEALPHA 0x128a
|
#define mmCNVC_CFG4_PRE_DEALPHA_BASE_IDX 2
|
#define mmCNVC_CFG4_PRE_CSC_MODE 0x128b
|
#define mmCNVC_CFG4_PRE_CSC_MODE_BASE_IDX 2
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#define mmCNVC_CFG4_PRE_CSC_C11_C12 0x128c
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#define mmCNVC_CFG4_PRE_CSC_C11_C12_BASE_IDX 2
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#define mmCNVC_CFG4_PRE_CSC_C13_C14 0x128d
|
#define mmCNVC_CFG4_PRE_CSC_C13_C14_BASE_IDX 2
|
#define mmCNVC_CFG4_PRE_CSC_C21_C22 0x128e
|
#define mmCNVC_CFG4_PRE_CSC_C21_C22_BASE_IDX 2
|
#define mmCNVC_CFG4_PRE_CSC_C23_C24 0x128f
|
#define mmCNVC_CFG4_PRE_CSC_C23_C24_BASE_IDX 2
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#define mmCNVC_CFG4_PRE_CSC_C31_C32 0x1290
|
#define mmCNVC_CFG4_PRE_CSC_C31_C32_BASE_IDX 2
|
#define mmCNVC_CFG4_PRE_CSC_C33_C34 0x1291
|
#define mmCNVC_CFG4_PRE_CSC_C33_C34_BASE_IDX 2
|
#define mmCNVC_CFG4_PRE_CSC_B_C11_C12 0x1292
|
#define mmCNVC_CFG4_PRE_CSC_B_C11_C12_BASE_IDX 2
|
#define mmCNVC_CFG4_PRE_CSC_B_C13_C14 0x1293
|
#define mmCNVC_CFG4_PRE_CSC_B_C13_C14_BASE_IDX 2
|
#define mmCNVC_CFG4_PRE_CSC_B_C21_C22 0x1294
|
#define mmCNVC_CFG4_PRE_CSC_B_C21_C22_BASE_IDX 2
|
#define mmCNVC_CFG4_PRE_CSC_B_C23_C24 0x1295
|
#define mmCNVC_CFG4_PRE_CSC_B_C23_C24_BASE_IDX 2
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#define mmCNVC_CFG4_PRE_CSC_B_C31_C32 0x1296
|
#define mmCNVC_CFG4_PRE_CSC_B_C31_C32_BASE_IDX 2
|
#define mmCNVC_CFG4_PRE_CSC_B_C33_C34 0x1297
|
#define mmCNVC_CFG4_PRE_CSC_B_C33_C34_BASE_IDX 2
|
#define mmCNVC_CFG4_CNVC_COEF_FORMAT 0x1298
|
#define mmCNVC_CFG4_CNVC_COEF_FORMAT_BASE_IDX 2
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#define mmCNVC_CFG4_PRE_DEGAM 0x1299
|
#define mmCNVC_CFG4_PRE_DEGAM_BASE_IDX 2
|
#define mmCNVC_CFG4_PRE_REALPHA 0x129a
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#define mmCNVC_CFG4_PRE_REALPHA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp4_dispdec_cnvc_cur_dispdec
|
// base address: 0x16b0
|
#define mmCNVC_CUR4_CURSOR0_CONTROL 0x129d
|
#define mmCNVC_CUR4_CURSOR0_CONTROL_BASE_IDX 2
|
#define mmCNVC_CUR4_CURSOR0_COLOR0 0x129e
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#define mmCNVC_CUR4_CURSOR0_COLOR0_BASE_IDX 2
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#define mmCNVC_CUR4_CURSOR0_COLOR1 0x129f
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#define mmCNVC_CUR4_CURSOR0_COLOR1_BASE_IDX 2
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#define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS 0x12a0
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#define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
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// addressBlock: dce_dc_dpp4_dispdec_dscl_dispdec
|
// base address: 0x16b0
|
#define mmDSCL4_SCL_COEF_RAM_TAP_SELECT 0x12a5
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#define mmDSCL4_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
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#define mmDSCL4_SCL_COEF_RAM_TAP_DATA 0x12a6
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#define mmDSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmDSCL4_SCL_MODE 0x12a7
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#define mmDSCL4_SCL_MODE_BASE_IDX 2
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#define mmDSCL4_SCL_TAP_CONTROL 0x12a8
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#define mmDSCL4_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmDSCL4_DSCL_CONTROL 0x12a9
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#define mmDSCL4_DSCL_CONTROL_BASE_IDX 2
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#define mmDSCL4_DSCL_2TAP_CONTROL 0x12aa
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#define mmDSCL4_DSCL_2TAP_CONTROL_BASE_IDX 2
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#define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x12ab
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#define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x12ac
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#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL4_SCL_HORZ_FILTER_INIT 0x12ad
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#define mmDSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C 0x12ae
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#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL4_SCL_HORZ_FILTER_INIT_C 0x12af
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#define mmDSCL4_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x12b0
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#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL4_SCL_VERT_FILTER_INIT 0x12b1
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#define mmDSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT 0x12b2
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#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C 0x12b3
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#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL4_SCL_VERT_FILTER_INIT_C 0x12b4
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#define mmDSCL4_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C 0x12b5
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#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
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#define mmDSCL4_SCL_BLACK_COLOR 0x12b6
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#define mmDSCL4_SCL_BLACK_COLOR_BASE_IDX 2
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#define mmDSCL4_DSCL_UPDATE 0x12b7
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#define mmDSCL4_DSCL_UPDATE_BASE_IDX 2
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#define mmDSCL4_DSCL_AUTOCAL 0x12b8
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#define mmDSCL4_DSCL_AUTOCAL_BASE_IDX 2
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#define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x12b9
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#define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x12ba
|
#define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
|
#define mmDSCL4_OTG_H_BLANK 0x12bb
|
#define mmDSCL4_OTG_H_BLANK_BASE_IDX 2
|
#define mmDSCL4_OTG_V_BLANK 0x12bc
|
#define mmDSCL4_OTG_V_BLANK_BASE_IDX 2
|
#define mmDSCL4_RECOUT_START 0x12bd
|
#define mmDSCL4_RECOUT_START_BASE_IDX 2
|
#define mmDSCL4_RECOUT_SIZE 0x12be
|
#define mmDSCL4_RECOUT_SIZE_BASE_IDX 2
|
#define mmDSCL4_MPC_SIZE 0x12bf
|
#define mmDSCL4_MPC_SIZE_BASE_IDX 2
|
#define mmDSCL4_LB_DATA_FORMAT 0x12c0
|
#define mmDSCL4_LB_DATA_FORMAT_BASE_IDX 2
|
#define mmDSCL4_LB_MEMORY_CTRL 0x12c1
|
#define mmDSCL4_LB_MEMORY_CTRL_BASE_IDX 2
|
#define mmDSCL4_LB_V_COUNTER 0x12c2
|
#define mmDSCL4_LB_V_COUNTER_BASE_IDX 2
|
#define mmDSCL4_DSCL_MEM_PWR_CTRL 0x12c3
|
#define mmDSCL4_DSCL_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDSCL4_DSCL_MEM_PWR_STATUS 0x12c4
|
#define mmDSCL4_DSCL_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDSCL4_OBUF_CONTROL 0x12c5
|
#define mmDSCL4_OBUF_CONTROL_BASE_IDX 2
|
#define mmDSCL4_OBUF_MEM_PWR_CTRL 0x12c6
|
#define mmDSCL4_OBUF_MEM_PWR_CTRL_BASE_IDX 2
|
|
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// addressBlock: dce_dc_dpp4_dispdec_cm_dispdec
|
// base address: 0x16b0
|
#define mmCM4_CM_CONTROL 0x12cc
|
#define mmCM4_CM_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_POST_CSC_CONTROL 0x12cd
|
#define mmCM4_CM_POST_CSC_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_POST_CSC_C11_C12 0x12ce
|
#define mmCM4_CM_POST_CSC_C11_C12_BASE_IDX 2
|
#define mmCM4_CM_POST_CSC_C13_C14 0x12cf
|
#define mmCM4_CM_POST_CSC_C13_C14_BASE_IDX 2
|
#define mmCM4_CM_POST_CSC_C21_C22 0x12d0
|
#define mmCM4_CM_POST_CSC_C21_C22_BASE_IDX 2
|
#define mmCM4_CM_POST_CSC_C23_C24 0x12d1
|
#define mmCM4_CM_POST_CSC_C23_C24_BASE_IDX 2
|
#define mmCM4_CM_POST_CSC_C31_C32 0x12d2
|
#define mmCM4_CM_POST_CSC_C31_C32_BASE_IDX 2
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#define mmCM4_CM_POST_CSC_C33_C34 0x12d3
|
#define mmCM4_CM_POST_CSC_C33_C34_BASE_IDX 2
|
#define mmCM4_CM_POST_CSC_B_C11_C12 0x12d4
|
#define mmCM4_CM_POST_CSC_B_C11_C12_BASE_IDX 2
|
#define mmCM4_CM_POST_CSC_B_C13_C14 0x12d5
|
#define mmCM4_CM_POST_CSC_B_C13_C14_BASE_IDX 2
|
#define mmCM4_CM_POST_CSC_B_C21_C22 0x12d6
|
#define mmCM4_CM_POST_CSC_B_C21_C22_BASE_IDX 2
|
#define mmCM4_CM_POST_CSC_B_C23_C24 0x12d7
|
#define mmCM4_CM_POST_CSC_B_C23_C24_BASE_IDX 2
|
#define mmCM4_CM_POST_CSC_B_C31_C32 0x12d8
|
#define mmCM4_CM_POST_CSC_B_C31_C32_BASE_IDX 2
|
#define mmCM4_CM_POST_CSC_B_C33_C34 0x12d9
|
#define mmCM4_CM_POST_CSC_B_C33_C34_BASE_IDX 2
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#define mmCM4_CM_GAMUT_REMAP_CONTROL 0x12da
|
#define mmCM4_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_C11_C12 0x12db
|
#define mmCM4_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_C13_C14 0x12dc
|
#define mmCM4_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_C21_C22 0x12dd
|
#define mmCM4_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_C23_C24 0x12de
|
#define mmCM4_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_C31_C32 0x12df
|
#define mmCM4_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_C33_C34 0x12e0
|
#define mmCM4_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_B_C11_C12 0x12e1
|
#define mmCM4_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_B_C13_C14 0x12e2
|
#define mmCM4_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_B_C21_C22 0x12e3
|
#define mmCM4_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_B_C23_C24 0x12e4
|
#define mmCM4_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_B_C31_C32 0x12e5
|
#define mmCM4_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_B_C33_C34 0x12e6
|
#define mmCM4_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
|
#define mmCM4_CM_BIAS_CR_R 0x12e7
|
#define mmCM4_CM_BIAS_CR_R_BASE_IDX 2
|
#define mmCM4_CM_BIAS_Y_G_CB_B 0x12e8
|
#define mmCM4_CM_BIAS_Y_G_CB_B_BASE_IDX 2
|
#define mmCM4_CM_GAMCOR_CONTROL 0x12e9
|
#define mmCM4_CM_GAMCOR_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_GAMCOR_LUT_INDEX 0x12ea
|
#define mmCM4_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
|
#define mmCM4_CM_GAMCOR_LUT_DATA 0x12eb
|
#define mmCM4_CM_GAMCOR_LUT_DATA_BASE_IDX 2
|
#define mmCM4_CM_GAMCOR_LUT_CONTROL 0x12ec
|
#define mmCM4_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_B 0x12ed
|
#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_G 0x12ee
|
#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_R 0x12ef
|
#define mmCM4_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x12f0
|
#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x12f1
|
#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x12f2
|
#define mmCM4_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x12f3
|
#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x12f4
|
#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x12f5
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#define mmCM4_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_B 0x12f6
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#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_B 0x12f7
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#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_G 0x12f8
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#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_G 0x12f9
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#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_R 0x12fa
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#define mmCM4_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_R 0x12fb
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#define mmCM4_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_OFFSET_B 0x12fc
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#define mmCM4_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_OFFSET_G 0x12fd
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#define mmCM4_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_OFFSET_R 0x12fe
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#define mmCM4_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_0_1 0x12ff
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#define mmCM4_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_2_3 0x1300
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#define mmCM4_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_4_5 0x1301
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#define mmCM4_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_6_7 0x1302
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#define mmCM4_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_8_9 0x1303
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#define mmCM4_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_10_11 0x1304
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#define mmCM4_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_12_13 0x1305
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#define mmCM4_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_14_15 0x1306
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#define mmCM4_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_16_17 0x1307
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#define mmCM4_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_18_19 0x1308
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#define mmCM4_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_20_21 0x1309
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#define mmCM4_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_22_23 0x130a
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#define mmCM4_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_24_25 0x130b
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#define mmCM4_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_26_27 0x130c
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#define mmCM4_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_28_29 0x130d
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#define mmCM4_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_30_31 0x130e
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#define mmCM4_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMA_REGION_32_33 0x130f
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#define mmCM4_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_B 0x1310
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#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_G 0x1311
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#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_R 0x1312
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#define mmCM4_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x1313
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#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x1314
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#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x1315
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#define mmCM4_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1316
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#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1317
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#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1318
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#define mmCM4_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_B 0x1319
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#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_B 0x131a
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#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_G 0x131b
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#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_G 0x131c
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#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_R 0x131d
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#define mmCM4_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_R 0x131e
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#define mmCM4_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_OFFSET_B 0x131f
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#define mmCM4_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_OFFSET_G 0x1320
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#define mmCM4_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_OFFSET_R 0x1321
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#define mmCM4_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_0_1 0x1322
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#define mmCM4_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_2_3 0x1323
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#define mmCM4_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_4_5 0x1324
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#define mmCM4_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_6_7 0x1325
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#define mmCM4_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_8_9 0x1326
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#define mmCM4_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_10_11 0x1327
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#define mmCM4_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_12_13 0x1328
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#define mmCM4_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_14_15 0x1329
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#define mmCM4_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_16_17 0x132a
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#define mmCM4_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_18_19 0x132b
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#define mmCM4_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_20_21 0x132c
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#define mmCM4_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_22_23 0x132d
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#define mmCM4_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_24_25 0x132e
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#define mmCM4_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_26_27 0x132f
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#define mmCM4_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_28_29 0x1330
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#define mmCM4_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_30_31 0x1331
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#define mmCM4_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM4_CM_GAMCOR_RAMB_REGION_32_33 0x1332
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#define mmCM4_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_CONTROL 0x1333
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#define mmCM4_CM_BLNDGAM_CONTROL_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_LUT_INDEX 0x1334
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#define mmCM4_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_LUT_DATA 0x1335
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#define mmCM4_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_LUT_CONTROL 0x1336
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#define mmCM4_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B 0x1337
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#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G 0x1338
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#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R 0x1339
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#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x133a
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#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x133b
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#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x133c
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#define mmCM4_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x133d
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#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x133e
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#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x133f
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#define mmCM4_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B 0x1340
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#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B 0x1341
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#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G 0x1342
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#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G 0x1343
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#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R 0x1344
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#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R 0x1345
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#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_B 0x1346
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#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_G 0x1347
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#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_R 0x1348
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#define mmCM4_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1 0x1349
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3 0x134a
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5 0x134b
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7 0x134c
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9 0x134d
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11 0x134e
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13 0x134f
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15 0x1350
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17 0x1351
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19 0x1352
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21 0x1353
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23 0x1354
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25 0x1355
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27 0x1356
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29 0x1357
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31 0x1358
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33 0x1359
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#define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B 0x135a
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#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G 0x135b
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#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R 0x135c
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#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x135d
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#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x135e
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#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x135f
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#define mmCM4_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x1360
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#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x1361
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#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x1362
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#define mmCM4_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B 0x1363
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#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B 0x1364
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#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G 0x1365
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#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1366
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#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1367
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#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1368
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#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_B 0x1369
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#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_G 0x136a
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#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_R 0x136b
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#define mmCM4_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1 0x136c
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3 0x136d
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5 0x136e
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7 0x136f
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9 0x1370
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11 0x1371
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13 0x1372
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15 0x1373
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17 0x1374
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19 0x1375
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21 0x1376
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23 0x1377
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25 0x1378
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27 0x1379
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29 0x137a
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31 0x137b
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33 0x137c
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM4_CM_HDR_MULT_COEF 0x137d
|
#define mmCM4_CM_HDR_MULT_COEF_BASE_IDX 2
|
#define mmCM4_CM_MEM_PWR_CTRL 0x137e
|
#define mmCM4_CM_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCM4_CM_MEM_PWR_STATUS 0x137f
|
#define mmCM4_CM_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCM4_CM_DEALPHA 0x1381
|
#define mmCM4_CM_DEALPHA_BASE_IDX 2
|
#define mmCM4_CM_COEF_FORMAT 0x1382
|
#define mmCM4_CM_COEF_FORMAT_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_CONTROL 0x1383
|
#define mmCM4_CM_SHAPER_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_OFFSET_R 0x1384
|
#define mmCM4_CM_SHAPER_OFFSET_R_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_OFFSET_G 0x1385
|
#define mmCM4_CM_SHAPER_OFFSET_G_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_OFFSET_B 0x1386
|
#define mmCM4_CM_SHAPER_OFFSET_B_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_SCALE_R 0x1387
|
#define mmCM4_CM_SHAPER_SCALE_R_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_SCALE_G_B 0x1388
|
#define mmCM4_CM_SHAPER_SCALE_G_B_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_LUT_INDEX 0x1389
|
#define mmCM4_CM_SHAPER_LUT_INDEX_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_LUT_DATA 0x138a
|
#define mmCM4_CM_SHAPER_LUT_DATA_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK 0x138b
|
#define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_B 0x138c
|
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_G 0x138d
|
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_R 0x138e
|
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_B 0x138f
|
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_G 0x1390
|
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_R 0x1391
|
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_0_1 0x1392
|
#define mmCM4_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_2_3 0x1393
|
#define mmCM4_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_4_5 0x1394
|
#define mmCM4_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_6_7 0x1395
|
#define mmCM4_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_8_9 0x1396
|
#define mmCM4_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_10_11 0x1397
|
#define mmCM4_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_12_13 0x1398
|
#define mmCM4_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_14_15 0x1399
|
#define mmCM4_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_16_17 0x139a
|
#define mmCM4_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_18_19 0x139b
|
#define mmCM4_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_20_21 0x139c
|
#define mmCM4_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_22_23 0x139d
|
#define mmCM4_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_24_25 0x139e
|
#define mmCM4_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_26_27 0x139f
|
#define mmCM4_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_28_29 0x13a0
|
#define mmCM4_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_30_31 0x13a1
|
#define mmCM4_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_32_33 0x13a2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_B 0x13a3
|
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_G 0x13a4
|
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_R 0x13a5
|
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_B 0x13a6
|
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_G 0x13a7
|
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_R 0x13a8
|
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_0_1 0x13a9
|
#define mmCM4_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_2_3 0x13aa
|
#define mmCM4_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_4_5 0x13ab
|
#define mmCM4_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_6_7 0x13ac
|
#define mmCM4_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_8_9 0x13ad
|
#define mmCM4_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_10_11 0x13ae
|
#define mmCM4_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_12_13 0x13af
|
#define mmCM4_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_14_15 0x13b0
|
#define mmCM4_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_16_17 0x13b1
|
#define mmCM4_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_18_19 0x13b2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_20_21 0x13b3
|
#define mmCM4_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_22_23 0x13b4
|
#define mmCM4_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_24_25 0x13b5
|
#define mmCM4_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_26_27 0x13b6
|
#define mmCM4_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM4_CM_SHAPER_RAMB_REGION_28_29 0x13b7
|
#define mmCM4_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_30_31 0x13b8
|
#define mmCM4_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_32_33 0x13b9
|
#define mmCM4_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM4_CM_MEM_PWR_CTRL2 0x13ba
|
#define mmCM4_CM_MEM_PWR_CTRL2_BASE_IDX 2
|
#define mmCM4_CM_MEM_PWR_STATUS2 0x13bb
|
#define mmCM4_CM_MEM_PWR_STATUS2_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_MODE 0x13bc
|
#define mmCM4_CM_3DLUT_MODE_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_INDEX 0x13bd
|
#define mmCM4_CM_3DLUT_INDEX_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_DATA 0x13be
|
#define mmCM4_CM_3DLUT_DATA_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_DATA_30BIT 0x13bf
|
#define mmCM4_CM_3DLUT_DATA_30BIT_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_READ_WRITE_CONTROL 0x13c0
|
#define mmCM4_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_OUT_NORM_FACTOR 0x13c1
|
#define mmCM4_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_OUT_OFFSET_R 0x13c2
|
#define mmCM4_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_OUT_OFFSET_G 0x13c3
|
#define mmCM4_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_OUT_OFFSET_B 0x13c4
|
#define mmCM4_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x4f40
|
#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x13d0
|
#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x13d1
|
#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x13d2
|
#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_CNTL 0x13d3
|
#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_CNTL2 0x13d4
|
#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x13d5
|
#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x13d6
|
#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_HI 0x13d7
|
#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_LOW 0x13d8
|
#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp5_dispdec_dpp_top_dispdec
|
// base address: 0x1c5c
|
#define mmDPP_TOP5_DPP_CONTROL 0x13dc
|
#define mmDPP_TOP5_DPP_CONTROL_BASE_IDX 2
|
#define mmDPP_TOP5_DPP_SOFT_RESET 0x13dd
|
#define mmDPP_TOP5_DPP_SOFT_RESET_BASE_IDX 2
|
#define mmDPP_TOP5_DPP_CRC_VAL_R_G 0x13de
|
#define mmDPP_TOP5_DPP_CRC_VAL_R_G_BASE_IDX 2
|
#define mmDPP_TOP5_DPP_CRC_VAL_B_A 0x13df
|
#define mmDPP_TOP5_DPP_CRC_VAL_B_A_BASE_IDX 2
|
#define mmDPP_TOP5_DPP_CRC_CTRL 0x13e0
|
#define mmDPP_TOP5_DPP_CRC_CTRL_BASE_IDX 2
|
#define mmDPP_TOP5_HOST_READ_CONTROL 0x13e1
|
#define mmDPP_TOP5_HOST_READ_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp5_dispdec_cnvc_cfg_dispdec
|
// base address: 0x1c5c
|
#define mmCNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT 0x13e6
|
#define mmCNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
|
#define mmCNVC_CFG5_FORMAT_CONTROL 0x13e7
|
#define mmCNVC_CFG5_FORMAT_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG5_FCNV_FP_BIAS_R 0x13e8
|
#define mmCNVC_CFG5_FCNV_FP_BIAS_R_BASE_IDX 2
|
#define mmCNVC_CFG5_FCNV_FP_BIAS_G 0x13e9
|
#define mmCNVC_CFG5_FCNV_FP_BIAS_G_BASE_IDX 2
|
#define mmCNVC_CFG5_FCNV_FP_BIAS_B 0x13ea
|
#define mmCNVC_CFG5_FCNV_FP_BIAS_B_BASE_IDX 2
|
#define mmCNVC_CFG5_FCNV_FP_SCALE_R 0x13eb
|
#define mmCNVC_CFG5_FCNV_FP_SCALE_R_BASE_IDX 2
|
#define mmCNVC_CFG5_FCNV_FP_SCALE_G 0x13ec
|
#define mmCNVC_CFG5_FCNV_FP_SCALE_G_BASE_IDX 2
|
#define mmCNVC_CFG5_FCNV_FP_SCALE_B 0x13ed
|
#define mmCNVC_CFG5_FCNV_FP_SCALE_B_BASE_IDX 2
|
#define mmCNVC_CFG5_COLOR_KEYER_CONTROL 0x13ee
|
#define mmCNVC_CFG5_COLOR_KEYER_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG5_COLOR_KEYER_ALPHA 0x13ef
|
#define mmCNVC_CFG5_COLOR_KEYER_ALPHA_BASE_IDX 2
|
#define mmCNVC_CFG5_COLOR_KEYER_RED 0x13f0
|
#define mmCNVC_CFG5_COLOR_KEYER_RED_BASE_IDX 2
|
#define mmCNVC_CFG5_COLOR_KEYER_GREEN 0x13f1
|
#define mmCNVC_CFG5_COLOR_KEYER_GREEN_BASE_IDX 2
|
#define mmCNVC_CFG5_COLOR_KEYER_BLUE 0x13f2
|
#define mmCNVC_CFG5_COLOR_KEYER_BLUE_BASE_IDX 2
|
#define mmCNVC_CFG5_ALPHA_2BIT_LUT 0x13f4
|
#define mmCNVC_CFG5_ALPHA_2BIT_LUT_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_DEALPHA 0x13f5
|
#define mmCNVC_CFG5_PRE_DEALPHA_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_MODE 0x13f6
|
#define mmCNVC_CFG5_PRE_CSC_MODE_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_C11_C12 0x13f7
|
#define mmCNVC_CFG5_PRE_CSC_C11_C12_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_C13_C14 0x13f8
|
#define mmCNVC_CFG5_PRE_CSC_C13_C14_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_C21_C22 0x13f9
|
#define mmCNVC_CFG5_PRE_CSC_C21_C22_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_C23_C24 0x13fa
|
#define mmCNVC_CFG5_PRE_CSC_C23_C24_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_C31_C32 0x13fb
|
#define mmCNVC_CFG5_PRE_CSC_C31_C32_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_C33_C34 0x13fc
|
#define mmCNVC_CFG5_PRE_CSC_C33_C34_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_B_C11_C12 0x13fd
|
#define mmCNVC_CFG5_PRE_CSC_B_C11_C12_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_B_C13_C14 0x13fe
|
#define mmCNVC_CFG5_PRE_CSC_B_C13_C14_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_B_C21_C22 0x13ff
|
#define mmCNVC_CFG5_PRE_CSC_B_C21_C22_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_B_C23_C24 0x1400
|
#define mmCNVC_CFG5_PRE_CSC_B_C23_C24_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_B_C31_C32 0x1401
|
#define mmCNVC_CFG5_PRE_CSC_B_C31_C32_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_CSC_B_C33_C34 0x1402
|
#define mmCNVC_CFG5_PRE_CSC_B_C33_C34_BASE_IDX 2
|
#define mmCNVC_CFG5_CNVC_COEF_FORMAT 0x1403
|
#define mmCNVC_CFG5_CNVC_COEF_FORMAT_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_DEGAM 0x1404
|
#define mmCNVC_CFG5_PRE_DEGAM_BASE_IDX 2
|
#define mmCNVC_CFG5_PRE_REALPHA 0x1405
|
#define mmCNVC_CFG5_PRE_REALPHA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp5_dispdec_cnvc_cur_dispdec
|
// base address: 0x1c5c
|
#define mmCNVC_CUR5_CURSOR0_CONTROL 0x1408
|
#define mmCNVC_CUR5_CURSOR0_CONTROL_BASE_IDX 2
|
#define mmCNVC_CUR5_CURSOR0_COLOR0 0x1409
|
#define mmCNVC_CUR5_CURSOR0_COLOR0_BASE_IDX 2
|
#define mmCNVC_CUR5_CURSOR0_COLOR1 0x140a
|
#define mmCNVC_CUR5_CURSOR0_COLOR1_BASE_IDX 2
|
#define mmCNVC_CUR5_CURSOR0_FP_SCALE_BIAS 0x140b
|
#define mmCNVC_CUR5_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp5_dispdec_dscl_dispdec
|
// base address: 0x1c5c
|
#define mmDSCL5_SCL_COEF_RAM_TAP_SELECT 0x1410
|
#define mmDSCL5_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
|
#define mmDSCL5_SCL_COEF_RAM_TAP_DATA 0x1411
|
#define mmDSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmDSCL5_SCL_MODE 0x1412
|
#define mmDSCL5_SCL_MODE_BASE_IDX 2
|
#define mmDSCL5_SCL_TAP_CONTROL 0x1413
|
#define mmDSCL5_SCL_TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL5_DSCL_CONTROL 0x1414
|
#define mmDSCL5_DSCL_CONTROL_BASE_IDX 2
|
#define mmDSCL5_DSCL_2TAP_CONTROL 0x1415
|
#define mmDSCL5_DSCL_2TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x1416
|
#define mmDSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
|
#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x1417
|
#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL5_SCL_HORZ_FILTER_INIT 0x1418
|
#define mmDSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1419
|
#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL5_SCL_HORZ_FILTER_INIT_C 0x141a
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#define mmDSCL5_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x141b
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#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL5_SCL_VERT_FILTER_INIT 0x141c
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#define mmDSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT 0x141d
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#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_C 0x141e
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#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL5_SCL_VERT_FILTER_INIT_C 0x141f
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#define mmDSCL5_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_C 0x1420
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#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
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#define mmDSCL5_SCL_BLACK_COLOR 0x1421
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#define mmDSCL5_SCL_BLACK_COLOR_BASE_IDX 2
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#define mmDSCL5_DSCL_UPDATE 0x1422
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#define mmDSCL5_DSCL_UPDATE_BASE_IDX 2
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#define mmDSCL5_DSCL_AUTOCAL 0x1423
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#define mmDSCL5_DSCL_AUTOCAL_BASE_IDX 2
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#define mmDSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x1424
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#define mmDSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmDSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x1425
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#define mmDSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmDSCL5_OTG_H_BLANK 0x1426
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#define mmDSCL5_OTG_H_BLANK_BASE_IDX 2
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#define mmDSCL5_OTG_V_BLANK 0x1427
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#define mmDSCL5_OTG_V_BLANK_BASE_IDX 2
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#define mmDSCL5_RECOUT_START 0x1428
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#define mmDSCL5_RECOUT_START_BASE_IDX 2
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#define mmDSCL5_RECOUT_SIZE 0x1429
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#define mmDSCL5_RECOUT_SIZE_BASE_IDX 2
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#define mmDSCL5_MPC_SIZE 0x142a
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#define mmDSCL5_MPC_SIZE_BASE_IDX 2
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#define mmDSCL5_LB_DATA_FORMAT 0x142b
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#define mmDSCL5_LB_DATA_FORMAT_BASE_IDX 2
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#define mmDSCL5_LB_MEMORY_CTRL 0x142c
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#define mmDSCL5_LB_MEMORY_CTRL_BASE_IDX 2
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#define mmDSCL5_LB_V_COUNTER 0x142d
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#define mmDSCL5_LB_V_COUNTER_BASE_IDX 2
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#define mmDSCL5_DSCL_MEM_PWR_CTRL 0x142e
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#define mmDSCL5_DSCL_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDSCL5_DSCL_MEM_PWR_STATUS 0x142f
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#define mmDSCL5_DSCL_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDSCL5_OBUF_CONTROL 0x1430
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#define mmDSCL5_OBUF_CONTROL_BASE_IDX 2
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#define mmDSCL5_OBUF_MEM_PWR_CTRL 0x1431
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#define mmDSCL5_OBUF_MEM_PWR_CTRL_BASE_IDX 2
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// addressBlock: dce_dc_dpp5_dispdec_cm_dispdec
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// base address: 0x1c5c
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#define mmCM5_CM_CONTROL 0x1437
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#define mmCM5_CM_CONTROL_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_CONTROL 0x1438
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#define mmCM5_CM_POST_CSC_CONTROL_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_C11_C12 0x1439
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#define mmCM5_CM_POST_CSC_C11_C12_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_C13_C14 0x143a
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#define mmCM5_CM_POST_CSC_C13_C14_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_C21_C22 0x143b
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#define mmCM5_CM_POST_CSC_C21_C22_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_C23_C24 0x143c
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#define mmCM5_CM_POST_CSC_C23_C24_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_C31_C32 0x143d
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#define mmCM5_CM_POST_CSC_C31_C32_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_C33_C34 0x143e
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#define mmCM5_CM_POST_CSC_C33_C34_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_B_C11_C12 0x143f
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#define mmCM5_CM_POST_CSC_B_C11_C12_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_B_C13_C14 0x1440
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#define mmCM5_CM_POST_CSC_B_C13_C14_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_B_C21_C22 0x1441
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#define mmCM5_CM_POST_CSC_B_C21_C22_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_B_C23_C24 0x1442
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#define mmCM5_CM_POST_CSC_B_C23_C24_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_B_C31_C32 0x1443
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#define mmCM5_CM_POST_CSC_B_C31_C32_BASE_IDX 2
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#define mmCM5_CM_POST_CSC_B_C33_C34 0x1444
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#define mmCM5_CM_POST_CSC_B_C33_C34_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_CONTROL 0x1445
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#define mmCM5_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_C11_C12 0x1446
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#define mmCM5_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_C13_C14 0x1447
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#define mmCM5_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_C21_C22 0x1448
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#define mmCM5_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_C23_C24 0x1449
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#define mmCM5_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_C31_C32 0x144a
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#define mmCM5_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_C33_C34 0x144b
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#define mmCM5_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_B_C11_C12 0x144c
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#define mmCM5_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_B_C13_C14 0x144d
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#define mmCM5_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_B_C21_C22 0x144e
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#define mmCM5_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_B_C23_C24 0x144f
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#define mmCM5_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_B_C31_C32 0x1450
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#define mmCM5_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
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#define mmCM5_CM_GAMUT_REMAP_B_C33_C34 0x1451
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#define mmCM5_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
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#define mmCM5_CM_BIAS_CR_R 0x1452
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#define mmCM5_CM_BIAS_CR_R_BASE_IDX 2
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#define mmCM5_CM_BIAS_Y_G_CB_B 0x1453
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#define mmCM5_CM_BIAS_Y_G_CB_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_CONTROL 0x1454
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#define mmCM5_CM_GAMCOR_CONTROL_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_LUT_INDEX 0x1455
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#define mmCM5_CM_GAMCOR_LUT_INDEX_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_LUT_DATA 0x1456
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#define mmCM5_CM_GAMCOR_LUT_DATA_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_LUT_CONTROL 0x1457
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#define mmCM5_CM_GAMCOR_LUT_CONTROL_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_START_CNTL_B 0x1458
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#define mmCM5_CM_GAMCOR_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_START_CNTL_G 0x1459
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#define mmCM5_CM_GAMCOR_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_START_CNTL_R 0x145a
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#define mmCM5_CM_GAMCOR_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x145b
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#define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x145c
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#define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x145d
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#define mmCM5_CM_GAMCOR_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_B 0x145e
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#define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_G 0x145f
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#define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_R 0x1460
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#define mmCM5_CM_GAMCOR_RAMA_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_B 0x1461
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#define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_B 0x1462
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#define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_G 0x1463
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#define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_G 0x1464
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#define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_R 0x1465
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#define mmCM5_CM_GAMCOR_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_R 0x1466
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#define mmCM5_CM_GAMCOR_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_OFFSET_B 0x1467
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#define mmCM5_CM_GAMCOR_RAMA_OFFSET_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_OFFSET_G 0x1468
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#define mmCM5_CM_GAMCOR_RAMA_OFFSET_G_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_OFFSET_R 0x1469
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#define mmCM5_CM_GAMCOR_RAMA_OFFSET_R_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_0_1 0x146a
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#define mmCM5_CM_GAMCOR_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_2_3 0x146b
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#define mmCM5_CM_GAMCOR_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_4_5 0x146c
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#define mmCM5_CM_GAMCOR_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_6_7 0x146d
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#define mmCM5_CM_GAMCOR_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_8_9 0x146e
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#define mmCM5_CM_GAMCOR_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_10_11 0x146f
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#define mmCM5_CM_GAMCOR_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_12_13 0x1470
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#define mmCM5_CM_GAMCOR_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_14_15 0x1471
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#define mmCM5_CM_GAMCOR_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_16_17 0x1472
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#define mmCM5_CM_GAMCOR_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_18_19 0x1473
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#define mmCM5_CM_GAMCOR_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_20_21 0x1474
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#define mmCM5_CM_GAMCOR_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_22_23 0x1475
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#define mmCM5_CM_GAMCOR_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_24_25 0x1476
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#define mmCM5_CM_GAMCOR_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_26_27 0x1477
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#define mmCM5_CM_GAMCOR_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_28_29 0x1478
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#define mmCM5_CM_GAMCOR_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_30_31 0x1479
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#define mmCM5_CM_GAMCOR_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMA_REGION_32_33 0x147a
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#define mmCM5_CM_GAMCOR_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_START_CNTL_B 0x147b
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#define mmCM5_CM_GAMCOR_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_START_CNTL_G 0x147c
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#define mmCM5_CM_GAMCOR_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_START_CNTL_R 0x147d
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#define mmCM5_CM_GAMCOR_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B 0x147e
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#define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G 0x147f
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#define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R 0x1480
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#define mmCM5_CM_GAMCOR_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_B 0x1481
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#define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_G 0x1482
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#define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_R 0x1483
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#define mmCM5_CM_GAMCOR_RAMB_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_B 0x1484
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#define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_B 0x1485
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#define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_G 0x1486
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#define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_G 0x1487
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#define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_R 0x1488
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#define mmCM5_CM_GAMCOR_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_R 0x1489
|
#define mmCM5_CM_GAMCOR_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_OFFSET_B 0x148a
|
#define mmCM5_CM_GAMCOR_RAMB_OFFSET_B_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_OFFSET_G 0x148b
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#define mmCM5_CM_GAMCOR_RAMB_OFFSET_G_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_OFFSET_R 0x148c
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#define mmCM5_CM_GAMCOR_RAMB_OFFSET_R_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_0_1 0x148d
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#define mmCM5_CM_GAMCOR_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_2_3 0x148e
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#define mmCM5_CM_GAMCOR_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_4_5 0x148f
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#define mmCM5_CM_GAMCOR_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_6_7 0x1490
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#define mmCM5_CM_GAMCOR_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_8_9 0x1491
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#define mmCM5_CM_GAMCOR_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_10_11 0x1492
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#define mmCM5_CM_GAMCOR_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_12_13 0x1493
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#define mmCM5_CM_GAMCOR_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_14_15 0x1494
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#define mmCM5_CM_GAMCOR_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_16_17 0x1495
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#define mmCM5_CM_GAMCOR_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_18_19 0x1496
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#define mmCM5_CM_GAMCOR_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_20_21 0x1497
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#define mmCM5_CM_GAMCOR_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_22_23 0x1498
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#define mmCM5_CM_GAMCOR_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_24_25 0x1499
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#define mmCM5_CM_GAMCOR_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_26_27 0x149a
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#define mmCM5_CM_GAMCOR_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_28_29 0x149b
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#define mmCM5_CM_GAMCOR_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_30_31 0x149c
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#define mmCM5_CM_GAMCOR_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM5_CM_GAMCOR_RAMB_REGION_32_33 0x149d
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#define mmCM5_CM_GAMCOR_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_CONTROL 0x149e
|
#define mmCM5_CM_BLNDGAM_CONTROL_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_LUT_INDEX 0x149f
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#define mmCM5_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_LUT_DATA 0x14a0
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#define mmCM5_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_LUT_CONTROL 0x14a1
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#define mmCM5_CM_BLNDGAM_LUT_CONTROL_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_B 0x14a2
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#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_G 0x14a3
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#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_R 0x14a4
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#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B 0x14a5
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#define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G 0x14a6
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#define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R 0x14a7
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#define mmCM5_CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_B 0x14a8
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#define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_G 0x14a9
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#define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_R 0x14aa
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#define mmCM5_CM_BLNDGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_B 0x14ab
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#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_B 0x14ac
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#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_G 0x14ad
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#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_G 0x14ae
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#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_R 0x14af
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#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_R 0x14b0
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#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_OFFSET_B 0x14b1
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#define mmCM5_CM_BLNDGAM_RAMA_OFFSET_B_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_OFFSET_G 0x14b2
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#define mmCM5_CM_BLNDGAM_RAMA_OFFSET_G_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_OFFSET_R 0x14b3
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#define mmCM5_CM_BLNDGAM_RAMA_OFFSET_R_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_0_1 0x14b4
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_2_3 0x14b5
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_4_5 0x14b6
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_6_7 0x14b7
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_8_9 0x14b8
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_10_11 0x14b9
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_12_13 0x14ba
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_14_15 0x14bb
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_16_17 0x14bc
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_18_19 0x14bd
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_20_21 0x14be
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_22_23 0x14bf
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_24_25 0x14c0
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_26_27 0x14c1
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_28_29 0x14c2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_30_31 0x14c3
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_32_33 0x14c4
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#define mmCM5_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_B 0x14c5
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#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_G 0x14c6
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#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_R 0x14c7
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#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B 0x14c8
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#define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G 0x14c9
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#define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R 0x14ca
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#define mmCM5_CM_BLNDGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_B 0x14cb
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#define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_G 0x14cc
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#define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_R 0x14cd
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#define mmCM5_CM_BLNDGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_B 0x14ce
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#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_B 0x14cf
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#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_G 0x14d0
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#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_G 0x14d1
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#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_R 0x14d2
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#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_R 0x14d3
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#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_OFFSET_B 0x14d4
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#define mmCM5_CM_BLNDGAM_RAMB_OFFSET_B_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_OFFSET_G 0x14d5
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#define mmCM5_CM_BLNDGAM_RAMB_OFFSET_G_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_OFFSET_R 0x14d6
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#define mmCM5_CM_BLNDGAM_RAMB_OFFSET_R_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_0_1 0x14d7
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_2_3 0x14d8
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_4_5 0x14d9
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_6_7 0x14da
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_8_9 0x14db
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_10_11 0x14dc
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_12_13 0x14dd
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_14_15 0x14de
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_16_17 0x14df
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_18_19 0x14e0
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_20_21 0x14e1
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_22_23 0x14e2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_24_25 0x14e3
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_26_27 0x14e4
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_28_29 0x14e5
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_30_31 0x14e6
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_32_33 0x14e7
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#define mmCM5_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM5_CM_HDR_MULT_COEF 0x14e8
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#define mmCM5_CM_HDR_MULT_COEF_BASE_IDX 2
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#define mmCM5_CM_MEM_PWR_CTRL 0x14e9
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#define mmCM5_CM_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCM5_CM_MEM_PWR_STATUS 0x14ea
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#define mmCM5_CM_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCM5_CM_DEALPHA 0x14ec
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#define mmCM5_CM_DEALPHA_BASE_IDX 2
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#define mmCM5_CM_COEF_FORMAT 0x14ed
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#define mmCM5_CM_COEF_FORMAT_BASE_IDX 2
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#define mmCM5_CM_SHAPER_CONTROL 0x14ee
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#define mmCM5_CM_SHAPER_CONTROL_BASE_IDX 2
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#define mmCM5_CM_SHAPER_OFFSET_R 0x14ef
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#define mmCM5_CM_SHAPER_OFFSET_R_BASE_IDX 2
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#define mmCM5_CM_SHAPER_OFFSET_G 0x14f0
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#define mmCM5_CM_SHAPER_OFFSET_G_BASE_IDX 2
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#define mmCM5_CM_SHAPER_OFFSET_B 0x14f1
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#define mmCM5_CM_SHAPER_OFFSET_B_BASE_IDX 2
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#define mmCM5_CM_SHAPER_SCALE_R 0x14f2
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#define mmCM5_CM_SHAPER_SCALE_R_BASE_IDX 2
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#define mmCM5_CM_SHAPER_SCALE_G_B 0x14f3
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#define mmCM5_CM_SHAPER_SCALE_G_B_BASE_IDX 2
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#define mmCM5_CM_SHAPER_LUT_INDEX 0x14f4
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#define mmCM5_CM_SHAPER_LUT_INDEX_BASE_IDX 2
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#define mmCM5_CM_SHAPER_LUT_DATA 0x14f5
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#define mmCM5_CM_SHAPER_LUT_DATA_BASE_IDX 2
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#define mmCM5_CM_SHAPER_LUT_WRITE_EN_MASK 0x14f6
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#define mmCM5_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_START_CNTL_B 0x14f7
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#define mmCM5_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_START_CNTL_G 0x14f8
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#define mmCM5_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_START_CNTL_R 0x14f9
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#define mmCM5_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_END_CNTL_B 0x14fa
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#define mmCM5_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_END_CNTL_G 0x14fb
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#define mmCM5_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_END_CNTL_R 0x14fc
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#define mmCM5_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_0_1 0x14fd
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#define mmCM5_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_2_3 0x14fe
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#define mmCM5_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_4_5 0x14ff
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#define mmCM5_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_6_7 0x1500
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#define mmCM5_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_8_9 0x1501
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#define mmCM5_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_10_11 0x1502
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#define mmCM5_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_12_13 0x1503
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#define mmCM5_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_14_15 0x1504
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#define mmCM5_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_16_17 0x1505
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#define mmCM5_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_18_19 0x1506
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#define mmCM5_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_20_21 0x1507
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#define mmCM5_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_22_23 0x1508
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#define mmCM5_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_24_25 0x1509
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#define mmCM5_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_26_27 0x150a
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#define mmCM5_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_28_29 0x150b
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#define mmCM5_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_30_31 0x150c
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#define mmCM5_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMA_REGION_32_33 0x150d
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#define mmCM5_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_START_CNTL_B 0x150e
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#define mmCM5_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_START_CNTL_G 0x150f
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#define mmCM5_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_START_CNTL_R 0x1510
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#define mmCM5_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_END_CNTL_B 0x1511
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#define mmCM5_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_END_CNTL_G 0x1512
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#define mmCM5_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_END_CNTL_R 0x1513
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#define mmCM5_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_0_1 0x1514
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#define mmCM5_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_2_3 0x1515
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#define mmCM5_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_4_5 0x1516
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#define mmCM5_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_6_7 0x1517
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#define mmCM5_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_8_9 0x1518
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#define mmCM5_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_10_11 0x1519
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#define mmCM5_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_12_13 0x151a
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#define mmCM5_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_14_15 0x151b
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#define mmCM5_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_16_17 0x151c
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#define mmCM5_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_18_19 0x151d
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#define mmCM5_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_20_21 0x151e
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#define mmCM5_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_22_23 0x151f
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#define mmCM5_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_24_25 0x1520
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#define mmCM5_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_26_27 0x1521
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#define mmCM5_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_28_29 0x1522
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#define mmCM5_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_30_31 0x1523
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#define mmCM5_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM5_CM_SHAPER_RAMB_REGION_32_33 0x1524
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#define mmCM5_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM5_CM_MEM_PWR_CTRL2 0x1525
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#define mmCM5_CM_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmCM5_CM_MEM_PWR_STATUS2 0x1526
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#define mmCM5_CM_MEM_PWR_STATUS2_BASE_IDX 2
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#define mmCM5_CM_3DLUT_MODE 0x1527
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#define mmCM5_CM_3DLUT_MODE_BASE_IDX 2
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#define mmCM5_CM_3DLUT_INDEX 0x1528
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#define mmCM5_CM_3DLUT_INDEX_BASE_IDX 2
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#define mmCM5_CM_3DLUT_DATA 0x1529
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#define mmCM5_CM_3DLUT_DATA_BASE_IDX 2
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#define mmCM5_CM_3DLUT_DATA_30BIT 0x152a
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#define mmCM5_CM_3DLUT_DATA_30BIT_BASE_IDX 2
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#define mmCM5_CM_3DLUT_READ_WRITE_CONTROL 0x152b
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#define mmCM5_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
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#define mmCM5_CM_3DLUT_OUT_NORM_FACTOR 0x152c
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#define mmCM5_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
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#define mmCM5_CM_3DLUT_OUT_OFFSET_R 0x152d
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#define mmCM5_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
|
#define mmCM5_CM_3DLUT_OUT_OFFSET_G 0x152e
|
#define mmCM5_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
|
#define mmCM5_CM_3DLUT_OUT_OFFSET_B 0x152f
|
#define mmCM5_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
|
|
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// addressBlock: dce_dc_dpp5_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x54ec
|
#define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x153b
|
#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x153c
|
#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFCOUNTER_STATE 0x153d
|
#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_CNTL 0x153e
|
#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_CNTL2 0x153f
|
#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1540
|
#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x1541
|
#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_HI 0x1542
|
#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_LOW 0x1543
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#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_opp_fmt0_dispdec
|
// base address: 0x0
|
#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c
|
#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d
|
#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e
|
#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f
|
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT0_FMT_CONTROL 0x1840
|
#define mmFMT0_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841
|
#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842
|
#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
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#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843
|
#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844
|
#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT0_FMT_CLAMP_CNTL 0x1845
|
#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846
|
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847
|
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
#define mmFMT0_FMT_422_CONTROL 0x1849
|
#define mmFMT0_FMT_422_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_opp_dpg0_dispdec
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// base address: 0x0
|
#define mmDPG0_DPG_CONTROL 0x1854
|
#define mmDPG0_DPG_CONTROL_BASE_IDX 2
|
#define mmDPG0_DPG_RAMP_CONTROL 0x1855
|
#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2
|
#define mmDPG0_DPG_DIMENSIONS 0x1856
|
#define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2
|
#define mmDPG0_DPG_COLOUR_R_CR 0x1857
|
#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2
|
#define mmDPG0_DPG_COLOUR_G_Y 0x1858
|
#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2
|
#define mmDPG0_DPG_COLOUR_B_CB 0x1859
|
#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2
|
#define mmDPG0_DPG_OFFSET_SEGMENT 0x185a
|
#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2
|
#define mmDPG0_DPG_STATUS 0x185b
|
#define mmDPG0_DPG_STATUS_BASE_IDX 2
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|
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// addressBlock: dce_dc_opp_oppbuf0_dispdec
|
// base address: 0x0
|
#define mmOPPBUF0_OPPBUF_CONTROL 0x1884
|
#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885
|
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886
|
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
|
#define mmOPPBUF0_OPPBUF_CONTROL1 0x1889
|
#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2
|
|
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// addressBlock: dce_dc_opp_opp_pipe0_dispdec
|
// base address: 0x0
|
#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c
|
#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
|
// base address: 0x0
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
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|
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// addressBlock: dce_dc_opp_fmt1_dispdec
|
// base address: 0x168
|
#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896
|
#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897
|
#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898
|
#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899
|
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT1_FMT_CONTROL 0x189a
|
#define mmFMT1_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b
|
#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c
|
#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d
|
#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e
|
#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT1_FMT_CLAMP_CNTL 0x189f
|
#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0
|
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1
|
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
#define mmFMT1_FMT_422_CONTROL 0x18a3
|
#define mmFMT1_FMT_422_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dpg1_dispdec
|
// base address: 0x168
|
#define mmDPG1_DPG_CONTROL 0x18ae
|
#define mmDPG1_DPG_CONTROL_BASE_IDX 2
|
#define mmDPG1_DPG_RAMP_CONTROL 0x18af
|
#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2
|
#define mmDPG1_DPG_DIMENSIONS 0x18b0
|
#define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2
|
#define mmDPG1_DPG_COLOUR_R_CR 0x18b1
|
#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2
|
#define mmDPG1_DPG_COLOUR_G_Y 0x18b2
|
#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2
|
#define mmDPG1_DPG_COLOUR_B_CB 0x18b3
|
#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2
|
#define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4
|
#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2
|
#define mmDPG1_DPG_STATUS 0x18b5
|
#define mmDPG1_DPG_STATUS_BASE_IDX 2
|
|
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// addressBlock: dce_dc_opp_oppbuf1_dispdec
|
// base address: 0x168
|
#define mmOPPBUF1_OPPBUF_CONTROL 0x18de
|
#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df
|
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0
|
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
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#define mmOPPBUF1_OPPBUF_CONTROL1 0x18e3
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#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2
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// addressBlock: dce_dc_opp_opp_pipe1_dispdec
|
// base address: 0x168
|
#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6
|
#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
|
// base address: 0x168
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_fmt2_dispdec
|
// base address: 0x2d0
|
#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0
|
#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1
|
#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2
|
#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3
|
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT2_FMT_CONTROL 0x18f4
|
#define mmFMT2_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5
|
#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6
|
#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7
|
#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8
|
#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT2_FMT_CLAMP_CNTL 0x18f9
|
#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa
|
#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb
|
#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
#define mmFMT2_FMT_422_CONTROL 0x18fd
|
#define mmFMT2_FMT_422_CONTROL_BASE_IDX 2
|
|
|
|
// addressBlock: dce_dc_opp_dpg2_dispdec
|
// base address: 0x2d0
|
#define mmDPG2_DPG_CONTROL 0x1908
|
#define mmDPG2_DPG_CONTROL_BASE_IDX 2
|
#define mmDPG2_DPG_RAMP_CONTROL 0x1909
|
#define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX 2
|
#define mmDPG2_DPG_DIMENSIONS 0x190a
|
#define mmDPG2_DPG_DIMENSIONS_BASE_IDX 2
|
#define mmDPG2_DPG_COLOUR_R_CR 0x190b
|
#define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX 2
|
#define mmDPG2_DPG_COLOUR_G_Y 0x190c
|
#define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX 2
|
#define mmDPG2_DPG_COLOUR_B_CB 0x190d
|
#define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX 2
|
#define mmDPG2_DPG_OFFSET_SEGMENT 0x190e
|
#define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2
|
#define mmDPG2_DPG_STATUS 0x190f
|
#define mmDPG2_DPG_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_oppbuf2_dispdec
|
// base address: 0x2d0
|
#define mmOPPBUF2_OPPBUF_CONTROL 0x1938
|
#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939
|
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a
|
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
|
#define mmOPPBUF2_OPPBUF_CONTROL1 0x193d
|
#define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe2_dispdec
|
// base address: 0x2d0
|
#define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940
|
#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
|
// base address: 0x2d0
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_fmt3_dispdec
|
// base address: 0x438
|
#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a
|
#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b
|
#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c
|
#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d
|
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT3_FMT_CONTROL 0x194e
|
#define mmFMT3_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f
|
#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950
|
#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951
|
#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952
|
#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT3_FMT_CLAMP_CNTL 0x1953
|
#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954
|
#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955
|
#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
#define mmFMT3_FMT_422_CONTROL 0x1957
|
#define mmFMT3_FMT_422_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dpg3_dispdec
|
// base address: 0x438
|
#define mmDPG3_DPG_CONTROL 0x1962
|
#define mmDPG3_DPG_CONTROL_BASE_IDX 2
|
#define mmDPG3_DPG_RAMP_CONTROL 0x1963
|
#define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX 2
|
#define mmDPG3_DPG_DIMENSIONS 0x1964
|
#define mmDPG3_DPG_DIMENSIONS_BASE_IDX 2
|
#define mmDPG3_DPG_COLOUR_R_CR 0x1965
|
#define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX 2
|
#define mmDPG3_DPG_COLOUR_G_Y 0x1966
|
#define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX 2
|
#define mmDPG3_DPG_COLOUR_B_CB 0x1967
|
#define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX 2
|
#define mmDPG3_DPG_OFFSET_SEGMENT 0x1968
|
#define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2
|
#define mmDPG3_DPG_STATUS 0x1969
|
#define mmDPG3_DPG_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_oppbuf3_dispdec
|
// base address: 0x438
|
#define mmOPPBUF3_OPPBUF_CONTROL 0x1992
|
#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993
|
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994
|
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
|
#define mmOPPBUF3_OPPBUF_CONTROL1 0x1997
|
#define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe3_dispdec
|
// base address: 0x438
|
#define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a
|
#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
|
// base address: 0x438
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
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#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2
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#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
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#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3
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#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
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// addressBlock: dce_dc_opp_fmt4_dispdec
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// base address: 0x5a0
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#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4
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#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
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#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5
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#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
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#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6
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#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
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#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7
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#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
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#define mmFMT4_FMT_CONTROL 0x19a8
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#define mmFMT4_FMT_CONTROL_BASE_IDX 2
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#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9
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#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
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#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa
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#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
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#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab
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#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
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#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac
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#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
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#define mmFMT4_FMT_CLAMP_CNTL 0x19ad
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#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
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#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19ae
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#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
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#define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19af
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#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
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#define mmFMT4_FMT_422_CONTROL 0x19b1
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#define mmFMT4_FMT_422_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_opp_dpg4_dispdec
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// base address: 0x5a0
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#define mmDPG4_DPG_CONTROL 0x19bc
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#define mmDPG4_DPG_CONTROL_BASE_IDX 2
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#define mmDPG4_DPG_RAMP_CONTROL 0x19bd
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#define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX 2
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#define mmDPG4_DPG_DIMENSIONS 0x19be
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#define mmDPG4_DPG_DIMENSIONS_BASE_IDX 2
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#define mmDPG4_DPG_COLOUR_R_CR 0x19bf
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#define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX 2
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#define mmDPG4_DPG_COLOUR_G_Y 0x19c0
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#define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX 2
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#define mmDPG4_DPG_COLOUR_B_CB 0x19c1
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#define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX 2
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#define mmDPG4_DPG_OFFSET_SEGMENT 0x19c2
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#define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX 2
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#define mmDPG4_DPG_STATUS 0x19c3
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#define mmDPG4_DPG_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_opp_oppbuf4_dispdec
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// base address: 0x5a0
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#define mmOPPBUF4_OPPBUF_CONTROL 0x19ec
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#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2
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#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed
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#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
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#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee
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#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
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#define mmOPPBUF4_OPPBUF_CONTROL1 0x19f1
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#define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX 2
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// addressBlock: dce_dc_opp_opp_pipe4_dispdec
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// base address: 0x5a0
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#define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4
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#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
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// base address: 0x5a0
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#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9
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#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
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#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa
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#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2
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#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb
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#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
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#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc
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#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
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#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd
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#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
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// addressBlock: dce_dc_opp_fmt5_dispdec
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// base address: 0x708
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#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe
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#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
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#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff
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#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
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#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00
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#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
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#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01
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#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
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#define mmFMT5_FMT_CONTROL 0x1a02
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#define mmFMT5_FMT_CONTROL_BASE_IDX 2
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#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03
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#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
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#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04
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#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
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#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05
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#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
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#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06
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#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
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#define mmFMT5_FMT_CLAMP_CNTL 0x1a07
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#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2
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#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a08
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#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
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#define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a09
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#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
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#define mmFMT5_FMT_422_CONTROL 0x1a0b
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#define mmFMT5_FMT_422_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_opp_dpg5_dispdec
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// base address: 0x708
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#define mmDPG5_DPG_CONTROL 0x1a16
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#define mmDPG5_DPG_CONTROL_BASE_IDX 2
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#define mmDPG5_DPG_RAMP_CONTROL 0x1a17
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#define mmDPG5_DPG_RAMP_CONTROL_BASE_IDX 2
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#define mmDPG5_DPG_DIMENSIONS 0x1a18
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#define mmDPG5_DPG_DIMENSIONS_BASE_IDX 2
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#define mmDPG5_DPG_COLOUR_R_CR 0x1a19
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#define mmDPG5_DPG_COLOUR_R_CR_BASE_IDX 2
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#define mmDPG5_DPG_COLOUR_G_Y 0x1a1a
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#define mmDPG5_DPG_COLOUR_G_Y_BASE_IDX 2
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#define mmDPG5_DPG_COLOUR_B_CB 0x1a1b
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#define mmDPG5_DPG_COLOUR_B_CB_BASE_IDX 2
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#define mmDPG5_DPG_OFFSET_SEGMENT 0x1a1c
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#define mmDPG5_DPG_OFFSET_SEGMENT_BASE_IDX 2
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#define mmDPG5_DPG_STATUS 0x1a1d
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#define mmDPG5_DPG_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_opp_oppbuf5_dispdec
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// base address: 0x708
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#define mmOPPBUF5_OPPBUF_CONTROL 0x1a46
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#define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2
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#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47
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#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
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#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48
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#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
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#define mmOPPBUF5_OPPBUF_CONTROL1 0x1a4b
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#define mmOPPBUF5_OPPBUF_CONTROL1_BASE_IDX 2
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// addressBlock: dce_dc_opp_opp_pipe5_dispdec
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// base address: 0x708
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#define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e
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#define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
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// base address: 0x708
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#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53
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#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
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#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54
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#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2
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#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55
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#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
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#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56
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#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
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#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57
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#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
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// addressBlock: dce_dc_opp_opp_top_dispdec
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// base address: 0x0
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#define mmOPP_TOP_CLK_CONTROL 0x1a5e
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#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2
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#define mmOPP_ABM_CONTROL 0x1a60
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#define mmOPP_ABM_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_opp_dscrm0_dispdec
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// base address: 0x0
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#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64
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#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
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// addressBlock: dce_dc_opp_dscrm1_dispdec
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// base address: 0x4
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#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65
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#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
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// addressBlock: dce_dc_opp_dscrm2_dispdec
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// base address: 0x8
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#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66
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#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
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// addressBlock: dce_dc_opp_dscrm3_dispdec
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// base address: 0xc
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#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67
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#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
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// addressBlock: dce_dc_opp_dscrm4_dispdec
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// base address: 0x10
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#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG 0x1a68
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#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
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// addressBlock: dce_dc_opp_dscrm5_dispdec
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// base address: 0x14
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#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG 0x1a69
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#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
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// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x6af8
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#define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1abe
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#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1abf
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#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1ac0
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#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON18_PERFMON_CNTL 0x1ac1
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#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON18_PERFMON_CNTL2 0x1ac2
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#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1ac3
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#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1ac4
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#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON18_PERFMON_HI 0x1ac5
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#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON18_PERFMON_LOW 0x1ac6
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#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_optc_odm0_dispdec
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// base address: 0x0
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#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca
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#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
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#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb
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#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
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#define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc
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#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
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#define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd
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#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
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#define mmODM0_OPTC_WIDTH_CONTROL 0x1ace
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#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2
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#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf
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#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
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#define mmODM0_OPTC_MEMORY_CONFIG 0x1ad0
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#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2
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#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1
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#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_odm1_dispdec
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// base address: 0x40
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#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada
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#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
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#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb
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#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
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#define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc
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#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
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#define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add
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#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
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#define mmODM1_OPTC_WIDTH_CONTROL 0x1ade
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#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2
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#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf
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#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
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#define mmODM1_OPTC_MEMORY_CONFIG 0x1ae0
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#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2
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#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1
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#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_odm2_dispdec
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// base address: 0x80
|
#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea
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#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
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#define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb
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#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
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#define mmODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec
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#define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
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#define mmODM2_OPTC_BYTES_PER_PIXEL 0x1aed
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#define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
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#define mmODM2_OPTC_WIDTH_CONTROL 0x1aee
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#define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2
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#define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef
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#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
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#define mmODM2_OPTC_MEMORY_CONFIG 0x1af0
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#define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2
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#define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1
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#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_odm3_dispdec
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// base address: 0xc0
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#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa
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#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
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#define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb
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#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
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#define mmODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc
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#define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
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#define mmODM3_OPTC_BYTES_PER_PIXEL 0x1afd
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#define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
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#define mmODM3_OPTC_WIDTH_CONTROL 0x1afe
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#define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2
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#define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff
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#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
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#define mmODM3_OPTC_MEMORY_CONFIG 0x1b00
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#define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2
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#define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01
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#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_odm4_dispdec
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// base address: 0x100
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#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a
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#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
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#define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b
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#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
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#define mmODM4_OPTC_DATA_FORMAT_CONTROL 0x1b0c
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#define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
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#define mmODM4_OPTC_BYTES_PER_PIXEL 0x1b0d
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#define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
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#define mmODM4_OPTC_WIDTH_CONTROL 0x1b0e
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#define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX 2
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#define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0f
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#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
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#define mmODM4_OPTC_MEMORY_CONFIG 0x1b10
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#define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX 2
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#define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b11
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#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_odm5_dispdec
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// base address: 0x140
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#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a
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#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
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#define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b
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#define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
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#define mmODM5_OPTC_DATA_FORMAT_CONTROL 0x1b1c
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#define mmODM5_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
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#define mmODM5_OPTC_BYTES_PER_PIXEL 0x1b1d
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#define mmODM5_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
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#define mmODM5_OPTC_WIDTH_CONTROL 0x1b1e
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#define mmODM5_OPTC_WIDTH_CONTROL_BASE_IDX 2
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#define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1f
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#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
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#define mmODM5_OPTC_MEMORY_CONFIG 0x1b20
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#define mmODM5_OPTC_MEMORY_CONFIG_BASE_IDX 2
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#define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b21
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#define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_otg0_dispdec
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// base address: 0x0
|
#define mmOTG0_OTG_H_TOTAL 0x1b2a
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#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2
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#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b
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#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2
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#define mmOTG0_OTG_H_SYNC_A 0x1b2c
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#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2
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#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d
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#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e
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#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_V_TOTAL 0x1b2f
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#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2
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#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30
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#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2
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#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31
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#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2
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#define mmOTG0_OTG_V_TOTAL_MID 0x1b32
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#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2
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#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33
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#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34
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#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35
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#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_V_BLANK_START_END 0x1b36
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#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2
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#define mmOTG0_OTG_V_SYNC_A 0x1b37
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#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2
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#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38
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#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_TRIGA_CNTL 0x1b39
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#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a
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#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b
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#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c
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#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d
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#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e
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#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f
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#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmOTG0_OTG_CONTROL 0x1b41
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#define mmOTG0_OTG_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_BLANK_CONTROL 0x1b42
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#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44
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#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45
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#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47
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#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48
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#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmOTG0_OTG_STATUS 0x1b49
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#define mmOTG0_OTG_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_STATUS_POSITION 0x1b4a
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#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b
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#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c
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#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d
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#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2
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#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e
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#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2
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#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f
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#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_COUNT_RESET 0x1b50
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#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2
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#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51
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#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52
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#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_STEREO_STATUS 0x1b53
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#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_STEREO_CONTROL 0x1b54
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#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55
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#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56
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#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57
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#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58
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#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59
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#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a
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#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b
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#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_MASTER_EN 0x1b5c
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#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2
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#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e
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#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f
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#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62
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#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63
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#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64
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#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65
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#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66
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#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67
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#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC_CNTL 0x1b68
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#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_CRC_CNTL2 0x1b69
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#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2
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#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a
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#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b
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#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c
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#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d
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#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e
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#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2
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#define mmOTG0_OTG_CRC0_DATA_B 0x1b6f
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#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2
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#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70
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#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71
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#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72
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#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73
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#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC1_DATA_RG 0x1b74
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#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2
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#define mmOTG0_OTG_CRC1_DATA_B 0x1b75
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#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2
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#define mmOTG0_OTG_CRC2_DATA_RG 0x1b76
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#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2
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#define mmOTG0_OTG_CRC2_DATA_B 0x1b77
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#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2
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#define mmOTG0_OTG_CRC3_DATA_RG 0x1b78
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#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2
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#define mmOTG0_OTG_CRC3_DATA_B 0x1b79
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#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2
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#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a
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#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b
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#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82
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#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83
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#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84
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#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85
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#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmOTG0_OTG_CLOCK_CONTROL 0x1b86
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#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87
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#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2
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#define mmOTG0_OTG_VUPDATE_PARAM 0x1b88
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#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2
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#define mmOTG0_OTG_VREADY_PARAM 0x1b89
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#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2
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#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a
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#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b
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#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG0_OTG_GSL_CONTROL 0x1b8c
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#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d
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#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2
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#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e
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#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2
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#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f
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#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
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#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90
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#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2
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#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91
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#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2
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#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92
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#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2
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#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93
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#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2
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#define mmOTG0_OTG_GLOBAL_CONTROL4 0x1b94
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#define mmOTG0_OTG_GLOBAL_CONTROL4_BASE_IDX 2
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#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b95
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#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b96
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#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_DRR_TIMING_INT_STATUS 0x1b97
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#define mmOTG0_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE 0x1b98
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#define mmOTG0_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
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#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE 0x1b99
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#define mmOTG0_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
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#define mmOTG0_OTG_DRR_TRIGGER_WINDOW 0x1b9a
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#define mmOTG0_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
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#define mmOTG0_OTG_DRR_CONTROL 0x1b9b
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#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_M_CONST_DTO0 0x1b9c
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#define mmOTG0_OTG_M_CONST_DTO0_BASE_IDX 2
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#define mmOTG0_OTG_M_CONST_DTO1 0x1b9d
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#define mmOTG0_OTG_M_CONST_DTO1_BASE_IDX 2
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#define mmOTG0_OTG_REQUEST_CONTROL 0x1b9e
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#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_DSC_START_POSITION 0x1b9f
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#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_PIPE_UPDATE_STATUS 0x1ba0
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#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_SPARE_REGISTER 0x1ba2
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#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_otg1_dispdec
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// base address: 0x200
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#define mmOTG1_OTG_H_TOTAL 0x1baa
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#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2
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#define mmOTG1_OTG_H_BLANK_START_END 0x1bab
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#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2
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#define mmOTG1_OTG_H_SYNC_A 0x1bac
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#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2
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#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad
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#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae
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#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2
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#define mmOTG1_OTG_V_TOTAL 0x1baf
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#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2
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#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0
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#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2
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#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1
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#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2
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#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2
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#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2
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#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3
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#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4
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#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5
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#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6
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#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2
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#define mmOTG1_OTG_V_SYNC_A 0x1bb7
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#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2
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#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8
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#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9
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#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2
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#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba
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#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb
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#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2
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#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc
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#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd
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#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe
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#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf
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#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmOTG1_OTG_CONTROL 0x1bc1
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#define mmOTG1_OTG_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2
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#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX
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#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4
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#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5
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#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7
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#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8
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#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmOTG1_OTG_STATUS 0x1bc9
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#define mmOTG1_OTG_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_STATUS_POSITION 0x1bca
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#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb
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#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc
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#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd
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#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2
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#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce
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#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2
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#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf
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#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_COUNT_RESET 0x1bd0
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#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2
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#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1
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#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2
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#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_STEREO_STATUS 0x1bd3
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#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4
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#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5
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#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6
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#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7
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#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8
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#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9
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#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_UPDATE_LOCK 0x1bda
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#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb
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#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_MASTER_EN 0x1bdc
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#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2
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#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde
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#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf
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#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3
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#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4
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#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5
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#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6
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#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7
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#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC_CNTL 0x1be8
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#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2
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#define mmOTG1_OTG_CRC_CNTL2 0x1be9
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#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2
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#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea
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#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb
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#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec
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#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed
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#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC0_DATA_RG 0x1bee
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#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2
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#define mmOTG1_OTG_CRC0_DATA_B 0x1bef
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#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2
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#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0
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#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1
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#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2
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#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3
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#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4
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#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2
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#define mmOTG1_OTG_CRC1_DATA_B 0x1bf5
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#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2
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#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf6
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#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2
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#define mmOTG1_OTG_CRC2_DATA_B 0x1bf7
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#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2
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#define mmOTG1_OTG_CRC3_DATA_RG 0x1bf8
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#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2
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#define mmOTG1_OTG_CRC3_DATA_B 0x1bf9
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#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2
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#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa
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#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb
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#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02
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#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03
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#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04
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#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05
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#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmOTG1_OTG_CLOCK_CONTROL 0x1c06
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#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07
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#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2
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#define mmOTG1_OTG_VUPDATE_PARAM 0x1c08
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#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2
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#define mmOTG1_OTG_VREADY_PARAM 0x1c09
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#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2
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#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a
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#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b
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#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG1_OTG_GSL_CONTROL 0x1c0c
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#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d
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#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2
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#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e
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#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2
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#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f
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#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
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#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10
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#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2
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#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11
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#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2
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#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12
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#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2
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#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13
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#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2
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#define mmOTG1_OTG_GLOBAL_CONTROL4 0x1c14
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#define mmOTG1_OTG_GLOBAL_CONTROL4_BASE_IDX 2
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#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c15
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#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c16
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#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_DRR_TIMING_INT_STATUS 0x1c17
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#define mmOTG1_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c18
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#define mmOTG1_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
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#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE 0x1c19
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#define mmOTG1_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
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#define mmOTG1_OTG_DRR_TRIGGER_WINDOW 0x1c1a
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#define mmOTG1_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
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#define mmOTG1_OTG_DRR_CONTROL 0x1c1b
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#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_M_CONST_DTO0 0x1c1c
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#define mmOTG1_OTG_M_CONST_DTO0_BASE_IDX 2
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#define mmOTG1_OTG_M_CONST_DTO1 0x1c1d
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#define mmOTG1_OTG_M_CONST_DTO1_BASE_IDX 2
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#define mmOTG1_OTG_REQUEST_CONTROL 0x1c1e
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#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_DSC_START_POSITION 0x1c1f
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#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_PIPE_UPDATE_STATUS 0x1c20
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#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_SPARE_REGISTER 0x1c22
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#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_otg2_dispdec
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// base address: 0x400
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#define mmOTG2_OTG_H_TOTAL 0x1c2a
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#define mmOTG2_OTG_H_TOTAL_BASE_IDX 2
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#define mmOTG2_OTG_H_BLANK_START_END 0x1c2b
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#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2
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#define mmOTG2_OTG_H_SYNC_A 0x1c2c
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#define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2
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#define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d
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#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e
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#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_V_TOTAL 0x1c2f
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#define mmOTG2_OTG_V_TOTAL_BASE_IDX 2
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#define mmOTG2_OTG_V_TOTAL_MIN 0x1c30
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#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2
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#define mmOTG2_OTG_V_TOTAL_MAX 0x1c31
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#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2
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#define mmOTG2_OTG_V_TOTAL_MID 0x1c32
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#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2
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#define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33
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#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34
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#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35
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#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_V_BLANK_START_END 0x1c36
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#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2
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#define mmOTG2_OTG_V_SYNC_A 0x1c37
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#define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2
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#define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38
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#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_TRIGA_CNTL 0x1c39
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#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a
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#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG2_OTG_TRIGB_CNTL 0x1c3b
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#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c
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#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d
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#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_FLOW_CONTROL 0x1c3e
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#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f
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#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmOTG2_OTG_CONTROL 0x1c41
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#define mmOTG2_OTG_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_BLANK_CONTROL 0x1c42
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#define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44
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#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_INTERLACE_STATUS 0x1c45
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#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47
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#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48
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#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmOTG2_OTG_STATUS 0x1c49
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#define mmOTG2_OTG_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_STATUS_POSITION 0x1c4a
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#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b
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#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c
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#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d
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#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2
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#define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e
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#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2
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#define mmOTG2_OTG_COUNT_CONTROL 0x1c4f
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#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_COUNT_RESET 0x1c50
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#define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2
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#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51
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#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52
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#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_STEREO_STATUS 0x1c53
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#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_STEREO_CONTROL 0x1c54
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#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55
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#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56
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#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57
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#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58
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#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59
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#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_UPDATE_LOCK 0x1c5a
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#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b
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#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_MASTER_EN 0x1c5c
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#define mmOTG2_OTG_MASTER_EN_BASE_IDX 2
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#define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c5e
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#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c5f
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#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62
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#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63
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#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64
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#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65
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#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66
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#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67
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#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC_CNTL 0x1c68
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#define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_CRC_CNTL2 0x1c69
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#define mmOTG2_OTG_CRC_CNTL2_BASE_IDX 2
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#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a
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#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b
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#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c
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#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d
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#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC0_DATA_RG 0x1c6e
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#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2
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#define mmOTG2_OTG_CRC0_DATA_B 0x1c6f
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#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2
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#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70
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#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71
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#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72
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#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73
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#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC1_DATA_RG 0x1c74
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#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2
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#define mmOTG2_OTG_CRC1_DATA_B 0x1c75
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#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2
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#define mmOTG2_OTG_CRC2_DATA_RG 0x1c76
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#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2
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#define mmOTG2_OTG_CRC2_DATA_B 0x1c77
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#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2
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#define mmOTG2_OTG_CRC3_DATA_RG 0x1c78
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#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2
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#define mmOTG2_OTG_CRC3_DATA_B 0x1c79
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#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2
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#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a
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#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b
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#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82
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#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83
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#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c84
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#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c85
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#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmOTG2_OTG_CLOCK_CONTROL 0x1c86
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#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_VSTARTUP_PARAM 0x1c87
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#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2
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#define mmOTG2_OTG_VUPDATE_PARAM 0x1c88
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#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2
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#define mmOTG2_OTG_VREADY_PARAM 0x1c89
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#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2
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#define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a
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#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b
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#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG2_OTG_GSL_CONTROL 0x1c8c
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#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_GSL_WINDOW_X 0x1c8d
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#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2
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#define mmOTG2_OTG_GSL_WINDOW_Y 0x1c8e
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#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2
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#define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f
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#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
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#define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c90
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#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2
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#define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c91
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#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2
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#define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c92
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#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2
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#define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c93
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#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2
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#define mmOTG2_OTG_GLOBAL_CONTROL4 0x1c94
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#define mmOTG2_OTG_GLOBAL_CONTROL4_BASE_IDX 2
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#define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c95
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#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c96
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#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_DRR_TIMING_INT_STATUS 0x1c97
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#define mmOTG2_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE 0x1c98
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#define mmOTG2_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
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#define mmOTG2_OTG_DRR_V_TOTAL_CHANGE 0x1c99
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#define mmOTG2_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
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#define mmOTG2_OTG_DRR_TRIGGER_WINDOW 0x1c9a
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#define mmOTG2_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
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#define mmOTG2_OTG_DRR_CONTROL 0x1c9b
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#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_M_CONST_DTO0 0x1c9c
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#define mmOTG2_OTG_M_CONST_DTO0_BASE_IDX 2
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#define mmOTG2_OTG_M_CONST_DTO1 0x1c9d
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#define mmOTG2_OTG_M_CONST_DTO1_BASE_IDX 2
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#define mmOTG2_OTG_REQUEST_CONTROL 0x1c9e
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#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_DSC_START_POSITION 0x1c9f
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#define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_PIPE_UPDATE_STATUS 0x1ca0
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#define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_SPARE_REGISTER 0x1ca2
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#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_otg3_dispdec
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// base address: 0x600
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#define mmOTG3_OTG_H_TOTAL 0x1caa
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#define mmOTG3_OTG_H_TOTAL_BASE_IDX 2
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#define mmOTG3_OTG_H_BLANK_START_END 0x1cab
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#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2
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#define mmOTG3_OTG_H_SYNC_A 0x1cac
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#define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2
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#define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad
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#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_H_TIMING_CNTL 0x1cae
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#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_V_TOTAL 0x1caf
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#define mmOTG3_OTG_V_TOTAL_BASE_IDX 2
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#define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0
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#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2
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#define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1
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#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2
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#define mmOTG3_OTG_V_TOTAL_MID 0x1cb2
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#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2
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#define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3
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#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4
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#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5
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#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_V_BLANK_START_END 0x1cb6
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#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2
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#define mmOTG3_OTG_V_SYNC_A 0x1cb7
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#define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2
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#define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8
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#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_TRIGA_CNTL 0x1cb9
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#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba
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#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG3_OTG_TRIGB_CNTL 0x1cbb
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#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc
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#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd
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#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_FLOW_CONTROL 0x1cbe
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#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf
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#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmOTG3_OTG_CONTROL 0x1cc1
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#define mmOTG3_OTG_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_BLANK_CONTROL 0x1cc2
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#define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4
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#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5
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#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7
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#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8
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#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmOTG3_OTG_STATUS 0x1cc9
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#define mmOTG3_OTG_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_STATUS_POSITION 0x1cca
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#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb
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#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc
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#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd
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#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2
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#define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce
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#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2
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#define mmOTG3_OTG_COUNT_CONTROL 0x1ccf
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#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_COUNT_RESET 0x1cd0
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#define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2
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#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1
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#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2
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#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_STEREO_STATUS 0x1cd3
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#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_STEREO_CONTROL 0x1cd4
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#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5
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#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6
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#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7
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#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8
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#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9
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#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_UPDATE_LOCK 0x1cda
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#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb
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#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_MASTER_EN 0x1cdc
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#define mmOTG3_OTG_MASTER_EN_BASE_IDX 2
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#define mmOTG3_OTG_BLANK_DATA_COLOR 0x1cde
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#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1cdf
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#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3
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#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4
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#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5
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#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6
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#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7
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#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC_CNTL 0x1ce8
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#define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_CRC_CNTL2 0x1ce9
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#define mmOTG3_OTG_CRC_CNTL2_BASE_IDX 2
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#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea
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#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb
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#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec
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#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced
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#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC0_DATA_RG 0x1cee
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#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2
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#define mmOTG3_OTG_CRC0_DATA_B 0x1cef
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#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2
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#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0
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#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1
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#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2
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#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3
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#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC1_DATA_RG 0x1cf4
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#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2
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#define mmOTG3_OTG_CRC1_DATA_B 0x1cf5
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#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2
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#define mmOTG3_OTG_CRC2_DATA_RG 0x1cf6
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#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2
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#define mmOTG3_OTG_CRC2_DATA_B 0x1cf7
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#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2
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#define mmOTG3_OTG_CRC3_DATA_RG 0x1cf8
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#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2
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#define mmOTG3_OTG_CRC3_DATA_B 0x1cf9
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#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2
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#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa
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#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb
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#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02
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#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03
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#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d04
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#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d05
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#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmOTG3_OTG_CLOCK_CONTROL 0x1d06
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#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_VSTARTUP_PARAM 0x1d07
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#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2
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#define mmOTG3_OTG_VUPDATE_PARAM 0x1d08
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#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2
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#define mmOTG3_OTG_VREADY_PARAM 0x1d09
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#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2
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#define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a
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#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b
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#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG3_OTG_GSL_CONTROL 0x1d0c
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#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_GSL_WINDOW_X 0x1d0d
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#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2
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#define mmOTG3_OTG_GSL_WINDOW_Y 0x1d0e
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#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2
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#define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f
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#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
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#define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d10
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#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2
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#define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d11
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#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2
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#define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d12
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#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2
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#define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d13
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#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2
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#define mmOTG3_OTG_GLOBAL_CONTROL4 0x1d14
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#define mmOTG3_OTG_GLOBAL_CONTROL4_BASE_IDX 2
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#define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d15
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#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d16
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#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_DRR_TIMING_INT_STATUS 0x1d17
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#define mmOTG3_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d18
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#define mmOTG3_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
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#define mmOTG3_OTG_DRR_V_TOTAL_CHANGE 0x1d19
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#define mmOTG3_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
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#define mmOTG3_OTG_DRR_TRIGGER_WINDOW 0x1d1a
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#define mmOTG3_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
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#define mmOTG3_OTG_DRR_CONTROL 0x1d1b
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#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_M_CONST_DTO0 0x1d1c
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#define mmOTG3_OTG_M_CONST_DTO0_BASE_IDX 2
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#define mmOTG3_OTG_M_CONST_DTO1 0x1d1d
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#define mmOTG3_OTG_M_CONST_DTO1_BASE_IDX 2
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#define mmOTG3_OTG_REQUEST_CONTROL 0x1d1e
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#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_DSC_START_POSITION 0x1d1f
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#define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_PIPE_UPDATE_STATUS 0x1d20
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#define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_SPARE_REGISTER 0x1d22
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#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2
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|
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// addressBlock: dce_dc_optc_otg4_dispdec
|
// base address: 0x800
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#define mmOTG4_OTG_H_TOTAL 0x1d2a
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#define mmOTG4_OTG_H_TOTAL_BASE_IDX 2
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#define mmOTG4_OTG_H_BLANK_START_END 0x1d2b
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#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2
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#define mmOTG4_OTG_H_SYNC_A 0x1d2c
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#define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2
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#define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d
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#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e
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#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_V_TOTAL 0x1d2f
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#define mmOTG4_OTG_V_TOTAL_BASE_IDX 2
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#define mmOTG4_OTG_V_TOTAL_MIN 0x1d30
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#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2
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#define mmOTG4_OTG_V_TOTAL_MAX 0x1d31
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#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2
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#define mmOTG4_OTG_V_TOTAL_MID 0x1d32
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#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2
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#define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33
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#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34
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#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35
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#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_V_BLANK_START_END 0x1d36
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#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2
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#define mmOTG4_OTG_V_SYNC_A 0x1d37
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#define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2
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#define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38
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#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_TRIGA_CNTL 0x1d39
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#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a
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#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG4_OTG_TRIGB_CNTL 0x1d3b
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#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c
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#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d
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#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_FLOW_CONTROL 0x1d3e
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#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f
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#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmOTG4_OTG_CONTROL 0x1d41
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#define mmOTG4_OTG_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_BLANK_CONTROL 0x1d42
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#define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44
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#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_INTERLACE_STATUS 0x1d45
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#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47
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#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48
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#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmOTG4_OTG_STATUS 0x1d49
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#define mmOTG4_OTG_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_STATUS_POSITION 0x1d4a
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#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b
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#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c
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#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d
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#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2
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#define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e
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#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2
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#define mmOTG4_OTG_COUNT_CONTROL 0x1d4f
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#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_COUNT_RESET 0x1d50
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#define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2
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#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51
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#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52
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#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_STEREO_STATUS 0x1d53
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#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_STEREO_CONTROL 0x1d54
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#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55
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#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56
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#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57
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#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58
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#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59
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#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_UPDATE_LOCK 0x1d5a
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#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b
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#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_MASTER_EN 0x1d5c
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#define mmOTG4_OTG_MASTER_EN_BASE_IDX 2
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#define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d5e
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#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d5f
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#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d62
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#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d63
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#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d64
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#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d65
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#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d66
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#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d67
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#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC_CNTL 0x1d68
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#define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_CRC_CNTL2 0x1d69
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#define mmOTG4_OTG_CRC_CNTL2_BASE_IDX 2
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#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6a
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#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6b
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#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6c
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#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6d
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#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC0_DATA_RG 0x1d6e
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#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2
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#define mmOTG4_OTG_CRC0_DATA_B 0x1d6f
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#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2
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#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d70
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#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d71
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#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d72
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#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d73
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#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC1_DATA_RG 0x1d74
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#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2
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#define mmOTG4_OTG_CRC1_DATA_B 0x1d75
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#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2
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#define mmOTG4_OTG_CRC2_DATA_RG 0x1d76
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#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2
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#define mmOTG4_OTG_CRC2_DATA_B 0x1d77
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#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2
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#define mmOTG4_OTG_CRC3_DATA_RG 0x1d78
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#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2
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#define mmOTG4_OTG_CRC3_DATA_B 0x1d79
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#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2
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#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7a
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#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7b
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#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d82
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#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d83
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#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d84
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#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d85
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#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmOTG4_OTG_CLOCK_CONTROL 0x1d86
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#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_VSTARTUP_PARAM 0x1d87
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#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2
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#define mmOTG4_OTG_VUPDATE_PARAM 0x1d88
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#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2
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#define mmOTG4_OTG_VREADY_PARAM 0x1d89
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#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2
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#define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8a
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#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8b
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#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG4_OTG_GSL_CONTROL 0x1d8c
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#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_GSL_WINDOW_X 0x1d8d
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#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2
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#define mmOTG4_OTG_GSL_WINDOW_Y 0x1d8e
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#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2
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#define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d8f
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#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
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#define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d90
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#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2
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#define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d91
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#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2
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#define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d92
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#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2
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#define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d93
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#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2
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#define mmOTG4_OTG_GLOBAL_CONTROL4 0x1d94
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#define mmOTG4_OTG_GLOBAL_CONTROL4_BASE_IDX 2
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#define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d95
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#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d96
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#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_DRR_TIMING_INT_STATUS 0x1d97
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#define mmOTG4_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_DRR_V_TOTAL_REACH_RANGE 0x1d98
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#define mmOTG4_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
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#define mmOTG4_OTG_DRR_V_TOTAL_CHANGE 0x1d99
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#define mmOTG4_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
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#define mmOTG4_OTG_DRR_TRIGGER_WINDOW 0x1d9a
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#define mmOTG4_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
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#define mmOTG4_OTG_DRR_CONTROL 0x1d9b
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#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_M_CONST_DTO0 0x1d9c
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#define mmOTG4_OTG_M_CONST_DTO0_BASE_IDX 2
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#define mmOTG4_OTG_M_CONST_DTO1 0x1d9d
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#define mmOTG4_OTG_M_CONST_DTO1_BASE_IDX 2
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#define mmOTG4_OTG_REQUEST_CONTROL 0x1d9e
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#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_DSC_START_POSITION 0x1d9f
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#define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_PIPE_UPDATE_STATUS 0x1da0
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#define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_SPARE_REGISTER 0x1da2
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#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2
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|
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// addressBlock: dce_dc_optc_otg5_dispdec
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// base address: 0xa00
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#define mmOTG5_OTG_H_TOTAL 0x1daa
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#define mmOTG5_OTG_H_TOTAL_BASE_IDX 2
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#define mmOTG5_OTG_H_BLANK_START_END 0x1dab
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#define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2
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#define mmOTG5_OTG_H_SYNC_A 0x1dac
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#define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2
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#define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad
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#define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_H_TIMING_CNTL 0x1dae
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#define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_V_TOTAL 0x1daf
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#define mmOTG5_OTG_V_TOTAL_BASE_IDX 2
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#define mmOTG5_OTG_V_TOTAL_MIN 0x1db0
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#define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2
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#define mmOTG5_OTG_V_TOTAL_MAX 0x1db1
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#define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2
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#define mmOTG5_OTG_V_TOTAL_MID 0x1db2
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#define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2
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#define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3
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#define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4
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#define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5
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#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_V_BLANK_START_END 0x1db6
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#define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2
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#define mmOTG5_OTG_V_SYNC_A 0x1db7
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#define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2
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#define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8
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#define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_TRIGA_CNTL 0x1db9
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#define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba
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#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG5_OTG_TRIGB_CNTL 0x1dbb
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#define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc
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#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd
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#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_FLOW_CONTROL 0x1dbe
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#define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf
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#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmOTG5_OTG_CONTROL 0x1dc1
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#define mmOTG5_OTG_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_BLANK_CONTROL 0x1dc2
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#define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4
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#define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5
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#define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7
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#define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8
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#define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmOTG5_OTG_STATUS 0x1dc9
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#define mmOTG5_OTG_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_STATUS_POSITION 0x1dca
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#define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb
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#define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc
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#define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd
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#define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2
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#define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce
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#define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2
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#define mmOTG5_OTG_COUNT_CONTROL 0x1dcf
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#define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_COUNT_RESET 0x1dd0
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#define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2
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#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1
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#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2
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#define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_STEREO_STATUS 0x1dd3
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#define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_STEREO_CONTROL 0x1dd4
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#define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5
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#define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6
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#define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7
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#define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8
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#define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9
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#define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_UPDATE_LOCK 0x1dda
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#define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb
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#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_MASTER_EN 0x1ddc
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#define mmOTG5_OTG_MASTER_EN_BASE_IDX 2
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#define mmOTG5_OTG_BLANK_DATA_COLOR 0x1dde
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#define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1ddf
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#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de3
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#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de4
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#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de5
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#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de6
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#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1de7
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#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC_CNTL 0x1de8
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#define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_CRC_CNTL2 0x1de9
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#define mmOTG5_OTG_CRC_CNTL2_BASE_IDX 2
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#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dea
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#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1deb
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#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dec
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#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ded
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#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC0_DATA_RG 0x1dee
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#define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2
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#define mmOTG5_OTG_CRC0_DATA_B 0x1def
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#define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2
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#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df0
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#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df1
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#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df2
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#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df3
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#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC1_DATA_RG 0x1df4
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#define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2
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#define mmOTG5_OTG_CRC1_DATA_B 0x1df5
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#define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2
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#define mmOTG5_OTG_CRC2_DATA_RG 0x1df6
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#define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2
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#define mmOTG5_OTG_CRC2_DATA_B 0x1df7
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#define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2
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#define mmOTG5_OTG_CRC3_DATA_RG 0x1df8
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#define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2
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#define mmOTG5_OTG_CRC3_DATA_B 0x1df9
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#define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2
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#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfa
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#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfb
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#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e02
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#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e03
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#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e04
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#define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e05
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#define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmOTG5_OTG_CLOCK_CONTROL 0x1e06
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#define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_VSTARTUP_PARAM 0x1e07
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#define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2
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#define mmOTG5_OTG_VUPDATE_PARAM 0x1e08
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#define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2
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#define mmOTG5_OTG_VREADY_PARAM 0x1e09
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#define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2
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#define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0a
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#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0b
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#define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG5_OTG_GSL_CONTROL 0x1e0c
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#define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_GSL_WINDOW_X 0x1e0d
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#define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2
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#define mmOTG5_OTG_GSL_WINDOW_Y 0x1e0e
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#define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2
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#define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e0f
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#define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
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#define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e10
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#define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2
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#define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e11
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#define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2
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#define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e12
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#define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2
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#define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e13
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#define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2
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#define mmOTG5_OTG_GLOBAL_CONTROL4 0x1e14
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#define mmOTG5_OTG_GLOBAL_CONTROL4_BASE_IDX 2
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#define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e15
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#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e16
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#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_DRR_TIMING_INT_STATUS 0x1e17
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#define mmOTG5_OTG_DRR_TIMING_INT_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_DRR_V_TOTAL_REACH_RANGE 0x1e18
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#define mmOTG5_OTG_DRR_V_TOTAL_REACH_RANGE_BASE_IDX 2
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#define mmOTG5_OTG_DRR_V_TOTAL_CHANGE 0x1e19
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#define mmOTG5_OTG_DRR_V_TOTAL_CHANGE_BASE_IDX 2
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#define mmOTG5_OTG_DRR_TRIGGER_WINDOW 0x1e1a
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#define mmOTG5_OTG_DRR_TRIGGER_WINDOW_BASE_IDX 2
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#define mmOTG5_OTG_DRR_CONTROL 0x1e1b
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#define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_M_CONST_DTO0 0x1e1c
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#define mmOTG5_OTG_M_CONST_DTO0_BASE_IDX 2
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#define mmOTG5_OTG_M_CONST_DTO1 0x1e1d
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#define mmOTG5_OTG_M_CONST_DTO1_BASE_IDX 2
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#define mmOTG5_OTG_REQUEST_CONTROL 0x1e1e
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#define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_DSC_START_POSITION 0x1e1f
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#define mmOTG5_OTG_DSC_START_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_PIPE_UPDATE_STATUS 0x1e20
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#define mmOTG5_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_SPARE_REGISTER 0x1e22
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#define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_optc_misc_dispdec
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// base address: 0x0
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#define mmDWB_SOURCE_SELECT 0x1e2a
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#define mmDWB_SOURCE_SELECT_BASE_IDX 2
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#define mmGSL_SOURCE_SELECT 0x1e2b
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#define mmGSL_SOURCE_SELECT_BASE_IDX 2
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#define mmOPTC_CLOCK_CONTROL 0x1e2c
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#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2
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#define mmODM_MEM_PWR_CTRL 0x1e2d
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#define mmODM_MEM_PWR_CTRL_BASE_IDX 2
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#define mmODM_MEM_PWR_CTRL2 0x1e2e
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#define mmODM_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmODM_MEM_PWR_CTRL3 0x1e2f
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#define mmODM_MEM_PWR_CTRL3_BASE_IDX 2
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#define mmODM_MEM_PWR_STATUS 0x1e30
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#define mmODM_MEM_PWR_STATUS_BASE_IDX 2
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#define mmOPTC_MISC_SPARE_REGISTER 0x1e31
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#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
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// base address: 0x79a8
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#define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x1e6a
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#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x1e6b
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#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON19_PERFCOUNTER_STATE 0x1e6c
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#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON19_PERFMON_CNTL 0x1e6d
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#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON19_PERFMON_CNTL2 0x1e6e
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#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x1e6f
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#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x1e70
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#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON19_PERFMON_HI 0x1e71
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#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON19_PERFMON_LOW 0x1e72
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#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dio_dout_i2c_dispdec
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// base address: 0x0
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#define mmDC_I2C_CONTROL 0x1e98
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#define mmDC_I2C_CONTROL_BASE_IDX 2
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#define mmDC_I2C_ARBITRATION 0x1e99
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#define mmDC_I2C_ARBITRATION_BASE_IDX 2
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#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a
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#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDC_I2C_SW_STATUS 0x1e9b
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#define mmDC_I2C_SW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c
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#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d
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#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC3_HW_STATUS 0x1e9e
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#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC4_HW_STATUS 0x1e9f
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#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC5_HW_STATUS 0x1ea0
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#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC6_HW_STATUS 0x1ea1
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#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
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#define mmDC_I2C_DDC1_SPEED 0x1ea2
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#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC1_SETUP 0x1ea3
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#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC2_SPEED 0x1ea4
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#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC2_SETUP 0x1ea5
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#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC3_SPEED 0x1ea6
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#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC3_SETUP 0x1ea7
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#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC4_SPEED 0x1ea8
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#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC4_SETUP 0x1ea9
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#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC5_SPEED 0x1eaa
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#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC5_SETUP 0x1eab
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#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC6_SPEED 0x1eac
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#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC6_SETUP 0x1ead
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#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
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#define mmDC_I2C_TRANSACTION0 0x1eae
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#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
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#define mmDC_I2C_TRANSACTION1 0x1eaf
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#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
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#define mmDC_I2C_TRANSACTION2 0x1eb0
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#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
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#define mmDC_I2C_TRANSACTION3 0x1eb1
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#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
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#define mmDC_I2C_DATA 0x1eb2
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#define mmDC_I2C_DATA_BASE_IDX 2
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#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6
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#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
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#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7
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#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
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// addressBlock: dce_dc_dio_dio_misc_dispdec
|
// base address: 0x0
|
#define mmDIO_SCRATCH0 0x1eca
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#define mmDIO_SCRATCH0_BASE_IDX 2
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#define mmDIO_SCRATCH1 0x1ecb
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#define mmDIO_SCRATCH1_BASE_IDX 2
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#define mmDIO_SCRATCH2 0x1ecc
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#define mmDIO_SCRATCH2_BASE_IDX 2
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#define mmDIO_SCRATCH3 0x1ecd
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#define mmDIO_SCRATCH3_BASE_IDX 2
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#define mmDIO_SCRATCH4 0x1ece
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#define mmDIO_SCRATCH4_BASE_IDX 2
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#define mmDIO_SCRATCH5 0x1ecf
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#define mmDIO_SCRATCH5_BASE_IDX 2
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#define mmDIO_SCRATCH6 0x1ed0
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#define mmDIO_SCRATCH6_BASE_IDX 2
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#define mmDIO_SCRATCH7 0x1ed1
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#define mmDIO_SCRATCH7_BASE_IDX 2
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#define mmDIO_MEM_PWR_STATUS 0x1edd
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#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDIO_MEM_PWR_CTRL 0x1ede
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#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDIO_MEM_PWR_CTRL2 0x1edf
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#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2
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#define mmDIO_CLK_CNTL 0x1ee0
|
#define mmDIO_CLK_CNTL_BASE_IDX 2
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#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4
|
#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
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#define mmDIG_SOFT_RESET 0x1eee
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#define mmDIG_SOFT_RESET_BASE_IDX 2
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#define mmDIO_CLK_CNTL2 0x1ef2
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#define mmDIO_CLK_CNTL2_BASE_IDX 2
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#define mmDIO_CLK_CNTL3 0x1ef3
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#define mmDIO_CLK_CNTL3_BASE_IDX 2
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#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff
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#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
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#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02
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#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
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#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03
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#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
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// addressBlock: dce_dc_dio_hpd0_dispdec
|
// base address: 0x0
|
#define mmHPD0_DC_HPD_INT_STATUS 0x1f14
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#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15
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#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD0_DC_HPD_CONTROL 0x1f16
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#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17
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#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18
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#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_hpd1_dispdec
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// base address: 0x20
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#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c
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#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d
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#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD1_DC_HPD_CONTROL 0x1f1e
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#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f
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#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20
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#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_hpd2_dispdec
|
// base address: 0x40
|
#define mmHPD2_DC_HPD_INT_STATUS 0x1f24
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#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD2_DC_HPD_INT_CONTROL 0x1f25
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#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD2_DC_HPD_CONTROL 0x1f26
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#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27
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#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28
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#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_hpd3_dispdec
|
// base address: 0x60
|
#define mmHPD3_DC_HPD_INT_STATUS 0x1f2c
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#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d
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#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD3_DC_HPD_CONTROL 0x1f2e
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#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f
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#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30
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#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_hpd4_dispdec
|
// base address: 0x80
|
#define mmHPD4_DC_HPD_INT_STATUS 0x1f34
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#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD4_DC_HPD_INT_CONTROL 0x1f35
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#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD4_DC_HPD_CONTROL 0x1f36
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#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37
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#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38
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#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_hpd5_dispdec
|
// base address: 0xa0
|
#define mmHPD5_DC_HPD_INT_STATUS 0x1f3c
|
#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2
|
#define mmHPD5_DC_HPD_INT_CONTROL 0x1f3d
|
#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2
|
#define mmHPD5_DC_HPD_CONTROL 0x1f3e
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#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x1f3f
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#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x1f40
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#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x7d10
|
#define mmDC_PERFMON20_PERFCOUNTER_CNTL 0x1f44
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#define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFCOUNTER_CNTL2 0x1f45
|
#define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFCOUNTER_STATE 0x1f46
|
#define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFMON_CNTL 0x1f47
|
#define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFMON_CNTL2 0x1f48
|
#define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x1f49
|
#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFMON_CVALUE_LOW 0x1f4a
|
#define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON20_PERFMON_HI 0x1f4b
|
#define mmDC_PERFMON20_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON20_PERFMON_LOW 0x1f4c
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#define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX 2
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|
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// addressBlock: dce_dc_dio_dp_aux0_dispdec
|
// base address: 0x0
|
#define mmDP_AUX0_AUX_CONTROL 0x1f50
|
#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51
|
#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52
|
#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53
|
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_SW_STATUS 0x1f54
|
#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX0_AUX_LS_STATUS 0x1f55
|
#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX0_AUX_SW_DATA 0x1f56
|
#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
|
#define mmDP_AUX0_AUX_LS_DATA 0x1f57
|
#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58
|
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59
|
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a
|
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b
|
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c
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#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d
|
#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e
|
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f
|
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60
|
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
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#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61
|
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
#define mmDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66
|
#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp_aux1_dispdec
|
// base address: 0x70
|
#define mmDP_AUX1_AUX_CONTROL 0x1f6c
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#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d
|
#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e
|
#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
|
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f
|
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDP_AUX1_AUX_SW_STATUS 0x1f70
|
#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_LS_STATUS 0x1f71
|
#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_SW_DATA 0x1f72
|
#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX1_AUX_LS_DATA 0x1f73
|
#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
|
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74
|
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75
|
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76
|
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
|
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77
|
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78
|
#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79
|
#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a
|
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
|
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b
|
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c
|
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d
|
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82
|
#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2
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|
|
// addressBlock: dce_dc_dio_dp_aux2_dispdec
|
// base address: 0xe0
|
#define mmDP_AUX2_AUX_CONTROL 0x1f88
|
#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_SW_CONTROL 0x1f89
|
#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a
|
#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b
|
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_SW_STATUS 0x1f8c
|
#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_LS_STATUS 0x1f8d
|
#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_SW_DATA 0x1f8e
|
#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
|
#define mmDP_AUX2_AUX_LS_DATA 0x1f8f
|
#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90
|
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91
|
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92
|
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93
|
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94
|
#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95
|
#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96
|
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97
|
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98
|
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99
|
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e
|
#define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2
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|
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// addressBlock: dce_dc_dio_dp_aux3_dispdec
|
// base address: 0x150
|
#define mmDP_AUX3_AUX_CONTROL 0x1fa4
|
#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5
|
#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6
|
#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7
|
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_SW_STATUS 0x1fa8
|
#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
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#define mmDP_AUX3_AUX_LS_STATUS 0x1fa9
|
#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_SW_DATA 0x1faa
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#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX3_AUX_LS_DATA 0x1fab
|
#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac
|
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad
|
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae
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#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf
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#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0
|
#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1
|
#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2
|
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3
|
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4
|
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5
|
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba
|
#define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2
|
|
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// addressBlock: dce_dc_dio_dp_aux4_dispdec
|
// base address: 0x1c0
|
#define mmDP_AUX4_AUX_CONTROL 0x1fc0
|
#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1
|
#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2
|
#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3
|
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_SW_STATUS 0x1fc4
|
#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX4_AUX_LS_STATUS 0x1fc5
|
#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX4_AUX_SW_DATA 0x1fc6
|
#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
|
#define mmDP_AUX4_AUX_LS_DATA 0x1fc7
|
#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
|
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8
|
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9
|
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca
|
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
|
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb
|
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc
|
#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd
|
#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
|
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce
|
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf
|
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0
|
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1
|
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
#define mmDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6
|
#define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp_aux5_dispdec
|
// base address: 0x230
|
#define mmDP_AUX5_AUX_CONTROL 0x1fdc
|
#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_SW_CONTROL 0x1fdd
|
#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_ARB_CONTROL 0x1fde
|
#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x1fdf
|
#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_SW_STATUS 0x1fe0
|
#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX5_AUX_LS_STATUS 0x1fe1
|
#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX5_AUX_SW_DATA 0x1fe2
|
#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2
|
#define mmDP_AUX5_AUX_LS_DATA 0x1fe3
|
#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x1fe4
|
#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x1fe5
|
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x1fe6
|
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x1fe7
|
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x1fe8
|
#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x1fe9
|
#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2
|
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x1fea
|
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1feb
|
#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fec
|
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1fed
|
#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
#define mmDP_AUX5_AUX_PHY_WAKE_CNTL 0x1ff2
|
#define mmDP_AUX5_AUX_PHY_WAKE_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dig0_vpg_vpg_dispdec
|
// base address: 0x154a0
|
#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2068
|
#define mmVPG0_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
|
#define mmVPG0_VPG_GENERIC_PACKET_DATA 0x2069
|
#define mmVPG0_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
|
#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL 0x206a
|
#define mmVPG0_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
|
#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x206b
|
#define mmVPG0_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
|
#define mmVPG0_VPG_GENERIC_STATUS 0x206c
|
#define mmVPG0_VPG_GENERIC_STATUS_BASE_IDX 2
|
#define mmVPG0_VPG_MEM_PWR 0x206d
|
#define mmVPG0_VPG_MEM_PWR_BASE_IDX 2
|
#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL 0x206e
|
#define mmVPG0_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
|
#define mmVPG0_VPG_ISRC1_2_DATA 0x206f
|
#define mmVPG0_VPG_ISRC1_2_DATA_BASE_IDX 2
|
#define mmVPG0_VPG_MPEG_INFO0 0x2070
|
#define mmVPG0_VPG_MPEG_INFO0_BASE_IDX 2
|
#define mmVPG0_VPG_MPEG_INFO1 0x2071
|
#define mmVPG0_VPG_MPEG_INFO1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dig0_afmt_afmt_dispdec
|
// base address: 0x154cc
|
#define mmAFMT0_AFMT_VBI_PACKET_CONTROL 0x2074
|
#define mmAFMT0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2 0x2075
|
#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
|
#define mmAFMT0_AFMT_AUDIO_INFO0 0x2076
|
#define mmAFMT0_AFMT_AUDIO_INFO0_BASE_IDX 2
|
#define mmAFMT0_AFMT_AUDIO_INFO1 0x2077
|
#define mmAFMT0_AFMT_AUDIO_INFO1_BASE_IDX 2
|
#define mmAFMT0_AFMT_60958_0 0x2078
|
#define mmAFMT0_AFMT_60958_0_BASE_IDX 2
|
#define mmAFMT0_AFMT_60958_1 0x2079
|
#define mmAFMT0_AFMT_60958_1_BASE_IDX 2
|
#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL 0x207a
|
#define mmAFMT0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
|
#define mmAFMT0_AFMT_RAMP_CONTROL0 0x207b
|
#define mmAFMT0_AFMT_RAMP_CONTROL0_BASE_IDX 2
|
#define mmAFMT0_AFMT_RAMP_CONTROL1 0x207c
|
#define mmAFMT0_AFMT_RAMP_CONTROL1_BASE_IDX 2
|
#define mmAFMT0_AFMT_RAMP_CONTROL2 0x207d
|
#define mmAFMT0_AFMT_RAMP_CONTROL2_BASE_IDX 2
|
#define mmAFMT0_AFMT_RAMP_CONTROL3 0x207e
|
#define mmAFMT0_AFMT_RAMP_CONTROL3_BASE_IDX 2
|
#define mmAFMT0_AFMT_60958_2 0x207f
|
#define mmAFMT0_AFMT_60958_2_BASE_IDX 2
|
#define mmAFMT0_AFMT_AUDIO_CRC_RESULT 0x2080
|
#define mmAFMT0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
|
#define mmAFMT0_AFMT_STATUS 0x2081
|
#define mmAFMT0_AFMT_STATUS_BASE_IDX 2
|
#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL 0x2082
|
#define mmAFMT0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmAFMT0_AFMT_INFOFRAME_CONTROL0 0x2083
|
#define mmAFMT0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmAFMT0_AFMT_INTERRUPT_STATUS 0x2084
|
#define mmAFMT0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL 0x2085
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#define mmAFMT0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmAFMT0_AFMT_MEM_PWR 0x2087
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#define mmAFMT0_AFMT_MEM_PWR_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig0_dme_dme_dispdec
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// base address: 0x15524
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#define mmDME0_DME_CONTROL 0x2089
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#define mmDME0_DME_CONTROL_BASE_IDX 2
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#define mmDME0_DME_MEMORY_CONTROL 0x208a
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#define mmDME0_DME_MEMORY_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig0_dispdec
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// base address: 0x0
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#define mmDIG0_DIG_FE_CNTL 0x208b
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#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x208c
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#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x208d
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#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG0_DIG_CLOCK_PATTERN 0x208e
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#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG0_DIG_TEST_PATTERN 0x208f
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#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x2090
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#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG0_DIG_FIFO_STATUS 0x2091
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#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x2092
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#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_CONTROL 0x2093
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#define mmDIG0_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_STATUS 0x2094
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#define mmDIG0_HDMI_STATUS_BASE_IDX 2
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#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2095
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#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2096
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#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2097
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#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2098
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#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2099
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#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x209a
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6 0x209b
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x209c
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
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#define mmDIG0_HDMI_GC 0x209d
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#define mmDIG0_HDMI_GC_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x209e
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x209f
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x20a0
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x20a1
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7 0x20a2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8 0x20a3
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9 0x20a4
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10 0x20a5
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
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#define mmDIG0_HDMI_DB_CONTROL 0x20a6
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#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_32_0 0x20a7
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#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_32_1 0x20a8
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#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_44_0 0x20a9
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#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_44_1 0x20aa
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#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_48_0 0x20ab
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#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_48_1 0x20ac
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#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_STATUS_0 0x20ad
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#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_STATUS_1 0x20ae
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#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG0_AFMT_CNTL 0x20af
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#define mmDIG0_AFMT_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_BE_CNTL 0x20b0
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#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_BE_EN_CNTL 0x20b1
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#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG0_TMDS_CNTL 0x20d7
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#define mmDIG0_TMDS_CNTL_BASE_IDX 2
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#define mmDIG0_TMDS_CONTROL_CHAR 0x20d8
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#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d9
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#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20da
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#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20db
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#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20dc
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#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG0_TMDS_CTL_BITS 0x20de
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#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20df
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#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20e0
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#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
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#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20e1
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#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20e2
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#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_VERSION 0x20e4
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#define mmDIG0_DIG_VERSION_BASE_IDX 2
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#define mmDIG0_DIG_LANE_ENABLE 0x20e5
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#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG0_FORCE_DIG_DISABLE 0x20e6
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#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp0_dispdec
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// base address: 0x0
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#define mmDP0_DP_LINK_CNTL 0x2108
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#define mmDP0_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP0_DP_PIXEL_FORMAT 0x2109
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#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP0_DP_MSA_COLORIMETRY 0x210a
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#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP0_DP_CONFIG 0x210b
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#define mmDP0_DP_CONFIG_BASE_IDX 2
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#define mmDP0_DP_VID_STREAM_CNTL 0x210c
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#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP0_DP_STEER_FIFO 0x210d
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#define mmDP0_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP0_DP_MSA_MISC 0x210e
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#define mmDP0_DP_MSA_MISC_BASE_IDX 2
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#define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
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#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
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#define mmDP0_DP_VID_TIMING 0x2110
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#define mmDP0_DP_VID_TIMING_BASE_IDX 2
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#define mmDP0_DP_VID_N 0x2111
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#define mmDP0_DP_VID_N_BASE_IDX 2
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#define mmDP0_DP_VID_M 0x2112
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#define mmDP0_DP_VID_M_BASE_IDX 2
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#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113
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#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114
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#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP0_DP_VID_MSA_VBID 0x2115
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#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116
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#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_CNTL 0x2117
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#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118
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#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP0_DP_DPHY_SYM0 0x2119
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#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP0_DP_DPHY_SYM1 0x211a
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#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP0_DP_DPHY_SYM2 0x211b
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#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c
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#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d
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#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e
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#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_CRC_EN 0x211f
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#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP0_DP_DPHY_CRC_CNTL 0x2120
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#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_CRC_RESULT 0x2121
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#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122
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#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123
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#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124
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#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125
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#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL 0x212b
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#define mmDP0_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL1 0x212c
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#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP0_DP_SEC_FRAMING1 0x212d
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#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP0_DP_SEC_FRAMING2 0x212e
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#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP0_DP_SEC_FRAMING3 0x212f
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#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP0_DP_SEC_FRAMING4 0x2130
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#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP0_DP_SEC_AUD_N 0x2131
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#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132
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#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP0_DP_SEC_AUD_M 0x2133
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#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134
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#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP0_DP_SEC_TIMESTAMP 0x2135
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#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP0_DP_SEC_PACKET_CNTL 0x2136
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#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP0_DP_MSE_RATE_CNTL 0x2137
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#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP0_DP_MSE_RATE_UPDATE 0x2139
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#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT0 0x213a
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#define mmDP0_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT1 0x213b
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#define mmDP0_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT2 0x213c
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#define mmDP0_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT_UPDATE 0x213d
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#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP0_DP_MSE_LINK_TIMING 0x213e
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#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP0_DP_MSE_MISC_CNTL 0x213f
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#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144
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#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145
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#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT0_STATUS 0x2147
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#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT1_STATUS 0x2148
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#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT2_STATUS 0x2149
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#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
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#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c
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#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2
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#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d
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#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2
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#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e
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#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2
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#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f
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#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2
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#define mmDP0_DP_MSO_CNTL 0x2150
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#define mmDP0_DP_MSO_CNTL_BASE_IDX 2
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#define mmDP0_DP_MSO_CNTL1 0x2151
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#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2
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#define mmDP0_DP_DSC_CNTL 0x2152
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#define mmDP0_DP_DSC_CNTL_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL2 0x2153
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#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL3 0x2154
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#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL4 0x2155
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#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL5 0x2156
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#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL6 0x2157
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#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL7 0x2158
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#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2
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#define mmDP0_DP_DB_CNTL 0x2159
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#define mmDP0_DP_DB_CNTL_BASE_IDX 2
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#define mmDP0_DP_MSA_VBID_MISC 0x215a
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#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2
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#define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b
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#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
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#define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c
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#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
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#define mmDP0_DP_ALPM_CNTL 0x215d
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#define mmDP0_DP_ALPM_CNTL_BASE_IDX 2
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#define mmDP0_DP_GSP8_CNTL 0x215e
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#define mmDP0_DP_GSP8_CNTL_BASE_IDX 2
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#define mmDP0_DP_GSP9_CNTL 0x215f
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#define mmDP0_DP_GSP9_CNTL_BASE_IDX 2
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#define mmDP0_DP_GSP10_CNTL 0x2160
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#define mmDP0_DP_GSP10_CNTL_BASE_IDX 2
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#define mmDP0_DP_GSP11_CNTL 0x2161
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#define mmDP0_DP_GSP11_CNTL_BASE_IDX 2
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#define mmDP0_DP_GSP_EN_DB_STATUS 0x2162
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#define mmDP0_DP_GSP_EN_DB_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig1_vpg_vpg_dispdec
|
// base address: 0x158a0
|
#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2168
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#define mmVPG1_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
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#define mmVPG1_VPG_GENERIC_PACKET_DATA 0x2169
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#define mmVPG1_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
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#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL 0x216a
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#define mmVPG1_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
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#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x216b
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#define mmVPG1_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
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#define mmVPG1_VPG_GENERIC_STATUS 0x216c
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#define mmVPG1_VPG_GENERIC_STATUS_BASE_IDX 2
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#define mmVPG1_VPG_MEM_PWR 0x216d
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#define mmVPG1_VPG_MEM_PWR_BASE_IDX 2
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#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL 0x216e
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#define mmVPG1_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
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#define mmVPG1_VPG_ISRC1_2_DATA 0x216f
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#define mmVPG1_VPG_ISRC1_2_DATA_BASE_IDX 2
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#define mmVPG1_VPG_MPEG_INFO0 0x2170
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#define mmVPG1_VPG_MPEG_INFO0_BASE_IDX 2
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#define mmVPG1_VPG_MPEG_INFO1 0x2171
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#define mmVPG1_VPG_MPEG_INFO1_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig1_afmt_afmt_dispdec
|
// base address: 0x158cc
|
#define mmAFMT1_AFMT_VBI_PACKET_CONTROL 0x2174
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#define mmAFMT1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2 0x2175
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#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmAFMT1_AFMT_AUDIO_INFO0 0x2176
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#define mmAFMT1_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmAFMT1_AFMT_AUDIO_INFO1 0x2177
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#define mmAFMT1_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmAFMT1_AFMT_60958_0 0x2178
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#define mmAFMT1_AFMT_60958_0_BASE_IDX 2
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#define mmAFMT1_AFMT_60958_1 0x2179
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#define mmAFMT1_AFMT_60958_1_BASE_IDX 2
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#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL 0x217a
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#define mmAFMT1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmAFMT1_AFMT_RAMP_CONTROL0 0x217b
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#define mmAFMT1_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmAFMT1_AFMT_RAMP_CONTROL1 0x217c
|
#define mmAFMT1_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmAFMT1_AFMT_RAMP_CONTROL2 0x217d
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#define mmAFMT1_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmAFMT1_AFMT_RAMP_CONTROL3 0x217e
|
#define mmAFMT1_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmAFMT1_AFMT_60958_2 0x217f
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#define mmAFMT1_AFMT_60958_2_BASE_IDX 2
|
#define mmAFMT1_AFMT_AUDIO_CRC_RESULT 0x2180
|
#define mmAFMT1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
|
#define mmAFMT1_AFMT_STATUS 0x2181
|
#define mmAFMT1_AFMT_STATUS_BASE_IDX 2
|
#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL 0x2182
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#define mmAFMT1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmAFMT1_AFMT_INFOFRAME_CONTROL0 0x2183
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#define mmAFMT1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmAFMT1_AFMT_INTERRUPT_STATUS 0x2184
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#define mmAFMT1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL 0x2185
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#define mmAFMT1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmAFMT1_AFMT_MEM_PWR 0x2187
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#define mmAFMT1_AFMT_MEM_PWR_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig1_dme_dme_dispdec
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// base address: 0x15924
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#define mmDME1_DME_CONTROL 0x2189
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#define mmDME1_DME_CONTROL_BASE_IDX 2
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#define mmDME1_DME_MEMORY_CONTROL 0x218a
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#define mmDME1_DME_MEMORY_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig1_dispdec
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// base address: 0x400
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#define mmDIG1_DIG_FE_CNTL 0x218b
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#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x218c
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#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x218d
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#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG1_DIG_CLOCK_PATTERN 0x218e
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#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG1_DIG_TEST_PATTERN 0x218f
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#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x2190
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#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG1_DIG_FIFO_STATUS 0x2191
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#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x2192
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#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_CONTROL 0x2193
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#define mmDIG1_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_STATUS 0x2194
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#define mmDIG1_HDMI_STATUS_BASE_IDX 2
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#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2195
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#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2196
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#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2197
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#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2198
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#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2199
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#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x219a
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6 0x219b
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x219c
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
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#define mmDIG1_HDMI_GC 0x219d
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#define mmDIG1_HDMI_GC_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x219e
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x219f
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x21a0
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x21a1
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7 0x21a2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8 0x21a3
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9 0x21a4
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10 0x21a5
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
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#define mmDIG1_HDMI_DB_CONTROL 0x21a6
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#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_32_0 0x21a7
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#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_32_1 0x21a8
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#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_44_0 0x21a9
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#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_44_1 0x21aa
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#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_48_0 0x21ab
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#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_48_1 0x21ac
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#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_STATUS_0 0x21ad
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#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_STATUS_1 0x21ae
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#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG1_AFMT_CNTL 0x21af
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#define mmDIG1_AFMT_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_BE_CNTL 0x21b0
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#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_BE_EN_CNTL 0x21b1
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#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG1_TMDS_CNTL 0x21d7
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#define mmDIG1_TMDS_CNTL_BASE_IDX 2
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#define mmDIG1_TMDS_CONTROL_CHAR 0x21d8
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#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d9
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#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21da
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#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21db
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#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21dc
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#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG1_TMDS_CTL_BITS 0x21de
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#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21df
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#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21e0
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#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
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#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21e1
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#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21e2
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#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_VERSION 0x21e4
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#define mmDIG1_DIG_VERSION_BASE_IDX 2
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#define mmDIG1_DIG_LANE_ENABLE 0x21e5
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#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG1_FORCE_DIG_DISABLE 0x21e6
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#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp1_dispdec
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// base address: 0x400
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#define mmDP1_DP_LINK_CNTL 0x2208
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#define mmDP1_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP1_DP_PIXEL_FORMAT 0x2209
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#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP1_DP_MSA_COLORIMETRY 0x220a
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#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP1_DP_CONFIG 0x220b
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#define mmDP1_DP_CONFIG_BASE_IDX 2
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#define mmDP1_DP_VID_STREAM_CNTL 0x220c
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#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP1_DP_STEER_FIFO 0x220d
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#define mmDP1_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP1_DP_MSA_MISC 0x220e
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#define mmDP1_DP_MSA_MISC_BASE_IDX 2
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#define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
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#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
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#define mmDP1_DP_VID_TIMING 0x2210
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#define mmDP1_DP_VID_TIMING_BASE_IDX 2
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#define mmDP1_DP_VID_N 0x2211
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#define mmDP1_DP_VID_N_BASE_IDX 2
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#define mmDP1_DP_VID_M 0x2212
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#define mmDP1_DP_VID_M_BASE_IDX 2
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#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213
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#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214
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#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP1_DP_VID_MSA_VBID 0x2215
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#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216
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#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_CNTL 0x2217
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#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218
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#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP1_DP_DPHY_SYM0 0x2219
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#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP1_DP_DPHY_SYM1 0x221a
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#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP1_DP_DPHY_SYM2 0x221b
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#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c
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#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d
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#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e
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#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_CRC_EN 0x221f
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#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP1_DP_DPHY_CRC_CNTL 0x2220
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#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_CRC_RESULT 0x2221
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#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222
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#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223
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#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224
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#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225
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#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP1_DP_SEC_CNTL 0x222b
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#define mmDP1_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP1_DP_SEC_CNTL1 0x222c
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#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP1_DP_SEC_FRAMING1 0x222d
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#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP1_DP_SEC_FRAMING2 0x222e
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#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP1_DP_SEC_FRAMING3 0x222f
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#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP1_DP_SEC_FRAMING4 0x2230
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#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP1_DP_SEC_AUD_N 0x2231
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#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232
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#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP1_DP_SEC_AUD_M 0x2233
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#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234
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#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP1_DP_SEC_TIMESTAMP 0x2235
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#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP1_DP_SEC_PACKET_CNTL 0x2236
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#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP1_DP_MSE_RATE_CNTL 0x2237
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#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP1_DP_MSE_RATE_UPDATE 0x2239
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#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP1_DP_MSE_SAT0 0x223a
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#define mmDP1_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP1_DP_MSE_SAT1 0x223b
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#define mmDP1_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP1_DP_MSE_SAT2 0x223c
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#define mmDP1_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP1_DP_MSE_SAT_UPDATE 0x223d
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#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP1_DP_MSE_LINK_TIMING 0x223e
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#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP1_DP_MSE_MISC_CNTL 0x223f
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#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244
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#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245
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#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP1_DP_MSE_SAT0_STATUS 0x2247
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#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP1_DP_MSE_SAT1_STATUS 0x2248
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#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP1_DP_MSE_SAT2_STATUS 0x2249
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#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
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#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c
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#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2
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#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d
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#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2
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#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e
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#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2
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#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f
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#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2
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#define mmDP1_DP_MSO_CNTL 0x2250
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#define mmDP1_DP_MSO_CNTL_BASE_IDX 2
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#define mmDP1_DP_MSO_CNTL1 0x2251
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#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2
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#define mmDP1_DP_DSC_CNTL 0x2252
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#define mmDP1_DP_DSC_CNTL_BASE_IDX 2
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#define mmDP1_DP_SEC_CNTL2 0x2253
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#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2
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#define mmDP1_DP_SEC_CNTL3 0x2254
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#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2
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#define mmDP1_DP_SEC_CNTL4 0x2255
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#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2
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#define mmDP1_DP_SEC_CNTL5 0x2256
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#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2
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#define mmDP1_DP_SEC_CNTL6 0x2257
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#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2
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#define mmDP1_DP_SEC_CNTL7 0x2258
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#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2
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#define mmDP1_DP_DB_CNTL 0x2259
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#define mmDP1_DP_DB_CNTL_BASE_IDX 2
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#define mmDP1_DP_MSA_VBID_MISC 0x225a
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#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2
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#define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b
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#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
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#define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c
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#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
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#define mmDP1_DP_ALPM_CNTL 0x225d
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#define mmDP1_DP_ALPM_CNTL_BASE_IDX 2
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#define mmDP1_DP_GSP8_CNTL 0x225e
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#define mmDP1_DP_GSP8_CNTL_BASE_IDX 2
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#define mmDP1_DP_GSP9_CNTL 0x225f
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#define mmDP1_DP_GSP9_CNTL_BASE_IDX 2
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#define mmDP1_DP_GSP10_CNTL 0x2260
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#define mmDP1_DP_GSP10_CNTL_BASE_IDX 2
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#define mmDP1_DP_GSP11_CNTL 0x2261
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#define mmDP1_DP_GSP11_CNTL_BASE_IDX 2
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#define mmDP1_DP_GSP_EN_DB_STATUS 0x2262
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#define mmDP1_DP_GSP_EN_DB_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig2_vpg_vpg_dispdec
|
// base address: 0x15ca0
|
#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2268
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#define mmVPG2_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
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#define mmVPG2_VPG_GENERIC_PACKET_DATA 0x2269
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#define mmVPG2_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
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#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL 0x226a
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#define mmVPG2_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
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#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x226b
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#define mmVPG2_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
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#define mmVPG2_VPG_GENERIC_STATUS 0x226c
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#define mmVPG2_VPG_GENERIC_STATUS_BASE_IDX 2
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#define mmVPG2_VPG_MEM_PWR 0x226d
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#define mmVPG2_VPG_MEM_PWR_BASE_IDX 2
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#define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL 0x226e
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#define mmVPG2_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
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#define mmVPG2_VPG_ISRC1_2_DATA 0x226f
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#define mmVPG2_VPG_ISRC1_2_DATA_BASE_IDX 2
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#define mmVPG2_VPG_MPEG_INFO0 0x2270
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#define mmVPG2_VPG_MPEG_INFO0_BASE_IDX 2
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#define mmVPG2_VPG_MPEG_INFO1 0x2271
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#define mmVPG2_VPG_MPEG_INFO1_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig2_afmt_afmt_dispdec
|
// base address: 0x15ccc
|
#define mmAFMT2_AFMT_VBI_PACKET_CONTROL 0x2274
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#define mmAFMT2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2 0x2275
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#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmAFMT2_AFMT_AUDIO_INFO0 0x2276
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#define mmAFMT2_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmAFMT2_AFMT_AUDIO_INFO1 0x2277
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#define mmAFMT2_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmAFMT2_AFMT_60958_0 0x2278
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#define mmAFMT2_AFMT_60958_0_BASE_IDX 2
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#define mmAFMT2_AFMT_60958_1 0x2279
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#define mmAFMT2_AFMT_60958_1_BASE_IDX 2
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#define mmAFMT2_AFMT_AUDIO_CRC_CONTROL 0x227a
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#define mmAFMT2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmAFMT2_AFMT_RAMP_CONTROL0 0x227b
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#define mmAFMT2_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmAFMT2_AFMT_RAMP_CONTROL1 0x227c
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#define mmAFMT2_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmAFMT2_AFMT_RAMP_CONTROL2 0x227d
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#define mmAFMT2_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmAFMT2_AFMT_RAMP_CONTROL3 0x227e
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#define mmAFMT2_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmAFMT2_AFMT_60958_2 0x227f
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#define mmAFMT2_AFMT_60958_2_BASE_IDX 2
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#define mmAFMT2_AFMT_AUDIO_CRC_RESULT 0x2280
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#define mmAFMT2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmAFMT2_AFMT_STATUS 0x2281
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#define mmAFMT2_AFMT_STATUS_BASE_IDX 2
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#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL 0x2282
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#define mmAFMT2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmAFMT2_AFMT_INFOFRAME_CONTROL0 0x2283
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#define mmAFMT2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmAFMT2_AFMT_INTERRUPT_STATUS 0x2284
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#define mmAFMT2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL 0x2285
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#define mmAFMT2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmAFMT2_AFMT_MEM_PWR 0x2287
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#define mmAFMT2_AFMT_MEM_PWR_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig2_dme_dme_dispdec
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// base address: 0x15d24
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#define mmDME2_DME_CONTROL 0x2289
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#define mmDME2_DME_CONTROL_BASE_IDX 2
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#define mmDME2_DME_MEMORY_CONTROL 0x228a
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#define mmDME2_DME_MEMORY_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig2_dispdec
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// base address: 0x800
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#define mmDIG2_DIG_FE_CNTL 0x228b
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#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x228c
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#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x228d
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#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG2_DIG_CLOCK_PATTERN 0x228e
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#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG2_DIG_TEST_PATTERN 0x228f
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#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x2290
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#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG2_DIG_FIFO_STATUS 0x2291
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#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG2_HDMI_METADATA_PACKET_CONTROL 0x2292
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#define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_CONTROL 0x2293
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#define mmDIG2_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_STATUS 0x2294
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#define mmDIG2_HDMI_STATUS_BASE_IDX 2
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#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2295
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#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2296
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#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2297
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#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2298
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#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2299
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#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x229a
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6 0x229b
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x229c
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
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#define mmDIG2_HDMI_GC 0x229d
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#define mmDIG2_HDMI_GC_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x229e
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x229f
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x22a0
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x22a1
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7 0x22a2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8 0x22a3
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9 0x22a4
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10 0x22a5
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
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#define mmDIG2_HDMI_DB_CONTROL 0x22a6
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#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_32_0 0x22a7
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#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_32_1 0x22a8
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#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_44_0 0x22a9
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#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_44_1 0x22aa
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#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_48_0 0x22ab
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#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_48_1 0x22ac
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#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_STATUS_0 0x22ad
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#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_STATUS_1 0x22ae
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#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG2_AFMT_CNTL 0x22af
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#define mmDIG2_AFMT_CNTL_BASE_IDX 2
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#define mmDIG2_DIG_BE_CNTL 0x22b0
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#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG2_DIG_BE_EN_CNTL 0x22b1
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#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG2_TMDS_CNTL 0x22d7
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#define mmDIG2_TMDS_CNTL_BASE_IDX 2
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#define mmDIG2_TMDS_CONTROL_CHAR 0x22d8
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#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d9
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#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22da
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#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22db
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#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22dc
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#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG2_TMDS_CTL_BITS 0x22de
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#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22df
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#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22e0
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#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
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#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22e1
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#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22e2
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#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG2_DIG_VERSION 0x22e4
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#define mmDIG2_DIG_VERSION_BASE_IDX 2
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#define mmDIG2_DIG_LANE_ENABLE 0x22e5
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#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG2_FORCE_DIG_DISABLE 0x22e6
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#define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp2_dispdec
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// base address: 0x800
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#define mmDP2_DP_LINK_CNTL 0x2308
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#define mmDP2_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP2_DP_PIXEL_FORMAT 0x2309
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#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP2_DP_MSA_COLORIMETRY 0x230a
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#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP2_DP_CONFIG 0x230b
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#define mmDP2_DP_CONFIG_BASE_IDX 2
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#define mmDP2_DP_VID_STREAM_CNTL 0x230c
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#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP2_DP_STEER_FIFO 0x230d
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#define mmDP2_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP2_DP_MSA_MISC 0x230e
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#define mmDP2_DP_MSA_MISC_BASE_IDX 2
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#define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
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#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
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#define mmDP2_DP_VID_TIMING 0x2310
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#define mmDP2_DP_VID_TIMING_BASE_IDX 2
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#define mmDP2_DP_VID_N 0x2311
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#define mmDP2_DP_VID_N_BASE_IDX 2
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#define mmDP2_DP_VID_M 0x2312
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#define mmDP2_DP_VID_M_BASE_IDX 2
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#define mmDP2_DP_LINK_FRAMING_CNTL 0x2313
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#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP2_DP_HBR2_EYE_PATTERN 0x2314
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#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP2_DP_VID_MSA_VBID 0x2315
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#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316
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#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_CNTL 0x2317
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#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318
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#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP2_DP_DPHY_SYM0 0x2319
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#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP2_DP_DPHY_SYM1 0x231a
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#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP2_DP_DPHY_SYM2 0x231b
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#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP2_DP_DPHY_8B10B_CNTL 0x231c
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#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_PRBS_CNTL 0x231d
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#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e
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#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_EN 0x231f
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#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_CNTL 0x2320
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#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_RESULT 0x2321
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#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322
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#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323
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#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP2_DP_DPHY_FAST_TRAINING 0x2324
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#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325
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#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL 0x232b
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#define mmDP2_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL1 0x232c
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#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP2_DP_SEC_FRAMING1 0x232d
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#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP2_DP_SEC_FRAMING2 0x232e
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#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP2_DP_SEC_FRAMING3 0x232f
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#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP2_DP_SEC_FRAMING4 0x2330
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#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP2_DP_SEC_AUD_N 0x2331
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#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP2_DP_SEC_AUD_N_READBACK 0x2332
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#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP2_DP_SEC_AUD_M 0x2333
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#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP2_DP_SEC_AUD_M_READBACK 0x2334
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#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP2_DP_SEC_TIMESTAMP 0x2335
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#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP2_DP_SEC_PACKET_CNTL 0x2336
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#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP2_DP_MSE_RATE_CNTL 0x2337
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#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP2_DP_MSE_RATE_UPDATE 0x2339
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#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT0 0x233a
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#define mmDP2_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT1 0x233b
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#define mmDP2_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT2 0x233c
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#define mmDP2_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT_UPDATE 0x233d
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#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP2_DP_MSE_LINK_TIMING 0x233e
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#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP2_DP_MSE_MISC_CNTL 0x233f
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#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344
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#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345
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#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT0_STATUS 0x2347
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#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT1_STATUS 0x2348
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#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT2_STATUS 0x2349
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#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
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#define mmDP2_DP_MSA_TIMING_PARAM1 0x234c
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#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2
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#define mmDP2_DP_MSA_TIMING_PARAM2 0x234d
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#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2
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#define mmDP2_DP_MSA_TIMING_PARAM3 0x234e
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#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2
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#define mmDP2_DP_MSA_TIMING_PARAM4 0x234f
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#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2
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#define mmDP2_DP_MSO_CNTL 0x2350
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#define mmDP2_DP_MSO_CNTL_BASE_IDX 2
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#define mmDP2_DP_MSO_CNTL1 0x2351
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#define mmDP2_DP_MSO_CNTL1_BASE_IDX 2
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#define mmDP2_DP_DSC_CNTL 0x2352
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#define mmDP2_DP_DSC_CNTL_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL2 0x2353
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#define mmDP2_DP_SEC_CNTL2_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL3 0x2354
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#define mmDP2_DP_SEC_CNTL3_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL4 0x2355
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#define mmDP2_DP_SEC_CNTL4_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL5 0x2356
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#define mmDP2_DP_SEC_CNTL5_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL6 0x2357
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#define mmDP2_DP_SEC_CNTL6_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL7 0x2358
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#define mmDP2_DP_SEC_CNTL7_BASE_IDX 2
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#define mmDP2_DP_DB_CNTL 0x2359
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#define mmDP2_DP_DB_CNTL_BASE_IDX 2
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#define mmDP2_DP_MSA_VBID_MISC 0x235a
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#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2
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#define mmDP2_DP_SEC_METADATA_TRANSMISSION 0x235b
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#define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
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#define mmDP2_DP_DSC_BYTES_PER_PIXEL 0x235c
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#define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
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#define mmDP2_DP_ALPM_CNTL 0x235d
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#define mmDP2_DP_ALPM_CNTL_BASE_IDX 2
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#define mmDP2_DP_GSP8_CNTL 0x235e
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#define mmDP2_DP_GSP8_CNTL_BASE_IDX 2
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#define mmDP2_DP_GSP9_CNTL 0x235f
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#define mmDP2_DP_GSP9_CNTL_BASE_IDX 2
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#define mmDP2_DP_GSP10_CNTL 0x2360
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#define mmDP2_DP_GSP10_CNTL_BASE_IDX 2
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#define mmDP2_DP_GSP11_CNTL 0x2361
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#define mmDP2_DP_GSP11_CNTL_BASE_IDX 2
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#define mmDP2_DP_GSP_EN_DB_STATUS 0x2362
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#define mmDP2_DP_GSP_EN_DB_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig3_vpg_vpg_dispdec
|
// base address: 0x160a0
|
#define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2368
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#define mmVPG3_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
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#define mmVPG3_VPG_GENERIC_PACKET_DATA 0x2369
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#define mmVPG3_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
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#define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL 0x236a
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#define mmVPG3_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
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#define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x236b
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#define mmVPG3_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
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#define mmVPG3_VPG_GENERIC_STATUS 0x236c
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#define mmVPG3_VPG_GENERIC_STATUS_BASE_IDX 2
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#define mmVPG3_VPG_MEM_PWR 0x236d
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#define mmVPG3_VPG_MEM_PWR_BASE_IDX 2
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#define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL 0x236e
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#define mmVPG3_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
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#define mmVPG3_VPG_ISRC1_2_DATA 0x236f
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#define mmVPG3_VPG_ISRC1_2_DATA_BASE_IDX 2
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#define mmVPG3_VPG_MPEG_INFO0 0x2370
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#define mmVPG3_VPG_MPEG_INFO0_BASE_IDX 2
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#define mmVPG3_VPG_MPEG_INFO1 0x2371
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#define mmVPG3_VPG_MPEG_INFO1_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig3_afmt_afmt_dispdec
|
// base address: 0x160cc
|
#define mmAFMT3_AFMT_VBI_PACKET_CONTROL 0x2374
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#define mmAFMT3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2 0x2375
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#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmAFMT3_AFMT_AUDIO_INFO0 0x2376
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#define mmAFMT3_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmAFMT3_AFMT_AUDIO_INFO1 0x2377
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#define mmAFMT3_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmAFMT3_AFMT_60958_0 0x2378
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#define mmAFMT3_AFMT_60958_0_BASE_IDX 2
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#define mmAFMT3_AFMT_60958_1 0x2379
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#define mmAFMT3_AFMT_60958_1_BASE_IDX 2
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#define mmAFMT3_AFMT_AUDIO_CRC_CONTROL 0x237a
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#define mmAFMT3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmAFMT3_AFMT_RAMP_CONTROL0 0x237b
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#define mmAFMT3_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmAFMT3_AFMT_RAMP_CONTROL1 0x237c
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#define mmAFMT3_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmAFMT3_AFMT_RAMP_CONTROL2 0x237d
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#define mmAFMT3_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmAFMT3_AFMT_RAMP_CONTROL3 0x237e
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#define mmAFMT3_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmAFMT3_AFMT_60958_2 0x237f
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#define mmAFMT3_AFMT_60958_2_BASE_IDX 2
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#define mmAFMT3_AFMT_AUDIO_CRC_RESULT 0x2380
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#define mmAFMT3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmAFMT3_AFMT_STATUS 0x2381
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#define mmAFMT3_AFMT_STATUS_BASE_IDX 2
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#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL 0x2382
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#define mmAFMT3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmAFMT3_AFMT_INFOFRAME_CONTROL0 0x2383
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#define mmAFMT3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmAFMT3_AFMT_INTERRUPT_STATUS 0x2384
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#define mmAFMT3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmAFMT3_AFMT_AUDIO_SRC_CONTROL 0x2385
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#define mmAFMT3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmAFMT3_AFMT_MEM_PWR 0x2387
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#define mmAFMT3_AFMT_MEM_PWR_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig3_dme_dme_dispdec
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// base address: 0x16124
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#define mmDME3_DME_CONTROL 0x2389
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#define mmDME3_DME_CONTROL_BASE_IDX 2
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#define mmDME3_DME_MEMORY_CONTROL 0x238a
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#define mmDME3_DME_MEMORY_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig3_dispdec
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// base address: 0xc00
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#define mmDIG3_DIG_FE_CNTL 0x238b
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#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x238c
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#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x238d
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#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG3_DIG_CLOCK_PATTERN 0x238e
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#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG3_DIG_TEST_PATTERN 0x238f
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#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x2390
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#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG3_DIG_FIFO_STATUS 0x2391
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#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG3_HDMI_METADATA_PACKET_CONTROL 0x2392
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#define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_CONTROL 0x2393
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#define mmDIG3_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_STATUS 0x2394
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#define mmDIG3_HDMI_STATUS_BASE_IDX 2
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#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2395
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#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2396
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#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2397
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#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2398
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#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2399
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#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x239a
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6 0x239b
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x239c
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
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#define mmDIG3_HDMI_GC 0x239d
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#define mmDIG3_HDMI_GC_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x239e
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x239f
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x23a0
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x23a1
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7 0x23a2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8 0x23a3
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9 0x23a4
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10 0x23a5
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
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#define mmDIG3_HDMI_DB_CONTROL 0x23a6
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#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_32_0 0x23a7
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#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_32_1 0x23a8
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#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_44_0 0x23a9
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#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_44_1 0x23aa
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#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_48_0 0x23ab
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#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_48_1 0x23ac
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#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_STATUS_0 0x23ad
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#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_STATUS_1 0x23ae
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#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG3_AFMT_CNTL 0x23af
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#define mmDIG3_AFMT_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_BE_CNTL 0x23b0
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#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_BE_EN_CNTL 0x23b1
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#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG3_TMDS_CNTL 0x23d7
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#define mmDIG3_TMDS_CNTL_BASE_IDX 2
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#define mmDIG3_TMDS_CONTROL_CHAR 0x23d8
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#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d9
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#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23da
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#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23db
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#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23dc
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#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG3_TMDS_CTL_BITS 0x23de
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#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23df
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#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23e0
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#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
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#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23e1
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#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23e2
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#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_VERSION 0x23e4
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#define mmDIG3_DIG_VERSION_BASE_IDX 2
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#define mmDIG3_DIG_LANE_ENABLE 0x23e5
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#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG3_FORCE_DIG_DISABLE 0x23e6
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#define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp3_dispdec
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// base address: 0xc00
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#define mmDP3_DP_LINK_CNTL 0x2408
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#define mmDP3_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP3_DP_PIXEL_FORMAT 0x2409
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#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP3_DP_MSA_COLORIMETRY 0x240a
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#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP3_DP_CONFIG 0x240b
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#define mmDP3_DP_CONFIG_BASE_IDX 2
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#define mmDP3_DP_VID_STREAM_CNTL 0x240c
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#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP3_DP_STEER_FIFO 0x240d
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#define mmDP3_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP3_DP_MSA_MISC 0x240e
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#define mmDP3_DP_MSA_MISC_BASE_IDX 2
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#define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
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#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
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#define mmDP3_DP_VID_TIMING 0x2410
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#define mmDP3_DP_VID_TIMING_BASE_IDX 2
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#define mmDP3_DP_VID_N 0x2411
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#define mmDP3_DP_VID_N_BASE_IDX 2
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#define mmDP3_DP_VID_M 0x2412
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#define mmDP3_DP_VID_M_BASE_IDX 2
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#define mmDP3_DP_LINK_FRAMING_CNTL 0x2413
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#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP3_DP_HBR2_EYE_PATTERN 0x2414
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#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP3_DP_VID_MSA_VBID 0x2415
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#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416
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#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_CNTL 0x2417
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#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418
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#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP3_DP_DPHY_SYM0 0x2419
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#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP3_DP_DPHY_SYM1 0x241a
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#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP3_DP_DPHY_SYM2 0x241b
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#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP3_DP_DPHY_8B10B_CNTL 0x241c
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#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_PRBS_CNTL 0x241d
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#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e
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#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_EN 0x241f
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#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_CNTL 0x2420
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#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_RESULT 0x2421
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#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422
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#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423
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#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP3_DP_DPHY_FAST_TRAINING 0x2424
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#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425
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#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL 0x242b
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#define mmDP3_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL1 0x242c
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#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP3_DP_SEC_FRAMING1 0x242d
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#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP3_DP_SEC_FRAMING2 0x242e
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#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP3_DP_SEC_FRAMING3 0x242f
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#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP3_DP_SEC_FRAMING4 0x2430
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#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP3_DP_SEC_AUD_N 0x2431
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#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP3_DP_SEC_AUD_N_READBACK 0x2432
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#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP3_DP_SEC_AUD_M 0x2433
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#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP3_DP_SEC_AUD_M_READBACK 0x2434
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#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP3_DP_SEC_TIMESTAMP 0x2435
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#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP3_DP_SEC_PACKET_CNTL 0x2436
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#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP3_DP_MSE_RATE_CNTL 0x2437
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#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP3_DP_MSE_RATE_UPDATE 0x2439
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#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT0 0x243a
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#define mmDP3_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT1 0x243b
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#define mmDP3_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT2 0x243c
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#define mmDP3_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT_UPDATE 0x243d
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#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP3_DP_MSE_LINK_TIMING 0x243e
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#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP3_DP_MSE_MISC_CNTL 0x243f
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#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444
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#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445
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#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT0_STATUS 0x2447
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#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT1_STATUS 0x2448
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#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT2_STATUS 0x2449
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#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
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#define mmDP3_DP_MSA_TIMING_PARAM1 0x244c
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#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2
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#define mmDP3_DP_MSA_TIMING_PARAM2 0x244d
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#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2
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#define mmDP3_DP_MSA_TIMING_PARAM3 0x244e
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#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2
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#define mmDP3_DP_MSA_TIMING_PARAM4 0x244f
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#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2
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#define mmDP3_DP_MSO_CNTL 0x2450
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#define mmDP3_DP_MSO_CNTL_BASE_IDX 2
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#define mmDP3_DP_MSO_CNTL1 0x2451
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#define mmDP3_DP_MSO_CNTL1_BASE_IDX 2
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#define mmDP3_DP_DSC_CNTL 0x2452
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#define mmDP3_DP_DSC_CNTL_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL2 0x2453
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#define mmDP3_DP_SEC_CNTL2_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL3 0x2454
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#define mmDP3_DP_SEC_CNTL3_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL4 0x2455
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#define mmDP3_DP_SEC_CNTL4_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL5 0x2456
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#define mmDP3_DP_SEC_CNTL5_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL6 0x2457
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#define mmDP3_DP_SEC_CNTL6_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL7 0x2458
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#define mmDP3_DP_SEC_CNTL7_BASE_IDX 2
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#define mmDP3_DP_DB_CNTL 0x2459
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#define mmDP3_DP_DB_CNTL_BASE_IDX 2
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#define mmDP3_DP_MSA_VBID_MISC 0x245a
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#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2
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#define mmDP3_DP_SEC_METADATA_TRANSMISSION 0x245b
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#define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
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#define mmDP3_DP_DSC_BYTES_PER_PIXEL 0x245c
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#define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
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#define mmDP3_DP_ALPM_CNTL 0x245d
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#define mmDP3_DP_ALPM_CNTL_BASE_IDX 2
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#define mmDP3_DP_GSP8_CNTL 0x245e
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#define mmDP3_DP_GSP8_CNTL_BASE_IDX 2
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#define mmDP3_DP_GSP9_CNTL 0x245f
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#define mmDP3_DP_GSP9_CNTL_BASE_IDX 2
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#define mmDP3_DP_GSP10_CNTL 0x2460
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#define mmDP3_DP_GSP10_CNTL_BASE_IDX 2
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#define mmDP3_DP_GSP11_CNTL 0x2461
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#define mmDP3_DP_GSP11_CNTL_BASE_IDX 2
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#define mmDP3_DP_GSP_EN_DB_STATUS 0x2462
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#define mmDP3_DP_GSP_EN_DB_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig4_vpg_vpg_dispdec
|
// base address: 0x164a0
|
#define mmVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2468
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#define mmVPG4_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
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#define mmVPG4_VPG_GENERIC_PACKET_DATA 0x2469
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#define mmVPG4_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
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#define mmVPG4_VPG_GSP_FRAME_UPDATE_CTRL 0x246a
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#define mmVPG4_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
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#define mmVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x246b
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#define mmVPG4_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
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#define mmVPG4_VPG_GENERIC_STATUS 0x246c
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#define mmVPG4_VPG_GENERIC_STATUS_BASE_IDX 2
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#define mmVPG4_VPG_MEM_PWR 0x246d
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#define mmVPG4_VPG_MEM_PWR_BASE_IDX 2
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#define mmVPG4_VPG_ISRC1_2_ACCESS_CTRL 0x246e
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#define mmVPG4_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
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#define mmVPG4_VPG_ISRC1_2_DATA 0x246f
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#define mmVPG4_VPG_ISRC1_2_DATA_BASE_IDX 2
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#define mmVPG4_VPG_MPEG_INFO0 0x2470
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#define mmVPG4_VPG_MPEG_INFO0_BASE_IDX 2
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#define mmVPG4_VPG_MPEG_INFO1 0x2471
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#define mmVPG4_VPG_MPEG_INFO1_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig4_afmt_afmt_dispdec
|
#define mmAFMT4_AFMT_VBI_PACKET_CONTROL 0x2474
|
#define mmAFMT4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL2 0x2475
|
#define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
|
#define mmAFMT4_AFMT_AUDIO_INFO0 0x2476
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#define mmAFMT4_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmAFMT4_AFMT_AUDIO_INFO1 0x2477
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#define mmAFMT4_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmAFMT4_AFMT_60958_0 0x2478
|
#define mmAFMT4_AFMT_60958_0_BASE_IDX 2
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#define mmAFMT4_AFMT_60958_1 0x2479
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#define mmAFMT4_AFMT_60958_1_BASE_IDX 2
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#define mmAFMT4_AFMT_AUDIO_CRC_CONTROL 0x247a
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#define mmAFMT4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmAFMT4_AFMT_RAMP_CONTROL0 0x247b
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#define mmAFMT4_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmAFMT4_AFMT_RAMP_CONTROL1 0x247c
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#define mmAFMT4_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmAFMT4_AFMT_RAMP_CONTROL2 0x247d
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#define mmAFMT4_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmAFMT4_AFMT_RAMP_CONTROL3 0x247e
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#define mmAFMT4_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmAFMT4_AFMT_60958_2 0x247f
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#define mmAFMT4_AFMT_60958_2_BASE_IDX 2
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#define mmAFMT4_AFMT_AUDIO_CRC_RESULT 0x2480
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#define mmAFMT4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmAFMT4_AFMT_STATUS 0x2481
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#define mmAFMT4_AFMT_STATUS_BASE_IDX 2
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#define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL 0x2482
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#define mmAFMT4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmAFMT4_AFMT_INFOFRAME_CONTROL0 0x2483
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#define mmAFMT4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmAFMT4_AFMT_INTERRUPT_STATUS 0x2484
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#define mmAFMT4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmAFMT4_AFMT_AUDIO_SRC_CONTROL 0x2485
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#define mmAFMT4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmAFMT4_AFMT_MEM_PWR 0x2487
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#define mmAFMT4_AFMT_MEM_PWR_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig4_dme_dme_dispdec
|
// base address: 0x16524
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#define mmDME4_DME_CONTROL 0x2489
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#define mmDME4_DME_CONTROL_BASE_IDX 2
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#define mmDME4_DME_MEMORY_CONTROL 0x248a
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#define mmDME4_DME_MEMORY_CONTROL_BASE_IDX 2
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|
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// addressBlock: dce_dc_dio_dig4_dispdec
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// base address: 0x1000
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#define mmDIG4_DIG_FE_CNTL 0x248b
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#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x248c
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#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x248d
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#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG4_DIG_CLOCK_PATTERN 0x248e
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#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG4_DIG_TEST_PATTERN 0x248f
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#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x2490
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#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG4_DIG_FIFO_STATUS 0x2491
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#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG4_HDMI_METADATA_PACKET_CONTROL 0x2492
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#define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_CONTROL 0x2493
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#define mmDIG4_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_STATUS 0x2494
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#define mmDIG4_HDMI_STATUS_BASE_IDX 2
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#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2495
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#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2496
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#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2497
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#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2498
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#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2499
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#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x249a
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL6 0x249b
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x249c
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
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#define mmDIG4_HDMI_GC 0x249d
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#define mmDIG4_HDMI_GC_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x249e
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x249f
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x24a0
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x24a1
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL7 0x24a2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL8 0x24a3
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL9 0x24a4
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL10 0x24a5
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
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#define mmDIG4_HDMI_DB_CONTROL 0x24a6
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#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_32_0 0x24a7
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#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_32_1 0x24a8
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#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_44_0 0x24a9
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#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_44_1 0x24aa
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#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_48_0 0x24ab
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#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_48_1 0x24ac
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#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_STATUS_0 0x24ad
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#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_STATUS_1 0x24ae
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#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG4_AFMT_CNTL 0x24af
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#define mmDIG4_AFMT_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_BE_CNTL 0x24b0
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#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_BE_EN_CNTL 0x24b1
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#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG4_TMDS_CNTL 0x24d7
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#define mmDIG4_TMDS_CNTL_BASE_IDX 2
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#define mmDIG4_TMDS_CONTROL_CHAR 0x24d8
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#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d9
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#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24da
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#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24db
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#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24dc
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#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG4_TMDS_CTL_BITS 0x24de
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#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24df
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#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24e0
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#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
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#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24e1
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#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24e2
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#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_VERSION 0x24e4
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#define mmDIG4_DIG_VERSION_BASE_IDX 2
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#define mmDIG4_DIG_LANE_ENABLE 0x24e5
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#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG4_FORCE_DIG_DISABLE 0x24e6
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#define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp4_dispdec
|
// base address: 0x1000
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#define mmDP4_DP_LINK_CNTL 0x2508
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#define mmDP4_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP4_DP_PIXEL_FORMAT 0x2509
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#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP4_DP_MSA_COLORIMETRY 0x250a
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#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP4_DP_CONFIG 0x250b
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#define mmDP4_DP_CONFIG_BASE_IDX 2
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#define mmDP4_DP_VID_STREAM_CNTL 0x250c
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#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP4_DP_STEER_FIFO 0x250d
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#define mmDP4_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP4_DP_MSA_MISC 0x250e
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#define mmDP4_DP_MSA_MISC_BASE_IDX 2
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#define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
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#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
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#define mmDP4_DP_VID_TIMING 0x2510
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#define mmDP4_DP_VID_TIMING_BASE_IDX 2
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#define mmDP4_DP_VID_N 0x2511
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#define mmDP4_DP_VID_N_BASE_IDX 2
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#define mmDP4_DP_VID_M 0x2512
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#define mmDP4_DP_VID_M_BASE_IDX 2
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#define mmDP4_DP_LINK_FRAMING_CNTL 0x2513
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#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP4_DP_HBR2_EYE_PATTERN 0x2514
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#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP4_DP_VID_MSA_VBID 0x2515
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#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516
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#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_CNTL 0x2517
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#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518
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#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP4_DP_DPHY_SYM0 0x2519
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#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP4_DP_DPHY_SYM1 0x251a
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#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP4_DP_DPHY_SYM2 0x251b
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#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP4_DP_DPHY_8B10B_CNTL 0x251c
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#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_PRBS_CNTL 0x251d
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#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e
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#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_EN 0x251f
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#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_CNTL 0x2520
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#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_RESULT 0x2521
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#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522
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#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523
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#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP4_DP_DPHY_FAST_TRAINING 0x2524
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#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525
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#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL 0x252b
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#define mmDP4_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL1 0x252c
|
#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP4_DP_SEC_FRAMING1 0x252d
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#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP4_DP_SEC_FRAMING2 0x252e
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#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
|
#define mmDP4_DP_SEC_FRAMING3 0x252f
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#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP4_DP_SEC_FRAMING4 0x2530
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#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP4_DP_SEC_AUD_N 0x2531
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#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP4_DP_SEC_AUD_N_READBACK 0x2532
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#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP4_DP_SEC_AUD_M 0x2533
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#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP4_DP_SEC_AUD_M_READBACK 0x2534
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#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP4_DP_SEC_TIMESTAMP 0x2535
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#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP4_DP_SEC_PACKET_CNTL 0x2536
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#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP4_DP_MSE_RATE_CNTL 0x2537
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#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
|
#define mmDP4_DP_MSE_RATE_UPDATE 0x2539
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#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT0 0x253a
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#define mmDP4_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT1 0x253b
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#define mmDP4_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT2 0x253c
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#define mmDP4_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT_UPDATE 0x253d
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#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP4_DP_MSE_LINK_TIMING 0x253e
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#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP4_DP_MSE_MISC_CNTL 0x253f
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#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544
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#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545
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#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT0_STATUS 0x2547
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#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT1_STATUS 0x2548
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#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT2_STATUS 0x2549
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#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
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#define mmDP4_DP_MSA_TIMING_PARAM1 0x254c
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#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2
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#define mmDP4_DP_MSA_TIMING_PARAM2 0x254d
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#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2
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#define mmDP4_DP_MSA_TIMING_PARAM3 0x254e
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#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2
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#define mmDP4_DP_MSA_TIMING_PARAM4 0x254f
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#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2
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#define mmDP4_DP_MSO_CNTL 0x2550
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#define mmDP4_DP_MSO_CNTL_BASE_IDX 2
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#define mmDP4_DP_MSO_CNTL1 0x2551
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#define mmDP4_DP_MSO_CNTL1_BASE_IDX 2
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#define mmDP4_DP_DSC_CNTL 0x2552
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#define mmDP4_DP_DSC_CNTL_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL2 0x2553
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#define mmDP4_DP_SEC_CNTL2_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL3 0x2554
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#define mmDP4_DP_SEC_CNTL3_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL4 0x2555
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#define mmDP4_DP_SEC_CNTL4_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL5 0x2556
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#define mmDP4_DP_SEC_CNTL5_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL6 0x2557
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#define mmDP4_DP_SEC_CNTL6_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL7 0x2558
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#define mmDP4_DP_SEC_CNTL7_BASE_IDX 2
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#define mmDP4_DP_DB_CNTL 0x2559
|
#define mmDP4_DP_DB_CNTL_BASE_IDX 2
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#define mmDP4_DP_MSA_VBID_MISC 0x255a
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#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2
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#define mmDP4_DP_SEC_METADATA_TRANSMISSION 0x255b
|
#define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
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#define mmDP4_DP_DSC_BYTES_PER_PIXEL 0x255c
|
#define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
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#define mmDP4_DP_ALPM_CNTL 0x255d
|
#define mmDP4_DP_ALPM_CNTL_BASE_IDX 2
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#define mmDP4_DP_GSP8_CNTL 0x255e
|
#define mmDP4_DP_GSP8_CNTL_BASE_IDX 2
|
#define mmDP4_DP_GSP9_CNTL 0x255f
|
#define mmDP4_DP_GSP9_CNTL_BASE_IDX 2
|
#define mmDP4_DP_GSP10_CNTL 0x2560
|
#define mmDP4_DP_GSP10_CNTL_BASE_IDX 2
|
#define mmDP4_DP_GSP11_CNTL 0x2561
|
#define mmDP4_DP_GSP11_CNTL_BASE_IDX 2
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#define mmDP4_DP_GSP_EN_DB_STATUS 0x2562
|
#define mmDP4_DP_GSP_EN_DB_STATUS_BASE_IDX 2
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|
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// addressBlock: dce_dc_dio_dig5_vpg_vpg_dispdec
|
// base address: 0x168a0
|
#define mmVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL 0x2568
|
#define mmVPG5_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 2
|
#define mmVPG5_VPG_GENERIC_PACKET_DATA 0x2569
|
#define mmVPG5_VPG_GENERIC_PACKET_DATA_BASE_IDX 2
|
#define mmVPG5_VPG_GSP_FRAME_UPDATE_CTRL 0x256a
|
#define mmVPG5_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 2
|
#define mmVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x256b
|
#define mmVPG5_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 2
|
#define mmVPG5_VPG_GENERIC_STATUS 0x256c
|
#define mmVPG5_VPG_GENERIC_STATUS_BASE_IDX 2
|
#define mmVPG5_VPG_MEM_PWR 0x256d
|
#define mmVPG5_VPG_MEM_PWR_BASE_IDX 2
|
#define mmVPG5_VPG_ISRC1_2_ACCESS_CTRL 0x256e
|
#define mmVPG5_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 2
|
#define mmVPG5_VPG_ISRC1_2_DATA 0x256f
|
#define mmVPG5_VPG_ISRC1_2_DATA_BASE_IDX 2
|
#define mmVPG5_VPG_MPEG_INFO0 0x2570
|
#define mmVPG5_VPG_MPEG_INFO0_BASE_IDX 2
|
#define mmVPG5_VPG_MPEG_INFO1 0x2571
|
#define mmVPG5_VPG_MPEG_INFO1_BASE_IDX 2
|
|
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// addressBlock: dce_dc_dio_dig5_afmt_afmt_dispdec
|
// base address: 0x168cc
|
#define mmAFMT5_AFMT_VBI_PACKET_CONTROL 0x2574
|
#define mmAFMT5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL2 0x2575
|
#define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
|
#define mmAFMT5_AFMT_AUDIO_INFO0 0x2576
|
#define mmAFMT5_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmAFMT5_AFMT_AUDIO_INFO1 0x2577
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#define mmAFMT5_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmAFMT5_AFMT_60958_0 0x2578
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#define mmAFMT5_AFMT_60958_0_BASE_IDX 2
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#define mmAFMT5_AFMT_60958_1 0x2579
|
#define mmAFMT5_AFMT_60958_1_BASE_IDX 2
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#define mmAFMT5_AFMT_AUDIO_CRC_CONTROL 0x257a
|
#define mmAFMT5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmAFMT5_AFMT_RAMP_CONTROL0 0x257b
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#define mmAFMT5_AFMT_RAMP_CONTROL0_BASE_IDX 2
|
#define mmAFMT5_AFMT_RAMP_CONTROL1 0x257c
|
#define mmAFMT5_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmAFMT5_AFMT_RAMP_CONTROL2 0x257d
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#define mmAFMT5_AFMT_RAMP_CONTROL2_BASE_IDX 2
|
#define mmAFMT5_AFMT_RAMP_CONTROL3 0x257e
|
#define mmAFMT5_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmAFMT5_AFMT_60958_2 0x257f
|
#define mmAFMT5_AFMT_60958_2_BASE_IDX 2
|
#define mmAFMT5_AFMT_AUDIO_CRC_RESULT 0x2580
|
#define mmAFMT5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
|
#define mmAFMT5_AFMT_STATUS 0x2581
|
#define mmAFMT5_AFMT_STATUS_BASE_IDX 2
|
#define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL 0x2582
|
#define mmAFMT5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmAFMT5_AFMT_INFOFRAME_CONTROL0 0x2583
|
#define mmAFMT5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmAFMT5_AFMT_INTERRUPT_STATUS 0x2584
|
#define mmAFMT5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmAFMT5_AFMT_AUDIO_SRC_CONTROL 0x2585
|
#define mmAFMT5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmAFMT5_AFMT_MEM_PWR 0x2587
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#define mmAFMT5_AFMT_MEM_PWR_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dig5_dme_dme_dispdec
|
// base address: 0x16924
|
#define mmDME5_DME_CONTROL 0x2589
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#define mmDME5_DME_CONTROL_BASE_IDX 2
|
#define mmDME5_DME_MEMORY_CONTROL 0x258a
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#define mmDME5_DME_MEMORY_CONTROL_BASE_IDX 2
|
|
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// addressBlock: dce_dc_dio_dig5_dispdec
|
// base address: 0x1400
|
#define mmDIG5_DIG_FE_CNTL 0x258b
|
#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
|
#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x258c
|
#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
|
#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x258d
|
#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
|
#define mmDIG5_DIG_CLOCK_PATTERN 0x258e
|
#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG5_DIG_TEST_PATTERN 0x258f
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#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x2590
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#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG5_DIG_FIFO_STATUS 0x2591
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#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG5_HDMI_METADATA_PACKET_CONTROL 0x2592
|
#define mmDIG5_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG5_HDMI_CONTROL 0x2593
|
#define mmDIG5_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG5_HDMI_STATUS 0x2594
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#define mmDIG5_HDMI_STATUS_BASE_IDX 2
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#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x2595
|
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x2596
|
#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x2597
|
#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x2598
|
#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x2599
|
#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x259a
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL6 0x259b
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL6_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5 0x259c
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
|
#define mmDIG5_HDMI_GC 0x259d
|
#define mmDIG5_HDMI_GC_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x259e
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0x259f
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0x25a0
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
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#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4 0x25a1
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL7 0x25a2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL7_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL8 0x25a3
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL8_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL9 0x25a4
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL9_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL10 0x25a5
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL10_BASE_IDX 2
|
#define mmDIG5_HDMI_DB_CONTROL 0x25a6
|
#define mmDIG5_HDMI_DB_CONTROL_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_32_0 0x25a7
|
#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_32_1 0x25a8
|
#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_44_0 0x25a9
|
#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_44_1 0x25aa
|
#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_48_0 0x25ab
|
#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_48_1 0x25ac
|
#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_STATUS_0 0x25ad
|
#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_STATUS_1 0x25ae
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#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
|
#define mmDIG5_AFMT_CNTL 0x25af
|
#define mmDIG5_AFMT_CNTL_BASE_IDX 2
|
#define mmDIG5_DIG_BE_CNTL 0x25b0
|
#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
|
#define mmDIG5_DIG_BE_EN_CNTL 0x25b1
|
#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
|
|
#define mmDIG5_TMDS_CNTL 0x25d7
|
#define mmDIG5_TMDS_CNTL_BASE_IDX 2
|
#define mmDIG5_TMDS_CONTROL_CHAR 0x25d8
|
#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
|
#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x25d9
|
#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
|
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x25da
|
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
|
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x25db
|
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
|
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x25dc
|
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
|
#define mmDIG5_TMDS_CTL_BITS 0x25de
|
#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
|
#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x25df
|
#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
|
#define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR 0x25e0
|
#define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
|
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x25e1
|
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
|
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x25e2
|
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
|
#define mmDIG5_DIG_VERSION 0x25e4
|
#define mmDIG5_DIG_VERSION_BASE_IDX 2
|
#define mmDIG5_DIG_LANE_ENABLE 0x25e5
|
#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
|
#define mmDIG5_FORCE_DIG_DISABLE 0x25e6
|
#define mmDIG5_FORCE_DIG_DISABLE_BASE_IDX 2
|
|
// addressBlock: dce_dc_dio_dp5_dispdec
|
// base address: 0x1400
|
#define mmDP5_DP_LINK_CNTL 0x2608
|
#define mmDP5_DP_LINK_CNTL_BASE_IDX 2
|
#define mmDP5_DP_PIXEL_FORMAT 0x2609
|
#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
|
#define mmDP5_DP_MSA_COLORIMETRY 0x260a
|
#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
|
#define mmDP5_DP_CONFIG 0x260b
|
#define mmDP5_DP_CONFIG_BASE_IDX 2
|
#define mmDP5_DP_VID_STREAM_CNTL 0x260c
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#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
|
#define mmDP5_DP_STEER_FIFO 0x260d
|
#define mmDP5_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP5_DP_MSA_MISC 0x260e
|
#define mmDP5_DP_MSA_MISC_BASE_IDX 2
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#define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
|
#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
|
#define mmDP5_DP_VID_TIMING 0x2610
|
#define mmDP5_DP_VID_TIMING_BASE_IDX 2
|
#define mmDP5_DP_VID_N 0x2611
|
#define mmDP5_DP_VID_N_BASE_IDX 2
|
#define mmDP5_DP_VID_M 0x2612
|
#define mmDP5_DP_VID_M_BASE_IDX 2
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#define mmDP5_DP_LINK_FRAMING_CNTL 0x2613
|
#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
|
#define mmDP5_DP_HBR2_EYE_PATTERN 0x2614
|
#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
|
#define mmDP5_DP_VID_MSA_VBID 0x2615
|
#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
|
#define mmDP5_DP_VID_INTERRUPT_CNTL 0x2616
|
#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CNTL 0x2617
|
#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x2618
|
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_SYM0 0x2619
|
#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
|
#define mmDP5_DP_DPHY_SYM1 0x261a
|
#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
|
#define mmDP5_DP_DPHY_SYM2 0x261b
|
#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
|
#define mmDP5_DP_DPHY_8B10B_CNTL 0x261c
|
#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_PRBS_CNTL 0x261d
|
#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_SCRAM_CNTL 0x261e
|
#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_EN 0x261f
|
#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_CNTL 0x2620
|
#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_RESULT 0x2621
|
#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x2622
|
#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x2623
|
#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
|
#define mmDP5_DP_DPHY_FAST_TRAINING 0x2624
|
#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
|
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x2625
|
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL 0x262b
|
#define mmDP5_DP_SEC_CNTL_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL1 0x262c
|
#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
|
#define mmDP5_DP_SEC_FRAMING1 0x262d
|
#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
|
#define mmDP5_DP_SEC_FRAMING2 0x262e
|
#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
|
#define mmDP5_DP_SEC_FRAMING3 0x262f
|
#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
|
#define mmDP5_DP_SEC_FRAMING4 0x2630
|
#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
|
#define mmDP5_DP_SEC_AUD_N 0x2631
|
#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
|
#define mmDP5_DP_SEC_AUD_N_READBACK 0x2632
|
#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
|
#define mmDP5_DP_SEC_AUD_M 0x2633
|
#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
|
#define mmDP5_DP_SEC_AUD_M_READBACK 0x2634
|
#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
|
#define mmDP5_DP_SEC_TIMESTAMP 0x2635
|
#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
|
#define mmDP5_DP_SEC_PACKET_CNTL 0x2636
|
#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
|
#define mmDP5_DP_MSE_RATE_CNTL 0x2637
|
#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
|
#define mmDP5_DP_MSE_RATE_UPDATE 0x2639
|
#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT0 0x263a
|
#define mmDP5_DP_MSE_SAT0_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT1 0x263b
|
#define mmDP5_DP_MSE_SAT1_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT2 0x263c
|
#define mmDP5_DP_MSE_SAT2_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT_UPDATE 0x263d
|
#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
|
#define mmDP5_DP_MSE_LINK_TIMING 0x263e
|
#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
|
#define mmDP5_DP_MSE_MISC_CNTL 0x263f
|
#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x2644
|
#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x2645
|
#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT0_STATUS 0x2647
|
#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT1_STATUS 0x2648
|
#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT2_STATUS 0x2649
|
#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
|
#define mmDP5_DP_MSA_TIMING_PARAM1 0x264c
|
#define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 2
|
#define mmDP5_DP_MSA_TIMING_PARAM2 0x264d
|
#define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX 2
|
#define mmDP5_DP_MSA_TIMING_PARAM3 0x264e
|
#define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX 2
|
#define mmDP5_DP_MSA_TIMING_PARAM4 0x264f
|
#define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX 2
|
#define mmDP5_DP_MSO_CNTL 0x2650
|
#define mmDP5_DP_MSO_CNTL_BASE_IDX 2
|
#define mmDP5_DP_MSO_CNTL1 0x2651
|
#define mmDP5_DP_MSO_CNTL1_BASE_IDX 2
|
#define mmDP5_DP_DSC_CNTL 0x2652
|
#define mmDP5_DP_DSC_CNTL_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL2 0x2653
|
#define mmDP5_DP_SEC_CNTL2_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL3 0x2654
|
#define mmDP5_DP_SEC_CNTL3_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL4 0x2655
|
#define mmDP5_DP_SEC_CNTL4_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL5 0x2656
|
#define mmDP5_DP_SEC_CNTL5_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL6 0x2657
|
#define mmDP5_DP_SEC_CNTL6_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL7 0x2658
|
#define mmDP5_DP_SEC_CNTL7_BASE_IDX 2
|
#define mmDP5_DP_DB_CNTL 0x2659
|
#define mmDP5_DP_DB_CNTL_BASE_IDX 2
|
#define mmDP5_DP_MSA_VBID_MISC 0x265a
|
#define mmDP5_DP_MSA_VBID_MISC_BASE_IDX 2
|
#define mmDP5_DP_SEC_METADATA_TRANSMISSION 0x265b
|
#define mmDP5_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
|
#define mmDP5_DP_DSC_BYTES_PER_PIXEL 0x265c
|
#define mmDP5_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmDP5_DP_ALPM_CNTL 0x265d
|
#define mmDP5_DP_ALPM_CNTL_BASE_IDX 2
|
#define mmDP5_DP_GSP8_CNTL 0x265e
|
#define mmDP5_DP_GSP8_CNTL_BASE_IDX 2
|
#define mmDP5_DP_GSP9_CNTL 0x265f
|
#define mmDP5_DP_GSP9_CNTL_BASE_IDX 2
|
#define mmDP5_DP_GSP10_CNTL 0x2660
|
#define mmDP5_DP_GSP10_CNTL_BASE_IDX 2
|
#define mmDP5_DP_GSP11_CNTL 0x2661
|
#define mmDP5_DP_GSP11_CNTL_BASE_IDX 2
|
#define mmDP5_DP_GSP_EN_DB_STATUS 0x2662
|
#define mmDP5_DP_GSP_EN_DB_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcio_dcio_dispdec
|
// base address: 0x0
|
#define mmDC_GENERICA 0x2868
|
#define mmDC_GENERICA_BASE_IDX 2
|
#define mmDC_GENERICB 0x2869
|
#define mmDC_GENERICB_BASE_IDX 2
|
#define mmDCIO_CLOCK_CNTL 0x286a
|
#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
|
#define mmDC_REF_CLK_CNTL 0x286b
|
#define mmDC_REF_CLK_CNTL_BASE_IDX 2
|
#define mmUNIPHYA_LINK_CNTL 0x286d
|
#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
|
#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYB_LINK_CNTL 0x286f
|
#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
|
#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYC_LINK_CNTL 0x2871
|
#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
|
#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYD_LINK_CNTL 0x2873
|
#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
|
#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYE_LINK_CNTL 0x2875
|
#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
|
#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
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#define mmUNIPHYF_LINK_CNTL 0x2877
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#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
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#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x2878
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#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
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#define mmDCIO_WRCMD_DELAY 0x287e
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#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
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#define mmDC_PINSTRAPS 0x2880
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#define mmDC_PINSTRAPS_BASE_IDX 2
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#define mmLVTMA_PWRSEQ_CNTL 0x2883
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#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
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#define mmLVTMA_PWRSEQ_STATE 0x2884
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#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
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#define mmLVTMA_PWRSEQ_REF_DIV 0x2885
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#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
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#define mmLVTMA_PWRSEQ_DELAY1 0x2886
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#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
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#define mmLVTMA_PWRSEQ_DELAY2 0x2887
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#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
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#define mmBL_PWM_CNTL 0x2888
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#define mmBL_PWM_CNTL_BASE_IDX 2
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#define mmBL_PWM_CNTL2 0x2889
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#define mmBL_PWM_CNTL2_BASE_IDX 2
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#define mmBL_PWM_PERIOD_CNTL 0x288a
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#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
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#define mmBL_PWM_GRP1_REG_LOCK 0x288b
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#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
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#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c
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#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
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#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
|
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
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#define mmDCIO_SOFT_RESET 0x289e
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#define mmDCIO_SOFT_RESET_BASE_IDX 2
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// addressBlock: dce_dc_dcio_dcio_chip_dispdec
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// base address: 0x0
|
#define mmDC_GPIO_GENERIC_MASK 0x28c8
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#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
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#define mmDC_GPIO_GENERIC_A 0x28c9
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#define mmDC_GPIO_GENERIC_A_BASE_IDX 2
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#define mmDC_GPIO_GENERIC_EN 0x28ca
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#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
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#define mmDC_GPIO_GENERIC_Y 0x28cb
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#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC1_MASK 0x28d0
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#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC1_A 0x28d1
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#define mmDC_GPIO_DDC1_A_BASE_IDX 2
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#define mmDC_GPIO_DDC1_EN 0x28d2
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#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC1_Y 0x28d3
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#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC2_MASK 0x28d4
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#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC2_A 0x28d5
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#define mmDC_GPIO_DDC2_A_BASE_IDX 2
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#define mmDC_GPIO_DDC2_EN 0x28d6
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#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC2_Y 0x28d7
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#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC3_MASK 0x28d8
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#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC3_A 0x28d9
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#define mmDC_GPIO_DDC3_A_BASE_IDX 2
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#define mmDC_GPIO_DDC3_EN 0x28da
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#define mmDC_GPIO_DDC3_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC3_Y 0x28db
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#define mmDC_GPIO_DDC3_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC4_MASK 0x28dc
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#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC4_A 0x28dd
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#define mmDC_GPIO_DDC4_A_BASE_IDX 2
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#define mmDC_GPIO_DDC4_EN 0x28de
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#define mmDC_GPIO_DDC4_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC4_Y 0x28df
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#define mmDC_GPIO_DDC4_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC5_MASK 0x28e0
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#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC5_A 0x28e1
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#define mmDC_GPIO_DDC5_A_BASE_IDX 2
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#define mmDC_GPIO_DDC5_EN 0x28e2
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#define mmDC_GPIO_DDC5_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC5_Y 0x28e3
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#define mmDC_GPIO_DDC5_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC6_MASK 0x28e4
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#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC6_A 0x28e5
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#define mmDC_GPIO_DDC6_A_BASE_IDX 2
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#define mmDC_GPIO_DDC6_EN 0x28e6
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#define mmDC_GPIO_DDC6_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC6_Y 0x28e7
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#define mmDC_GPIO_DDC6_Y_BASE_IDX 2
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#define mmDC_GPIO_DDCVGA_MASK 0x28e8
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#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDCVGA_A 0x28e9
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#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
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#define mmDC_GPIO_DDCVGA_EN 0x28ea
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#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
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#define mmDC_GPIO_DDCVGA_Y 0x28eb
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#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
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#define mmDC_GPIO_GENLK_MASK 0x28f0
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#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
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#define mmDC_GPIO_GENLK_A 0x28f1
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#define mmDC_GPIO_GENLK_A_BASE_IDX 2
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#define mmDC_GPIO_GENLK_EN 0x28f2
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#define mmDC_GPIO_GENLK_EN_BASE_IDX 2
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#define mmDC_GPIO_GENLK_Y 0x28f3
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#define mmDC_GPIO_GENLK_Y_BASE_IDX 2
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#define mmDC_GPIO_HPD_MASK 0x28f4
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#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
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#define mmDC_GPIO_HPD_A 0x28f5
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#define mmDC_GPIO_HPD_A_BASE_IDX 2
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#define mmDC_GPIO_HPD_EN 0x28f6
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#define mmDC_GPIO_HPD_EN_BASE_IDX 2
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#define mmDC_GPIO_HPD_Y 0x28f7
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#define mmDC_GPIO_HPD_Y_BASE_IDX 2
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#define mmDC_GPIO_PWRSEQ_MASK 0x28f8
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#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
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#define mmDC_GPIO_PWRSEQ_A 0x28f9
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#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
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#define mmDC_GPIO_PWRSEQ_EN 0x28fa
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#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
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#define mmDC_GPIO_PWRSEQ_Y 0x28fb
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#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
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#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc
|
#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
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#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd
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#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
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#define mmPHY_AUX_CNTL 0x28ff
|
#define mmPHY_AUX_CNTL_BASE_IDX 2
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#define mmDC_GPIO_TX12_EN 0x2915
|
#define mmDC_GPIO_TX12_EN_BASE_IDX 2
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#define mmDC_GPIO_AUX_CTRL_0 0x2916
|
#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
|
#define mmDC_GPIO_AUX_CTRL_1 0x2917
|
#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
|
#define mmDC_GPIO_AUX_CTRL_2 0x2918
|
#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
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#define mmDC_GPIO_RXEN 0x2919
|
#define mmDC_GPIO_RXEN_BASE_IDX 2
|
#define mmDC_GPIO_PULLUPEN 0x291a
|
#define mmDC_GPIO_PULLUPEN_BASE_IDX 2
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#define mmDC_GPIO_AUX_CTRL_3 0x291b
|
#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2
|
#define mmDC_GPIO_AUX_CTRL_4 0x291c
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#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2
|
#define mmDC_GPIO_AUX_CTRL_5 0x291d
|
#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2
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#define mmAUXI2C_PAD_ALL_PWR_OK 0x291e
|
#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
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// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
|
// base address: 0x0
|
#define mmDSC_TOP0_DSC_TOP_CONTROL 0x3000
|
#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2
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#define mmDSC_TOP0_DSC_DEBUG_CONTROL 0x3001
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#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2
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|
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// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
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// base address: 0x0
|
#define mmDSCCIF0_DSCCIF_CONFIG0 0x3005
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#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2
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#define mmDSCCIF0_DSCCIF_CONFIG1 0x3006
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#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2
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// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
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// base address: 0x0
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#define mmDSCC0_DSCC_CONFIG0 0x300a
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#define mmDSCC0_DSCC_CONFIG0_BASE_IDX 2
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#define mmDSCC0_DSCC_CONFIG1 0x300b
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#define mmDSCC0_DSCC_CONFIG1_BASE_IDX 2
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#define mmDSCC0_DSCC_STATUS 0x300c
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#define mmDSCC0_DSCC_STATUS_BASE_IDX 2
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#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d
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#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG0 0x300e
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#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG1 0x300f
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#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG2 0x3010
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#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG3 0x3011
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#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG4 0x3012
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#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG5 0x3013
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#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG6 0x3014
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#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG7 0x3015
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#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG8 0x3016
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#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG9 0x3017
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#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG10 0x3018
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#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG11 0x3019
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#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG12 0x301a
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#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG13 0x301b
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#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG14 0x301c
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#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG15 0x301d
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#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG16 0x301e
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#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG17 0x301f
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#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG18 0x3020
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#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG19 0x3021
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#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG20 0x3022
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#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG21 0x3023
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#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2
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#define mmDSCC0_DSCC_PPS_CONFIG22 0x3024
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#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2
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#define mmDSCC0_DSCC_MEM_POWER_CONTROL 0x3025
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#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
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#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026
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#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
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#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027
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#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
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#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028
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#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
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#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029
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#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
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#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a
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#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
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#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b
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#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
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#define mmDSCC0_DSCC_MAX_ABS_ERROR0 0x302c
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#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
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#define mmDSCC0_DSCC_MAX_ABS_ERROR1 0x302d
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#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
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#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e
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#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f
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#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
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#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030
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#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
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#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031
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#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
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#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032
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#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
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#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033
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#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
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#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034
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#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
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#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035
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#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
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// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xc140
|
#define mmDC_PERFMON21_PERFCOUNTER_CNTL 0x3050
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#define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON21_PERFCOUNTER_CNTL2 0x3051
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#define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON21_PERFCOUNTER_STATE 0x3052
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#define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON21_PERFMON_CNTL 0x3053
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#define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON21_PERFMON_CNTL2 0x3054
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#define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x3055
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#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON21_PERFMON_CVALUE_LOW 0x3056
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#define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON21_PERFMON_HI 0x3057
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#define mmDC_PERFMON21_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON21_PERFMON_LOW 0x3058
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#define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
|
// base address: 0x170
|
#define mmDSC_TOP1_DSC_TOP_CONTROL 0x305c
|
#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2
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#define mmDSC_TOP1_DSC_DEBUG_CONTROL 0x305d
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#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
|
// base address: 0x170
|
#define mmDSCCIF1_DSCCIF_CONFIG0 0x3061
|
#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2
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#define mmDSCCIF1_DSCCIF_CONFIG1 0x3062
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#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2
|
|
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// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
|
// base address: 0x170
|
#define mmDSCC1_DSCC_CONFIG0 0x3066
|
#define mmDSCC1_DSCC_CONFIG0_BASE_IDX 2
|
#define mmDSCC1_DSCC_CONFIG1 0x3067
|
#define mmDSCC1_DSCC_CONFIG1_BASE_IDX 2
|
#define mmDSCC1_DSCC_STATUS 0x3068
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#define mmDSCC1_DSCC_STATUS_BASE_IDX 2
|
#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069
|
#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG0 0x306a
|
#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG1 0x306b
|
#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG2 0x306c
|
#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG3 0x306d
|
#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG4 0x306e
|
#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG5 0x306f
|
#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG6 0x3070
|
#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG7 0x3071
|
#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG8 0x3072
|
#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG9 0x3073
|
#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG10 0x3074
|
#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG11 0x3075
|
#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG12 0x3076
|
#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG13 0x3077
|
#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG14 0x3078
|
#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG15 0x3079
|
#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG16 0x307a
|
#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG17 0x307b
|
#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG18 0x307c
|
#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG19 0x307d
|
#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG20 0x307e
|
#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG21 0x307f
|
#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG22 0x3080
|
#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2
|
#define mmDSCC1_DSCC_MEM_POWER_CONTROL 0x3081
|
#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
|
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082
|
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083
|
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084
|
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085
|
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086
|
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087
|
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC1_DSCC_MAX_ABS_ERROR0 0x3088
|
#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
|
#define mmDSCC1_DSCC_MAX_ABS_ERROR1 0x3089
|
#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a
|
#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b
|
#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c
|
#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d
|
#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xc2b0
|
#define mmDC_PERFMON22_PERFCOUNTER_CNTL 0x30ac
|
#define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFCOUNTER_CNTL2 0x30ad
|
#define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFCOUNTER_STATE 0x30ae
|
#define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFMON_CNTL 0x30af
|
#define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFMON_CNTL2 0x30b0
|
#define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x30b1
|
#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFMON_CVALUE_LOW 0x30b2
|
#define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFMON_HI 0x30b3
|
#define mmDC_PERFMON22_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFMON_LOW 0x30b4
|
#define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
|
// base address: 0x2e0
|
#define mmDSC_TOP2_DSC_TOP_CONTROL 0x30b8
|
#define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2
|
#define mmDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9
|
#define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
|
// base address: 0x2e0
|
#define mmDSCCIF2_DSCCIF_CONFIG0 0x30bd
|
#define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2
|
#define mmDSCCIF2_DSCCIF_CONFIG1 0x30be
|
#define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
|
// base address: 0x2e0
|
#define mmDSCC2_DSCC_CONFIG0 0x30c2
|
#define mmDSCC2_DSCC_CONFIG0_BASE_IDX 2
|
#define mmDSCC2_DSCC_CONFIG1 0x30c3
|
#define mmDSCC2_DSCC_CONFIG1_BASE_IDX 2
|
#define mmDSCC2_DSCC_STATUS 0x30c4
|
#define mmDSCC2_DSCC_STATUS_BASE_IDX 2
|
#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5
|
#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG0 0x30c6
|
#define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG1 0x30c7
|
#define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG2 0x30c8
|
#define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG3 0x30c9
|
#define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG4 0x30ca
|
#define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG5 0x30cb
|
#define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG6 0x30cc
|
#define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG7 0x30cd
|
#define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG8 0x30ce
|
#define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG9 0x30cf
|
#define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG10 0x30d0
|
#define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG11 0x30d1
|
#define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG12 0x30d2
|
#define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG13 0x30d3
|
#define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG14 0x30d4
|
#define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG15 0x30d5
|
#define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG16 0x30d6
|
#define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG17 0x30d7
|
#define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG18 0x30d8
|
#define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG19 0x30d9
|
#define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG20 0x30da
|
#define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG21 0x30db
|
#define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG22 0x30dc
|
#define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2
|
#define mmDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd
|
#define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
|
#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de
|
#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df
|
#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0
|
#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1
|
#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2
|
#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3
|
#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4
|
#define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
|
#define mmDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5
|
#define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6
|
#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7
|
#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8
|
#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9
|
#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xc420
|
#define mmDC_PERFMON23_PERFCOUNTER_CNTL 0x3108
|
#define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFCOUNTER_CNTL2 0x3109
|
#define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFCOUNTER_STATE 0x310a
|
#define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFMON_CNTL 0x310b
|
#define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFMON_CNTL2 0x310c
|
#define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x310d
|
#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFMON_CVALUE_LOW 0x310e
|
#define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFMON_HI 0x310f
|
#define mmDC_PERFMON23_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFMON_LOW 0x3110
|
#define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
|
// base address: 0x450
|
#define mmDSC_TOP3_DSC_TOP_CONTROL 0x3114
|
#define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2
|
#define mmDSC_TOP3_DSC_DEBUG_CONTROL 0x3115
|
#define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
|
// base address: 0x450
|
#define mmDSCCIF3_DSCCIF_CONFIG0 0x3119
|
#define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2
|
#define mmDSCCIF3_DSCCIF_CONFIG1 0x311a
|
#define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
|
// base address: 0x450
|
#define mmDSCC3_DSCC_CONFIG0 0x311e
|
#define mmDSCC3_DSCC_CONFIG0_BASE_IDX 2
|
#define mmDSCC3_DSCC_CONFIG1 0x311f
|
#define mmDSCC3_DSCC_CONFIG1_BASE_IDX 2
|
#define mmDSCC3_DSCC_STATUS 0x3120
|
#define mmDSCC3_DSCC_STATUS_BASE_IDX 2
|
#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121
|
#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG0 0x3122
|
#define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG1 0x3123
|
#define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG2 0x3124
|
#define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG3 0x3125
|
#define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG4 0x3126
|
#define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG5 0x3127
|
#define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG6 0x3128
|
#define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG7 0x3129
|
#define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG8 0x312a
|
#define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG9 0x312b
|
#define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG10 0x312c
|
#define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG11 0x312d
|
#define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG12 0x312e
|
#define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG13 0x312f
|
#define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG14 0x3130
|
#define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG15 0x3131
|
#define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG16 0x3132
|
#define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG17 0x3133
|
#define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG18 0x3134
|
#define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG19 0x3135
|
#define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG20 0x3136
|
#define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG21 0x3137
|
#define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG22 0x3138
|
#define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2
|
#define mmDSCC3_DSCC_MEM_POWER_CONTROL 0x3139
|
#define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
|
#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a
|
#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b
|
#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c
|
#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d
|
#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e
|
#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f
|
#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC3_DSCC_MAX_ABS_ERROR0 0x3140
|
#define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
|
#define mmDSCC3_DSCC_MAX_ABS_ERROR1 0x3141
|
#define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142
|
#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143
|
#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144
|
#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145
|
#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xc590
|
#define mmDC_PERFMON24_PERFCOUNTER_CNTL 0x3164
|
#define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFCOUNTER_CNTL2 0x3165
|
#define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFCOUNTER_STATE 0x3166
|
#define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFMON_CNTL 0x3167
|
#define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFMON_CNTL2 0x3168
|
#define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC 0x3169
|
#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFMON_CVALUE_LOW 0x316a
|
#define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFMON_HI 0x316b
|
#define mmDC_PERFMON24_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFMON_LOW 0x316c
|
#define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec
|
// base address: 0x5c0
|
#define mmDSC_TOP4_DSC_TOP_CONTROL 0x3170
|
#define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX 2
|
#define mmDSC_TOP4_DSC_DEBUG_CONTROL 0x3171
|
#define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec
|
// base address: 0x5c0
|
#define mmDSCCIF4_DSCCIF_CONFIG0 0x3175
|
#define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX 2
|
#define mmDSCCIF4_DSCCIF_CONFIG1 0x3176
|
#define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec
|
// base address: 0x5c0
|
#define mmDSCC4_DSCC_CONFIG0 0x317a
|
#define mmDSCC4_DSCC_CONFIG0_BASE_IDX 2
|
#define mmDSCC4_DSCC_CONFIG1 0x317b
|
#define mmDSCC4_DSCC_CONFIG1_BASE_IDX 2
|
#define mmDSCC4_DSCC_STATUS 0x317c
|
#define mmDSCC4_DSCC_STATUS_BASE_IDX 2
|
#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS 0x317d
|
#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG0 0x317e
|
#define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG1 0x317f
|
#define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG2 0x3180
|
#define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG3 0x3181
|
#define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG4 0x3182
|
#define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG5 0x3183
|
#define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG6 0x3184
|
#define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG7 0x3185
|
#define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG8 0x3186
|
#define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG9 0x3187
|
#define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG10 0x3188
|
#define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG11 0x3189
|
#define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG12 0x318a
|
#define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG13 0x318b
|
#define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG14 0x318c
|
#define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG15 0x318d
|
#define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG16 0x318e
|
#define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG17 0x318f
|
#define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG18 0x3190
|
#define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG19 0x3191
|
#define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG20 0x3192
|
#define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG21 0x3193
|
#define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG22 0x3194
|
#define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX 2
|
#define mmDSCC4_DSCC_MEM_POWER_CONTROL 0x3195
|
#define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
|
#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3196
|
#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3197
|
#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3198
|
#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3199
|
#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER 0x319a
|
#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER 0x319b
|
#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC4_DSCC_MAX_ABS_ERROR0 0x319c
|
#define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
|
#define mmDSCC4_DSCC_MAX_ABS_ERROR1 0x319d
|
#define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x319e
|
#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x319f
|
#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31a0
|
#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31a1
|
#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31a2
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31a3
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x31a4
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x31a5
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xc700
|
#define mmDC_PERFMON25_PERFCOUNTER_CNTL 0x31c0
|
#define mmDC_PERFMON25_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFCOUNTER_CNTL2 0x31c1
|
#define mmDC_PERFMON25_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFCOUNTER_STATE 0x31c2
|
#define mmDC_PERFMON25_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFMON_CNTL 0x31c3
|
#define mmDC_PERFMON25_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFMON_CNTL2 0x31c4
|
#define mmDC_PERFMON25_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC 0x31c5
|
#define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFMON_CVALUE_LOW 0x31c6
|
#define mmDC_PERFMON25_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFMON_HI 0x31c7
|
#define mmDC_PERFMON25_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFMON_LOW 0x31c8
|
#define mmDC_PERFMON25_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec
|
// base address: 0x730
|
#define mmDSC_TOP5_DSC_TOP_CONTROL 0x31cc
|
#define mmDSC_TOP5_DSC_TOP_CONTROL_BASE_IDX 2
|
#define mmDSC_TOP5_DSC_DEBUG_CONTROL 0x31cd
|
#define mmDSC_TOP5_DSC_DEBUG_CONTROL_BASE_IDX 2
|
|
// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec
|
// base address: 0x730
|
#define mmDSCCIF5_DSCCIF_CONFIG0 0x31d1
|
#define mmDSCCIF5_DSCCIF_CONFIG0_BASE_IDX 2
|
#define mmDSCCIF5_DSCCIF_CONFIG1 0x31d2
|
#define mmDSCCIF5_DSCCIF_CONFIG1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec
|
// base address: 0x730
|
#define mmDSCC5_DSCC_CONFIG0 0x31d6
|
#define mmDSCC5_DSCC_CONFIG0_BASE_IDX 2
|
#define mmDSCC5_DSCC_CONFIG1 0x31d7
|
#define mmDSCC5_DSCC_CONFIG1_BASE_IDX 2
|
#define mmDSCC5_DSCC_STATUS 0x31d8
|
#define mmDSCC5_DSCC_STATUS_BASE_IDX 2
|
#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS 0x31d9
|
#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG0 0x31da
|
#define mmDSCC5_DSCC_PPS_CONFIG0_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG1 0x31db
|
#define mmDSCC5_DSCC_PPS_CONFIG1_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG2 0x31dc
|
#define mmDSCC5_DSCC_PPS_CONFIG2_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG3 0x31dd
|
#define mmDSCC5_DSCC_PPS_CONFIG3_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG4 0x31de
|
#define mmDSCC5_DSCC_PPS_CONFIG4_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG5 0x31df
|
#define mmDSCC5_DSCC_PPS_CONFIG5_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG6 0x31e0
|
#define mmDSCC5_DSCC_PPS_CONFIG6_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG7 0x31e1
|
#define mmDSCC5_DSCC_PPS_CONFIG7_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG8 0x31e2
|
#define mmDSCC5_DSCC_PPS_CONFIG8_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG9 0x31e3
|
#define mmDSCC5_DSCC_PPS_CONFIG9_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG10 0x31e4
|
#define mmDSCC5_DSCC_PPS_CONFIG10_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG11 0x31e5
|
#define mmDSCC5_DSCC_PPS_CONFIG11_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG12 0x31e6
|
#define mmDSCC5_DSCC_PPS_CONFIG12_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG13 0x31e7
|
#define mmDSCC5_DSCC_PPS_CONFIG13_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG14 0x31e8
|
#define mmDSCC5_DSCC_PPS_CONFIG14_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG15 0x31e9
|
#define mmDSCC5_DSCC_PPS_CONFIG15_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG16 0x31ea
|
#define mmDSCC5_DSCC_PPS_CONFIG16_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG17 0x31eb
|
#define mmDSCC5_DSCC_PPS_CONFIG17_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG18 0x31ec
|
#define mmDSCC5_DSCC_PPS_CONFIG18_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG19 0x31ed
|
#define mmDSCC5_DSCC_PPS_CONFIG19_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG20 0x31ee
|
#define mmDSCC5_DSCC_PPS_CONFIG20_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG21 0x31ef
|
#define mmDSCC5_DSCC_PPS_CONFIG21_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG22 0x31f0
|
#define mmDSCC5_DSCC_PPS_CONFIG22_BASE_IDX 2
|
#define mmDSCC5_DSCC_MEM_POWER_CONTROL 0x31f1
|
#define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
|
#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER 0x31f2
|
#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER 0x31f3
|
#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER 0x31f4
|
#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER 0x31f5
|
#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER 0x31f6
|
#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER 0x31f7
|
#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC5_DSCC_MAX_ABS_ERROR0 0x31f8
|
#define mmDSCC5_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
|
#define mmDSCC5_DSCC_MAX_ABS_ERROR1 0x31f9
|
#define mmDSCC5_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x31fa
|
#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x31fb
|
#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31fc
|
#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31fd
|
#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31fe
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31ff
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3200
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3201
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xc870
|
#define mmDC_PERFMON26_PERFCOUNTER_CNTL 0x321c
|
#define mmDC_PERFMON26_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFCOUNTER_CNTL2 0x321d
|
#define mmDC_PERFMON26_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFCOUNTER_STATE 0x321e
|
#define mmDC_PERFMON26_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFMON_CNTL 0x321f
|
#define mmDC_PERFMON26_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFMON_CNTL2 0x3220
|
#define mmDC_PERFMON26_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC 0x3221
|
#define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFMON_CVALUE_LOW 0x3222
|
#define mmDC_PERFMON26_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFMON_HI 0x3223
|
#define mmDC_PERFMON26_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFMON_LOW 0x3224
|
#define mmDC_PERFMON26_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_wb0_dispdec_dwb_top_dispdec
|
// base address: 0x0
|
#define mmDWB_ENABLE_CLK_CTRL 0x3228
|
#define mmDWB_ENABLE_CLK_CTRL_BASE_IDX 2
|
#define mmDWB_MEM_PWR_CTRL 0x3229
|
#define mmDWB_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmFC_MODE_CTRL 0x322a
|
#define mmFC_MODE_CTRL_BASE_IDX 2
|
#define mmFC_FLOW_CTRL 0x322b
|
#define mmFC_FLOW_CTRL_BASE_IDX 2
|
#define mmFC_WINDOW_START 0x322c
|
#define mmFC_WINDOW_START_BASE_IDX 2
|
#define mmFC_WINDOW_SIZE 0x322d
|
#define mmFC_WINDOW_SIZE_BASE_IDX 2
|
#define mmFC_SOURCE_SIZE 0x322e
|
#define mmFC_SOURCE_SIZE_BASE_IDX 2
|
#define mmDWB_UPDATE_CTRL 0x322f
|
#define mmDWB_UPDATE_CTRL_BASE_IDX 2
|
#define mmDWB_CRC_CTRL 0x3230
|
#define mmDWB_CRC_CTRL_BASE_IDX 2
|
#define mmDWB_CRC_MASK_R_G 0x3231
|
#define mmDWB_CRC_MASK_R_G_BASE_IDX 2
|
#define mmDWB_CRC_MASK_B_A 0x3232
|
#define mmDWB_CRC_MASK_B_A_BASE_IDX 2
|
#define mmDWB_CRC_VAL_R_G 0x3233
|
#define mmDWB_CRC_VAL_R_G_BASE_IDX 2
|
#define mmDWB_CRC_VAL_B_A 0x3234
|
#define mmDWB_CRC_VAL_B_A_BASE_IDX 2
|
#define mmDWB_OUT_CTRL 0x3235
|
#define mmDWB_OUT_CTRL_BASE_IDX 2
|
#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN 0x3236
|
#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_EN_BASE_IDX 2
|
#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT 0x3237
|
#define mmDWB_MMHUBBUB_BACKPRESSURE_CNT_BASE_IDX 2
|
#define mmDWB_HOST_READ_CONTROL 0x3238
|
#define mmDWB_HOST_READ_CONTROL_BASE_IDX 2
|
#define mmDWB_OVERFLOW_STATUS 0x3239
|
#define mmDWB_OVERFLOW_STATUS_BASE_IDX 2
|
#define mmDWB_OVERFLOW_COUNTER 0x323a
|
#define mmDWB_OVERFLOW_COUNTER_BASE_IDX 2
|
#define mmDWB_SOFT_RESET 0x323b
|
#define mmDWB_SOFT_RESET_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xca20
|
#define mmDC_PERFMON27_PERFCOUNTER_CNTL 0x3288
|
#define mmDC_PERFMON27_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFCOUNTER_CNTL2 0x3289
|
#define mmDC_PERFMON27_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFCOUNTER_STATE 0x328a
|
#define mmDC_PERFMON27_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFMON_CNTL 0x328b
|
#define mmDC_PERFMON27_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFMON_CNTL2 0x328c
|
#define mmDC_PERFMON27_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFMON_CVALUE_INT_MISC 0x328d
|
#define mmDC_PERFMON27_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFMON_CVALUE_LOW 0x328e
|
#define mmDC_PERFMON27_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFMON_HI 0x328f
|
#define mmDC_PERFMON27_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFMON_LOW 0x3290
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#define mmDC_PERFMON27_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_wb0_dispdec_dwbcp_dispdec
|
// base address: 0x0
|
#define mmDWB_HDR_MULT_COEF 0x3294
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#define mmDWB_HDR_MULT_COEF_BASE_IDX 2
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#define mmDWB_GAMUT_REMAP_MODE 0x3295
|
#define mmDWB_GAMUT_REMAP_MODE_BASE_IDX 2
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#define mmDWB_GAMUT_REMAP_COEF_FORMAT 0x3296
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#define mmDWB_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 2
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#define mmDWB_GAMUT_REMAPA_C11_C12 0x3297
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#define mmDWB_GAMUT_REMAPA_C11_C12_BASE_IDX 2
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#define mmDWB_GAMUT_REMAPA_C13_C14 0x3298
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#define mmDWB_GAMUT_REMAPA_C13_C14_BASE_IDX 2
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#define mmDWB_GAMUT_REMAPA_C21_C22 0x3299
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#define mmDWB_GAMUT_REMAPA_C21_C22_BASE_IDX 2
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#define mmDWB_GAMUT_REMAPA_C23_C24 0x329a
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#define mmDWB_GAMUT_REMAPA_C23_C24_BASE_IDX 2
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#define mmDWB_GAMUT_REMAPA_C31_C32 0x329b
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#define mmDWB_GAMUT_REMAPA_C31_C32_BASE_IDX 2
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#define mmDWB_GAMUT_REMAPA_C33_C34 0x329c
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#define mmDWB_GAMUT_REMAPA_C33_C34_BASE_IDX 2
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#define mmDWB_GAMUT_REMAPB_C11_C12 0x329d
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#define mmDWB_GAMUT_REMAPB_C11_C12_BASE_IDX 2
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#define mmDWB_GAMUT_REMAPB_C13_C14 0x329e
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#define mmDWB_GAMUT_REMAPB_C13_C14_BASE_IDX 2
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#define mmDWB_GAMUT_REMAPB_C21_C22 0x329f
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#define mmDWB_GAMUT_REMAPB_C21_C22_BASE_IDX 2
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#define mmDWB_GAMUT_REMAPB_C23_C24 0x32a0
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#define mmDWB_GAMUT_REMAPB_C23_C24_BASE_IDX 2
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#define mmDWB_GAMUT_REMAPB_C31_C32 0x32a1
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#define mmDWB_GAMUT_REMAPB_C31_C32_BASE_IDX 2
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#define mmDWB_GAMUT_REMAPB_C33_C34 0x32a2
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#define mmDWB_GAMUT_REMAPB_C33_C34_BASE_IDX 2
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#define mmDWB_OGAM_CONTROL 0x32a3
|
#define mmDWB_OGAM_CONTROL_BASE_IDX 2
|
#define mmDWB_OGAM_LUT_INDEX 0x32a4
|
#define mmDWB_OGAM_LUT_INDEX_BASE_IDX 2
|
#define mmDWB_OGAM_LUT_DATA 0x32a5
|
#define mmDWB_OGAM_LUT_DATA_BASE_IDX 2
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#define mmDWB_OGAM_LUT_CONTROL 0x32a6
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#define mmDWB_OGAM_LUT_CONTROL_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_START_CNTL_B 0x32a7
|
#define mmDWB_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_START_CNTL_G 0x32a8
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#define mmDWB_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_START_CNTL_R 0x32a9
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#define mmDWB_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B 0x32aa
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#define mmDWB_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B 0x32ab
|
#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G 0x32ac
|
#define mmDWB_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G 0x32ad
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#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R 0x32ae
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#define mmDWB_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R 0x32af
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#define mmDWB_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_END_CNTL1_B 0x32b0
|
#define mmDWB_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_END_CNTL2_B 0x32b1
|
#define mmDWB_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_END_CNTL1_G 0x32b2
|
#define mmDWB_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_END_CNTL2_G 0x32b3
|
#define mmDWB_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_END_CNTL1_R 0x32b4
|
#define mmDWB_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_END_CNTL2_R 0x32b5
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#define mmDWB_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_OFFSET_B 0x32b6
|
#define mmDWB_OGAM_RAMA_OFFSET_B_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_OFFSET_G 0x32b7
|
#define mmDWB_OGAM_RAMA_OFFSET_G_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_OFFSET_R 0x32b8
|
#define mmDWB_OGAM_RAMA_OFFSET_R_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_0_1 0x32b9
|
#define mmDWB_OGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_2_3 0x32ba
|
#define mmDWB_OGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_4_5 0x32bb
|
#define mmDWB_OGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_6_7 0x32bc
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#define mmDWB_OGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_8_9 0x32bd
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#define mmDWB_OGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_10_11 0x32be
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#define mmDWB_OGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_12_13 0x32bf
|
#define mmDWB_OGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmDWB_OGAM_RAMA_REGION_14_15 0x32c0
|
#define mmDWB_OGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_16_17 0x32c1
|
#define mmDWB_OGAM_RAMA_REGION_16_17_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_18_19 0x32c2
|
#define mmDWB_OGAM_RAMA_REGION_18_19_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_20_21 0x32c3
|
#define mmDWB_OGAM_RAMA_REGION_20_21_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_22_23 0x32c4
|
#define mmDWB_OGAM_RAMA_REGION_22_23_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_24_25 0x32c5
|
#define mmDWB_OGAM_RAMA_REGION_24_25_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_26_27 0x32c6
|
#define mmDWB_OGAM_RAMA_REGION_26_27_BASE_IDX 2
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#define mmDWB_OGAM_RAMA_REGION_28_29 0x32c7
|
#define mmDWB_OGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmDWB_OGAM_RAMA_REGION_30_31 0x32c8
|
#define mmDWB_OGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmDWB_OGAM_RAMA_REGION_32_33 0x32c9
|
#define mmDWB_OGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_START_CNTL_B 0x32ca
|
#define mmDWB_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_START_CNTL_G 0x32cb
|
#define mmDWB_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_START_CNTL_R 0x32cc
|
#define mmDWB_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B 0x32cd
|
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B 0x32ce
|
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G 0x32cf
|
#define mmDWB_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G 0x32d0
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#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R 0x32d1
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#define mmDWB_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R 0x32d2
|
#define mmDWB_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_END_CNTL1_B 0x32d3
|
#define mmDWB_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_END_CNTL2_B 0x32d4
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#define mmDWB_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_END_CNTL1_G 0x32d5
|
#define mmDWB_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_END_CNTL2_G 0x32d6
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#define mmDWB_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_END_CNTL1_R 0x32d7
|
#define mmDWB_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_END_CNTL2_R 0x32d8
|
#define mmDWB_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_OFFSET_B 0x32d9
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#define mmDWB_OGAM_RAMB_OFFSET_B_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_OFFSET_G 0x32da
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#define mmDWB_OGAM_RAMB_OFFSET_G_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_OFFSET_R 0x32db
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#define mmDWB_OGAM_RAMB_OFFSET_R_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_REGION_0_1 0x32dc
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#define mmDWB_OGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_REGION_2_3 0x32dd
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#define mmDWB_OGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_REGION_4_5 0x32de
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#define mmDWB_OGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_REGION_6_7 0x32df
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#define mmDWB_OGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_REGION_8_9 0x32e0
|
#define mmDWB_OGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_REGION_10_11 0x32e1
|
#define mmDWB_OGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_REGION_12_13 0x32e2
|
#define mmDWB_OGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_REGION_14_15 0x32e3
|
#define mmDWB_OGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_REGION_16_17 0x32e4
|
#define mmDWB_OGAM_RAMB_REGION_16_17_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_REGION_18_19 0x32e5
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#define mmDWB_OGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_REGION_20_21 0x32e6
|
#define mmDWB_OGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_REGION_22_23 0x32e7
|
#define mmDWB_OGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_REGION_24_25 0x32e8
|
#define mmDWB_OGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_REGION_26_27 0x32e9
|
#define mmDWB_OGAM_RAMB_REGION_26_27_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_REGION_28_29 0x32ea
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#define mmDWB_OGAM_RAMB_REGION_28_29_BASE_IDX 2
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#define mmDWB_OGAM_RAMB_REGION_30_31 0x32eb
|
#define mmDWB_OGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmDWB_OGAM_RAMB_REGION_32_33 0x32ec
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#define mmDWB_OGAM_RAMB_REGION_32_33_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc0_dispdec
|
// base address: 0x0
|
#define mmMPCC0_MPCC_TOP_SEL 0x0000
|
#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 3
|
#define mmMPCC0_MPCC_BOT_SEL 0x0001
|
#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 3
|
#define mmMPCC0_MPCC_OPP_ID 0x0002
|
#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 3
|
#define mmMPCC0_MPCC_CONTROL 0x0003
|
#define mmMPCC0_MPCC_CONTROL_BASE_IDX 3
|
#define mmMPCC0_MPCC_SM_CONTROL 0x0004
|
#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 3
|
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x0005
|
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
|
#define mmMPCC0_MPCC_TOP_GAIN 0x0006
|
#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 3
|
#define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x0007
|
#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
|
#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x0008
|
#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
|
#define mmMPCC0_MPCC_BG_R_CR 0x0009
|
#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 3
|
#define mmMPCC0_MPCC_BG_G_Y 0x000a
|
#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 3
|
#define mmMPCC0_MPCC_BG_B_CB 0x000b
|
#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 3
|
#define mmMPCC0_MPCC_MEM_PWR_CTRL 0x000c
|
#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 3
|
#define mmMPCC0_MPCC_STATUS 0x000d
|
#define mmMPCC0_MPCC_STATUS_BASE_IDX 3
|
|
|
// addressBlock: dce_dc_mpc_mpcc1_dispdec
|
// base address: 0x80
|
#define mmMPCC1_MPCC_TOP_SEL 0x0020
|
#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 3
|
#define mmMPCC1_MPCC_BOT_SEL 0x0021
|
#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 3
|
#define mmMPCC1_MPCC_OPP_ID 0x0022
|
#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 3
|
#define mmMPCC1_MPCC_CONTROL 0x0023
|
#define mmMPCC1_MPCC_CONTROL_BASE_IDX 3
|
#define mmMPCC1_MPCC_SM_CONTROL 0x0024
|
#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 3
|
#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x0025
|
#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
|
#define mmMPCC1_MPCC_TOP_GAIN 0x0026
|
#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 3
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#define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x0027
|
#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
|
#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x0028
|
#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
|
#define mmMPCC1_MPCC_BG_R_CR 0x0029
|
#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 3
|
#define mmMPCC1_MPCC_BG_G_Y 0x002a
|
#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 3
|
#define mmMPCC1_MPCC_BG_B_CB 0x002b
|
#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 3
|
#define mmMPCC1_MPCC_MEM_PWR_CTRL 0x002c
|
#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 3
|
#define mmMPCC1_MPCC_STATUS 0x002d
|
#define mmMPCC1_MPCC_STATUS_BASE_IDX 3
|
|
|
// addressBlock: dce_dc_mpc_mpcc2_dispdec
|
// base address: 0x100
|
#define mmMPCC2_MPCC_TOP_SEL 0x0040
|
#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 3
|
#define mmMPCC2_MPCC_BOT_SEL 0x0041
|
#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 3
|
#define mmMPCC2_MPCC_OPP_ID 0x0042
|
#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 3
|
#define mmMPCC2_MPCC_CONTROL 0x0043
|
#define mmMPCC2_MPCC_CONTROL_BASE_IDX 3
|
#define mmMPCC2_MPCC_SM_CONTROL 0x0044
|
#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 3
|
#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x0045
|
#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
|
#define mmMPCC2_MPCC_TOP_GAIN 0x0046
|
#define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX 3
|
#define mmMPCC2_MPCC_BOT_GAIN_INSIDE 0x0047
|
#define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
|
#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x0048
|
#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
|
#define mmMPCC2_MPCC_BG_R_CR 0x0049
|
#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 3
|
#define mmMPCC2_MPCC_BG_G_Y 0x004a
|
#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 3
|
#define mmMPCC2_MPCC_BG_B_CB 0x004b
|
#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 3
|
#define mmMPCC2_MPCC_MEM_PWR_CTRL 0x004c
|
#define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 3
|
#define mmMPCC2_MPCC_STATUS 0x004d
|
#define mmMPCC2_MPCC_STATUS_BASE_IDX 3
|
|
|
// addressBlock: dce_dc_mpc_mpcc3_dispdec
|
// base address: 0x180
|
#define mmMPCC3_MPCC_TOP_SEL 0x0060
|
#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 3
|
#define mmMPCC3_MPCC_BOT_SEL 0x0061
|
#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 3
|
#define mmMPCC3_MPCC_OPP_ID 0x0062
|
#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 3
|
#define mmMPCC3_MPCC_CONTROL 0x0063
|
#define mmMPCC3_MPCC_CONTROL_BASE_IDX 3
|
#define mmMPCC3_MPCC_SM_CONTROL 0x0064
|
#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 3
|
#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x0065
|
#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
|
#define mmMPCC3_MPCC_TOP_GAIN 0x0066
|
#define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX 3
|
#define mmMPCC3_MPCC_BOT_GAIN_INSIDE 0x0067
|
#define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
|
#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x0068
|
#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
|
#define mmMPCC3_MPCC_BG_R_CR 0x0069
|
#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 3
|
#define mmMPCC3_MPCC_BG_G_Y 0x006a
|
#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 3
|
#define mmMPCC3_MPCC_BG_B_CB 0x006b
|
#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 3
|
#define mmMPCC3_MPCC_MEM_PWR_CTRL 0x006c
|
#define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 3
|
#define mmMPCC3_MPCC_STATUS 0x006d
|
#define mmMPCC3_MPCC_STATUS_BASE_IDX 3
|
|
|
// addressBlock: dce_dc_mpc_mpcc4_dispdec
|
// base address: 0x200
|
#define mmMPCC4_MPCC_TOP_SEL 0x0080
|
#define mmMPCC4_MPCC_TOP_SEL_BASE_IDX 3
|
#define mmMPCC4_MPCC_BOT_SEL 0x0081
|
#define mmMPCC4_MPCC_BOT_SEL_BASE_IDX 3
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#define mmMPCC4_MPCC_OPP_ID 0x0082
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#define mmMPCC4_MPCC_OPP_ID_BASE_IDX 3
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#define mmMPCC4_MPCC_CONTROL 0x0083
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#define mmMPCC4_MPCC_CONTROL_BASE_IDX 3
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#define mmMPCC4_MPCC_SM_CONTROL 0x0084
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#define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX 3
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#define mmMPCC4_MPCC_UPDATE_LOCK_SEL 0x0085
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#define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
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#define mmMPCC4_MPCC_TOP_GAIN 0x0086
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#define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX 3
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#define mmMPCC4_MPCC_BOT_GAIN_INSIDE 0x0087
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#define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
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#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE 0x0088
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#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
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#define mmMPCC4_MPCC_BG_R_CR 0x0089
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#define mmMPCC4_MPCC_BG_R_CR_BASE_IDX 3
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#define mmMPCC4_MPCC_BG_G_Y 0x008a
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#define mmMPCC4_MPCC_BG_G_Y_BASE_IDX 3
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#define mmMPCC4_MPCC_BG_B_CB 0x008b
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#define mmMPCC4_MPCC_BG_B_CB_BASE_IDX 3
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#define mmMPCC4_MPCC_MEM_PWR_CTRL 0x008c
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#define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX 3
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#define mmMPCC4_MPCC_STATUS 0x008d
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#define mmMPCC4_MPCC_STATUS_BASE_IDX 3
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// addressBlock: dce_dc_mpc_mpcc5_dispdec
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// base address: 0x280
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#define mmMPCC5_MPCC_TOP_SEL 0x00a0
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#define mmMPCC5_MPCC_TOP_SEL_BASE_IDX 3
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#define mmMPCC5_MPCC_BOT_SEL 0x00a1
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#define mmMPCC5_MPCC_BOT_SEL_BASE_IDX 3
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#define mmMPCC5_MPCC_OPP_ID 0x00a2
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#define mmMPCC5_MPCC_OPP_ID_BASE_IDX 3
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#define mmMPCC5_MPCC_CONTROL 0x00a3
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#define mmMPCC5_MPCC_CONTROL_BASE_IDX 3
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#define mmMPCC5_MPCC_SM_CONTROL 0x00a4
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#define mmMPCC5_MPCC_SM_CONTROL_BASE_IDX 3
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#define mmMPCC5_MPCC_UPDATE_LOCK_SEL 0x00a5
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#define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX 3
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#define mmMPCC5_MPCC_TOP_GAIN 0x00a6
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#define mmMPCC5_MPCC_TOP_GAIN_BASE_IDX 3
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#define mmMPCC5_MPCC_BOT_GAIN_INSIDE 0x00a7
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#define mmMPCC5_MPCC_BOT_GAIN_INSIDE_BASE_IDX 3
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#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE 0x00a8
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#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 3
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#define mmMPCC5_MPCC_BG_R_CR 0x00a9
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#define mmMPCC5_MPCC_BG_R_CR_BASE_IDX 3
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#define mmMPCC5_MPCC_BG_G_Y 0x00aa
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#define mmMPCC5_MPCC_BG_G_Y_BASE_IDX 3
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#define mmMPCC5_MPCC_BG_B_CB 0x00ab
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#define mmMPCC5_MPCC_BG_B_CB_BASE_IDX 3
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#define mmMPCC5_MPCC_MEM_PWR_CTRL 0x00ac
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#define mmMPCC5_MPCC_MEM_PWR_CTRL_BASE_IDX 3
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#define mmMPCC5_MPCC_STATUS 0x00ad
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#define mmMPCC5_MPCC_STATUS_BASE_IDX 3
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// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
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// base address: 0x0
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#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL 0x0100
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#define mmMPCC_OGAM0_MPCC_OGAM_CONTROL_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x0101
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#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x0102
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#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL 0x0103
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#define mmMPCC_OGAM0_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x0104
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x0105
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x0106
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0107
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0108
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0109
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x010a
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x010b
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x010c
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x010d
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x010e
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x010f
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x0110
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x0111
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x0112
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B 0x0113
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G 0x0114
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R 0x0115
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x0116
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x0117
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x0118
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x0119
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x011a
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x011b
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x011c
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x011d
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x011e
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x011f
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x0120
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x0121
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x0122
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x0123
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x0124
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x0125
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x0126
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x0127
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x0128
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x0129
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x012a
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x012b
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x012c
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x012d
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x012e
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x012f
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x0130
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x0131
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x0132
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x0133
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x0134
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x0135
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B 0x0136
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G 0x0137
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R 0x0138
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x0139
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x013a
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x013b
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x013c
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x013d
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x013e
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x013f
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x0140
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x0141
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x0142
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x0143
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x0144
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x0145
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x0146
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x0147
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x0148
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x0149
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#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT 0x014a
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#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
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#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE 0x014b
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#define mmMPCC_OGAM0_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A 0x014c
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A 0x014d
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A 0x014e
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A 0x014f
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A 0x0150
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A 0x0151
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B 0x0152
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B 0x0153
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B 0x0154
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B 0x0155
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B 0x0156
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B 0x0157
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#define mmMPCC_OGAM0_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
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// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
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// base address: 0x200
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#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL 0x0180
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#define mmMPCC_OGAM1_MPCC_OGAM_CONTROL_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x0181
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#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x0182
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#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL 0x0183
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#define mmMPCC_OGAM1_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x0184
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x0185
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x0186
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0187
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0188
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0189
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x018a
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x018b
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x018c
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x018d
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x018e
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x018f
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x0190
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x0191
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x0192
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B 0x0193
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G 0x0194
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R 0x0195
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x0196
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x0197
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x0198
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x0199
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x019a
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x019b
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x019c
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x019d
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x019e
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x019f
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x01a0
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x01a1
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x01a2
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x01a3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x01a4
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x01a5
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x01a6
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x01a7
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x01a8
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x01a9
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x01aa
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x01ab
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x01ac
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x01ad
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x01ae
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x01af
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x01b0
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x01b1
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x01b2
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x01b3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x01b4
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x01b5
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B 0x01b6
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G 0x01b7
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R 0x01b8
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x01b9
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x01ba
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x01bb
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x01bc
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x01bd
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x01be
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x01bf
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x01c0
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x01c1
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x01c2
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x01c3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x01c4
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x01c5
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x01c6
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x01c7
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x01c8
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x01c9
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#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT 0x01ca
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#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
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#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE 0x01cb
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#define mmMPCC_OGAM1_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A 0x01cc
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A 0x01cd
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A 0x01ce
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A 0x01cf
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A 0x01d0
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A 0x01d1
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B 0x01d2
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B 0x01d3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B 0x01d4
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B 0x01d5
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B 0x01d6
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B 0x01d7
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#define mmMPCC_OGAM1_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
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// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
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// base address: 0x400
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#define mmMPCC_OGAM2_MPCC_OGAM_CONTROL 0x0200
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#define mmMPCC_OGAM2_MPCC_OGAM_CONTROL_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x0201
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#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x0202
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#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL 0x0203
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#define mmMPCC_OGAM2_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x0204
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x0205
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x0206
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0207
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0208
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0209
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x020a
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x020b
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x020c
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x020d
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x020e
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x020f
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x0210
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x0211
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x0212
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B 0x0213
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G 0x0214
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R 0x0215
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x0216
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x0217
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x0218
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x0219
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x021a
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x021b
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x021c
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x021d
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x021e
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x021f
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x0220
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x0221
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x0222
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x0223
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x0224
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x0225
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x0226
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x0227
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x0228
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x0229
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x022a
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x022b
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x022c
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x022d
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x022e
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x022f
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x0230
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x0231
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x0232
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x0233
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x0234
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x0235
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B 0x0236
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G 0x0237
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R 0x0238
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x0239
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x023a
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x023b
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x023c
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x023d
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x023e
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x023f
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x0240
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x0241
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x0242
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x0243
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x0244
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x0245
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x0246
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x0247
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x0248
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x0249
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#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT 0x024a
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#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
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#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE 0x024b
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#define mmMPCC_OGAM2_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A 0x024c
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A 0x024d
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A 0x024e
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A 0x024f
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A 0x0250
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A 0x0251
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B 0x0252
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B 0x0253
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B 0x0254
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B 0x0255
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B 0x0256
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B 0x0257
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#define mmMPCC_OGAM2_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
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// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
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// base address: 0x600
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#define mmMPCC_OGAM3_MPCC_OGAM_CONTROL 0x0280
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#define mmMPCC_OGAM3_MPCC_OGAM_CONTROL_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x0281
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#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x0282
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#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL 0x0283
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#define mmMPCC_OGAM3_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x0284
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x0285
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x0286
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0287
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0288
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0289
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x028a
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x028b
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x028c
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x028d
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x028e
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x028f
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x0290
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x0291
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x0292
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B 0x0293
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G 0x0294
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R 0x0295
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x0296
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x0297
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x0298
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x0299
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x029a
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x029b
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x029c
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x029d
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x029e
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x029f
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x02a0
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x02a1
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x02a2
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x02a3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x02a4
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x02a5
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x02a6
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x02a7
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x02a8
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x02a9
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x02aa
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x02ab
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x02ac
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x02ad
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x02ae
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x02af
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x02b0
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x02b1
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x02b2
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x02b3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x02b4
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x02b5
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B 0x02b6
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G 0x02b7
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R 0x02b8
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x02b9
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x02ba
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x02bb
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x02bc
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x02bd
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x02be
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x02bf
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x02c0
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x02c1
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x02c2
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x02c3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x02c4
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x02c5
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x02c6
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x02c7
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x02c8
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x02c9
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#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT 0x02ca
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#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
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#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE 0x02cb
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#define mmMPCC_OGAM3_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A 0x02cc
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A 0x02cd
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A 0x02ce
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A 0x02cf
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A 0x02d0
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A 0x02d1
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B 0x02d2
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B 0x02d3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B 0x02d4
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B 0x02d5
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B 0x02d6
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B 0x02d7
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#define mmMPCC_OGAM3_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
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// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec
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// base address: 0x800
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#define mmMPCC_OGAM4_MPCC_OGAM_CONTROL 0x0300
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#define mmMPCC_OGAM4_MPCC_OGAM_CONTROL_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX 0x0301
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#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA 0x0302
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#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_LUT_CONTROL 0x0303
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#define mmMPCC_OGAM4_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B 0x0304
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G 0x0305
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R 0x0306
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0307
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0308
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0309
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x030a
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x030b
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x030c
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B 0x030d
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B 0x030e
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G 0x030f
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G 0x0310
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R 0x0311
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R 0x0312
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_B 0x0313
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_G 0x0314
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_R 0x0315
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 0x0316
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 0x0317
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 0x0318
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 0x0319
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 0x031a
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 0x031b
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 0x031c
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 0x031d
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 0x031e
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 0x031f
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 0x0320
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 0x0321
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 0x0322
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 0x0323
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 0x0324
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 0x0325
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 0x0326
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B 0x0327
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G 0x0328
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R 0x0329
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x032a
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x032b
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x032c
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x032d
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x032e
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x032f
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B 0x0330
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B 0x0331
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G 0x0332
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G 0x0333
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R 0x0334
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R 0x0335
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_B 0x0336
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_G 0x0337
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_R 0x0338
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 0x0339
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 0x033a
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 0x033b
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 0x033c
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 0x033d
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 0x033e
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 0x033f
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 0x0340
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 0x0341
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 0x0342
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 0x0343
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 0x0344
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 0x0345
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 0x0346
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 0x0347
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 0x0348
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 0x0349
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#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_COEF_FORMAT 0x034a
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#define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
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#define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_MODE 0x034b
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#define mmMPCC_OGAM4_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_A 0x034c
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_A 0x034d
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_A 0x034e
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_A 0x034f
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_A 0x0350
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_A 0x0351
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_B 0x0352
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_B 0x0353
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_B 0x0354
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_B 0x0355
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_B 0x0356
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_B 0x0357
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#define mmMPCC_OGAM4_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
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// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec
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// base address: 0xa00
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#define mmMPCC_OGAM5_MPCC_OGAM_CONTROL 0x0380
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#define mmMPCC_OGAM5_MPCC_OGAM_CONTROL_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX 0x0381
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#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA 0x0382
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#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_LUT_CONTROL 0x0383
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#define mmMPCC_OGAM5_MPCC_OGAM_LUT_CONTROL_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B 0x0384
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G 0x0385
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R 0x0386
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x0387
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x0388
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x0389
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_SLOPE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_B 0x038a
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_G 0x038b
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_R 0x038c
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_BASE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B 0x038d
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B 0x038e
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G 0x038f
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G 0x0390
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R 0x0391
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R 0x0392
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_B 0x0393
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_G 0x0394
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_G_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_R 0x0395
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_OFFSET_R_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1 0x0396
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3 0x0397
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5 0x0398
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7 0x0399
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9 0x039a
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11 0x039b
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13 0x039c
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15 0x039d
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17 0x039e
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19 0x039f
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21 0x03a0
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23 0x03a1
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25 0x03a2
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27 0x03a3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29 0x03a4
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31 0x03a5
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33 0x03a6
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B 0x03a7
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G 0x03a8
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R 0x03a9
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B 0x03aa
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G 0x03ab
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R 0x03ac
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_SLOPE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_B 0x03ad
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_G 0x03ae
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_G_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_R 0x03af
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_BASE_CNTL_R_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B 0x03b0
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B 0x03b1
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G 0x03b2
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G 0x03b3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R 0x03b4
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R 0x03b5
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_B 0x03b6
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_G 0x03b7
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_G_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_R 0x03b8
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_OFFSET_R_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1 0x03b9
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3 0x03ba
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5 0x03bb
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7 0x03bc
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9 0x03bd
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11 0x03be
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13 0x03bf
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15 0x03c0
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17 0x03c1
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19 0x03c2
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21 0x03c3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23 0x03c4
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25 0x03c5
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27 0x03c6
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29 0x03c7
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31 0x03c8
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33 0x03c9
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#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_GAMUT_REMAP_COEF_FORMAT 0x03ca
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#define mmMPCC_OGAM5_MPCC_GAMUT_REMAP_COEF_FORMAT_BASE_IDX 3
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#define mmMPCC_OGAM5_MPCC_GAMUT_REMAP_MODE 0x03cb
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#define mmMPCC_OGAM5_MPCC_GAMUT_REMAP_MODE_BASE_IDX 3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C11_C12_A 0x03cc
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C11_C12_A_BASE_IDX 3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C13_C14_A 0x03cd
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C13_C14_A_BASE_IDX 3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C21_C22_A 0x03ce
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C21_C22_A_BASE_IDX 3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C23_C24_A 0x03cf
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C23_C24_A_BASE_IDX 3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C31_C32_A 0x03d0
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C31_C32_A_BASE_IDX 3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C33_C34_A 0x03d1
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C33_C34_A_BASE_IDX 3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C11_C12_B 0x03d2
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C11_C12_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C13_C14_B 0x03d3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C13_C14_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C21_C22_B 0x03d4
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C21_C22_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C23_C24_B 0x03d5
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C23_C24_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C31_C32_B 0x03d6
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C31_C32_B_BASE_IDX 3
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C33_C34_B 0x03d7
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#define mmMPCC_OGAM5_MPC_GAMUT_REMAP_C33_C34_B_BASE_IDX 3
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// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
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// base address: 0x0
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#define mmMPC_CLOCK_CONTROL 0x0500
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#define mmMPC_CLOCK_CONTROL_BASE_IDX 3
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#define mmMPC_SOFT_RESET 0x0501
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#define mmMPC_SOFT_RESET_BASE_IDX 3
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#define mmMPC_CRC_CTRL 0x0502
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#define mmMPC_CRC_CTRL_BASE_IDX 3
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#define mmMPC_CRC_SEL_CONTROL 0x0503
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#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 3
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#define mmMPC_CRC_RESULT_AR 0x0504
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#define mmMPC_CRC_RESULT_AR_BASE_IDX 3
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#define mmMPC_CRC_RESULT_GB 0x0505
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#define mmMPC_CRC_RESULT_GB_BASE_IDX 3
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#define mmMPC_CRC_RESULT_C 0x0506
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#define mmMPC_CRC_RESULT_C_BASE_IDX 3
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#define mmMPC_PERFMON_EVENT_CTRL 0x0509
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#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 3
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#define mmMPC_BYPASS_BG_AR 0x050a
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#define mmMPC_BYPASS_BG_AR_BASE_IDX 3
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#define mmMPC_BYPASS_BG_GB 0x050b
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#define mmMPC_BYPASS_BG_GB_BASE_IDX 3
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#define mmMPC_HOST_READ_CONTROL 0x050c
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#define mmMPC_HOST_READ_CONTROL_BASE_IDX 3
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#define mmMPC_DPP_PENDING_STATUS 0x050d
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#define mmMPC_DPP_PENDING_STATUS_BASE_IDX 3
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#define mmMPC_PENDING_STATUS_MISC 0x050e
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#define mmMPC_PENDING_STATUS_MISC_BASE_IDX 3
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#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x050f
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#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 3
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#define mmADR_CFG_VUPDATE_LOCK_SET0 0x0510
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#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 3
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#define mmADR_VUPDATE_LOCK_SET0 0x0511
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#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 3
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#define mmCFG_VUPDATE_LOCK_SET0 0x0512
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#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 3
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#define mmCUR_VUPDATE_LOCK_SET0 0x0513
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#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 3
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#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x0514
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#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 3
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#define mmADR_CFG_VUPDATE_LOCK_SET1 0x0515
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#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 3
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#define mmADR_VUPDATE_LOCK_SET1 0x0516
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#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 3
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#define mmCFG_VUPDATE_LOCK_SET1 0x0517
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#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 3
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#define mmCUR_VUPDATE_LOCK_SET1 0x0518
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#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 3
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#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2 0x0519
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#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 3
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#define mmADR_CFG_VUPDATE_LOCK_SET2 0x051a
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#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 3
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#define mmADR_VUPDATE_LOCK_SET2 0x051b
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#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 3
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#define mmCFG_VUPDATE_LOCK_SET2 0x051c
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#define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX 3
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#define mmCUR_VUPDATE_LOCK_SET2 0x051d
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#define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX 3
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#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3 0x051e
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#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 3
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#define mmADR_CFG_VUPDATE_LOCK_SET3 0x051f
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#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 3
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#define mmADR_VUPDATE_LOCK_SET3 0x0520
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#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 3
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#define mmCFG_VUPDATE_LOCK_SET3 0x0521
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#define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX 3
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#define mmCUR_VUPDATE_LOCK_SET3 0x0522
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#define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX 3
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#define mmADR_CFG_CUR_VUPDATE_LOCK_SET4 0x0523
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#define mmADR_CFG_CUR_VUPDATE_LOCK_SET4_BASE_IDX 3
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#define mmADR_CFG_VUPDATE_LOCK_SET4 0x0524
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#define mmADR_CFG_VUPDATE_LOCK_SET4_BASE_IDX 3
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#define mmADR_VUPDATE_LOCK_SET4 0x0525
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#define mmADR_VUPDATE_LOCK_SET4_BASE_IDX 3
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#define mmCFG_VUPDATE_LOCK_SET4 0x0526
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#define mmCFG_VUPDATE_LOCK_SET4_BASE_IDX 3
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#define mmCUR_VUPDATE_LOCK_SET4 0x0527
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#define mmCUR_VUPDATE_LOCK_SET4_BASE_IDX 3
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#define mmADR_CFG_CUR_VUPDATE_LOCK_SET5 0x0528
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#define mmADR_CFG_CUR_VUPDATE_LOCK_SET5_BASE_IDX 3
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#define mmADR_CFG_VUPDATE_LOCK_SET5 0x0529
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#define mmADR_CFG_VUPDATE_LOCK_SET5_BASE_IDX 3
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#define mmADR_VUPDATE_LOCK_SET5 0x052a
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#define mmADR_VUPDATE_LOCK_SET5_BASE_IDX 3
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#define mmCFG_VUPDATE_LOCK_SET5 0x052b
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#define mmCFG_VUPDATE_LOCK_SET5_BASE_IDX 3
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#define mmCUR_VUPDATE_LOCK_SET5 0x052c
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#define mmCUR_VUPDATE_LOCK_SET5_BASE_IDX 3
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#define mmMPC_DWB0_MUX 0x055c
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#define mmMPC_DWB0_MUX_BASE_IDX 3
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// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
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// base address: 0x0
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#define mmMPC_OUT0_MUX 0x0580
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#define mmMPC_OUT0_MUX_BASE_IDX 3
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#define mmMPC_OUT0_DENORM_CONTROL 0x0581
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#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 3
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#define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x0582
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#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 3
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#define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x0583
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#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 3
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#define mmMPC_OUT1_MUX 0x0584
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#define mmMPC_OUT1_MUX_BASE_IDX 3
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#define mmMPC_OUT1_DENORM_CONTROL 0x0585
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#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 3
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#define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x0586
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#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 3
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#define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x0587
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#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 3
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#define mmMPC_OUT2_MUX 0x0588
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#define mmMPC_OUT2_MUX_BASE_IDX 3
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#define mmMPC_OUT2_DENORM_CONTROL 0x0589
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#define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX 3
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#define mmMPC_OUT2_DENORM_CLAMP_G_Y 0x058a
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#define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 3
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#define mmMPC_OUT2_DENORM_CLAMP_B_CB 0x058b
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#define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 3
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#define mmMPC_OUT3_MUX 0x058c
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#define mmMPC_OUT3_MUX_BASE_IDX 3
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#define mmMPC_OUT3_DENORM_CONTROL 0x058d
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#define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX 3
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#define mmMPC_OUT3_DENORM_CLAMP_G_Y 0x058e
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#define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 3
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#define mmMPC_OUT3_DENORM_CLAMP_B_CB 0x058f
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#define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 3
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#define mmMPC_OUT4_MUX 0x0590
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#define mmMPC_OUT4_MUX_BASE_IDX 3
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#define mmMPC_OUT4_DENORM_CONTROL 0x0591
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#define mmMPC_OUT4_DENORM_CONTROL_BASE_IDX 3
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#define mmMPC_OUT4_DENORM_CLAMP_G_Y 0x0592
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#define mmMPC_OUT4_DENORM_CLAMP_G_Y_BASE_IDX 3
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#define mmMPC_OUT4_DENORM_CLAMP_B_CB 0x0593
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#define mmMPC_OUT4_DENORM_CLAMP_B_CB_BASE_IDX 3
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#define mmMPC_OUT5_MUX 0x0594
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#define mmMPC_OUT5_MUX_BASE_IDX 3
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#define mmMPC_OUT5_DENORM_CONTROL 0x0595
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#define mmMPC_OUT5_DENORM_CONTROL_BASE_IDX 3
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#define mmMPC_OUT5_DENORM_CLAMP_G_Y 0x0596
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#define mmMPC_OUT5_DENORM_CLAMP_G_Y_BASE_IDX 3
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#define mmMPC_OUT5_DENORM_CLAMP_B_CB 0x0597
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#define mmMPC_OUT5_DENORM_CLAMP_B_CB_BASE_IDX 3
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#define mmMPC_OUT_CSC_COEF_FORMAT 0x0598
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#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 3
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#define mmMPC_OUT0_CSC_MODE 0x0599
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#define mmMPC_OUT0_CSC_MODE_BASE_IDX 3
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#define mmMPC_OUT0_CSC_C11_C12_A 0x059a
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#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 3
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#define mmMPC_OUT0_CSC_C13_C14_A 0x059b
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#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 3
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#define mmMPC_OUT0_CSC_C21_C22_A 0x059c
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#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 3
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#define mmMPC_OUT0_CSC_C23_C24_A 0x059d
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#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 3
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#define mmMPC_OUT0_CSC_C31_C32_A 0x059e
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#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 3
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#define mmMPC_OUT0_CSC_C33_C34_A 0x059f
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#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 3
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#define mmMPC_OUT0_CSC_C11_C12_B 0x05a0
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#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 3
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#define mmMPC_OUT0_CSC_C13_C14_B 0x05a1
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#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 3
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#define mmMPC_OUT0_CSC_C21_C22_B 0x05a2
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#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 3
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#define mmMPC_OUT0_CSC_C23_C24_B 0x05a3
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#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 3
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#define mmMPC_OUT0_CSC_C31_C32_B 0x05a4
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#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 3
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#define mmMPC_OUT0_CSC_C33_C34_B 0x05a5
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#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 3
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#define mmMPC_OUT1_CSC_MODE 0x05a6
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#define mmMPC_OUT1_CSC_MODE_BASE_IDX 3
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#define mmMPC_OUT1_CSC_C11_C12_A 0x05a7
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#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 3
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#define mmMPC_OUT1_CSC_C13_C14_A 0x05a8
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#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 3
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#define mmMPC_OUT1_CSC_C21_C22_A 0x05a9
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#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 3
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#define mmMPC_OUT1_CSC_C23_C24_A 0x05aa
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#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 3
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#define mmMPC_OUT1_CSC_C31_C32_A 0x05ab
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#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 3
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#define mmMPC_OUT1_CSC_C33_C34_A 0x05ac
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#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 3
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#define mmMPC_OUT1_CSC_C11_C12_B 0x05ad
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#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 3
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#define mmMPC_OUT1_CSC_C13_C14_B 0x05ae
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#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 3
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#define mmMPC_OUT1_CSC_C21_C22_B 0x05af
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#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 3
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#define mmMPC_OUT1_CSC_C23_C24_B 0x05b0
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#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 3
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#define mmMPC_OUT1_CSC_C31_C32_B 0x05b1
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#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 3
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#define mmMPC_OUT1_CSC_C33_C34_B 0x05b2
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#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 3
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#define mmMPC_OUT2_CSC_MODE 0x05b3
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#define mmMPC_OUT2_CSC_MODE_BASE_IDX 3
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#define mmMPC_OUT2_CSC_C11_C12_A 0x05b4
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#define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX 3
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#define mmMPC_OUT2_CSC_C13_C14_A 0x05b5
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#define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX 3
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#define mmMPC_OUT2_CSC_C21_C22_A 0x05b6
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#define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX 3
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#define mmMPC_OUT2_CSC_C23_C24_A 0x05b7
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#define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX 3
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#define mmMPC_OUT2_CSC_C31_C32_A 0x05b8
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#define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX 3
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#define mmMPC_OUT2_CSC_C33_C34_A 0x05b9
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#define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX 3
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#define mmMPC_OUT2_CSC_C11_C12_B 0x05ba
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#define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX 3
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#define mmMPC_OUT2_CSC_C13_C14_B 0x05bb
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#define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX 3
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#define mmMPC_OUT2_CSC_C21_C22_B 0x05bc
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#define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX 3
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#define mmMPC_OUT2_CSC_C23_C24_B 0x05bd
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#define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX 3
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#define mmMPC_OUT2_CSC_C31_C32_B 0x05be
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#define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX 3
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#define mmMPC_OUT2_CSC_C33_C34_B 0x05bf
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#define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX 3
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#define mmMPC_OUT3_CSC_MODE 0x05c0
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#define mmMPC_OUT3_CSC_MODE_BASE_IDX 3
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#define mmMPC_OUT3_CSC_C11_C12_A 0x05c1
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#define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX 3
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#define mmMPC_OUT3_CSC_C13_C14_A 0x05c2
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#define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX 3
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#define mmMPC_OUT3_CSC_C21_C22_A 0x05c3
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#define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX 3
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#define mmMPC_OUT3_CSC_C23_C24_A 0x05c4
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#define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX 3
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#define mmMPC_OUT3_CSC_C31_C32_A 0x05c5
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#define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX 3
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#define mmMPC_OUT3_CSC_C33_C34_A 0x05c6
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#define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX 3
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#define mmMPC_OUT3_CSC_C11_C12_B 0x05c7
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#define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX 3
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#define mmMPC_OUT3_CSC_C13_C14_B 0x05c8
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#define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX 3
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#define mmMPC_OUT3_CSC_C21_C22_B 0x05c9
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#define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX 3
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#define mmMPC_OUT3_CSC_C23_C24_B 0x05ca
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#define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX 3
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#define mmMPC_OUT3_CSC_C31_C32_B 0x05cb
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#define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX 3
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#define mmMPC_OUT3_CSC_C33_C34_B 0x05cc
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#define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX 3
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#define mmMPC_OUT4_CSC_MODE 0x05cd
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#define mmMPC_OUT4_CSC_MODE_BASE_IDX 3
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#define mmMPC_OUT4_CSC_C11_C12_A 0x05ce
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#define mmMPC_OUT4_CSC_C11_C12_A_BASE_IDX 3
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#define mmMPC_OUT4_CSC_C13_C14_A 0x05cf
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#define mmMPC_OUT4_CSC_C13_C14_A_BASE_IDX 3
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#define mmMPC_OUT4_CSC_C21_C22_A 0x05d0
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#define mmMPC_OUT4_CSC_C21_C22_A_BASE_IDX 3
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#define mmMPC_OUT4_CSC_C23_C24_A 0x05d1
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#define mmMPC_OUT4_CSC_C23_C24_A_BASE_IDX 3
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#define mmMPC_OUT4_CSC_C31_C32_A 0x05d2
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#define mmMPC_OUT4_CSC_C31_C32_A_BASE_IDX 3
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#define mmMPC_OUT4_CSC_C33_C34_A 0x05d3
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#define mmMPC_OUT4_CSC_C33_C34_A_BASE_IDX 3
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#define mmMPC_OUT4_CSC_C11_C12_B 0x05d4
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#define mmMPC_OUT4_CSC_C11_C12_B_BASE_IDX 3
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#define mmMPC_OUT4_CSC_C13_C14_B 0x05d5
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#define mmMPC_OUT4_CSC_C13_C14_B_BASE_IDX 3
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#define mmMPC_OUT4_CSC_C21_C22_B 0x05d6
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#define mmMPC_OUT4_CSC_C21_C22_B_BASE_IDX 3
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#define mmMPC_OUT4_CSC_C23_C24_B 0x05d7
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#define mmMPC_OUT4_CSC_C23_C24_B_BASE_IDX 3
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#define mmMPC_OUT4_CSC_C31_C32_B 0x05d8
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#define mmMPC_OUT4_CSC_C31_C32_B_BASE_IDX 3
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#define mmMPC_OUT4_CSC_C33_C34_B 0x05d9
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#define mmMPC_OUT4_CSC_C33_C34_B_BASE_IDX 3
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#define mmMPC_OUT5_CSC_MODE 0x05da
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#define mmMPC_OUT5_CSC_MODE_BASE_IDX 3
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#define mmMPC_OUT5_CSC_C11_C12_A 0x05db
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#define mmMPC_OUT5_CSC_C11_C12_A_BASE_IDX 3
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#define mmMPC_OUT5_CSC_C13_C14_A 0x05dc
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#define mmMPC_OUT5_CSC_C13_C14_A_BASE_IDX 3
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#define mmMPC_OUT5_CSC_C21_C22_A 0x05dd
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#define mmMPC_OUT5_CSC_C21_C22_A_BASE_IDX 3
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#define mmMPC_OUT5_CSC_C23_C24_A 0x05de
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#define mmMPC_OUT5_CSC_C23_C24_A_BASE_IDX 3
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#define mmMPC_OUT5_CSC_C31_C32_A 0x05df
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#define mmMPC_OUT5_CSC_C31_C32_A_BASE_IDX 3
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#define mmMPC_OUT5_CSC_C33_C34_A 0x05e0
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#define mmMPC_OUT5_CSC_C33_C34_A_BASE_IDX 3
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#define mmMPC_OUT5_CSC_C11_C12_B 0x05e1
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#define mmMPC_OUT5_CSC_C11_C12_B_BASE_IDX 3
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#define mmMPC_OUT5_CSC_C13_C14_B 0x05e2
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#define mmMPC_OUT5_CSC_C13_C14_B_BASE_IDX 3
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#define mmMPC_OUT5_CSC_C21_C22_B 0x05e3
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#define mmMPC_OUT5_CSC_C21_C22_B_BASE_IDX 3
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#define mmMPC_OUT5_CSC_C23_C24_B 0x05e4
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#define mmMPC_OUT5_CSC_C23_C24_B_BASE_IDX 3
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#define mmMPC_OUT5_CSC_C31_C32_B 0x05e5
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#define mmMPC_OUT5_CSC_C31_C32_B_BASE_IDX 3
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#define mmMPC_OUT5_CSC_C33_C34_B 0x05e6
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#define mmMPC_OUT5_CSC_C33_C34_B_BASE_IDX 3
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// addressBlock: dce_dc_mpc_mpc_rmu_dispdec
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// base address: 0x0
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#define mmMPC_RMU_CONTROL 0x0680
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#define mmMPC_RMU_CONTROL_BASE_IDX 3
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#define mmMPC_RMU_MEM_PWR_CTRL 0x0681
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#define mmMPC_RMU_MEM_PWR_CTRL_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_CONTROL 0x0682
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#define mmMPC_RMU0_SHAPER_CONTROL_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_OFFSET_R 0x0683
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#define mmMPC_RMU0_SHAPER_OFFSET_R_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_OFFSET_G 0x0684
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#define mmMPC_RMU0_SHAPER_OFFSET_G_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_OFFSET_B 0x0685
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#define mmMPC_RMU0_SHAPER_OFFSET_B_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_SCALE_R 0x0686
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#define mmMPC_RMU0_SHAPER_SCALE_R_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_SCALE_G_B 0x0687
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#define mmMPC_RMU0_SHAPER_SCALE_G_B_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_LUT_INDEX 0x0688
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#define mmMPC_RMU0_SHAPER_LUT_INDEX_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_LUT_DATA 0x0689
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#define mmMPC_RMU0_SHAPER_LUT_DATA_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK 0x068a
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#define mmMPC_RMU0_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B 0x068b
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#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G 0x068c
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#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R 0x068d
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#define mmMPC_RMU0_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B 0x068e
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#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G 0x068f
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#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R 0x0690
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#define mmMPC_RMU0_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1 0x0691
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_0_1_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3 0x0692
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_2_3_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5 0x0693
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_4_5_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7 0x0694
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_6_7_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9 0x0695
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_8_9_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11 0x0696
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_10_11_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13 0x0697
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_12_13_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15 0x0698
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_14_15_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17 0x0699
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_16_17_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19 0x069a
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_18_19_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21 0x069b
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_20_21_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23 0x069c
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_22_23_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25 0x069d
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_24_25_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27 0x069e
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_26_27_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29 0x069f
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_28_29_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31 0x06a0
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_30_31_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33 0x06a1
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#define mmMPC_RMU0_SHAPER_RAMA_REGION_32_33_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B 0x06a2
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#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G 0x06a3
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#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R 0x06a4
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#define mmMPC_RMU0_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B 0x06a5
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#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G 0x06a6
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#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R 0x06a7
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#define mmMPC_RMU0_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1 0x06a8
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_0_1_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3 0x06a9
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_2_3_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5 0x06aa
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_4_5_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7 0x06ab
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_6_7_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9 0x06ac
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_8_9_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11 0x06ad
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_10_11_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13 0x06ae
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_12_13_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15 0x06af
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_14_15_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17 0x06b0
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_16_17_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19 0x06b1
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_18_19_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21 0x06b2
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_20_21_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23 0x06b3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_22_23_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25 0x06b4
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_24_25_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27 0x06b5
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_26_27_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29 0x06b6
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_28_29_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31 0x06b7
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_30_31_BASE_IDX 3
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33 0x06b8
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#define mmMPC_RMU0_SHAPER_RAMB_REGION_32_33_BASE_IDX 3
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#define mmMPC_RMU0_3DLUT_MODE 0x06b9
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#define mmMPC_RMU0_3DLUT_MODE_BASE_IDX 3
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#define mmMPC_RMU0_3DLUT_INDEX 0x06ba
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#define mmMPC_RMU0_3DLUT_INDEX_BASE_IDX 3
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#define mmMPC_RMU0_3DLUT_DATA 0x06bb
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#define mmMPC_RMU0_3DLUT_DATA_BASE_IDX 3
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#define mmMPC_RMU0_3DLUT_DATA_30BIT 0x06bc
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#define mmMPC_RMU0_3DLUT_DATA_30BIT_BASE_IDX 3
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#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL 0x06bd
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#define mmMPC_RMU0_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3
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#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR 0x06be
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#define mmMPC_RMU0_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3
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#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R 0x06bf
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#define mmMPC_RMU0_3DLUT_OUT_OFFSET_R_BASE_IDX 3
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#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G 0x06c0
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#define mmMPC_RMU0_3DLUT_OUT_OFFSET_G_BASE_IDX 3
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#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B 0x06c1
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#define mmMPC_RMU0_3DLUT_OUT_OFFSET_B_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_CONTROL 0x06c2
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#define mmMPC_RMU1_SHAPER_CONTROL_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_OFFSET_R 0x06c3
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#define mmMPC_RMU1_SHAPER_OFFSET_R_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_OFFSET_G 0x06c4
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#define mmMPC_RMU1_SHAPER_OFFSET_G_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_OFFSET_B 0x06c5
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#define mmMPC_RMU1_SHAPER_OFFSET_B_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_SCALE_R 0x06c6
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#define mmMPC_RMU1_SHAPER_SCALE_R_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_SCALE_G_B 0x06c7
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#define mmMPC_RMU1_SHAPER_SCALE_G_B_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_LUT_INDEX 0x06c8
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#define mmMPC_RMU1_SHAPER_LUT_INDEX_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_LUT_DATA 0x06c9
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#define mmMPC_RMU1_SHAPER_LUT_DATA_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK 0x06ca
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#define mmMPC_RMU1_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B 0x06cb
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#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G 0x06cc
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#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R 0x06cd
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#define mmMPC_RMU1_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B 0x06ce
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#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G 0x06cf
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#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R 0x06d0
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#define mmMPC_RMU1_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1 0x06d1
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_0_1_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3 0x06d2
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_2_3_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5 0x06d3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_4_5_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7 0x06d4
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_6_7_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9 0x06d5
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_8_9_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11 0x06d6
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_10_11_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13 0x06d7
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_12_13_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15 0x06d8
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_14_15_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17 0x06d9
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_16_17_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19 0x06da
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_18_19_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21 0x06db
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_20_21_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23 0x06dc
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_22_23_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25 0x06dd
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_24_25_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27 0x06de
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_26_27_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29 0x06df
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_28_29_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31 0x06e0
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_30_31_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33 0x06e1
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#define mmMPC_RMU1_SHAPER_RAMA_REGION_32_33_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B 0x06e2
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#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G 0x06e3
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#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R 0x06e4
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#define mmMPC_RMU1_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B 0x06e5
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#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G 0x06e6
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#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R 0x06e7
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#define mmMPC_RMU1_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1 0x06e8
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_0_1_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3 0x06e9
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_2_3_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5 0x06ea
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_4_5_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7 0x06eb
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_6_7_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9 0x06ec
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_8_9_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11 0x06ed
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_10_11_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13 0x06ee
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_12_13_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15 0x06ef
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_14_15_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17 0x06f0
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_16_17_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19 0x06f1
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_18_19_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21 0x06f2
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_20_21_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23 0x06f3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_22_23_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25 0x06f4
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_24_25_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27 0x06f5
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_26_27_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29 0x06f6
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_28_29_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31 0x06f7
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_30_31_BASE_IDX 3
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33 0x06f8
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#define mmMPC_RMU1_SHAPER_RAMB_REGION_32_33_BASE_IDX 3
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#define mmMPC_RMU1_3DLUT_MODE 0x06f9
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#define mmMPC_RMU1_3DLUT_MODE_BASE_IDX 3
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#define mmMPC_RMU1_3DLUT_INDEX 0x06fa
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#define mmMPC_RMU1_3DLUT_INDEX_BASE_IDX 3
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#define mmMPC_RMU1_3DLUT_DATA 0x06fb
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#define mmMPC_RMU1_3DLUT_DATA_BASE_IDX 3
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#define mmMPC_RMU1_3DLUT_DATA_30BIT 0x06fc
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#define mmMPC_RMU1_3DLUT_DATA_30BIT_BASE_IDX 3
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#define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL 0x06fd
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#define mmMPC_RMU1_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3
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#define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR 0x06fe
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#define mmMPC_RMU1_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3
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#define mmMPC_RMU1_3DLUT_OUT_OFFSET_R 0x06ff
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#define mmMPC_RMU1_3DLUT_OUT_OFFSET_R_BASE_IDX 3
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#define mmMPC_RMU1_3DLUT_OUT_OFFSET_G 0x0700
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#define mmMPC_RMU1_3DLUT_OUT_OFFSET_G_BASE_IDX 3
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#define mmMPC_RMU1_3DLUT_OUT_OFFSET_B 0x0701
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#define mmMPC_RMU1_3DLUT_OUT_OFFSET_B_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_CONTROL 0x0702
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#define mmMPC_RMU2_SHAPER_CONTROL_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_OFFSET_R 0x0703
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#define mmMPC_RMU2_SHAPER_OFFSET_R_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_OFFSET_G 0x0704
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#define mmMPC_RMU2_SHAPER_OFFSET_G_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_OFFSET_B 0x0705
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#define mmMPC_RMU2_SHAPER_OFFSET_B_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_SCALE_R 0x0706
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#define mmMPC_RMU2_SHAPER_SCALE_R_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_SCALE_G_B 0x0707
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#define mmMPC_RMU2_SHAPER_SCALE_G_B_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_LUT_INDEX 0x0708
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#define mmMPC_RMU2_SHAPER_LUT_INDEX_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_LUT_DATA 0x0709
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#define mmMPC_RMU2_SHAPER_LUT_DATA_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_LUT_WRITE_EN_MASK 0x070a
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#define mmMPC_RMU2_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_B 0x070b
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#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_B_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_G 0x070c
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#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_G_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_R 0x070d
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#define mmMPC_RMU2_SHAPER_RAMA_START_CNTL_R_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_B 0x070e
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#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_B_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_G 0x070f
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#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_G_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_R 0x0710
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#define mmMPC_RMU2_SHAPER_RAMA_END_CNTL_R_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_0_1 0x0711
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_0_1_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_2_3 0x0712
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_2_3_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_4_5 0x0713
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_4_5_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_6_7 0x0714
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_6_7_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_8_9 0x0715
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_8_9_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_10_11 0x0716
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_10_11_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_12_13 0x0717
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_12_13_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_14_15 0x0718
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_14_15_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_16_17 0x0719
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_16_17_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_18_19 0x071a
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_18_19_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_20_21 0x071b
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_20_21_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_22_23 0x071c
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_22_23_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_24_25 0x071d
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_24_25_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_26_27 0x071e
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_26_27_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_28_29 0x071f
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_28_29_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_30_31 0x0720
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_30_31_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_32_33 0x0721
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#define mmMPC_RMU2_SHAPER_RAMA_REGION_32_33_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_B 0x0722
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#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_B_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_G 0x0723
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#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_G_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_R 0x0724
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#define mmMPC_RMU2_SHAPER_RAMB_START_CNTL_R_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_B 0x0725
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#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_B_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_G 0x0726
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#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_G_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_R 0x0727
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#define mmMPC_RMU2_SHAPER_RAMB_END_CNTL_R_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_0_1 0x0728
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_0_1_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_2_3 0x0729
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_2_3_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_4_5 0x072a
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_4_5_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_6_7 0x072b
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_6_7_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_8_9 0x072c
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_8_9_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_10_11 0x072d
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_10_11_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_12_13 0x072e
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_12_13_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_14_15 0x072f
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_14_15_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_16_17 0x0730
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_16_17_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_18_19 0x0731
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_18_19_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_20_21 0x0732
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_20_21_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_22_23 0x0733
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_22_23_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_24_25 0x0734
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_24_25_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_26_27 0x0735
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_26_27_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_28_29 0x0736
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_28_29_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_30_31 0x0737
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_30_31_BASE_IDX 3
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_32_33 0x0738
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#define mmMPC_RMU2_SHAPER_RAMB_REGION_32_33_BASE_IDX 3
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#define mmMPC_RMU2_3DLUT_MODE 0x0739
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#define mmMPC_RMU2_3DLUT_MODE_BASE_IDX 3
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#define mmMPC_RMU2_3DLUT_INDEX 0x073a
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#define mmMPC_RMU2_3DLUT_INDEX_BASE_IDX 3
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#define mmMPC_RMU2_3DLUT_DATA 0x073b
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#define mmMPC_RMU2_3DLUT_DATA_BASE_IDX 3
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#define mmMPC_RMU2_3DLUT_DATA_30BIT 0x073c
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#define mmMPC_RMU2_3DLUT_DATA_30BIT_BASE_IDX 3
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#define mmMPC_RMU2_3DLUT_READ_WRITE_CONTROL 0x073d
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#define mmMPC_RMU2_3DLUT_READ_WRITE_CONTROL_BASE_IDX 3
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#define mmMPC_RMU2_3DLUT_OUT_NORM_FACTOR 0x073e
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#define mmMPC_RMU2_3DLUT_OUT_NORM_FACTOR_BASE_IDX 3
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#define mmMPC_RMU2_3DLUT_OUT_OFFSET_R 0x073f
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#define mmMPC_RMU2_3DLUT_OUT_OFFSET_R_BASE_IDX 3
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#define mmMPC_RMU2_3DLUT_OUT_OFFSET_G 0x0740
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#define mmMPC_RMU2_3DLUT_OUT_OFFSET_G_BASE_IDX 3
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#define mmMPC_RMU2_3DLUT_OUT_OFFSET_B 0x0741
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#define mmMPC_RMU2_3DLUT_OUT_OFFSET_B_BASE_IDX 3
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// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
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// base address: 0x1901c
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#define mmDC_PERFMON28_PERFCOUNTER_CNTL 0x08c7
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#define mmDC_PERFMON28_PERFCOUNTER_CNTL_BASE_IDX 3
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#define mmDC_PERFMON28_PERFCOUNTER_CNTL2 0x08c8
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#define mmDC_PERFMON28_PERFCOUNTER_CNTL2_BASE_IDX 3
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#define mmDC_PERFMON28_PERFCOUNTER_STATE 0x08c9
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#define mmDC_PERFMON28_PERFCOUNTER_STATE_BASE_IDX 3
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#define mmDC_PERFMON28_PERFMON_CNTL 0x08ca
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#define mmDC_PERFMON28_PERFMON_CNTL_BASE_IDX 3
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#define mmDC_PERFMON28_PERFMON_CNTL2 0x08cb
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#define mmDC_PERFMON28_PERFMON_CNTL2_BASE_IDX 3
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#define mmDC_PERFMON28_PERFMON_CVALUE_INT_MISC 0x08cc
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#define mmDC_PERFMON28_PERFMON_CVALUE_INT_MISC_BASE_IDX 3
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#define mmDC_PERFMON28_PERFMON_CVALUE_LOW 0x08cd
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#define mmDC_PERFMON28_PERFMON_CVALUE_LOW_BASE_IDX 3
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#define mmDC_PERFMON28_PERFMON_HI 0x08ce
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#define mmDC_PERFMON28_PERFMON_HI_BASE_IDX 3
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#define mmDC_PERFMON28_PERFMON_LOW 0x08cf
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#define mmDC_PERFMON28_PERFMON_LOW_BASE_IDX 3
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// base address: 0x2646c
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#define mmAFMT6_AFMT_VBI_PACKET_CONTROL 0x091c
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#define mmAFMT6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 3
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#define mmAFMT6_AFMT_AUDIO_PACKET_CONTROL2 0x091d
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#define mmAFMT6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 3
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#define mmAFMT6_AFMT_AUDIO_INFO0 0x091e
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#define mmAFMT6_AFMT_AUDIO_INFO0_BASE_IDX 3
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#define mmAFMT6_AFMT_AUDIO_INFO1 0x091f
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#define mmAFMT6_AFMT_AUDIO_INFO1_BASE_IDX 3
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#define mmAFMT6_AFMT_60958_0 0x0920
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#define mmAFMT6_AFMT_60958_0_BASE_IDX 3
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#define mmAFMT6_AFMT_60958_1 0x0921
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#define mmAFMT6_AFMT_60958_1_BASE_IDX 3
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#define mmAFMT6_AFMT_AUDIO_CRC_CONTROL 0x0922
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#define mmAFMT6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 3
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#define mmAFMT6_AFMT_RAMP_CONTROL0 0x0923
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#define mmAFMT6_AFMT_RAMP_CONTROL0_BASE_IDX 3
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#define mmAFMT6_AFMT_RAMP_CONTROL1 0x0924
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#define mmAFMT6_AFMT_RAMP_CONTROL1_BASE_IDX 3
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#define mmAFMT6_AFMT_RAMP_CONTROL2 0x0925
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#define mmAFMT6_AFMT_RAMP_CONTROL2_BASE_IDX 3
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#define mmAFMT6_AFMT_RAMP_CONTROL3 0x0926
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#define mmAFMT6_AFMT_RAMP_CONTROL3_BASE_IDX 3
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#define mmAFMT6_AFMT_60958_2 0x0927
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#define mmAFMT6_AFMT_60958_2_BASE_IDX 3
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#define mmAFMT6_AFMT_AUDIO_CRC_RESULT 0x0928
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#define mmAFMT6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 3
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#define mmAFMT6_AFMT_STATUS 0x0929
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#define mmAFMT6_AFMT_STATUS_BASE_IDX 3
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#define mmAFMT6_AFMT_AUDIO_PACKET_CONTROL 0x092a
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#define mmAFMT6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 3
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#define mmAFMT6_AFMT_INFOFRAME_CONTROL0 0x092b
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#define mmAFMT6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 3
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#define mmAFMT6_AFMT_INTERRUPT_STATUS 0x092c
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#define mmAFMT6_AFMT_INTERRUPT_STATUS_BASE_IDX 3
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#define mmAFMT6_AFMT_AUDIO_SRC_CONTROL 0x092d
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#define mmAFMT6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 3
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#define mmAFMT6_AFMT_MEM_PWR 0x092f
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#define mmAFMT6_AFMT_MEM_PWR_BASE_IDX 3
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// base address: 0x264c4
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#define mmVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL 0x0931
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#define mmVPG6_VPG_GENERIC_PACKET_ACCESS_CTRL_BASE_IDX 3
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#define mmVPG6_VPG_GENERIC_PACKET_DATA 0x0932
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#define mmVPG6_VPG_GENERIC_PACKET_DATA_BASE_IDX 3
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#define mmVPG6_VPG_GSP_FRAME_UPDATE_CTRL 0x0933
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#define mmVPG6_VPG_GSP_FRAME_UPDATE_CTRL_BASE_IDX 3
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#define mmVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL 0x0934
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#define mmVPG6_VPG_GSP_IMMEDIATE_UPDATE_CTRL_BASE_IDX 3
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#define mmVPG6_VPG_GENERIC_STATUS 0x0935
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#define mmVPG6_VPG_GENERIC_STATUS_BASE_IDX 3
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#define mmVPG6_VPG_MEM_PWR 0x0936
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#define mmVPG6_VPG_MEM_PWR_BASE_IDX 3
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#define mmVPG6_VPG_ISRC1_2_ACCESS_CTRL 0x0937
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#define mmVPG6_VPG_ISRC1_2_ACCESS_CTRL_BASE_IDX 3
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#define mmVPG6_VPG_ISRC1_2_DATA 0x0938
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#define mmVPG6_VPG_ISRC1_2_DATA_BASE_IDX 3
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#define mmVPG6_VPG_MPEG_INFO0 0x0939
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#define mmVPG6_VPG_MPEG_INFO0_BASE_IDX 3
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#define mmVPG6_VPG_MPEG_INFO1 0x093a
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#define mmVPG6_VPG_MPEG_INFO1_BASE_IDX 3
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// base address: 0x264f0
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#define mmDME6_DME_CONTROL 0x093c
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#define mmDME6_DME_CONTROL_BASE_IDX 3
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#define mmDME6_DME_MEMORY_CONTROL 0x093d
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#define mmDME6_DME_MEMORY_CONTROL_BASE_IDX 3
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// base address: 0x1a698
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#define mmDC_PERFMON29_PERFCOUNTER_CNTL 0x0e66
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#define mmDC_PERFMON29_PERFCOUNTER_CNTL_BASE_IDX 3
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#define mmDC_PERFMON29_PERFCOUNTER_CNTL2 0x0e67
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#define mmDC_PERFMON29_PERFCOUNTER_CNTL2_BASE_IDX 3
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#define mmDC_PERFMON29_PERFCOUNTER_STATE 0x0e68
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#define mmDC_PERFMON29_PERFCOUNTER_STATE_BASE_IDX 3
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#define mmDC_PERFMON29_PERFMON_CNTL 0x0e69
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#define mmDC_PERFMON29_PERFMON_CNTL_BASE_IDX 3
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#define mmDC_PERFMON29_PERFMON_CNTL2 0x0e6a
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#define mmDC_PERFMON29_PERFMON_CNTL2_BASE_IDX 3
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#define mmDC_PERFMON29_PERFMON_CVALUE_INT_MISC 0x0e6b
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#define mmDC_PERFMON29_PERFMON_CVALUE_INT_MISC_BASE_IDX 3
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#define mmDC_PERFMON29_PERFMON_CVALUE_LOW 0x0e6c
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#define mmDC_PERFMON29_PERFMON_CVALUE_LOW_BASE_IDX 3
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#define mmDC_PERFMON29_PERFMON_HI 0x0e6d
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#define mmDC_PERFMON29_PERFMON_HI_BASE_IDX 3
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#define mmDC_PERFMON29_PERFMON_LOW 0x0e6e
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#define mmDC_PERFMON29_PERFMON_LOW_BASE_IDX 3
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// addressBlock: dce_dc_opp_abm0_dispdec
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// base address: 0x0
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#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0e7a
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#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
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#define mmABM0_BL1_PWM_USER_LEVEL 0x0e7b
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#define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX 3
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#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL 0x0e7c
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#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
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#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x0e7d
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#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
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#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x0e7e
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#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
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#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0e7f
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#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
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#define mmABM0_BL1_PWM_ABM_CNTL 0x0e80
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#define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX 3
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#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0e81
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#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
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#define mmABM0_BL1_PWM_GRP2_REG_LOCK 0x0e82
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#define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
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#define mmABM0_DC_ABM1_CNTL 0x0e83
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#define mmABM0_DC_ABM1_CNTL_BASE_IDX 3
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#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL 0x0e84
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#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0e85
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0e86
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0e87
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0e88
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0e89
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3
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#define mmABM0_DC_ABM1_ACE_THRES_12 0x0e8a
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#define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 3
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#define mmABM0_DC_ABM1_ACE_THRES_34 0x0e8b
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#define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 3
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#define mmABM0_DC_ABM1_ACE_CNTL_MISC 0x0e8c
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#define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
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#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0e8e
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#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_MISC_CTRL 0x0e8f
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#define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
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#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA 0x0e90
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#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
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#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x0e91
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#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
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#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0e92
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#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
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#define mmABM0_DC_ABM1_LS_PIXEL_COUNT 0x0e93
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#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
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#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0e94
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#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
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#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0e95
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#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
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#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0e96
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#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_SAMPLE_RATE 0x0e97
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#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
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#define mmABM0_DC_ABM1_LS_SAMPLE_RATE 0x0e98
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#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0e99
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#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0e9a
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#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0e9b
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#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0e9c
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#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0e9d
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#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_1 0x0e9e
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#define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_2 0x0e9f
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#define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_3 0x0ea0
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#define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_4 0x0ea1
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#define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_5 0x0ea2
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#define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_6 0x0ea3
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#define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_7 0x0ea4
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#define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_8 0x0ea5
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#define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_9 0x0ea6
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#define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_10 0x0ea7
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#define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_11 0x0ea8
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#define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_12 0x0ea9
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#define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_13 0x0eaa
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#define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_14 0x0eab
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#define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_15 0x0eac
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#define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_16 0x0ead
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#define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_17 0x0eae
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#define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_18 0x0eaf
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#define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_19 0x0eb0
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#define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_20 0x0eb1
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#define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_21 0x0eb2
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#define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_22 0x0eb3
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#define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_23 0x0eb4
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#define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 3
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#define mmABM0_DC_ABM1_HG_RESULT_24 0x0eb5
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#define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 3
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#define mmABM0_DC_ABM1_BL_MASTER_LOCK 0x0eb6
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#define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
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// addressBlock: dce_dc_opp_abm1_dispdec
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// base address: 0x104
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#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0ebb
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#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
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#define mmABM1_BL1_PWM_USER_LEVEL 0x0ebc
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#define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX 3
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#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL 0x0ebd
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#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
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#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x0ebe
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#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
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#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x0ebf
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#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
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#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0ec0
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#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
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#define mmABM1_BL1_PWM_ABM_CNTL 0x0ec1
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#define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX 3
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#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0ec2
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#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
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#define mmABM1_BL1_PWM_GRP2_REG_LOCK 0x0ec3
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#define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
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#define mmABM1_DC_ABM1_CNTL 0x0ec4
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#define mmABM1_DC_ABM1_CNTL_BASE_IDX 3
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#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL 0x0ec5
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#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0ec6
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0ec7
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0ec8
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0ec9
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0eca
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3
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#define mmABM1_DC_ABM1_ACE_THRES_12 0x0ecb
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#define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 3
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#define mmABM1_DC_ABM1_ACE_THRES_34 0x0ecc
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#define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 3
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#define mmABM1_DC_ABM1_ACE_CNTL_MISC 0x0ecd
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#define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
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#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0ecf
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#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_MISC_CTRL 0x0ed0
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#define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
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#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA 0x0ed1
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#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
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#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x0ed2
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#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
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#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0ed3
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#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
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#define mmABM1_DC_ABM1_LS_PIXEL_COUNT 0x0ed4
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#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
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#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0ed5
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#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
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#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0ed6
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#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
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#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0ed7
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#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_SAMPLE_RATE 0x0ed8
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#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
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#define mmABM1_DC_ABM1_LS_SAMPLE_RATE 0x0ed9
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#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0eda
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#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0edb
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#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0edc
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#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0edd
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#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0ede
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#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_1 0x0edf
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#define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_2 0x0ee0
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#define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_3 0x0ee1
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#define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_4 0x0ee2
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#define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_5 0x0ee3
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#define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_6 0x0ee4
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#define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_7 0x0ee5
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#define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_8 0x0ee6
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#define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_9 0x0ee7
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#define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_10 0x0ee8
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#define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_11 0x0ee9
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#define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_12 0x0eea
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#define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_13 0x0eeb
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#define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_14 0x0eec
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#define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_15 0x0eed
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#define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_16 0x0eee
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#define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_17 0x0eef
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#define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_18 0x0ef0
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#define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_19 0x0ef1
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#define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_20 0x0ef2
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#define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_21 0x0ef3
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#define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_22 0x0ef4
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#define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_23 0x0ef5
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#define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 3
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#define mmABM1_DC_ABM1_HG_RESULT_24 0x0ef6
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#define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 3
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#define mmABM1_DC_ABM1_BL_MASTER_LOCK 0x0ef7
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#define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
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// addressBlock: dce_dc_opp_abm2_dispdec
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// base address: 0x208
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#define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0efc
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#define mmABM2_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
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#define mmABM2_BL1_PWM_USER_LEVEL 0x0efd
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#define mmABM2_BL1_PWM_USER_LEVEL_BASE_IDX 3
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#define mmABM2_BL1_PWM_TARGET_ABM_LEVEL 0x0efe
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#define mmABM2_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
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#define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL 0x0eff
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#define mmABM2_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
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#define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE 0x0f00
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#define mmABM2_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
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#define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f01
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#define mmABM2_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
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#define mmABM2_BL1_PWM_ABM_CNTL 0x0f02
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#define mmABM2_BL1_PWM_ABM_CNTL_BASE_IDX 3
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#define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f03
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#define mmABM2_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
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#define mmABM2_BL1_PWM_GRP2_REG_LOCK 0x0f04
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#define mmABM2_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
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#define mmABM2_DC_ABM1_CNTL 0x0f05
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#define mmABM2_DC_ABM1_CNTL_BASE_IDX 3
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#define mmABM2_DC_ABM1_IPCSC_COEFF_SEL 0x0f06
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#define mmABM2_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
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#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f07
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#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3
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#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f08
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#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3
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#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f09
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#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3
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#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f0a
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#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3
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#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f0b
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#define mmABM2_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3
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#define mmABM2_DC_ABM1_ACE_THRES_12 0x0f0c
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#define mmABM2_DC_ABM1_ACE_THRES_12_BASE_IDX 3
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#define mmABM2_DC_ABM1_ACE_THRES_34 0x0f0d
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#define mmABM2_DC_ABM1_ACE_THRES_34_BASE_IDX 3
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#define mmABM2_DC_ABM1_ACE_CNTL_MISC 0x0f0e
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#define mmABM2_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
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#define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f10
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#define mmABM2_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_MISC_CTRL 0x0f11
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#define mmABM2_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
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#define mmABM2_DC_ABM1_LS_SUM_OF_LUMA 0x0f12
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#define mmABM2_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
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#define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA 0x0f13
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#define mmABM2_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
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#define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f14
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#define mmABM2_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
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#define mmABM2_DC_ABM1_LS_PIXEL_COUNT 0x0f15
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#define mmABM2_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
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#define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f16
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#define mmABM2_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
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#define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f17
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#define mmABM2_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
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#define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f18
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#define mmABM2_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_SAMPLE_RATE 0x0f19
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#define mmABM2_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
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#define mmABM2_DC_ABM1_LS_SAMPLE_RATE 0x0f1a
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#define mmABM2_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f1b
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#define mmABM2_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f1c
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#define mmABM2_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f1d
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#define mmABM2_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f1e
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#define mmABM2_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f1f
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#define mmABM2_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_1 0x0f20
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#define mmABM2_DC_ABM1_HG_RESULT_1_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_2 0x0f21
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#define mmABM2_DC_ABM1_HG_RESULT_2_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_3 0x0f22
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#define mmABM2_DC_ABM1_HG_RESULT_3_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_4 0x0f23
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#define mmABM2_DC_ABM1_HG_RESULT_4_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_5 0x0f24
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#define mmABM2_DC_ABM1_HG_RESULT_5_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_6 0x0f25
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#define mmABM2_DC_ABM1_HG_RESULT_6_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_7 0x0f26
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#define mmABM2_DC_ABM1_HG_RESULT_7_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_8 0x0f27
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#define mmABM2_DC_ABM1_HG_RESULT_8_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_9 0x0f28
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#define mmABM2_DC_ABM1_HG_RESULT_9_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_10 0x0f29
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#define mmABM2_DC_ABM1_HG_RESULT_10_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_11 0x0f2a
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#define mmABM2_DC_ABM1_HG_RESULT_11_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_12 0x0f2b
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#define mmABM2_DC_ABM1_HG_RESULT_12_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_13 0x0f2c
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#define mmABM2_DC_ABM1_HG_RESULT_13_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_14 0x0f2d
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#define mmABM2_DC_ABM1_HG_RESULT_14_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_15 0x0f2e
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#define mmABM2_DC_ABM1_HG_RESULT_15_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_16 0x0f2f
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#define mmABM2_DC_ABM1_HG_RESULT_16_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_17 0x0f30
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#define mmABM2_DC_ABM1_HG_RESULT_17_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_18 0x0f31
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#define mmABM2_DC_ABM1_HG_RESULT_18_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_19 0x0f32
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#define mmABM2_DC_ABM1_HG_RESULT_19_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_20 0x0f33
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#define mmABM2_DC_ABM1_HG_RESULT_20_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_21 0x0f34
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#define mmABM2_DC_ABM1_HG_RESULT_21_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_22 0x0f35
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#define mmABM2_DC_ABM1_HG_RESULT_22_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_23 0x0f36
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#define mmABM2_DC_ABM1_HG_RESULT_23_BASE_IDX 3
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#define mmABM2_DC_ABM1_HG_RESULT_24 0x0f37
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#define mmABM2_DC_ABM1_HG_RESULT_24_BASE_IDX 3
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#define mmABM2_DC_ABM1_BL_MASTER_LOCK 0x0f38
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#define mmABM2_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
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// addressBlock: dce_dc_opp_abm3_dispdec
|
// base address: 0x30c
|
#define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f3d
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#define mmABM3_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
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#define mmABM3_BL1_PWM_USER_LEVEL 0x0f3e
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#define mmABM3_BL1_PWM_USER_LEVEL_BASE_IDX 3
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#define mmABM3_BL1_PWM_TARGET_ABM_LEVEL 0x0f3f
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#define mmABM3_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
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#define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL 0x0f40
|
#define mmABM3_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
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#define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE 0x0f41
|
#define mmABM3_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
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#define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f42
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#define mmABM3_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
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#define mmABM3_BL1_PWM_ABM_CNTL 0x0f43
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#define mmABM3_BL1_PWM_ABM_CNTL_BASE_IDX 3
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#define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f44
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#define mmABM3_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
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#define mmABM3_BL1_PWM_GRP2_REG_LOCK 0x0f45
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#define mmABM3_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
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#define mmABM3_DC_ABM1_CNTL 0x0f46
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#define mmABM3_DC_ABM1_CNTL_BASE_IDX 3
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#define mmABM3_DC_ABM1_IPCSC_COEFF_SEL 0x0f47
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#define mmABM3_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
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#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f48
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#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3
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#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f49
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#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3
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#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f4a
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#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3
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#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f4b
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#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3
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#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f4c
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#define mmABM3_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3
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#define mmABM3_DC_ABM1_ACE_THRES_12 0x0f4d
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#define mmABM3_DC_ABM1_ACE_THRES_12_BASE_IDX 3
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#define mmABM3_DC_ABM1_ACE_THRES_34 0x0f4e
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#define mmABM3_DC_ABM1_ACE_THRES_34_BASE_IDX 3
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#define mmABM3_DC_ABM1_ACE_CNTL_MISC 0x0f4f
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#define mmABM3_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
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#define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f51
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#define mmABM3_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_MISC_CTRL 0x0f52
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#define mmABM3_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
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#define mmABM3_DC_ABM1_LS_SUM_OF_LUMA 0x0f53
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#define mmABM3_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
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#define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA 0x0f54
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#define mmABM3_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
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#define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f55
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#define mmABM3_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
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#define mmABM3_DC_ABM1_LS_PIXEL_COUNT 0x0f56
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#define mmABM3_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
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#define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f57
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#define mmABM3_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
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#define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f58
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#define mmABM3_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
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#define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f59
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#define mmABM3_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_SAMPLE_RATE 0x0f5a
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#define mmABM3_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
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#define mmABM3_DC_ABM1_LS_SAMPLE_RATE 0x0f5b
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#define mmABM3_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f5c
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#define mmABM3_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f5d
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#define mmABM3_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f5e
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#define mmABM3_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0f5f
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#define mmABM3_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0f60
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#define mmABM3_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_1 0x0f61
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#define mmABM3_DC_ABM1_HG_RESULT_1_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_2 0x0f62
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#define mmABM3_DC_ABM1_HG_RESULT_2_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_3 0x0f63
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#define mmABM3_DC_ABM1_HG_RESULT_3_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_4 0x0f64
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#define mmABM3_DC_ABM1_HG_RESULT_4_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_5 0x0f65
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#define mmABM3_DC_ABM1_HG_RESULT_5_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_6 0x0f66
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#define mmABM3_DC_ABM1_HG_RESULT_6_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_7 0x0f67
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#define mmABM3_DC_ABM1_HG_RESULT_7_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_8 0x0f68
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#define mmABM3_DC_ABM1_HG_RESULT_8_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_9 0x0f69
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#define mmABM3_DC_ABM1_HG_RESULT_9_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_10 0x0f6a
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#define mmABM3_DC_ABM1_HG_RESULT_10_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_11 0x0f6b
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#define mmABM3_DC_ABM1_HG_RESULT_11_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_12 0x0f6c
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#define mmABM3_DC_ABM1_HG_RESULT_12_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_13 0x0f6d
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#define mmABM3_DC_ABM1_HG_RESULT_13_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_14 0x0f6e
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#define mmABM3_DC_ABM1_HG_RESULT_14_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_15 0x0f6f
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#define mmABM3_DC_ABM1_HG_RESULT_15_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_16 0x0f70
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#define mmABM3_DC_ABM1_HG_RESULT_16_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_17 0x0f71
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#define mmABM3_DC_ABM1_HG_RESULT_17_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_18 0x0f72
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#define mmABM3_DC_ABM1_HG_RESULT_18_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_19 0x0f73
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#define mmABM3_DC_ABM1_HG_RESULT_19_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_20 0x0f74
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#define mmABM3_DC_ABM1_HG_RESULT_20_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_21 0x0f75
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#define mmABM3_DC_ABM1_HG_RESULT_21_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_22 0x0f76
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#define mmABM3_DC_ABM1_HG_RESULT_22_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_23 0x0f77
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#define mmABM3_DC_ABM1_HG_RESULT_23_BASE_IDX 3
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#define mmABM3_DC_ABM1_HG_RESULT_24 0x0f78
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#define mmABM3_DC_ABM1_HG_RESULT_24_BASE_IDX 3
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#define mmABM3_DC_ABM1_BL_MASTER_LOCK 0x0f79
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#define mmABM3_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
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// addressBlock: dce_dc_opp_abm4_dispdec
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// base address: 0x410
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#define mmABM4_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0f7e
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#define mmABM4_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
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#define mmABM4_BL1_PWM_USER_LEVEL 0x0f7f
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#define mmABM4_BL1_PWM_USER_LEVEL_BASE_IDX 3
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#define mmABM4_BL1_PWM_TARGET_ABM_LEVEL 0x0f80
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#define mmABM4_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
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#define mmABM4_BL1_PWM_CURRENT_ABM_LEVEL 0x0f81
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#define mmABM4_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
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#define mmABM4_BL1_PWM_FINAL_DUTY_CYCLE 0x0f82
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#define mmABM4_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
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#define mmABM4_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0f83
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#define mmABM4_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
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#define mmABM4_BL1_PWM_ABM_CNTL 0x0f84
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#define mmABM4_BL1_PWM_ABM_CNTL_BASE_IDX 3
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#define mmABM4_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0f85
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#define mmABM4_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
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#define mmABM4_BL1_PWM_GRP2_REG_LOCK 0x0f86
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#define mmABM4_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
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#define mmABM4_DC_ABM1_CNTL 0x0f87
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#define mmABM4_DC_ABM1_CNTL_BASE_IDX 3
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#define mmABM4_DC_ABM1_IPCSC_COEFF_SEL 0x0f88
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#define mmABM4_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
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#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0f89
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#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3
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#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0f8a
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#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3
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#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0f8b
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#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3
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#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0f8c
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#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3
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#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0f8d
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#define mmABM4_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3
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#define mmABM4_DC_ABM1_ACE_THRES_12 0x0f8e
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#define mmABM4_DC_ABM1_ACE_THRES_12_BASE_IDX 3
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#define mmABM4_DC_ABM1_ACE_THRES_34 0x0f8f
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#define mmABM4_DC_ABM1_ACE_THRES_34_BASE_IDX 3
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#define mmABM4_DC_ABM1_ACE_CNTL_MISC 0x0f90
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#define mmABM4_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
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#define mmABM4_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0f92
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#define mmABM4_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_MISC_CTRL 0x0f93
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#define mmABM4_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
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#define mmABM4_DC_ABM1_LS_SUM_OF_LUMA 0x0f94
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#define mmABM4_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
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#define mmABM4_DC_ABM1_LS_MIN_MAX_LUMA 0x0f95
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#define mmABM4_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
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#define mmABM4_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0f96
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#define mmABM4_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
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#define mmABM4_DC_ABM1_LS_PIXEL_COUNT 0x0f97
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#define mmABM4_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
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#define mmABM4_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0f98
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#define mmABM4_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
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#define mmABM4_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0f99
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#define mmABM4_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
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#define mmABM4_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0f9a
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#define mmABM4_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_SAMPLE_RATE 0x0f9b
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#define mmABM4_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
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#define mmABM4_DC_ABM1_LS_SAMPLE_RATE 0x0f9c
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#define mmABM4_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0f9d
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#define mmABM4_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0f9e
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#define mmABM4_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0f9f
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#define mmABM4_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0fa0
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#define mmABM4_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0fa1
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#define mmABM4_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_1 0x0fa2
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#define mmABM4_DC_ABM1_HG_RESULT_1_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_2 0x0fa3
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#define mmABM4_DC_ABM1_HG_RESULT_2_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_3 0x0fa4
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#define mmABM4_DC_ABM1_HG_RESULT_3_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_4 0x0fa5
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#define mmABM4_DC_ABM1_HG_RESULT_4_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_5 0x0fa6
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#define mmABM4_DC_ABM1_HG_RESULT_5_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_6 0x0fa7
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#define mmABM4_DC_ABM1_HG_RESULT_6_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_7 0x0fa8
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#define mmABM4_DC_ABM1_HG_RESULT_7_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_8 0x0fa9
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#define mmABM4_DC_ABM1_HG_RESULT_8_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_9 0x0faa
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#define mmABM4_DC_ABM1_HG_RESULT_9_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_10 0x0fab
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#define mmABM4_DC_ABM1_HG_RESULT_10_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_11 0x0fac
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#define mmABM4_DC_ABM1_HG_RESULT_11_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_12 0x0fad
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#define mmABM4_DC_ABM1_HG_RESULT_12_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_13 0x0fae
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#define mmABM4_DC_ABM1_HG_RESULT_13_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_14 0x0faf
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#define mmABM4_DC_ABM1_HG_RESULT_14_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_15 0x0fb0
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#define mmABM4_DC_ABM1_HG_RESULT_15_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_16 0x0fb1
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#define mmABM4_DC_ABM1_HG_RESULT_16_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_17 0x0fb2
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#define mmABM4_DC_ABM1_HG_RESULT_17_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_18 0x0fb3
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#define mmABM4_DC_ABM1_HG_RESULT_18_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_19 0x0fb4
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#define mmABM4_DC_ABM1_HG_RESULT_19_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_20 0x0fb5
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#define mmABM4_DC_ABM1_HG_RESULT_20_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_21 0x0fb6
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#define mmABM4_DC_ABM1_HG_RESULT_21_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_22 0x0fb7
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#define mmABM4_DC_ABM1_HG_RESULT_22_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_23 0x0fb8
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#define mmABM4_DC_ABM1_HG_RESULT_23_BASE_IDX 3
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#define mmABM4_DC_ABM1_HG_RESULT_24 0x0fb9
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#define mmABM4_DC_ABM1_HG_RESULT_24_BASE_IDX 3
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#define mmABM4_DC_ABM1_BL_MASTER_LOCK 0x0fba
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#define mmABM4_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
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// addressBlock: dce_dc_opp_abm5_dispdec
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// base address: 0x514
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#define mmABM5_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x0fbf
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#define mmABM5_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 3
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#define mmABM5_BL1_PWM_USER_LEVEL 0x0fc0
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#define mmABM5_BL1_PWM_USER_LEVEL_BASE_IDX 3
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#define mmABM5_BL1_PWM_TARGET_ABM_LEVEL 0x0fc1
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#define mmABM5_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 3
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#define mmABM5_BL1_PWM_CURRENT_ABM_LEVEL 0x0fc2
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#define mmABM5_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 3
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#define mmABM5_BL1_PWM_FINAL_DUTY_CYCLE 0x0fc3
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#define mmABM5_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 3
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#define mmABM5_BL1_PWM_MINIMUM_DUTY_CYCLE 0x0fc4
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#define mmABM5_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 3
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#define mmABM5_BL1_PWM_ABM_CNTL 0x0fc5
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#define mmABM5_BL1_PWM_ABM_CNTL_BASE_IDX 3
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#define mmABM5_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x0fc6
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#define mmABM5_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 3
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#define mmABM5_BL1_PWM_GRP2_REG_LOCK 0x0fc7
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#define mmABM5_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 3
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#define mmABM5_DC_ABM1_CNTL 0x0fc8
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#define mmABM5_DC_ABM1_CNTL_BASE_IDX 3
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#define mmABM5_DC_ABM1_IPCSC_COEFF_SEL 0x0fc9
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#define mmABM5_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 3
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#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_0 0x0fca
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#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 3
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#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_1 0x0fcb
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#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 3
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#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_2 0x0fcc
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#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 3
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#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_3 0x0fcd
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#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 3
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#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_4 0x0fce
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#define mmABM5_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 3
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#define mmABM5_DC_ABM1_ACE_THRES_12 0x0fcf
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#define mmABM5_DC_ABM1_ACE_THRES_12_BASE_IDX 3
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#define mmABM5_DC_ABM1_ACE_THRES_34 0x0fd0
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#define mmABM5_DC_ABM1_ACE_THRES_34_BASE_IDX 3
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#define mmABM5_DC_ABM1_ACE_CNTL_MISC 0x0fd1
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#define mmABM5_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 3
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#define mmABM5_DC_ABM1_HGLS_REG_READ_PROGRESS 0x0fd3
|
#define mmABM5_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_MISC_CTRL 0x0fd4
|
#define mmABM5_DC_ABM1_HG_MISC_CTRL_BASE_IDX 3
|
#define mmABM5_DC_ABM1_LS_SUM_OF_LUMA 0x0fd5
|
#define mmABM5_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 3
|
#define mmABM5_DC_ABM1_LS_MIN_MAX_LUMA 0x0fd6
|
#define mmABM5_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 3
|
#define mmABM5_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x0fd7
|
#define mmABM5_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 3
|
#define mmABM5_DC_ABM1_LS_PIXEL_COUNT 0x0fd8
|
#define mmABM5_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 3
|
#define mmABM5_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x0fd9
|
#define mmABM5_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 3
|
#define mmABM5_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x0fda
|
#define mmABM5_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 3
|
#define mmABM5_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x0fdb
|
#define mmABM5_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_SAMPLE_RATE 0x0fdc
|
#define mmABM5_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 3
|
#define mmABM5_DC_ABM1_LS_SAMPLE_RATE 0x0fdd
|
#define mmABM5_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x0fde
|
#define mmABM5_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x0fdf
|
#define mmABM5_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x0fe0
|
#define mmABM5_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x0fe1
|
#define mmABM5_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x0fe2
|
#define mmABM5_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_1 0x0fe3
|
#define mmABM5_DC_ABM1_HG_RESULT_1_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_2 0x0fe4
|
#define mmABM5_DC_ABM1_HG_RESULT_2_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_3 0x0fe5
|
#define mmABM5_DC_ABM1_HG_RESULT_3_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_4 0x0fe6
|
#define mmABM5_DC_ABM1_HG_RESULT_4_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_5 0x0fe7
|
#define mmABM5_DC_ABM1_HG_RESULT_5_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_6 0x0fe8
|
#define mmABM5_DC_ABM1_HG_RESULT_6_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_7 0x0fe9
|
#define mmABM5_DC_ABM1_HG_RESULT_7_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_8 0x0fea
|
#define mmABM5_DC_ABM1_HG_RESULT_8_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_9 0x0feb
|
#define mmABM5_DC_ABM1_HG_RESULT_9_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_10 0x0fec
|
#define mmABM5_DC_ABM1_HG_RESULT_10_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_11 0x0fed
|
#define mmABM5_DC_ABM1_HG_RESULT_11_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_12 0x0fee
|
#define mmABM5_DC_ABM1_HG_RESULT_12_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_13 0x0fef
|
#define mmABM5_DC_ABM1_HG_RESULT_13_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_14 0x0ff0
|
#define mmABM5_DC_ABM1_HG_RESULT_14_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_15 0x0ff1
|
#define mmABM5_DC_ABM1_HG_RESULT_15_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_16 0x0ff2
|
#define mmABM5_DC_ABM1_HG_RESULT_16_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_17 0x0ff3
|
#define mmABM5_DC_ABM1_HG_RESULT_17_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_18 0x0ff4
|
#define mmABM5_DC_ABM1_HG_RESULT_18_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_19 0x0ff5
|
#define mmABM5_DC_ABM1_HG_RESULT_19_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_20 0x0ff6
|
#define mmABM5_DC_ABM1_HG_RESULT_20_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_21 0x0ff7
|
#define mmABM5_DC_ABM1_HG_RESULT_21_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_22 0x0ff8
|
#define mmABM5_DC_ABM1_HG_RESULT_22_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_23 0x0ff9
|
#define mmABM5_DC_ABM1_HG_RESULT_23_BASE_IDX 3
|
#define mmABM5_DC_ABM1_HG_RESULT_24 0x0ffa
|
#define mmABM5_DC_ABM1_HG_RESULT_24_BASE_IDX 3
|
#define mmABM5_DC_ABM1_BL_MASTER_LOCK 0x0ffb
|
#define mmABM5_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 3
|
|
|
// addressBlock: dce_dc_hda_azcontroller_azdec
|
// base address: 0x0
|
#define mmCORB_WRITE_POINTER 0x0000
|
#define mmCORB_WRITE_POINTER_BASE_IDX 0
|
#define mmCORB_READ_POINTER 0x0000
|
#define mmCORB_READ_POINTER_BASE_IDX 0
|
#define mmCORB_CONTROL 0x0001
|
#define mmCORB_CONTROL_BASE_IDX 0
|
#define mmCORB_STATUS 0x0001
|
#define mmCORB_STATUS_BASE_IDX 0
|
#define mmCORB_SIZE 0x0001
|
#define mmCORB_SIZE_BASE_IDX 0
|
#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
|
#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
|
#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmRIRB_WRITE_POINTER 0x0004
|
#define mmRIRB_WRITE_POINTER_BASE_IDX 0
|
#define mmRESPONSE_INTERRUPT_COUNT 0x0004
|
#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
|
#define mmRIRB_CONTROL 0x0005
|
#define mmRIRB_CONTROL_BASE_IDX 0
|
#define mmRIRB_STATUS 0x0005
|
#define mmRIRB_STATUS_BASE_IDX 0
|
#define mmRIRB_SIZE 0x0005
|
#define mmRIRB_SIZE_BASE_IDX 0
|
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
|
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
|
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
|
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
|
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
|
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
|
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
|
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
|
#define mmIMMEDIATE_COMMAND_STATUS 0x0008
|
#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
|
#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
|
#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
|
#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
|
#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_hda_azendpoint_azdec
|
// base address: 0x0
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
|
|
|
// addressBlock: dce_dc_hda_azinputendpoint_azdec
|
// base address: 0x0
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
|
|
|
|
// addressBlock: vga_vgaseqind
|
// base address: 0x0
|
#define ixSEQ00 0x0000
|
#define ixSEQ01 0x0001
|
#define ixSEQ02 0x0002
|
#define ixSEQ03 0x0003
|
#define ixSEQ04 0x0004
|
|
|
// addressBlock: vga_vgacrtind
|
// base address: 0x0
|
#define ixCRT00 0x0000
|
#define ixCRT01 0x0001
|
#define ixCRT02 0x0002
|
#define ixCRT03 0x0003
|
#define ixCRT04 0x0004
|
#define ixCRT05 0x0005
|
#define ixCRT06 0x0006
|
#define ixCRT07 0x0007
|
#define ixCRT08 0x0008
|
#define ixCRT09 0x0009
|
#define ixCRT0A 0x000a
|
#define ixCRT0B 0x000b
|
#define ixCRT0C 0x000c
|
#define ixCRT0D 0x000d
|
#define ixCRT0E 0x000e
|
#define ixCRT0F 0x000f
|
#define ixCRT10 0x0010
|
#define ixCRT11 0x0011
|
#define ixCRT12 0x0012
|
#define ixCRT13 0x0013
|
#define ixCRT14 0x0014
|
#define ixCRT15 0x0015
|
#define ixCRT16 0x0016
|
#define ixCRT17 0x0017
|
#define ixCRT18 0x0018
|
#define ixCRT1E 0x001e
|
#define ixCRT1F 0x001f
|
#define ixCRT22 0x0022
|
|
|
// addressBlock: vga_vgagrphind
|
// base address: 0x0
|
#define ixGRA00 0x0000
|
#define ixGRA01 0x0001
|
#define ixGRA02 0x0002
|
#define ixGRA03 0x0003
|
#define ixGRA04 0x0004
|
#define ixGRA05 0x0005
|
#define ixGRA06 0x0006
|
#define ixGRA07 0x0007
|
#define ixGRA08 0x0008
|
|
|
// addressBlock: vga_vgaattrind
|
// base address: 0x0
|
#define ixATTR00 0x0000
|
#define ixATTR01 0x0001
|
#define ixATTR02 0x0002
|
#define ixATTR03 0x0003
|
#define ixATTR04 0x0004
|
#define ixATTR05 0x0005
|
#define ixATTR06 0x0006
|
#define ixATTR07 0x0007
|
#define ixATTR08 0x0008
|
#define ixATTR09 0x0009
|
#define ixATTR0A 0x000a
|
#define ixATTR0B 0x000b
|
#define ixATTR0C 0x000c
|
#define ixATTR0D 0x000d
|
#define ixATTR0E 0x000e
|
#define ixATTR0F 0x000f
|
#define ixATTR10 0x0010
|
#define ixATTR11 0x0011
|
#define ixATTR12 0x0012
|
#define ixATTR13 0x0013
|
#define ixATTR14 0x0014
|
|
|
// addressBlock: azendpoint_f2codecind
|
// base address: 0x0
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
|
#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
|
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
|
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
|
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
|
#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
|
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
|
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
|
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
|
|
|
// addressBlock: azendpoint_descriptorind
|
// base address: 0x0
|
#define ixAUDIO_DESCRIPTOR0 0x0001
|
#define ixAUDIO_DESCRIPTOR1 0x0002
|
#define ixAUDIO_DESCRIPTOR2 0x0003
|
#define ixAUDIO_DESCRIPTOR3 0x0004
|
#define ixAUDIO_DESCRIPTOR4 0x0005
|
#define ixAUDIO_DESCRIPTOR5 0x0006
|
#define ixAUDIO_DESCRIPTOR6 0x0007
|
#define ixAUDIO_DESCRIPTOR7 0x0008
|
#define ixAUDIO_DESCRIPTOR8 0x0009
|
#define ixAUDIO_DESCRIPTOR9 0x000a
|
#define ixAUDIO_DESCRIPTOR10 0x000b
|
#define ixAUDIO_DESCRIPTOR11 0x000c
|
#define ixAUDIO_DESCRIPTOR12 0x000d
|
#define ixAUDIO_DESCRIPTOR13 0x000e
|
|
|
// addressBlock: azendpoint_sinkinfoind
|
// base address: 0x0
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
|
#define ixSINK_DESCRIPTION0 0x0005
|
#define ixSINK_DESCRIPTION1 0x0006
|
#define ixSINK_DESCRIPTION2 0x0007
|
#define ixSINK_DESCRIPTION3 0x0008
|
#define ixSINK_DESCRIPTION4 0x0009
|
#define ixSINK_DESCRIPTION5 0x000a
|
#define ixSINK_DESCRIPTION6 0x000b
|
#define ixSINK_DESCRIPTION7 0x000c
|
#define ixSINK_DESCRIPTION8 0x000d
|
#define ixSINK_DESCRIPTION9 0x000e
|
#define ixSINK_DESCRIPTION10 0x000f
|
#define ixSINK_DESCRIPTION11 0x0010
|
#define ixSINK_DESCRIPTION12 0x0011
|
#define ixSINK_DESCRIPTION13 0x0012
|
#define ixSINK_DESCRIPTION14 0x0013
|
#define ixSINK_DESCRIPTION15 0x0014
|
#define ixSINK_DESCRIPTION16 0x0015
|
#define ixSINK_DESCRIPTION17 0x0016
|
|
|
// addressBlock: azf0controller_azinputcrc0resultind
|
// base address: 0x0
|
#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
|
#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
|
#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
|
#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
|
#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
|
#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
|
#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
|
#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
|
|
|
// addressBlock: azf0controller_azinputcrc1resultind
|
// base address: 0x0
|
#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
|
#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
|
#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
|
#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
|
#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
|
#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
|
#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
|
#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
|
|
|
// addressBlock: azf0controller_azcrc0resultind
|
// base address: 0x0
|
#define ixAZALIA_CRC0_CHANNEL0 0x0000
|
#define ixAZALIA_CRC0_CHANNEL1 0x0001
|
#define ixAZALIA_CRC0_CHANNEL2 0x0002
|
#define ixAZALIA_CRC0_CHANNEL3 0x0003
|
#define ixAZALIA_CRC0_CHANNEL4 0x0004
|
#define ixAZALIA_CRC0_CHANNEL5 0x0005
|
#define ixAZALIA_CRC0_CHANNEL6 0x0006
|
#define ixAZALIA_CRC0_CHANNEL7 0x0007
|
|
|
// addressBlock: azf0controller_azcrc1resultind
|
// base address: 0x0
|
#define ixAZALIA_CRC1_CHANNEL0 0x0000
|
#define ixAZALIA_CRC1_CHANNEL1 0x0001
|
#define ixAZALIA_CRC1_CHANNEL2 0x0002
|
#define ixAZALIA_CRC1_CHANNEL3 0x0003
|
#define ixAZALIA_CRC1_CHANNEL4 0x0004
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#define ixAZALIA_CRC1_CHANNEL5 0x0005
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#define ixAZALIA_CRC1_CHANNEL6 0x0006
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#define ixAZALIA_CRC1_CHANNEL7 0x0007
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|
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// addressBlock: azinputendpoint_f2codecind
|
// base address: 0x0
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
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#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
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#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
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|
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// addressBlock: azroot_f2codecind
|
// base address: 0x0
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#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
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#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
|
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
|
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
|
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
|
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
|
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
|
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
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|
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// addressBlock: azf0stream0_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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|
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// addressBlock: azf0stream1_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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|
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// addressBlock: azf0stream2_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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|
|
// addressBlock: azf0stream3_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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|
// addressBlock: azf0stream4_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream5_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream6_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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|
|
// addressBlock: azf0stream7_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream8_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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|
|
// addressBlock: azf0stream9_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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|
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// addressBlock: azf0stream10_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream11_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream12_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream13_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream14_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream15_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0endpoint0_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
|
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
|
|
|
// addressBlock: azf0endpoint1_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint2_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint3_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint4_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint5_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint6_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint7_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0inputendpoint0_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint1_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint2_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint3_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint4_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint5_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint6_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint7_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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#endif
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