/*
|
* Copyright (C) 2019 Advanced Micro Devices, Inc.
|
*
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
* copy of this software and associated documentation files (the "Software"),
|
* to deal in the Software without restriction, including without limitation
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
* and/or sell copies of the Software, and to permit persons to whom the
|
* Software is furnished to do so, subject to the following conditions:
|
*
|
* The above copyright notice and this permission notice shall be included
|
* in all copies or substantial portions of the Software.
|
*
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
|
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
|
* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
*/
|
#ifndef _dcn_2_0_0_OFFSET_HEADER
|
#define _dcn_2_0_0_OFFSET_HEADER
|
|
|
|
// addressBlock: dce_dc_mmhubbub_vga_dispdec
|
// base address: 0x0
|
#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
|
#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
|
#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
|
#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
|
#define mmVGA_RENDER_CONTROL 0x0000
|
#define mmVGA_RENDER_CONTROL_BASE_IDX 1
|
#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
|
#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
|
#define mmVGA_MODE_CONTROL 0x0002
|
#define mmVGA_MODE_CONTROL_BASE_IDX 1
|
#define mmVGA_SURFACE_PITCH_SELECT 0x0003
|
#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
|
#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
|
#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
|
#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
|
#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
|
#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
|
#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
|
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
|
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
|
#define mmVGA_HDP_CONTROL 0x000a
|
#define mmVGA_HDP_CONTROL_BASE_IDX 1
|
#define mmVGA_CACHE_CONTROL 0x000b
|
#define mmVGA_CACHE_CONTROL_BASE_IDX 1
|
#define mmD1VGA_CONTROL 0x000c
|
#define mmD1VGA_CONTROL_BASE_IDX 1
|
#define mmD2VGA_CONTROL 0x000e
|
#define mmD2VGA_CONTROL_BASE_IDX 1
|
#define mmVGA_STATUS 0x0010
|
#define mmVGA_STATUS_BASE_IDX 1
|
#define mmVGA_INTERRUPT_CONTROL 0x0011
|
#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
|
#define mmVGA_STATUS_CLEAR 0x0012
|
#define mmVGA_STATUS_CLEAR_BASE_IDX 1
|
#define mmVGA_INTERRUPT_STATUS 0x0013
|
#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
|
#define mmVGA_MAIN_CONTROL 0x0014
|
#define mmVGA_MAIN_CONTROL_BASE_IDX 1
|
#define mmVGA_TEST_CONTROL 0x0015
|
#define mmVGA_TEST_CONTROL_BASE_IDX 1
|
#define mmVGA_QOS_CTRL 0x0018
|
#define mmVGA_QOS_CTRL_BASE_IDX 1
|
#define mmCRTC8_IDX 0x002d
|
#define mmCRTC8_IDX_BASE_IDX 1
|
#define mmCRTC8_DATA 0x002d
|
#define mmCRTC8_DATA_BASE_IDX 1
|
#define mmGENFC_WT 0x002e
|
#define mmGENFC_WT_BASE_IDX 1
|
#define mmGENS1 0x002e
|
#define mmGENS1_BASE_IDX 1
|
#define mmATTRDW 0x0030
|
#define mmATTRDW_BASE_IDX 1
|
#define mmATTRX 0x0030
|
#define mmATTRX_BASE_IDX 1
|
#define mmATTRDR 0x0030
|
#define mmATTRDR_BASE_IDX 1
|
#define mmGENMO_WT 0x0030
|
#define mmGENMO_WT_BASE_IDX 1
|
#define mmGENS0 0x0030
|
#define mmGENS0_BASE_IDX 1
|
#define mmGENENB 0x0030
|
#define mmGENENB_BASE_IDX 1
|
#define mmSEQ8_IDX 0x0031
|
#define mmSEQ8_IDX_BASE_IDX 1
|
#define mmSEQ8_DATA 0x0031
|
#define mmSEQ8_DATA_BASE_IDX 1
|
#define mmDAC_MASK 0x0031
|
#define mmDAC_MASK_BASE_IDX 1
|
#define mmDAC_R_INDEX 0x0031
|
#define mmDAC_R_INDEX_BASE_IDX 1
|
#define mmDAC_W_INDEX 0x0032
|
#define mmDAC_W_INDEX_BASE_IDX 1
|
#define mmDAC_DATA 0x0032
|
#define mmDAC_DATA_BASE_IDX 1
|
#define mmGENFC_RD 0x0032
|
#define mmGENFC_RD_BASE_IDX 1
|
#define mmGENMO_RD 0x0033
|
#define mmGENMO_RD_BASE_IDX 1
|
#define mmGRPH8_IDX 0x0033
|
#define mmGRPH8_IDX_BASE_IDX 1
|
#define mmGRPH8_DATA 0x0033
|
#define mmGRPH8_DATA_BASE_IDX 1
|
#define mmCRTC8_IDX_1 0x0035
|
#define mmCRTC8_IDX_1_BASE_IDX 1
|
#define mmCRTC8_DATA_1 0x0035
|
#define mmCRTC8_DATA_1_BASE_IDX 1
|
#define mmGENFC_WT_1 0x0036
|
#define mmGENFC_WT_1_BASE_IDX 1
|
#define mmGENS1_1 0x0036
|
#define mmGENS1_1_BASE_IDX 1
|
#define mmD3VGA_CONTROL 0x0038
|
#define mmD3VGA_CONTROL_BASE_IDX 1
|
#define mmD4VGA_CONTROL 0x0039
|
#define mmD4VGA_CONTROL_BASE_IDX 1
|
#define mmD5VGA_CONTROL 0x003a
|
#define mmD5VGA_CONTROL_BASE_IDX 1
|
#define mmD6VGA_CONTROL 0x003b
|
#define mmD6VGA_CONTROL_BASE_IDX 1
|
#define mmVGA_SOURCE_SELECT 0x003c
|
#define mmVGA_SOURCE_SELECT_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_dccg_dccg_dispdec
|
// base address: 0x0
|
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
|
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
|
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
|
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
|
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmDP_DTO_DBUF_EN 0x0044
|
#define mmDP_DTO_DBUF_EN_BASE_IDX 1
|
#define mmDSCCLK3_DTO_PARAM 0x0045
|
#define mmDSCCLK3_DTO_PARAM_BASE_IDX 1
|
#define mmDSCCLK4_DTO_PARAM 0x0046
|
#define mmDSCCLK4_DTO_PARAM_BASE_IDX 1
|
#define mmDSCCLK5_DTO_PARAM 0x0047
|
#define mmDSCCLK5_DTO_PARAM_BASE_IDX 1
|
#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
|
#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmREFCLK_CNTL 0x0049
|
#define mmREFCLK_CNTL_BASE_IDX 1
|
#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
|
#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
|
#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmDCCG_PERFMON_CNTL2 0x004e
|
#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
|
#define mmDCCG_DS_DTO_INCR 0x0053
|
#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
|
#define mmDCCG_DS_DTO_MODULO 0x0054
|
#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
|
#define mmDCCG_DS_CNTL 0x0055
|
#define mmDCCG_DS_CNTL_BASE_IDX 1
|
#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
|
#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
|
#define mmDPREFCLK_CNTL 0x0058
|
#define mmDPREFCLK_CNTL_BASE_IDX 1
|
#define mmDCE_VERSION 0x005e
|
#define mmDCE_VERSION_BASE_IDX 1
|
#define mmDCCG_GTC_CNTL 0x0060
|
#define mmDCCG_GTC_CNTL_BASE_IDX 1
|
#define mmDCCG_GTC_DTO_INCR 0x0061
|
#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
|
#define mmDCCG_GTC_DTO_MODULO 0x0062
|
#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
|
#define mmDCCG_GTC_CURRENT 0x0063
|
#define mmDCCG_GTC_CURRENT_BASE_IDX 1
|
#define mmDSCCLK0_DTO_PARAM 0x006c
|
#define mmDSCCLK0_DTO_PARAM_BASE_IDX 1
|
#define mmDSCCLK1_DTO_PARAM 0x006d
|
#define mmDSCCLK1_DTO_PARAM_BASE_IDX 1
|
#define mmDSCCLK2_DTO_PARAM 0x006e
|
#define mmDSCCLK2_DTO_PARAM_BASE_IDX 1
|
#define mmMILLISECOND_TIME_BASE_DIV 0x0070
|
#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
|
#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
|
#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
|
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
|
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
|
#define mmDCCG_PERFMON_CNTL 0x0073
|
#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
|
#define mmDCCG_GATE_DISABLE_CNTL 0x0074
|
#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
|
#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
|
#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076
|
#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmDCCG_CAC_STATUS 0x0077
|
#define mmDCCG_CAC_STATUS_BASE_IDX 1
|
#define mmMICROSECOND_TIME_BASE_DIV 0x007b
|
#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
|
#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
|
#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
|
#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
|
#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
|
#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmDCCG_DISP_CNTL_REG 0x007f
|
#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
|
#define mmOTG0_PIXEL_RATE_CNTL 0x0080
|
#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO0_PHASE 0x0081
|
#define mmDP_DTO0_PHASE_BASE_IDX 1
|
#define mmDP_DTO0_MODULO 0x0082
|
#define mmDP_DTO0_MODULO_BASE_IDX 1
|
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083
|
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmOTG1_PIXEL_RATE_CNTL 0x0084
|
#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO1_PHASE 0x0085
|
#define mmDP_DTO1_PHASE_BASE_IDX 1
|
#define mmDP_DTO1_MODULO 0x0086
|
#define mmDP_DTO1_MODULO_BASE_IDX 1
|
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087
|
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmOTG2_PIXEL_RATE_CNTL 0x0088
|
#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO2_PHASE 0x0089
|
#define mmDP_DTO2_PHASE_BASE_IDX 1
|
#define mmDP_DTO2_MODULO 0x008a
|
#define mmDP_DTO2_MODULO_BASE_IDX 1
|
#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b
|
#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmOTG3_PIXEL_RATE_CNTL 0x008c
|
#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO3_PHASE 0x008d
|
#define mmDP_DTO3_PHASE_BASE_IDX 1
|
#define mmDP_DTO3_MODULO 0x008e
|
#define mmDP_DTO3_MODULO_BASE_IDX 1
|
#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f
|
#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmOTG4_PIXEL_RATE_CNTL 0x0090
|
#define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO4_PHASE 0x0091
|
#define mmDP_DTO4_PHASE_BASE_IDX 1
|
#define mmDP_DTO4_MODULO 0x0092
|
#define mmDP_DTO4_MODULO_BASE_IDX 1
|
#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093
|
#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmOTG5_PIXEL_RATE_CNTL 0x0094
|
#define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO5_PHASE 0x0095
|
#define mmDP_DTO5_PHASE_BASE_IDX 1
|
#define mmDP_DTO5_MODULO 0x0096
|
#define mmDP_DTO5_MODULO_BASE_IDX 1
|
#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097
|
#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098
|
#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmDPPCLK0_DTO_PARAM 0x0099
|
#define mmDPPCLK0_DTO_PARAM_BASE_IDX 1
|
#define mmDPPCLK1_DTO_PARAM 0x009a
|
#define mmDPPCLK1_DTO_PARAM_BASE_IDX 1
|
#define mmDPPCLK2_DTO_PARAM 0x009b
|
#define mmDPPCLK2_DTO_PARAM_BASE_IDX 1
|
#define mmDPPCLK3_DTO_PARAM 0x009c
|
#define mmDPPCLK3_DTO_PARAM_BASE_IDX 1
|
#define mmDPPCLK4_DTO_PARAM 0x009d
|
#define mmDPPCLK4_DTO_PARAM_BASE_IDX 1
|
#define mmDPPCLK5_DTO_PARAM 0x009e
|
#define mmDPPCLK5_DTO_PARAM_BASE_IDX 1
|
#define mmDCCG_CAC_STATUS2 0x009f
|
#define mmDCCG_CAC_STATUS2_BASE_IDX 1
|
#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
|
#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
|
#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
|
#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
|
#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKE_CLOCK_ENABLE 0x00a4
|
#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKF_CLOCK_ENABLE 0x00a5
|
#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
|
#define mmDCCG_SOFT_RESET 0x00a6
|
#define mmDCCG_SOFT_RESET_BASE_IDX 1
|
#define mmDSCCLK_DTO_CTRL 0x00a7
|
#define mmDSCCLK_DTO_CTRL_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
|
#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
|
#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
|
#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
|
#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
|
#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
|
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0
|
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1
|
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1
|
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1
|
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2
|
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1
|
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3
|
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1
|
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4
|
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1
|
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5
|
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1
|
#define mmDPPCLK_DTO_CTRL 0x00b6
|
#define mmDPPCLK_DTO_CTRL_BASE_IDX 1
|
#define mmDCCG_VSYNC_CNT_CTRL 0x00b8
|
#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1
|
#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9
|
#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1
|
#define mmFORCE_SYMCLK_DISABLE 0x00ba
|
#define mmFORCE_SYMCLK_DISABLE_BASE_IDX 1
|
#define mmDCCG_TEST_CLK_SEL 0x00be
|
#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
|
// base address: 0x0
|
#define mmDENTIST_DISPCLK_CNTL 0x0064
|
#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
|
// base address: 0x0
|
#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000
|
#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001
|
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002
|
#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFMON_CNTL 0x0003
|
#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004
|
#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005
|
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006
|
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFMON_HI 0x0007
|
#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFMON_LOW 0x0008
|
#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
|
// base address: 0x30
|
#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c
|
#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d
|
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e
|
#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFMON_CNTL 0x000f
|
#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010
|
#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011
|
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012
|
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFMON_HI 0x0013
|
#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFMON_LOW 0x0014
|
#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dccg_dccg_pll_dispdec
|
// base address: 0x0
|
#define mmPLL_MACRO_CNTL_RESERVED0 0x0018
|
#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED1 0x0019
|
#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED2 0x001a
|
#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED3 0x001b
|
#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED4 0x001c
|
#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED5 0x001d
|
#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED6 0x001e
|
#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED7 0x001f
|
#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED8 0x0020
|
#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED9 0x0021
|
#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED10 0x0022
|
#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED11 0x0023
|
#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED12 0x0024
|
#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED13 0x0025
|
#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED14 0x0026
|
#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED15 0x0027
|
#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED16 0x0028
|
#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED17 0x0029
|
#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED18 0x002a
|
#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED19 0x002b
|
#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED20 0x002c
|
#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED21 0x002d
|
#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED22 0x002e
|
#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED23 0x002f
|
#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED24 0x0030
|
#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED25 0x0031
|
#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED26 0x0032
|
#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED27 0x0033
|
#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED28 0x0034
|
#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED29 0x0035
|
#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED30 0x0036
|
#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED31 0x0037
|
#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED32 0x0038
|
#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED33 0x0039
|
#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED34 0x003a
|
#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED35 0x003b
|
#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED36 0x003c
|
#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED37 0x003d
|
#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED38 0x003e
|
#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED39 0x003f
|
#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED40 0x0040
|
#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2
|
#define mmPLL_MACRO_CNTL_RESERVED41 0x0041
|
#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dmu_rbbmif_dispdec
|
// base address: 0x0
|
#define mmRBBMIF_TIMEOUT 0x005b
|
#define mmRBBMIF_TIMEOUT_BASE_IDX 2
|
#define mmRBBMIF_STATUS 0x005c
|
#define mmRBBMIF_STATUS_BASE_IDX 2
|
#define mmRBBMIF_STATUS_2 0x005d
|
#define mmRBBMIF_STATUS_2_BASE_IDX 2
|
#define mmRBBMIF_INT_STATUS 0x005e
|
#define mmRBBMIF_INT_STATUS_BASE_IDX 2
|
#define mmRBBMIF_TIMEOUT_DIS 0x005f
|
#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
|
#define mmRBBMIF_TIMEOUT_DIS_2 0x0060
|
#define mmRBBMIF_TIMEOUT_DIS_2_BASE_IDX 2
|
#define mmRBBMIF_STATUS_FLAG 0x0061
|
#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dmu_dc_pg_dispdec
|
// base address: 0x0
|
#define mmDOMAIN0_PG_CONFIG 0x0080
|
#define mmDOMAIN0_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN0_PG_STATUS 0x0081
|
#define mmDOMAIN0_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN1_PG_CONFIG 0x0082
|
#define mmDOMAIN1_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN1_PG_STATUS 0x0083
|
#define mmDOMAIN1_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN2_PG_CONFIG 0x0084
|
#define mmDOMAIN2_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN2_PG_STATUS 0x0085
|
#define mmDOMAIN2_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN3_PG_CONFIG 0x0086
|
#define mmDOMAIN3_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN3_PG_STATUS 0x0087
|
#define mmDOMAIN3_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN4_PG_CONFIG 0x0088
|
#define mmDOMAIN4_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN4_PG_STATUS 0x0089
|
#define mmDOMAIN4_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN5_PG_CONFIG 0x008a
|
#define mmDOMAIN5_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN5_PG_STATUS 0x008b
|
#define mmDOMAIN5_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN6_PG_CONFIG 0x008c
|
#define mmDOMAIN6_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN6_PG_STATUS 0x008d
|
#define mmDOMAIN6_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN7_PG_CONFIG 0x008e
|
#define mmDOMAIN7_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN7_PG_STATUS 0x008f
|
#define mmDOMAIN7_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN8_PG_CONFIG 0x0090
|
#define mmDOMAIN8_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN8_PG_STATUS 0x0091
|
#define mmDOMAIN8_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN9_PG_CONFIG 0x0092
|
#define mmDOMAIN9_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN9_PG_STATUS 0x0093
|
#define mmDOMAIN9_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN10_PG_CONFIG 0x0094
|
#define mmDOMAIN10_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN10_PG_STATUS 0x0095
|
#define mmDOMAIN10_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN11_PG_CONFIG 0x0096
|
#define mmDOMAIN11_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN11_PG_STATUS 0x0097
|
#define mmDOMAIN11_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN16_PG_CONFIG 0x00a1
|
#define mmDOMAIN16_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN16_PG_STATUS 0x00a2
|
#define mmDOMAIN16_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN17_PG_CONFIG 0x00a3
|
#define mmDOMAIN17_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN17_PG_STATUS 0x00a4
|
#define mmDOMAIN17_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN18_PG_CONFIG 0x00a5
|
#define mmDOMAIN18_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN18_PG_STATUS 0x00a6
|
#define mmDOMAIN18_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN19_PG_CONFIG 0x00a7
|
#define mmDOMAIN19_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN19_PG_STATUS 0x00a8
|
#define mmDOMAIN19_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN20_PG_CONFIG 0x00a9
|
#define mmDOMAIN20_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN20_PG_STATUS 0x00aa
|
#define mmDOMAIN20_PG_STATUS_BASE_IDX 2
|
#define mmDOMAIN21_PG_CONFIG 0x00ab
|
#define mmDOMAIN21_PG_CONFIG_BASE_IDX 2
|
#define mmDOMAIN21_PG_STATUS 0x00ac
|
#define mmDOMAIN21_PG_STATUS_BASE_IDX 2
|
#define mmDCPG_INTERRUPT_STATUS 0x00ad
|
#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDCPG_INTERRUPT_STATUS_2 0x00ae
|
#define mmDCPG_INTERRUPT_STATUS_2_BASE_IDX 2
|
#define mmDCPG_INTERRUPT_CONTROL_1 0x00af
|
#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2
|
#define mmDCPG_INTERRUPT_CONTROL_2 0x00b0
|
#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2
|
#define mmDCPG_INTERRUPT_CONTROL_3 0x00b1
|
#define mmDCPG_INTERRUPT_CONTROL_3_BASE_IDX 2
|
#define mmDC_IP_REQUEST_CNTL 0x00b2
|
#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x2f8
|
#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be
|
#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf
|
#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0
|
#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON2_PERFMON_CNTL 0x00c1
|
#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2
|
#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3
|
#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4
|
#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON2_PERFMON_HI 0x00c5
|
#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON2_PERFMON_LOW 0x00c6
|
#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dmu_dmu_misc_dispdec
|
// base address: 0x0
|
#define mmCC_DC_PIPE_DIS 0x00ca
|
#define mmCC_DC_PIPE_DIS_BASE_IDX 2
|
#define mmDMU_CLK_CNTL 0x00cb
|
#define mmDMU_CLK_CNTL_BASE_IDX 2
|
#define mmDMU_MEM_PWR_CNTL 0x00cc
|
#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2
|
#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd
|
#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmSMU_INTERRUPT_CONTROL 0x00ce
|
#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDMU_MISC_ALLOW_DS_FORCE 0x00d6
|
#define mmDMU_MISC_ALLOW_DS_FORCE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dmu_dmcu_dispdec
|
// base address: 0x0
|
#define mmDMCU_CTRL 0x00da
|
#define mmDMCU_CTRL_BASE_IDX 2
|
#define mmDMCU_STATUS 0x00db
|
#define mmDMCU_STATUS_BASE_IDX 2
|
#define mmDMCU_PC_START_ADDR 0x00dc
|
#define mmDMCU_PC_START_ADDR_BASE_IDX 2
|
#define mmDMCU_FW_START_ADDR 0x00dd
|
#define mmDMCU_FW_START_ADDR_BASE_IDX 2
|
#define mmDMCU_FW_END_ADDR 0x00de
|
#define mmDMCU_FW_END_ADDR_BASE_IDX 2
|
#define mmDMCU_FW_ISR_START_ADDR 0x00df
|
#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
|
#define mmDMCU_FW_CS_HI 0x00e0
|
#define mmDMCU_FW_CS_HI_BASE_IDX 2
|
#define mmDMCU_FW_CS_LO 0x00e1
|
#define mmDMCU_FW_CS_LO_BASE_IDX 2
|
#define mmDMCU_RAM_ACCESS_CTRL 0x00e2
|
#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
|
#define mmDMCU_ERAM_WR_CTRL 0x00e3
|
#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
|
#define mmDMCU_ERAM_WR_DATA 0x00e4
|
#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
|
#define mmDMCU_ERAM_RD_CTRL 0x00e5
|
#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
|
#define mmDMCU_ERAM_RD_DATA 0x00e6
|
#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
|
#define mmDMCU_IRAM_WR_CTRL 0x00e7
|
#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
|
#define mmDMCU_IRAM_WR_DATA 0x00e8
|
#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
|
#define mmDMCU_IRAM_RD_CTRL 0x00e9
|
#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
|
#define mmDMCU_IRAM_RD_DATA 0x00ea
|
#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
|
#define mmDMCU_EVENT_TRIGGER 0x00eb
|
#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
|
#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec
|
#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
|
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed
|
#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_STATUS 0x00ee
|
#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_STATUS_1 0x00ef
|
#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0
|
#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
|
#define mmDC_DMCU_SCRATCH 0x00f5
|
#define mmDC_DMCU_SCRATCH_BASE_IDX 2
|
#define mmDMCU_INT_CNT 0x00f6
|
#define mmDMCU_INT_CNT_BASE_IDX 2
|
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7
|
#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
|
#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8
|
#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
|
#define mmMASTER_COMM_DATA_REG1 0x00f9
|
#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
|
#define mmMASTER_COMM_DATA_REG2 0x00fa
|
#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
|
#define mmMASTER_COMM_DATA_REG3 0x00fb
|
#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
|
#define mmMASTER_COMM_CMD_REG 0x00fc
|
#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
|
#define mmMASTER_COMM_CNTL_REG 0x00fd
|
#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
|
#define mmSLAVE_COMM_DATA_REG1 0x00fe
|
#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
|
#define mmSLAVE_COMM_DATA_REG2 0x00ff
|
#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
|
#define mmSLAVE_COMM_DATA_REG3 0x0100
|
#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
|
#define mmSLAVE_COMM_CMD_REG 0x0101
|
#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
|
#define mmSLAVE_COMM_CNTL_REG 0x0102
|
#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109
|
#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
|
#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114
|
#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
|
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115
|
#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
|
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116
|
#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119
|
#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2
|
#define mmDMCU_INT_CNT_CONTINUE 0x011c
|
#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2 0x011d
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONT2_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_STATUS_2 0x011e
|
#define mmDMCU_INTERRUPT_STATUS_2_BASE_IDX 2
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2 0x011f
|
#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dmu_ihc_dispdec
|
// base address: 0x0
|
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126
|
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127
|
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2
|
#define mmDC_GPU_TIMER_READ 0x0128
|
#define mmDC_GPU_TIMER_READ_BASE_IDX 2
|
#define mmDC_GPU_TIMER_READ_CNTL 0x0129
|
#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS 0x012a
|
#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141
|
#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142
|
#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143
|
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144
|
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE23 0x0145
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE23_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE24 0x0146
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE24_BASE_IDX 2
|
#define mmDCCG_INTERRUPT_DEST 0x0147
|
#define mmDCCG_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDMU_INTERRUPT_DEST 0x0148
|
#define mmDMU_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDCPG_INTERRUPT_DEST 0x0149
|
#define mmDCPG_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDCPG_INTERRUPT_DEST2 0x014a
|
#define mmDCPG_INTERRUPT_DEST2_BASE_IDX 2
|
#define mmMMHUBBUB_INTERRUPT_DEST 0x014b
|
#define mmMMHUBBUB_INTERRUPT_DEST_BASE_IDX 2
|
#define mmWB_INTERRUPT_DEST 0x014c
|
#define mmWB_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDCHUB_INTERRUPT_DEST 0x014d
|
#define mmDCHUB_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST 0x014e
|
#define mmDCHUB_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDCHUB_INTERRUPT_DEST2 0x014f
|
#define mmDCHUB_INTERRUPT_DEST2_BASE_IDX 2
|
#define mmDPP_PERFCOUNTER_INTERRUPT_DEST 0x0150
|
#define mmDPP_PERFCOUNTER_INTERRUPT_DEST_BASE_IDX 2
|
#define mmMPC_INTERRUPT_DEST 0x0151
|
#define mmMPC_INTERRUPT_DEST_BASE_IDX 2
|
#define mmOPP_INTERRUPT_DEST 0x0152
|
#define mmOPP_INTERRUPT_DEST_BASE_IDX 2
|
#define mmOPTC_INTERRUPT_DEST 0x0153
|
#define mmOPTC_INTERRUPT_DEST_BASE_IDX 2
|
#define mmOTG0_INTERRUPT_DEST 0x0154
|
#define mmOTG0_INTERRUPT_DEST_BASE_IDX 2
|
#define mmOTG1_INTERRUPT_DEST 0x0155
|
#define mmOTG1_INTERRUPT_DEST_BASE_IDX 2
|
#define mmOTG2_INTERRUPT_DEST 0x0156
|
#define mmOTG2_INTERRUPT_DEST_BASE_IDX 2
|
#define mmOTG3_INTERRUPT_DEST 0x0157
|
#define mmOTG3_INTERRUPT_DEST_BASE_IDX 2
|
#define mmOTG4_INTERRUPT_DEST 0x0158
|
#define mmOTG4_INTERRUPT_DEST_BASE_IDX 2
|
#define mmOTG5_INTERRUPT_DEST 0x0159
|
#define mmOTG5_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDIG_INTERRUPT_DEST 0x015a
|
#define mmDIG_INTERRUPT_DEST_BASE_IDX 2
|
#define mmI2C_DDC_HPD_INTERRUPT_DEST 0x015b
|
#define mmI2C_DDC_HPD_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDIO_INTERRUPT_DEST 0x015d
|
#define mmDIO_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDCIO_INTERRUPT_DEST 0x015e
|
#define mmDCIO_INTERRUPT_DEST_BASE_IDX 2
|
#define mmHPD_INTERRUPT_DEST 0x015f
|
#define mmHPD_INTERRUPT_DEST_BASE_IDX 2
|
#define mmAZ_INTERRUPT_DEST 0x0160
|
#define mmAZ_INTERRUPT_DEST_BASE_IDX 2
|
#define mmAUX_INTERRUPT_DEST 0x0161
|
#define mmAUX_INTERRUPT_DEST_BASE_IDX 2
|
#define mmDSC_INTERRUPT_DEST 0x0162
|
#define mmDSC_INTERRUPT_DEST_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec
|
// base address: 0x0
|
#define mmWB_ENABLE 0x01da
|
#define mmWB_ENABLE_BASE_IDX 2
|
#define mmWB_EC_CONFIG 0x01db
|
#define mmWB_EC_CONFIG_BASE_IDX 2
|
#define mmCNV_MODE 0x01dc
|
#define mmCNV_MODE_BASE_IDX 2
|
#define mmCNV_WINDOW_START 0x01dd
|
#define mmCNV_WINDOW_START_BASE_IDX 2
|
#define mmCNV_WINDOW_SIZE 0x01de
|
#define mmCNV_WINDOW_SIZE_BASE_IDX 2
|
#define mmCNV_UPDATE 0x01df
|
#define mmCNV_UPDATE_BASE_IDX 2
|
#define mmCNV_SOURCE_SIZE 0x01e0
|
#define mmCNV_SOURCE_SIZE_BASE_IDX 2
|
#define mmCNV_TEST_CNTL 0x01ee
|
#define mmCNV_TEST_CNTL_BASE_IDX 2
|
#define mmCNV_TEST_CRC_RED 0x01ef
|
#define mmCNV_TEST_CRC_RED_BASE_IDX 2
|
#define mmCNV_TEST_CRC_GREEN 0x01f0
|
#define mmCNV_TEST_CRC_GREEN_BASE_IDX 2
|
#define mmCNV_TEST_CRC_BLUE 0x01f1
|
#define mmCNV_TEST_CRC_BLUE_BASE_IDX 2
|
#define mmWB_DEBUG_CTRL 0x01f2
|
#define mmWB_DEBUG_CTRL_BASE_IDX 2
|
#define mmWB_DBG_MODE 0x01f3
|
#define mmWB_DBG_MODE_BASE_IDX 2
|
#define mmWB_HW_DEBUG 0x01f4
|
#define mmWB_HW_DEBUG_BASE_IDX 2
|
#define mmWB_SOFT_RESET 0x01f5
|
#define mmWB_SOFT_RESET_BASE_IDX 2
|
#define mmWB_WARM_UP_MODE_CTL1 0x01f6
|
#define mmWB_WARM_UP_MODE_CTL1_BASE_IDX 2
|
#define mmWB_WARM_UP_MODE_CTL2 0x01f7
|
#define mmWB_WARM_UP_MODE_CTL2_BASE_IDX 2
|
#define mmCNV_TEST_DEBUG_INDEX 0x01f8
|
#define mmCNV_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmCNV_TEST_DEBUG_DATA 0x01f9
|
#define mmCNV_TEST_DEBUG_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec
|
// base address: 0x0
|
#define mmWBSCL_COEF_RAM_SELECT 0x020a
|
#define mmWBSCL_COEF_RAM_SELECT_BASE_IDX 2
|
#define mmWBSCL_COEF_RAM_TAP_DATA 0x020b
|
#define mmWBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmWBSCL_MODE 0x020c
|
#define mmWBSCL_MODE_BASE_IDX 2
|
#define mmWBSCL_TAP_CONTROL 0x020d
|
#define mmWBSCL_TAP_CONTROL_BASE_IDX 2
|
#define mmWBSCL_DEST_SIZE 0x020e
|
#define mmWBSCL_DEST_SIZE_BASE_IDX 2
|
#define mmWBSCL_HORZ_FILTER_SCALE_RATIO 0x020f
|
#define mmWBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB 0x0210
|
#define mmWBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
|
#define mmWBSCL_HORZ_FILTER_INIT_CBCR 0x0211
|
#define mmWBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
|
#define mmWBSCL_VERT_FILTER_SCALE_RATIO 0x0212
|
#define mmWBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmWBSCL_VERT_FILTER_INIT_Y_RGB 0x0213
|
#define mmWBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
|
#define mmWBSCL_VERT_FILTER_INIT_CBCR 0x0214
|
#define mmWBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
|
#define mmWBSCL_ROUND_OFFSET 0x0215
|
#define mmWBSCL_ROUND_OFFSET_BASE_IDX 2
|
#define mmWBSCL_OVERFLOW_STATUS 0x0216
|
#define mmWBSCL_OVERFLOW_STATUS_BASE_IDX 2
|
#define mmWBSCL_COEF_RAM_CONFLICT_STATUS 0x0217
|
#define mmWBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
|
#define mmWBSCL_TEST_CNTL 0x0218
|
#define mmWBSCL_TEST_CNTL_BASE_IDX 2
|
#define mmWBSCL_TEST_CRC_RED 0x0219
|
#define mmWBSCL_TEST_CRC_RED_BASE_IDX 2
|
#define mmWBSCL_TEST_CRC_GREEN 0x021a
|
#define mmWBSCL_TEST_CRC_GREEN_BASE_IDX 2
|
#define mmWBSCL_TEST_CRC_BLUE 0x021b
|
#define mmWBSCL_TEST_CRC_BLUE_BASE_IDX 2
|
#define mmWBSCL_BACKPRESSURE_CNT_EN 0x021c
|
#define mmWBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
|
#define mmWB_MCIF_BACKPRESSURE_CNT 0x021d
|
#define mmWB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
|
#define mmWBSCL_CLAMP_Y_RGB 0x021e
|
#define mmWBSCL_CLAMP_Y_RGB_BASE_IDX 2
|
#define mmWBSCL_CLAMP_CBCR 0x021f
|
#define mmWBSCL_CLAMP_CBCR_BASE_IDX 2
|
#define mmWBSCL_OUTSIDE_PIX_STRATEGY 0x0220
|
#define mmWBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
|
#define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR 0x0221
|
#define mmWBSCL_OUTSIDE_PIX_STRATEGY_CBCR_BASE_IDX 2
|
#define mmWBSCL_DEBUG 0x0222
|
#define mmWBSCL_DEBUG_BASE_IDX 2
|
#define mmWBSCL_TEST_DEBUG_INDEX 0x0223
|
#define mmWBSCL_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmWBSCL_TEST_DEBUG_DATA 0x0224
|
#define mmWBSCL_TEST_DEBUG_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x8e8
|
#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x023a
|
#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x023b
|
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x023c
|
#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_CNTL 0x023d
|
#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_CNTL2 0x023e
|
#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x023f
|
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0240
|
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_HI 0x0241
|
#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_LOW 0x0242
|
#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
|
// base address: 0x0
|
#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2
|
#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3
|
#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x02b4
|
#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x02b5
|
#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x02b6
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x02b7
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x02b8
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x02b9
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x02ba
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x02bb
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x02bc
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x02bd
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x02be
|
#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x02bf
|
#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX 0x02c0
|
#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA 0x02c1
|
#define mmMCIF_WB0_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x02c2
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x02c4
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x02c6
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x02c8
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x02ca
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x02cc
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x02ce
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x02d0
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2
|
#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3
|
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x02d4
|
#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x02d5
|
#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6
|
#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x02d7
|
#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8
|
#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9
|
#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL 0x02da
|
#define mmMCIF_WB0_MCIF_WB_SECURITY_LEVEL_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db
|
#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
|
#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x02dd
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH 0x02de
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x02df
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH 0x02e0
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x02e1
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH 0x02e2
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x02e3
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH 0x02e4
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION 0x02e5
|
#define mmMCIF_WB0_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION 0x02e6
|
#define mmMCIF_WB0_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION 0x02e7
|
#define mmMCIF_WB0_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION 0x02e8
|
#define mmMCIF_WB0_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec
|
// base address: 0x100
|
#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2
|
#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3
|
#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02f4
|
#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02f5
|
#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02f6
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02f7
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02f8
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02f9
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02fa
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02fb
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02fc
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02fd
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02fe
|
#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02ff
|
#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX 0x0300
|
#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA 0x0301
|
#define mmMCIF_WB1_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x0302
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x0304
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x0306
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x0308
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x030a
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x030c
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x030e
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x0310
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312
|
#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313
|
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x0314
|
#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x0315
|
#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x0316
|
#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x0317
|
#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x0318
|
#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x0319
|
#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x031b
|
#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x031c
|
#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x031d
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH 0x031e
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x031f
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH 0x0320
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x0321
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH 0x0322
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x0323
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH 0x0324
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION 0x0325
|
#define mmMCIF_WB1_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION 0x0326
|
#define mmMCIF_WB1_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION 0x0327
|
#define mmMCIF_WB1_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION 0x0328
|
#define mmMCIF_WB1_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
|
// base address: 0x0
|
#define mmWBIF0_MISC_CTRL 0x0333
|
#define mmWBIF0_MISC_CTRL_BASE_IDX 2
|
#define mmWBIF0_SMU_WM_CONTROL 0x0334
|
#define mmWBIF0_SMU_WM_CONTROL_BASE_IDX 2
|
#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335
|
#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
|
#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336
|
#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
|
#define mmVGA_SRC_SPLIT_CNTL 0x033f
|
#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2
|
#define mmMMHUBBUB_MEM_PWR_STATUS 0x0340
|
#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmMMHUBBUB_MEM_PWR_CNTL 0x0341
|
#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2
|
#define mmMMHUBBUB_CLOCK_CNTL 0x0342
|
#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2
|
#define mmMMHUBBUB_SOFT_RESET 0x0343
|
#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2
|
#define mmDMU_IF_ERR_STATUS 0x0347
|
#define mmDMU_IF_ERR_STATUS_BASE_IDX 2
|
#define mmMMHUBBUB_CLIENT_UNIT_ID 0x0348
|
#define mmMMHUBBUB_CLIENT_UNIT_ID_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
|
// base address: 0x0
|
#define mmMCIF_CONTROL 0x034a
|
#define mmMCIF_CONTROL_BASE_IDX 2
|
#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b
|
#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
|
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e
|
#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
|
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f
|
#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
|
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350
|
#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xd48
|
#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x0352
|
#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x0353
|
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x0354
|
#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFMON_CNTL 0x0355
|
#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFMON_CNTL2 0x0356
|
#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x0357
|
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x0358
|
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFMON_HI 0x0359
|
#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFMON_LOW 0x035a
|
#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream0_dispdec
|
// base address: 0x0
|
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e
|
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f
|
#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream1_dispdec
|
// base address: 0x8
|
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360
|
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361
|
#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream2_dispdec
|
// base address: 0x10
|
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362
|
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363
|
#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream3_dispdec
|
// base address: 0x18
|
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364
|
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365
|
#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream4_dispdec
|
// base address: 0x20
|
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366
|
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367
|
#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream5_dispdec
|
// base address: 0x28
|
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368
|
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369
|
#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream6_dispdec
|
// base address: 0x30
|
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a
|
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b
|
#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream7_dispdec
|
// base address: 0x38
|
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c
|
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d
|
#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_az_misc_dispdec
|
// base address: 0x0
|
#define mmAZ_CLOCK_CNTL 0x0372
|
#define mmAZ_CLOCK_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xde8
|
#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x037a
|
#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x037b
|
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x037c
|
#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFMON_CNTL 0x037d
|
#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFMON_CNTL2 0x037e
|
#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x037f
|
#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0380
|
#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFMON_HI 0x0381
|
#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON5_PERFMON_LOW 0x0382
|
#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
|
// base address: 0x0
|
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386
|
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387
|
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
|
// base address: 0x18
|
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c
|
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d
|
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
|
// base address: 0x30
|
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392
|
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393
|
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
|
// base address: 0x48
|
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398
|
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399
|
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
|
// base address: 0x60
|
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e
|
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f
|
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
|
// base address: 0x78
|
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4
|
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5
|
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
|
// base address: 0x90
|
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa
|
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab
|
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
|
// base address: 0xa8
|
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0
|
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1
|
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0controller_dispdec
|
// base address: 0x0
|
#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2
|
#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
|
#define mmAZALIA_AUDIO_DTO 0x03c3
|
#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
|
#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4
|
#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
|
#define mmAZALIA_SOCCLK_CONTROL 0x03c5
|
#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
|
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6
|
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
|
#define mmAZALIA_DATA_DMA_CONTROL 0x03c7
|
#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
|
#define mmAZALIA_BDL_DMA_CONTROL 0x03c8
|
#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
|
#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9
|
#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
|
#define mmAZALIA_CORB_DMA_CONTROL 0x03ca
|
#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
|
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1
|
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
|
#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2
|
#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
|
#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3
|
#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
|
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4
|
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
|
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5
|
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
|
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6
|
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9
|
#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da
|
#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db
|
#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc
|
#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd
|
#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de
|
#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df
|
#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0
|
#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1
|
#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2
|
#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
|
#define mmAZALIA_CRC0_CONTROL0 0x03e3
|
#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
|
#define mmAZALIA_CRC0_CONTROL1 0x03e4
|
#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
|
#define mmAZALIA_CRC0_CONTROL2 0x03e5
|
#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
|
#define mmAZALIA_CRC0_CONTROL3 0x03e6
|
#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
|
#define mmAZALIA_CRC0_RESULT 0x03e7
|
#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
|
#define mmAZALIA_CRC1_CONTROL0 0x03e8
|
#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
|
#define mmAZALIA_CRC1_CONTROL1 0x03e9
|
#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
|
#define mmAZALIA_CRC1_CONTROL2 0x03ea
|
#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
|
#define mmAZALIA_CRC1_CONTROL3 0x03eb
|
#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
|
#define mmAZALIA_CRC1_RESULT 0x03ec
|
#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
|
#define mmAZALIA_MEM_PWR_CTRL 0x03ee
|
#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmAZALIA_MEM_PWR_STATUS 0x03ef
|
#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0root_dispdec
|
// base address: 0x0
|
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406
|
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
|
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407
|
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
|
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408
|
#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
|
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409
|
#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
|
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a
|
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
|
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b
|
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
|
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c
|
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
|
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d
|
#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
|
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e
|
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
|
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f
|
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
|
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410
|
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
|
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411
|
#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
|
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412
|
#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
|
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413
|
#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b
|
#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
|
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c
|
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
|
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d
|
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream8_dispdec
|
// base address: 0x320
|
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426
|
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427
|
#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream9_dispdec
|
// base address: 0x328
|
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428
|
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429
|
#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream10_dispdec
|
// base address: 0x330
|
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a
|
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b
|
#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream11_dispdec
|
// base address: 0x338
|
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c
|
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d
|
#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream12_dispdec
|
// base address: 0x340
|
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e
|
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f
|
#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream13_dispdec
|
// base address: 0x348
|
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430
|
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431
|
#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream14_dispdec
|
// base address: 0x350
|
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432
|
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433
|
#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0stream15_dispdec
|
// base address: 0x358
|
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434
|
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435
|
#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
|
// base address: 0x0
|
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a
|
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b
|
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
|
// base address: 0x10
|
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e
|
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f
|
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
|
// base address: 0x20
|
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442
|
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443
|
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
|
// base address: 0x30
|
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446
|
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447
|
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
|
// base address: 0x40
|
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a
|
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b
|
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
|
// base address: 0x50
|
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e
|
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f
|
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
|
// base address: 0x60
|
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452
|
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453
|
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
|
// base address: 0x70
|
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456
|
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457
|
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
|
// base address: 0x0
|
#define mmDCHUBBUB_SDPIF_CFG0 0x048f
|
#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2
|
#define mmVM_REQUEST_PHYSICAL 0x0490
|
#define mmVM_REQUEST_PHYSICAL_BASE_IDX 2
|
#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491
|
#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2
|
#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492
|
#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2
|
#define mmDCN_VM_FB_LOCATION_BASE 0x0493
|
#define mmDCN_VM_FB_LOCATION_BASE_BASE_IDX 2
|
#define mmDCN_VM_FB_LOCATION_TOP 0x0494
|
#define mmDCN_VM_FB_LOCATION_TOP_BASE_IDX 2
|
#define mmDCN_VM_FB_OFFSET 0x0495
|
#define mmDCN_VM_FB_OFFSET_BASE_IDX 2
|
#define mmDCN_VM_AGP_BOT 0x0496
|
#define mmDCN_VM_AGP_BOT_BASE_IDX 2
|
#define mmDCN_VM_AGP_TOP 0x0497
|
#define mmDCN_VM_AGP_TOP_BASE_IDX 2
|
#define mmDCN_VM_AGP_BASE 0x0498
|
#define mmDCN_VM_AGP_BASE_BASE_IDX 2
|
#define mmDCN_VM_LOCAL_HBM_ADDRESS_START 0x0499
|
#define mmDCN_VM_LOCAL_HBM_ADDRESS_START_BASE_IDX 2
|
#define mmDCN_VM_LOCAL_HBM_ADDRESS_END 0x049a
|
#define mmDCN_VM_LOCAL_HBM_ADDRESS_END_BASE_IDX 2
|
#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 0x049b
|
#define mmDCN_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_BASE_IDX 2
|
#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x04b8
|
#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2
|
#define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL 0x04b9
|
#define mmDCHUBBUB_SDPIF_PIPE_DMDATA_SEC_LVL_BASE_IDX 2
|
#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04ba
|
#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04bb
|
#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDCHUBBUB_SDPIF_CFG1 0x04bf
|
#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
|
// base address: 0x0
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG8_0 0x04e0
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG8_0_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG8_1 0x04e1
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG8_1_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG9_0 0x04e2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG9_0_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG9_1 0x04e3
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG9_1_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG10_0 0x04e4
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG10_0_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG10_1 0x04e5
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG10_1_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG11_0 0x04e6
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG11_0_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG11_1 0x04e7
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG11_1_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04ef
|
#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04f0
|
#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDCHUBBUB_CRC_CTRL 0x04f1
|
#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2
|
#define mmDCHUBBUB_CRC0_VAL_R_G 0x04f2
|
#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2
|
#define mmDCHUBBUB_CRC0_VAL_B_A 0x04f3
|
#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2
|
#define mmDCHUBBUB_CRC1_VAL_R_G 0x04f4
|
#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2
|
#define mmDCHUBBUB_CRC1_VAL_B_A 0x04f5
|
#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dchubbub_hubbub_dispdec
|
// base address: 0x0
|
#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505
|
#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506
|
#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507
|
#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508
|
#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509
|
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0x050a
|
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b
|
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c
|
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d
|
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e
|
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0x050f
|
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510
|
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511
|
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512
|
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513
|
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0x0514
|
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515
|
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516
|
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517
|
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518
|
#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0x0519
|
#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a
|
#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b
|
#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c
|
#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d
|
#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2
|
#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e
|
#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2
|
#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f
|
#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2
|
#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520
|
#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2
|
#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521
|
#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2
|
#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522
|
#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2
|
#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523
|
#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2
|
#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524
|
#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2
|
#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525
|
#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2
|
#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526
|
#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2
|
#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527
|
#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2
|
#define mmVTG0_CONTROL 0x0528
|
#define mmVTG0_CONTROL_BASE_IDX 2
|
#define mmVTG1_CONTROL 0x0529
|
#define mmVTG1_CONTROL_BASE_IDX 2
|
#define mmVTG2_CONTROL 0x052a
|
#define mmVTG2_CONTROL_BASE_IDX 2
|
#define mmVTG3_CONTROL 0x052b
|
#define mmVTG3_CONTROL_BASE_IDX 2
|
#define mmVTG4_CONTROL 0x052c
|
#define mmVTG4_CONTROL_BASE_IDX 2
|
#define mmVTG5_CONTROL 0x052d
|
#define mmVTG5_CONTROL_BASE_IDX 2
|
#define mmDCHUBBUB_SOFT_RESET 0x052e
|
#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2
|
#define mmDCHUBBUB_CLOCK_CNTL 0x052f
|
#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2
|
#define mmDCFCLK_CNTL 0x0530
|
#define mmDCFCLK_CNTL_BASE_IDX 2
|
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531
|
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2
|
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532
|
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2
|
#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533
|
#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2
|
#define mmDCHUBBUB_CTRL_STATUS 0x0534
|
#define mmDCHUBBUB_CTRL_STATUS_BASE_IDX 2
|
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1 0x053a
|
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL1_BASE_IDX 2
|
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2 0x053b
|
#define mmDCHUBBUB_TIMEOUT_DETECTION_CTRL2_BASE_IDX 2
|
#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS 0x053c
|
#define mmDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053d
|
#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053e
|
#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2
|
#define mmFMON_CTRL 0x0548
|
#define mmFMON_CTRL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x1534
|
#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x054d
|
#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x054e
|
#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x054f
|
#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON6_PERFMON_CNTL 0x0550
|
#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON6_PERFMON_CNTL2 0x0551
|
#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x0552
|
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0553
|
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON6_PERFMON_HI 0x0554
|
#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON6_PERFMON_LOW 0x0555
|
#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dchubbub_hubbub_vmrq_if_dispdec
|
// base address: 0x0
|
#define mmDCN_VM_CONTEXT0_CNTL 0x0559
|
#define mmDCN_VM_CONTEXT0_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x055a
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x055b
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x055c
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x055d
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x055e
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x055f
|
#define mmDCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_CNTL 0x0560
|
#define mmDCN_VM_CONTEXT1_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x0561
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x0562
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x0563
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x0564
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x0565
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x0566
|
#define mmDCN_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_CNTL 0x0567
|
#define mmDCN_VM_CONTEXT2_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x0568
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x0569
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x056a
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x056b
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x056c
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x056d
|
#define mmDCN_VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_CNTL 0x056e
|
#define mmDCN_VM_CONTEXT3_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x056f
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x0570
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x0571
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x0572
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x0573
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x0574
|
#define mmDCN_VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_CNTL 0x0575
|
#define mmDCN_VM_CONTEXT4_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x0576
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x0577
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x0578
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x0579
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x057a
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x057b
|
#define mmDCN_VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_CNTL 0x057c
|
#define mmDCN_VM_CONTEXT5_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x057d
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x057e
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x057f
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x0580
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x0581
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x0582
|
#define mmDCN_VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_CNTL 0x0583
|
#define mmDCN_VM_CONTEXT6_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x0584
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x0585
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x0586
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x0587
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x0588
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x0589
|
#define mmDCN_VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_CNTL 0x058a
|
#define mmDCN_VM_CONTEXT7_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x058b
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x058c
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x058d
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x058e
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x058f
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x0590
|
#define mmDCN_VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_CNTL 0x0591
|
#define mmDCN_VM_CONTEXT8_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x0592
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x0593
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x0594
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x0595
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x0596
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x0597
|
#define mmDCN_VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_CNTL 0x0598
|
#define mmDCN_VM_CONTEXT9_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x0599
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x059a
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x059b
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x059c
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x059d
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x059e
|
#define mmDCN_VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_CNTL 0x059f
|
#define mmDCN_VM_CONTEXT10_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x05a0
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x05a1
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x05a2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x05a3
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x05a4
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x05a5
|
#define mmDCN_VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_CNTL 0x05a6
|
#define mmDCN_VM_CONTEXT11_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x05a7
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x05a8
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x05a9
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x05aa
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x05ab
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x05ac
|
#define mmDCN_VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_CNTL 0x05ad
|
#define mmDCN_VM_CONTEXT12_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x05ae
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x05af
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x05b0
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x05b1
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x05b2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x05b3
|
#define mmDCN_VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_CNTL 0x05b4
|
#define mmDCN_VM_CONTEXT13_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x05b5
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x05b6
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x05b7
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x05b8
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x05b9
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x05ba
|
#define mmDCN_VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_CNTL 0x05bb
|
#define mmDCN_VM_CONTEXT14_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x05bc
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x05bd
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x05be
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x05bf
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x05c0
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x05c1
|
#define mmDCN_VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_CNTL 0x05c2
|
#define mmDCN_VM_CONTEXT15_CNTL_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x05c3
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x05c4
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x05c5
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x05c6
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x05c7
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 2
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x05c8
|
#define mmDCN_VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 2
|
#define mmDCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x05c9
|
#define mmDCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmDCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x05ca
|
#define mmDCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x05cb
|
#define mmDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x05cc
|
#define mmDCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmDCN_VM_FAULT_CNTL 0x05cd
|
#define mmDCN_VM_FAULT_CNTL_BASE_IDX 2
|
#define mmDCN_VM_FAULT_STATUS 0x05ce
|
#define mmDCN_VM_FAULT_STATUS_BASE_IDX 2
|
#define mmDCN_VM_FAULT_ADDR_MSB 0x05cf
|
#define mmDCN_VM_FAULT_ADDR_MSB_BASE_IDX 2
|
#define mmDCN_VM_FAULT_ADDR_LSB 0x05d0
|
#define mmDCN_VM_FAULT_ADDR_LSB_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
|
// base address: 0x0
|
#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x05e5
|
#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2
|
#define mmHUBP0_DCSURF_ADDR_CONFIG 0x05e6
|
#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2
|
#define mmHUBP0_DCSURF_TILING_CONFIG 0x05e7
|
#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x05e9
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x05ea
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x05eb
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x05ec
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x05ed
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x05ee
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x05ef
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x05f0
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x05f1
|
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
|
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x05f2
|
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
|
#define mmHUBP0_DCHUBP_CNTL 0x05f3
|
#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2
|
#define mmHUBP0_HUBP_CLK_CNTL 0x05f4
|
#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2
|
#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x05f5
|
#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2
|
#define mmHUBP0_HUBPREQ_DEBUG_DB 0x05f6
|
#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
|
#define mmHUBP0_HUBPREQ_DEBUG 0x05f7
|
#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2
|
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x05fb
|
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
|
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x05fc
|
#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
|
// base address: 0x0
|
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x0607
|
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x0608
|
#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
|
#define mmHUBPREQ0_VMID_SETTINGS_0 0x0609
|
#define mmHUBPREQ0_VMID_SETTINGS_0_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x060a
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x060b
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x060c
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x060d
|
#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x060e
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x060f
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0610
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0611
|
#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0612
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0613
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0614
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0615
|
#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0616
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0617
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0618
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0619
|
#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x061a
|
#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x061b
|
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x061c
|
#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_QUEUE_CONTROL 0x061d
|
#define mmHUBPREQ0_DCSURF_QUEUE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME 0x061e
|
#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
|
#define mmHUBPREQ0_SURFACE_CURRENT_PACING_COUNTER 0x061f
|
#define mmHUBPREQ0_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0620
|
#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0621
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0622
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0623
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0624
|
#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0625
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0626
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0627
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0628
|
#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x062c
|
#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x062d
|
#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x062e
|
#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x062f
|
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x0630
|
#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x0631
|
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x0632
|
#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x0633
|
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x0634
|
#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0 0x0635
|
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1 0x0636
|
#define mmHUBPREQ0_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0637
|
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0638
|
#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
|
#define mmHUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0639
|
#define mmHUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x063a
|
#define mmHUBPREQ0_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x063b
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x063c
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x063d
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x063e
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x063f
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0640
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0641
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0642
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x0643
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_CNTL 0x0644
|
#define mmHUBPREQ0_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
|
#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x0645
|
#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
|
#define mmHUBPREQ0_BLANK_OFFSET_0 0x0646
|
#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2
|
#define mmHUBPREQ0_BLANK_OFFSET_1 0x0647
|
#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2
|
#define mmHUBPREQ0_DST_DIMENSIONS 0x0648
|
#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2
|
#define mmHUBPREQ0_DST_AFTER_SCALER 0x0649
|
#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2
|
#define mmHUBPREQ0_PREFETCH_SETTINGS 0x064a
|
#define mmHUBPREQ0_PREFETCH_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ0_PREFETCH_SETTINGS_C 0x064b
|
#define mmHUBPREQ0_PREFETCH_SETTINGS_C_BASE_IDX 2
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x064c
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x064d
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x064e
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x064f
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x0650
|
#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ0_FLIP_PARAMETERS_0 0x0651
|
#define mmHUBPREQ0_FLIP_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ0_FLIP_PARAMETERS_1 0x0652
|
#define mmHUBPREQ0_FLIP_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ0_FLIP_PARAMETERS_2 0x0653
|
#define mmHUBPREQ0_FLIP_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_0 0x0654
|
#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_1 0x0655
|
#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_2 0x0656
|
#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_3 0x0657
|
#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_4 0x0658
|
#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_5 0x0659
|
#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_6 0x065a
|
#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2
|
#define mmHUBPREQ0_NOM_PARAMETERS_7 0x065b
|
#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2
|
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x065c
|
#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2
|
#define mmHUBPREQ0_PER_LINE_DELIVERY 0x065d
|
#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2
|
#define mmHUBPREQ0_CURSOR_SETTINGS 0x065e
|
#define mmHUBPREQ0_CURSOR_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x065f
|
#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
|
#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT 0x0660
|
#define mmHUBPREQ0_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
|
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x0661
|
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x0662
|
#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
|
// base address: 0x0
|
#define mmHUBPRET0_HUBPRET_CONTROL 0x066c
|
#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x066d
|
#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x066e
|
#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x066f
|
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x0670
|
#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_READ_LINE0 0x0671
|
#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_READ_LINE1 0x0672
|
#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_INTERRUPT 0x0673
|
#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x0674
|
#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
|
#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x0675
|
#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp0_dispdec_cursor0_dispdec
|
// base address: 0x0
|
#define mmCURSOR0_0_CURSOR_CONTROL 0x0678
|
#define mmCURSOR0_0_CURSOR_CONTROL_BASE_IDX 2
|
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS 0x0679
|
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH 0x067a
|
#define mmCURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmCURSOR0_0_CURSOR_SIZE 0x067b
|
#define mmCURSOR0_0_CURSOR_SIZE_BASE_IDX 2
|
#define mmCURSOR0_0_CURSOR_POSITION 0x067c
|
#define mmCURSOR0_0_CURSOR_POSITION_BASE_IDX 2
|
#define mmCURSOR0_0_CURSOR_HOT_SPOT 0x067d
|
#define mmCURSOR0_0_CURSOR_HOT_SPOT_BASE_IDX 2
|
#define mmCURSOR0_0_CURSOR_STEREO_CONTROL 0x067e
|
#define mmCURSOR0_0_CURSOR_STEREO_CONTROL_BASE_IDX 2
|
#define mmCURSOR0_0_CURSOR_DST_OFFSET 0x067f
|
#define mmCURSOR0_0_CURSOR_DST_OFFSET_BASE_IDX 2
|
#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL 0x0680
|
#define mmCURSOR0_0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS 0x0681
|
#define mmCURSOR0_0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH 0x0682
|
#define mmCURSOR0_0_DMDATA_ADDRESS_HIGH_BASE_IDX 2
|
#define mmCURSOR0_0_DMDATA_ADDRESS_LOW 0x0683
|
#define mmCURSOR0_0_DMDATA_ADDRESS_LOW_BASE_IDX 2
|
#define mmCURSOR0_0_DMDATA_CNTL 0x0684
|
#define mmCURSOR0_0_DMDATA_CNTL_BASE_IDX 2
|
#define mmCURSOR0_0_DMDATA_QOS_CNTL 0x0685
|
#define mmCURSOR0_0_DMDATA_QOS_CNTL_BASE_IDX 2
|
#define mmCURSOR0_0_DMDATA_STATUS 0x0686
|
#define mmCURSOR0_0_DMDATA_STATUS_BASE_IDX 2
|
#define mmCURSOR0_0_DMDATA_SW_CNTL 0x0687
|
#define mmCURSOR0_0_DMDATA_SW_CNTL_BASE_IDX 2
|
#define mmCURSOR0_0_DMDATA_SW_DATA 0x0688
|
#define mmCURSOR0_0_DMDATA_SW_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x1a74
|
#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x069d
|
#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x069e
|
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x069f
|
#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFMON_CNTL 0x06a0
|
#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFMON_CNTL2 0x06a1
|
#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x06a2
|
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x06a3
|
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFMON_HI 0x06a4
|
#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFMON_LOW 0x06a5
|
#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp0_dispdec_hubpxfc_dispdec
|
// base address: 0x0
|
#define mmHUBPXFC0_HUBP_XFC_CNTL 0x06a9
|
#define mmHUBPXFC0_HUBP_XFC_CNTL_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x06aa
|
#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x06ab
|
#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x06ac
|
#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x06ad
|
#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_PITCH 0x06ae
|
#define mmHUBPXFC0_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG0 0x06af
|
#define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG1 0x06b0
|
#define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG2 0x06b1
|
#define mmHUBPXFC0_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS 0x06b2
|
#define mmHUBPXFC0_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0 0x06b3
|
#define mmHUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1 0x06b4
|
#define mmHUBPXFC0_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG0 0x06b5
|
#define mmHUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG1 0x06b6
|
#define mmHUBPXFC0_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC0_HUBP_XFC_MPC_CONFIG 0x06b7
|
#define mmHUBPXFC0_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
|
// base address: 0x370
|
#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x06c1
|
#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2
|
#define mmHUBP1_DCSURF_ADDR_CONFIG 0x06c2
|
#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2
|
#define mmHUBP1_DCSURF_TILING_CONFIG 0x06c3
|
#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2
|
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x06c5
|
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x06c6
|
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x06c7
|
#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06c8
|
#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x06c9
|
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x06ca
|
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x06cb
|
#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06cc
|
#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x06cd
|
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
|
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x06ce
|
#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
|
#define mmHUBP1_DCHUBP_CNTL 0x06cf
|
#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2
|
#define mmHUBP1_HUBP_CLK_CNTL 0x06d0
|
#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2
|
#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x06d1
|
#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2
|
#define mmHUBP1_HUBPREQ_DEBUG_DB 0x06d2
|
#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
|
#define mmHUBP1_HUBPREQ_DEBUG 0x06d3
|
#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2
|
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06d7
|
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
|
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06d8
|
#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
|
// base address: 0x370
|
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x06e3
|
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x06e4
|
#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
|
#define mmHUBPREQ1_VMID_SETTINGS_0 0x06e5
|
#define mmHUBPREQ1_VMID_SETTINGS_0_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x06e6
|
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x06e7
|
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x06e8
|
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x06e9
|
#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x06ea
|
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x06eb
|
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x06ec
|
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x06ed
|
#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x06ee
|
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x06ef
|
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x06f0
|
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x06f1
|
#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x06f2
|
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x06f3
|
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x06f4
|
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x06f5
|
#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x06f6
|
#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x06f7
|
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x06f8
|
#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_QUEUE_CONTROL 0x06f9
|
#define mmHUBPREQ1_DCSURF_QUEUE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME 0x06fa
|
#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
|
#define mmHUBPREQ1_SURFACE_CURRENT_PACING_COUNTER 0x06fb
|
#define mmHUBPREQ1_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x06fc
|
#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x06fd
|
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x06fe
|
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x06ff
|
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x0700
|
#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x0701
|
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0702
|
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0703
|
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0704
|
#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x0708
|
#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0709
|
#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x070a
|
#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x070b
|
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x070c
|
#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x070d
|
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x070e
|
#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x070f
|
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0710
|
#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0 0x0711
|
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1 0x0712
|
#define mmHUBPREQ1_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0713
|
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0714
|
#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
|
#define mmHUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0715
|
#define mmHUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0716
|
#define mmHUBPREQ1_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x0717
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x0718
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0719
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x071a
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x071b
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x071c
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x071d
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x071e
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x071f
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_CNTL 0x0720
|
#define mmHUBPREQ1_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
|
#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0721
|
#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
|
#define mmHUBPREQ1_BLANK_OFFSET_0 0x0722
|
#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2
|
#define mmHUBPREQ1_BLANK_OFFSET_1 0x0723
|
#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2
|
#define mmHUBPREQ1_DST_DIMENSIONS 0x0724
|
#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2
|
#define mmHUBPREQ1_DST_AFTER_SCALER 0x0725
|
#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2
|
#define mmHUBPREQ1_PREFETCH_SETTINGS 0x0726
|
#define mmHUBPREQ1_PREFETCH_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ1_PREFETCH_SETTINGS_C 0x0727
|
#define mmHUBPREQ1_PREFETCH_SETTINGS_C_BASE_IDX 2
|
#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0728
|
#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0729
|
#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x072a
|
#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x072b
|
#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x072c
|
#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ1_FLIP_PARAMETERS_0 0x072d
|
#define mmHUBPREQ1_FLIP_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ1_FLIP_PARAMETERS_1 0x072e
|
#define mmHUBPREQ1_FLIP_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ1_FLIP_PARAMETERS_2 0x072f
|
#define mmHUBPREQ1_FLIP_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ1_NOM_PARAMETERS_0 0x0730
|
#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ1_NOM_PARAMETERS_1 0x0731
|
#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0732
|
#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0733
|
#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0734
|
#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ1_NOM_PARAMETERS_5 0x0735
|
#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2
|
#define mmHUBPREQ1_NOM_PARAMETERS_6 0x0736
|
#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2
|
#define mmHUBPREQ1_NOM_PARAMETERS_7 0x0737
|
#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2
|
#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x0738
|
#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2
|
#define mmHUBPREQ1_PER_LINE_DELIVERY 0x0739
|
#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2
|
#define mmHUBPREQ1_CURSOR_SETTINGS 0x073a
|
#define mmHUBPREQ1_CURSOR_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x073b
|
#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
|
#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT 0x073c
|
#define mmHUBPREQ1_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
|
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x073d
|
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x073e
|
#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
|
// base address: 0x370
|
#define mmHUBPRET1_HUBPRET_CONTROL 0x0748
|
#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2
|
#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x0749
|
#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x074a
|
#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x074b
|
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
|
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x074c
|
#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
|
#define mmHUBPRET1_HUBPRET_READ_LINE0 0x074d
|
#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2
|
#define mmHUBPRET1_HUBPRET_READ_LINE1 0x074e
|
#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2
|
#define mmHUBPRET1_HUBPRET_INTERRUPT 0x074f
|
#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2
|
#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x0750
|
#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
|
#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x0751
|
#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp1_dispdec_cursor0_dispdec
|
// base address: 0x370
|
#define mmCURSOR0_1_CURSOR_CONTROL 0x0754
|
#define mmCURSOR0_1_CURSOR_CONTROL_BASE_IDX 2
|
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS 0x0755
|
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH 0x0756
|
#define mmCURSOR0_1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmCURSOR0_1_CURSOR_SIZE 0x0757
|
#define mmCURSOR0_1_CURSOR_SIZE_BASE_IDX 2
|
#define mmCURSOR0_1_CURSOR_POSITION 0x0758
|
#define mmCURSOR0_1_CURSOR_POSITION_BASE_IDX 2
|
#define mmCURSOR0_1_CURSOR_HOT_SPOT 0x0759
|
#define mmCURSOR0_1_CURSOR_HOT_SPOT_BASE_IDX 2
|
#define mmCURSOR0_1_CURSOR_STEREO_CONTROL 0x075a
|
#define mmCURSOR0_1_CURSOR_STEREO_CONTROL_BASE_IDX 2
|
#define mmCURSOR0_1_CURSOR_DST_OFFSET 0x075b
|
#define mmCURSOR0_1_CURSOR_DST_OFFSET_BASE_IDX 2
|
#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL 0x075c
|
#define mmCURSOR0_1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS 0x075d
|
#define mmCURSOR0_1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH 0x075e
|
#define mmCURSOR0_1_DMDATA_ADDRESS_HIGH_BASE_IDX 2
|
#define mmCURSOR0_1_DMDATA_ADDRESS_LOW 0x075f
|
#define mmCURSOR0_1_DMDATA_ADDRESS_LOW_BASE_IDX 2
|
#define mmCURSOR0_1_DMDATA_CNTL 0x0760
|
#define mmCURSOR0_1_DMDATA_CNTL_BASE_IDX 2
|
#define mmCURSOR0_1_DMDATA_QOS_CNTL 0x0761
|
#define mmCURSOR0_1_DMDATA_QOS_CNTL_BASE_IDX 2
|
#define mmCURSOR0_1_DMDATA_STATUS 0x0762
|
#define mmCURSOR0_1_DMDATA_STATUS_BASE_IDX 2
|
#define mmCURSOR0_1_DMDATA_SW_CNTL 0x0763
|
#define mmCURSOR0_1_DMDATA_SW_CNTL_BASE_IDX 2
|
#define mmCURSOR0_1_DMDATA_SW_DATA 0x0764
|
#define mmCURSOR0_1_DMDATA_SW_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x1de4
|
#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0779
|
#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x077a
|
#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x077b
|
#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON8_PERFMON_CNTL 0x077c
|
#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON8_PERFMON_CNTL2 0x077d
|
#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x077e
|
#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x077f
|
#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON8_PERFMON_HI 0x0780
|
#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON8_PERFMON_LOW 0x0781
|
#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp1_dispdec_hubpxfc_dispdec
|
// base address: 0x370
|
#define mmHUBPXFC1_HUBP_XFC_CNTL 0x0785
|
#define mmHUBPXFC1_HUBP_XFC_CNTL_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x0786
|
#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x0787
|
#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0788
|
#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0789
|
#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_PITCH 0x078a
|
#define mmHUBPXFC1_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG0 0x078b
|
#define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG1 0x078c
|
#define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG2 0x078d
|
#define mmHUBPXFC1_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS 0x078e
|
#define mmHUBPXFC1_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0 0x078f
|
#define mmHUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1 0x0790
|
#define mmHUBPXFC1_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG0 0x0791
|
#define mmHUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG1 0x0792
|
#define mmHUBPXFC1_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC1_HUBP_XFC_MPC_CONFIG 0x0793
|
#define mmHUBPXFC1_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
|
// base address: 0x6e0
|
#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x079d
|
#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2
|
#define mmHUBP2_DCSURF_ADDR_CONFIG 0x079e
|
#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2
|
#define mmHUBP2_DCSURF_TILING_CONFIG 0x079f
|
#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2
|
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x07a1
|
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a2
|
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x07a3
|
#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07a4
|
#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x07a5
|
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x07a6
|
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x07a7
|
#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07a8
|
#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x07a9
|
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
|
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x07aa
|
#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
|
#define mmHUBP2_DCHUBP_CNTL 0x07ab
|
#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2
|
#define mmHUBP2_HUBP_CLK_CNTL 0x07ac
|
#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2
|
#define mmHUBP2_DCHUBP_VMPG_CONFIG 0x07ad
|
#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2
|
#define mmHUBP2_HUBPREQ_DEBUG_DB 0x07ae
|
#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2
|
#define mmHUBP2_HUBPREQ_DEBUG 0x07af
|
#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2
|
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07b3
|
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
|
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07b4
|
#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
|
// base address: 0x6e0
|
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x07bf
|
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x07c0
|
#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
|
#define mmHUBPREQ2_VMID_SETTINGS_0 0x07c1
|
#define mmHUBPREQ2_VMID_SETTINGS_0_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c2
|
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07c3
|
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07c4
|
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07c5
|
#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07c6
|
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07c7
|
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07c8
|
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07c9
|
#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07ca
|
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07cb
|
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07cc
|
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07cd
|
#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07ce
|
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07cf
|
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d0
|
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d1
|
#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x07d2
|
#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x07d3
|
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x07d4
|
#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_QUEUE_CONTROL 0x07d5
|
#define mmHUBPREQ2_DCSURF_QUEUE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME 0x07d6
|
#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
|
#define mmHUBPREQ2_SURFACE_CURRENT_PACING_COUNTER 0x07d7
|
#define mmHUBPREQ2_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x07d8
|
#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x07d9
|
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x07da
|
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x07db
|
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x07dc
|
#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x07dd
|
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07de
|
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07df
|
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e0
|
#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x07e4
|
#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x07e5
|
#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x07e6
|
#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x07e7
|
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x07e8
|
#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x07e9
|
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x07ea
|
#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x07eb
|
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x07ec
|
#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0 0x07ed
|
#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1 0x07ee
|
#define mmHUBPREQ2_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x07ef
|
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x07f0
|
#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
|
#define mmHUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x07f1
|
#define mmHUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x07f2
|
#define mmHUBPREQ2_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x07f3
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x07f4
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x07f5
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x07f6
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x07f7
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x07f8
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x07f9
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x07fa
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x07fb
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_CNTL 0x07fc
|
#define mmHUBPREQ2_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
|
#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x07fd
|
#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
|
#define mmHUBPREQ2_BLANK_OFFSET_0 0x07fe
|
#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2
|
#define mmHUBPREQ2_BLANK_OFFSET_1 0x07ff
|
#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2
|
#define mmHUBPREQ2_DST_DIMENSIONS 0x0800
|
#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2
|
#define mmHUBPREQ2_DST_AFTER_SCALER 0x0801
|
#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2
|
#define mmHUBPREQ2_PREFETCH_SETTINGS 0x0802
|
#define mmHUBPREQ2_PREFETCH_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ2_PREFETCH_SETTINGS_C 0x0803
|
#define mmHUBPREQ2_PREFETCH_SETTINGS_C_BASE_IDX 2
|
#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0804
|
#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0805
|
#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0806
|
#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0807
|
#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0808
|
#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ2_FLIP_PARAMETERS_0 0x0809
|
#define mmHUBPREQ2_FLIP_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ2_FLIP_PARAMETERS_1 0x080a
|
#define mmHUBPREQ2_FLIP_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ2_FLIP_PARAMETERS_2 0x080b
|
#define mmHUBPREQ2_FLIP_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ2_NOM_PARAMETERS_0 0x080c
|
#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ2_NOM_PARAMETERS_1 0x080d
|
#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ2_NOM_PARAMETERS_2 0x080e
|
#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ2_NOM_PARAMETERS_3 0x080f
|
#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ2_NOM_PARAMETERS_4 0x0810
|
#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ2_NOM_PARAMETERS_5 0x0811
|
#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2
|
#define mmHUBPREQ2_NOM_PARAMETERS_6 0x0812
|
#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2
|
#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0813
|
#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2
|
#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0814
|
#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2
|
#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0815
|
#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2
|
#define mmHUBPREQ2_CURSOR_SETTINGS 0x0816
|
#define mmHUBPREQ2_CURSOR_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0817
|
#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
|
#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT 0x0818
|
#define mmHUBPREQ2_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
|
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0819
|
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x081a
|
#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
|
// base address: 0x6e0
|
#define mmHUBPRET2_HUBPRET_CONTROL 0x0824
|
#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2
|
#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0825
|
#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x0826
|
#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x0827
|
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
|
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x0828
|
#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
|
#define mmHUBPRET2_HUBPRET_READ_LINE0 0x0829
|
#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2
|
#define mmHUBPRET2_HUBPRET_READ_LINE1 0x082a
|
#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2
|
#define mmHUBPRET2_HUBPRET_INTERRUPT 0x082b
|
#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2
|
#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x082c
|
#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
|
#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x082d
|
#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp2_dispdec_cursor0_dispdec
|
// base address: 0x6e0
|
#define mmCURSOR0_2_CURSOR_CONTROL 0x0830
|
#define mmCURSOR0_2_CURSOR_CONTROL_BASE_IDX 2
|
#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS 0x0831
|
#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH 0x0832
|
#define mmCURSOR0_2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmCURSOR0_2_CURSOR_SIZE 0x0833
|
#define mmCURSOR0_2_CURSOR_SIZE_BASE_IDX 2
|
#define mmCURSOR0_2_CURSOR_POSITION 0x0834
|
#define mmCURSOR0_2_CURSOR_POSITION_BASE_IDX 2
|
#define mmCURSOR0_2_CURSOR_HOT_SPOT 0x0835
|
#define mmCURSOR0_2_CURSOR_HOT_SPOT_BASE_IDX 2
|
#define mmCURSOR0_2_CURSOR_STEREO_CONTROL 0x0836
|
#define mmCURSOR0_2_CURSOR_STEREO_CONTROL_BASE_IDX 2
|
#define mmCURSOR0_2_CURSOR_DST_OFFSET 0x0837
|
#define mmCURSOR0_2_CURSOR_DST_OFFSET_BASE_IDX 2
|
#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL 0x0838
|
#define mmCURSOR0_2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS 0x0839
|
#define mmCURSOR0_2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH 0x083a
|
#define mmCURSOR0_2_DMDATA_ADDRESS_HIGH_BASE_IDX 2
|
#define mmCURSOR0_2_DMDATA_ADDRESS_LOW 0x083b
|
#define mmCURSOR0_2_DMDATA_ADDRESS_LOW_BASE_IDX 2
|
#define mmCURSOR0_2_DMDATA_CNTL 0x083c
|
#define mmCURSOR0_2_DMDATA_CNTL_BASE_IDX 2
|
#define mmCURSOR0_2_DMDATA_QOS_CNTL 0x083d
|
#define mmCURSOR0_2_DMDATA_QOS_CNTL_BASE_IDX 2
|
#define mmCURSOR0_2_DMDATA_STATUS 0x083e
|
#define mmCURSOR0_2_DMDATA_STATUS_BASE_IDX 2
|
#define mmCURSOR0_2_DMDATA_SW_CNTL 0x083f
|
#define mmCURSOR0_2_DMDATA_SW_CNTL_BASE_IDX 2
|
#define mmCURSOR0_2_DMDATA_SW_DATA 0x0840
|
#define mmCURSOR0_2_DMDATA_SW_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x2154
|
#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x0855
|
#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x0856
|
#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x0857
|
#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON9_PERFMON_CNTL 0x0858
|
#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON9_PERFMON_CNTL2 0x0859
|
#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x085a
|
#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x085b
|
#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON9_PERFMON_HI 0x085c
|
#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON9_PERFMON_LOW 0x085d
|
#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp2_dispdec_hubpxfc_dispdec
|
// base address: 0x6e0
|
#define mmHUBPXFC2_HUBP_XFC_CNTL 0x0861
|
#define mmHUBPXFC2_HUBP_XFC_CNTL_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x0862
|
#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x0863
|
#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0864
|
#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0865
|
#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_PITCH 0x0866
|
#define mmHUBPXFC2_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG0 0x0867
|
#define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG1 0x0868
|
#define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG2 0x0869
|
#define mmHUBPXFC2_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS 0x086a
|
#define mmHUBPXFC2_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0 0x086b
|
#define mmHUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1 0x086c
|
#define mmHUBPXFC2_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG0 0x086d
|
#define mmHUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG1 0x086e
|
#define mmHUBPXFC2_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC2_HUBP_XFC_MPC_CONFIG 0x086f
|
#define mmHUBPXFC2_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
|
// base address: 0xa50
|
#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x0879
|
#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2
|
#define mmHUBP3_DCSURF_ADDR_CONFIG 0x087a
|
#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2
|
#define mmHUBP3_DCSURF_TILING_CONFIG 0x087b
|
#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2
|
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x087d
|
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x087e
|
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x087f
|
#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0880
|
#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x0881
|
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x0882
|
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x0883
|
#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0884
|
#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x0885
|
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
|
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x0886
|
#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
|
#define mmHUBP3_DCHUBP_CNTL 0x0887
|
#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2
|
#define mmHUBP3_HUBP_CLK_CNTL 0x0888
|
#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2
|
#define mmHUBP3_DCHUBP_VMPG_CONFIG 0x0889
|
#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2
|
#define mmHUBP3_HUBPREQ_DEBUG_DB 0x088a
|
#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2
|
#define mmHUBP3_HUBPREQ_DEBUG 0x088b
|
#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2
|
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x088f
|
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
|
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0890
|
#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
|
// base address: 0xa50
|
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x089b
|
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x089c
|
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
|
#define mmHUBPREQ3_VMID_SETTINGS_0 0x089d
|
#define mmHUBPREQ3_VMID_SETTINGS_0_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x089e
|
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x089f
|
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x08a0
|
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x08a1
|
#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x08a2
|
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x08a3
|
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x08a4
|
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x08a5
|
#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x08a6
|
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x08a7
|
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x08a8
|
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x08a9
|
#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x08aa
|
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x08ab
|
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x08ac
|
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x08ad
|
#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x08ae
|
#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x08af
|
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x08b0
|
#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_QUEUE_CONTROL 0x08b1
|
#define mmHUBPREQ3_DCSURF_QUEUE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME 0x08b2
|
#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
|
#define mmHUBPREQ3_SURFACE_CURRENT_PACING_COUNTER 0x08b3
|
#define mmHUBPREQ3_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x08b4
|
#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x08b5
|
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x08b6
|
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x08b7
|
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x08b8
|
#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x08b9
|
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x08ba
|
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x08bb
|
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x08bc
|
#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x08c0
|
#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x08c1
|
#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x08c2
|
#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x08c3
|
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x08c4
|
#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x08c5
|
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x08c6
|
#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x08c7
|
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x08c8
|
#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0 0x08c9
|
#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1 0x08ca
|
#define mmHUBPREQ3_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x08cb
|
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x08cc
|
#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
|
#define mmHUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x08cd
|
#define mmHUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x08ce
|
#define mmHUBPREQ3_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x08cf
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x08d0
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x08d1
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x08d2
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x08d3
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x08d4
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x08d5
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x08d6
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x08d7
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_CNTL 0x08d8
|
#define mmHUBPREQ3_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
|
#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x08d9
|
#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
|
#define mmHUBPREQ3_BLANK_OFFSET_0 0x08da
|
#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2
|
#define mmHUBPREQ3_BLANK_OFFSET_1 0x08db
|
#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2
|
#define mmHUBPREQ3_DST_DIMENSIONS 0x08dc
|
#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2
|
#define mmHUBPREQ3_DST_AFTER_SCALER 0x08dd
|
#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2
|
#define mmHUBPREQ3_PREFETCH_SETTINGS 0x08de
|
#define mmHUBPREQ3_PREFETCH_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ3_PREFETCH_SETTINGS_C 0x08df
|
#define mmHUBPREQ3_PREFETCH_SETTINGS_C_BASE_IDX 2
|
#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x08e0
|
#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x08e1
|
#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x08e2
|
#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x08e3
|
#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x08e4
|
#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ3_FLIP_PARAMETERS_0 0x08e5
|
#define mmHUBPREQ3_FLIP_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ3_FLIP_PARAMETERS_1 0x08e6
|
#define mmHUBPREQ3_FLIP_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ3_FLIP_PARAMETERS_2 0x08e7
|
#define mmHUBPREQ3_FLIP_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ3_NOM_PARAMETERS_0 0x08e8
|
#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ3_NOM_PARAMETERS_1 0x08e9
|
#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ3_NOM_PARAMETERS_2 0x08ea
|
#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ3_NOM_PARAMETERS_3 0x08eb
|
#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ3_NOM_PARAMETERS_4 0x08ec
|
#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ3_NOM_PARAMETERS_5 0x08ed
|
#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2
|
#define mmHUBPREQ3_NOM_PARAMETERS_6 0x08ee
|
#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2
|
#define mmHUBPREQ3_NOM_PARAMETERS_7 0x08ef
|
#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2
|
#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x08f0
|
#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2
|
#define mmHUBPREQ3_PER_LINE_DELIVERY 0x08f1
|
#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2
|
#define mmHUBPREQ3_CURSOR_SETTINGS 0x08f2
|
#define mmHUBPREQ3_CURSOR_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x08f3
|
#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
|
#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT 0x08f4
|
#define mmHUBPREQ3_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
|
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x08f5
|
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x08f6
|
#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
|
// base address: 0xa50
|
#define mmHUBPRET3_HUBPRET_CONTROL 0x0900
|
#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2
|
#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x0901
|
#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x0902
|
#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x0903
|
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
|
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0904
|
#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
|
#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0905
|
#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2
|
#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0906
|
#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2
|
#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0907
|
#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2
|
#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0908
|
#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
|
#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0909
|
#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp3_dispdec_cursor0_dispdec
|
// base address: 0xa50
|
#define mmCURSOR0_3_CURSOR_CONTROL 0x090c
|
#define mmCURSOR0_3_CURSOR_CONTROL_BASE_IDX 2
|
#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS 0x090d
|
#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH 0x090e
|
#define mmCURSOR0_3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmCURSOR0_3_CURSOR_SIZE 0x090f
|
#define mmCURSOR0_3_CURSOR_SIZE_BASE_IDX 2
|
#define mmCURSOR0_3_CURSOR_POSITION 0x0910
|
#define mmCURSOR0_3_CURSOR_POSITION_BASE_IDX 2
|
#define mmCURSOR0_3_CURSOR_HOT_SPOT 0x0911
|
#define mmCURSOR0_3_CURSOR_HOT_SPOT_BASE_IDX 2
|
#define mmCURSOR0_3_CURSOR_STEREO_CONTROL 0x0912
|
#define mmCURSOR0_3_CURSOR_STEREO_CONTROL_BASE_IDX 2
|
#define mmCURSOR0_3_CURSOR_DST_OFFSET 0x0913
|
#define mmCURSOR0_3_CURSOR_DST_OFFSET_BASE_IDX 2
|
#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL 0x0914
|
#define mmCURSOR0_3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS 0x0915
|
#define mmCURSOR0_3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH 0x0916
|
#define mmCURSOR0_3_DMDATA_ADDRESS_HIGH_BASE_IDX 2
|
#define mmCURSOR0_3_DMDATA_ADDRESS_LOW 0x0917
|
#define mmCURSOR0_3_DMDATA_ADDRESS_LOW_BASE_IDX 2
|
#define mmCURSOR0_3_DMDATA_CNTL 0x0918
|
#define mmCURSOR0_3_DMDATA_CNTL_BASE_IDX 2
|
#define mmCURSOR0_3_DMDATA_QOS_CNTL 0x0919
|
#define mmCURSOR0_3_DMDATA_QOS_CNTL_BASE_IDX 2
|
#define mmCURSOR0_3_DMDATA_STATUS 0x091a
|
#define mmCURSOR0_3_DMDATA_STATUS_BASE_IDX 2
|
#define mmCURSOR0_3_DMDATA_SW_CNTL 0x091b
|
#define mmCURSOR0_3_DMDATA_SW_CNTL_BASE_IDX 2
|
#define mmCURSOR0_3_DMDATA_SW_DATA 0x091c
|
#define mmCURSOR0_3_DMDATA_SW_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x24c4
|
#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0931
|
#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x0932
|
#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x0933
|
#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON10_PERFMON_CNTL 0x0934
|
#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON10_PERFMON_CNTL2 0x0935
|
#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x0936
|
#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x0937
|
#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON10_PERFMON_HI 0x0938
|
#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON10_PERFMON_LOW 0x0939
|
#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp3_dispdec_hubpxfc_dispdec
|
// base address: 0xa50
|
#define mmHUBPXFC3_HUBP_XFC_CNTL 0x093d
|
#define mmHUBPXFC3_HUBP_XFC_CNTL_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x093e
|
#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x093f
|
#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0940
|
#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0941
|
#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_PITCH 0x0942
|
#define mmHUBPXFC3_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG0 0x0943
|
#define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG1 0x0944
|
#define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG2 0x0945
|
#define mmHUBPXFC3_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS 0x0946
|
#define mmHUBPXFC3_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0 0x0947
|
#define mmHUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1 0x0948
|
#define mmHUBPXFC3_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG0 0x0949
|
#define mmHUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG1 0x094a
|
#define mmHUBPXFC3_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC3_HUBP_XFC_MPC_CONFIG 0x094b
|
#define mmHUBPXFC3_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp4_dispdec_hubp_dispdec
|
// base address: 0xdc0
|
#define mmHUBP4_DCSURF_SURFACE_CONFIG 0x0955
|
#define mmHUBP4_DCSURF_SURFACE_CONFIG_BASE_IDX 2
|
#define mmHUBP4_DCSURF_ADDR_CONFIG 0x0956
|
#define mmHUBP4_DCSURF_ADDR_CONFIG_BASE_IDX 2
|
#define mmHUBP4_DCSURF_TILING_CONFIG 0x0957
|
#define mmHUBP4_DCSURF_TILING_CONFIG_BASE_IDX 2
|
#define mmHUBP4_DCSURF_PRI_VIEWPORT_START 0x0959
|
#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION 0x095a
|
#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C 0x095b
|
#define mmHUBP4_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x095c
|
#define mmHUBP4_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP4_DCSURF_SEC_VIEWPORT_START 0x095d
|
#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION 0x095e
|
#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C 0x095f
|
#define mmHUBP4_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0960
|
#define mmHUBP4_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG 0x0961
|
#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
|
#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C 0x0962
|
#define mmHUBP4_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
|
#define mmHUBP4_DCHUBP_CNTL 0x0963
|
#define mmHUBP4_DCHUBP_CNTL_BASE_IDX 2
|
#define mmHUBP4_HUBP_CLK_CNTL 0x0964
|
#define mmHUBP4_HUBP_CLK_CNTL_BASE_IDX 2
|
#define mmHUBP4_DCHUBP_VMPG_CONFIG 0x0965
|
#define mmHUBP4_DCHUBP_VMPG_CONFIG_BASE_IDX 2
|
#define mmHUBP4_HUBPREQ_DEBUG_DB 0x0966
|
#define mmHUBP4_HUBPREQ_DEBUG_DB_BASE_IDX 2
|
#define mmHUBP4_HUBPREQ_DEBUG 0x0967
|
#define mmHUBP4_HUBPREQ_DEBUG_BASE_IDX 2
|
#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x096b
|
#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
|
#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x096c
|
#define mmHUBP4_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp4_dispdec_hubpreq_dispdec
|
// base address: 0xdc0
|
#define mmHUBPREQ4_DCSURF_SURFACE_PITCH 0x0977
|
#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C 0x0978
|
#define mmHUBPREQ4_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
|
#define mmHUBPREQ4_VMID_SETTINGS_0 0x0979
|
#define mmHUBPREQ4_VMID_SETTINGS_0_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS 0x097a
|
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x097b
|
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x097c
|
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x097d
|
#define mmHUBPREQ4_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS 0x097e
|
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x097f
|
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0980
|
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0981
|
#define mmHUBPREQ4_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0982
|
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0983
|
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0984
|
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0985
|
#define mmHUBPREQ4_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0986
|
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0987
|
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0988
|
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0989
|
#define mmHUBPREQ4_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SURFACE_CONTROL 0x098a
|
#define mmHUBPREQ4_DCSURF_SURFACE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_FLIP_CONTROL 0x098b
|
#define mmHUBPREQ4_DCSURF_FLIP_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_FLIP_CONTROL2 0x098c
|
#define mmHUBPREQ4_DCSURF_FLIP_CONTROL2_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_QUEUE_CONTROL 0x098d
|
#define mmHUBPREQ4_DCSURF_QUEUE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_FRAME_PACING_TIME 0x098e
|
#define mmHUBPREQ4_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
|
#define mmHUBPREQ4_SURFACE_CURRENT_PACING_COUNTER 0x098f
|
#define mmHUBPREQ4_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT 0x0990
|
#define mmHUBPREQ4_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE 0x0991
|
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH 0x0992
|
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C 0x0993
|
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C 0x0994
|
#define mmHUBPREQ4_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE 0x0995
|
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0996
|
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0997
|
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0998
|
#define mmHUBPREQ4_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_EXPANSION_MODE 0x099c
|
#define mmHUBPREQ4_DCN_EXPANSION_MODE_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_TTU_QOS_WM 0x099d
|
#define mmHUBPREQ4_DCN_TTU_QOS_WM_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL 0x099e
|
#define mmHUBPREQ4_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0 0x099f
|
#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1 0x09a0
|
#define mmHUBPREQ4_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0 0x09a1
|
#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1 0x09a2
|
#define mmHUBPREQ4_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0 0x09a3
|
#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1 0x09a4
|
#define mmHUBPREQ4_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0 0x09a5
|
#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1 0x09a6
|
#define mmHUBPREQ4_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x09a7
|
#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x09a8
|
#define mmHUBPREQ4_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
|
#define mmHUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x09a9
|
#define mmHUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x09aa
|
#define mmHUBPREQ4_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x09ab
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x09ac
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x09ad
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x09ae
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x09af
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x09b0
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x09b1
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x09b2
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x09b3
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_CNTL 0x09b4
|
#define mmHUBPREQ4_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
|
#define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL 0x09b5
|
#define mmHUBPREQ4_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
|
#define mmHUBPREQ4_BLANK_OFFSET_0 0x09b6
|
#define mmHUBPREQ4_BLANK_OFFSET_0_BASE_IDX 2
|
#define mmHUBPREQ4_BLANK_OFFSET_1 0x09b7
|
#define mmHUBPREQ4_BLANK_OFFSET_1_BASE_IDX 2
|
#define mmHUBPREQ4_DST_DIMENSIONS 0x09b8
|
#define mmHUBPREQ4_DST_DIMENSIONS_BASE_IDX 2
|
#define mmHUBPREQ4_DST_AFTER_SCALER 0x09b9
|
#define mmHUBPREQ4_DST_AFTER_SCALER_BASE_IDX 2
|
#define mmHUBPREQ4_PREFETCH_SETTINGS 0x09ba
|
#define mmHUBPREQ4_PREFETCH_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ4_PREFETCH_SETTINGS_C 0x09bb
|
#define mmHUBPREQ4_PREFETCH_SETTINGS_C_BASE_IDX 2
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_0 0x09bc
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_1 0x09bd
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_2 0x09be
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_3 0x09bf
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_4 0x09c0
|
#define mmHUBPREQ4_VBLANK_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ4_FLIP_PARAMETERS_0 0x09c1
|
#define mmHUBPREQ4_FLIP_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ4_FLIP_PARAMETERS_1 0x09c2
|
#define mmHUBPREQ4_FLIP_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ4_FLIP_PARAMETERS_2 0x09c3
|
#define mmHUBPREQ4_FLIP_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ4_NOM_PARAMETERS_0 0x09c4
|
#define mmHUBPREQ4_NOM_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ4_NOM_PARAMETERS_1 0x09c5
|
#define mmHUBPREQ4_NOM_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ4_NOM_PARAMETERS_2 0x09c6
|
#define mmHUBPREQ4_NOM_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ4_NOM_PARAMETERS_3 0x09c7
|
#define mmHUBPREQ4_NOM_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ4_NOM_PARAMETERS_4 0x09c8
|
#define mmHUBPREQ4_NOM_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ4_NOM_PARAMETERS_5 0x09c9
|
#define mmHUBPREQ4_NOM_PARAMETERS_5_BASE_IDX 2
|
#define mmHUBPREQ4_NOM_PARAMETERS_6 0x09ca
|
#define mmHUBPREQ4_NOM_PARAMETERS_6_BASE_IDX 2
|
#define mmHUBPREQ4_NOM_PARAMETERS_7 0x09cb
|
#define mmHUBPREQ4_NOM_PARAMETERS_7_BASE_IDX 2
|
#define mmHUBPREQ4_PER_LINE_DELIVERY_PRE 0x09cc
|
#define mmHUBPREQ4_PER_LINE_DELIVERY_PRE_BASE_IDX 2
|
#define mmHUBPREQ4_PER_LINE_DELIVERY 0x09cd
|
#define mmHUBPREQ4_PER_LINE_DELIVERY_BASE_IDX 2
|
#define mmHUBPREQ4_CURSOR_SETTINGS 0x09ce
|
#define mmHUBPREQ4_CURSOR_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ 0x09cf
|
#define mmHUBPREQ4_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
|
#define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT 0x09d0
|
#define mmHUBPREQ4_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
|
#define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL 0x09d1
|
#define mmHUBPREQ4_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS 0x09d2
|
#define mmHUBPREQ4_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp4_dispdec_hubpret_dispdec
|
// base address: 0xdc0
|
#define mmHUBPRET4_HUBPRET_CONTROL 0x09dc
|
#define mmHUBPRET4_HUBPRET_CONTROL_BASE_IDX 2
|
#define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL 0x09dd
|
#define mmHUBPRET4_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS 0x09de
|
#define mmHUBPRET4_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0 0x09df
|
#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
|
#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1 0x09e0
|
#define mmHUBPRET4_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
|
#define mmHUBPRET4_HUBPRET_READ_LINE0 0x09e1
|
#define mmHUBPRET4_HUBPRET_READ_LINE0_BASE_IDX 2
|
#define mmHUBPRET4_HUBPRET_READ_LINE1 0x09e2
|
#define mmHUBPRET4_HUBPRET_READ_LINE1_BASE_IDX 2
|
#define mmHUBPRET4_HUBPRET_INTERRUPT 0x09e3
|
#define mmHUBPRET4_HUBPRET_INTERRUPT_BASE_IDX 2
|
#define mmHUBPRET4_HUBPRET_READ_LINE_VALUE 0x09e4
|
#define mmHUBPRET4_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
|
#define mmHUBPRET4_HUBPRET_READ_LINE_STATUS 0x09e5
|
#define mmHUBPRET4_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp4_dispdec_cursor0_dispdec
|
// base address: 0xdc0
|
#define mmCURSOR0_4_CURSOR_CONTROL 0x09e8
|
#define mmCURSOR0_4_CURSOR_CONTROL_BASE_IDX 2
|
#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS 0x09e9
|
#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH 0x09ea
|
#define mmCURSOR0_4_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmCURSOR0_4_CURSOR_SIZE 0x09eb
|
#define mmCURSOR0_4_CURSOR_SIZE_BASE_IDX 2
|
#define mmCURSOR0_4_CURSOR_POSITION 0x09ec
|
#define mmCURSOR0_4_CURSOR_POSITION_BASE_IDX 2
|
#define mmCURSOR0_4_CURSOR_HOT_SPOT 0x09ed
|
#define mmCURSOR0_4_CURSOR_HOT_SPOT_BASE_IDX 2
|
#define mmCURSOR0_4_CURSOR_STEREO_CONTROL 0x09ee
|
#define mmCURSOR0_4_CURSOR_STEREO_CONTROL_BASE_IDX 2
|
#define mmCURSOR0_4_CURSOR_DST_OFFSET 0x09ef
|
#define mmCURSOR0_4_CURSOR_DST_OFFSET_BASE_IDX 2
|
#define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL 0x09f0
|
#define mmCURSOR0_4_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS 0x09f1
|
#define mmCURSOR0_4_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCURSOR0_4_DMDATA_ADDRESS_HIGH 0x09f2
|
#define mmCURSOR0_4_DMDATA_ADDRESS_HIGH_BASE_IDX 2
|
#define mmCURSOR0_4_DMDATA_ADDRESS_LOW 0x09f3
|
#define mmCURSOR0_4_DMDATA_ADDRESS_LOW_BASE_IDX 2
|
#define mmCURSOR0_4_DMDATA_CNTL 0x09f4
|
#define mmCURSOR0_4_DMDATA_CNTL_BASE_IDX 2
|
#define mmCURSOR0_4_DMDATA_QOS_CNTL 0x09f5
|
#define mmCURSOR0_4_DMDATA_QOS_CNTL_BASE_IDX 2
|
#define mmCURSOR0_4_DMDATA_STATUS 0x09f6
|
#define mmCURSOR0_4_DMDATA_STATUS_BASE_IDX 2
|
#define mmCURSOR0_4_DMDATA_SW_CNTL 0x09f7
|
#define mmCURSOR0_4_DMDATA_SW_CNTL_BASE_IDX 2
|
#define mmCURSOR0_4_DMDATA_SW_DATA 0x09f8
|
#define mmCURSOR0_4_DMDATA_SW_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp4_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x2834
|
#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x0a0d
|
#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x0a0e
|
#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x0a0f
|
#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON11_PERFMON_CNTL 0x0a10
|
#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON11_PERFMON_CNTL2 0x0a11
|
#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0a12
|
#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0a13
|
#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON11_PERFMON_HI 0x0a14
|
#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON11_PERFMON_LOW 0x0a15
|
#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp4_dispdec_hubpxfc_dispdec
|
// base address: 0xdc0
|
#define mmHUBPXFC4_HUBP_XFC_CNTL 0x0a19
|
#define mmHUBPXFC4_HUBP_XFC_CNTL_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x0a1a
|
#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x0a1b
|
#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0a1c
|
#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0a1d
|
#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_PITCH 0x0a1e
|
#define mmHUBPXFC4_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG0 0x0a1f
|
#define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG1 0x0a20
|
#define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG2 0x0a21
|
#define mmHUBPXFC4_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS 0x0a22
|
#define mmHUBPXFC4_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0 0x0a23
|
#define mmHUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1 0x0a24
|
#define mmHUBPXFC4_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG0 0x0a25
|
#define mmHUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG1 0x0a26
|
#define mmHUBPXFC4_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC4_HUBP_XFC_MPC_CONFIG 0x0a27
|
#define mmHUBPXFC4_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp5_dispdec_hubp_dispdec
|
// base address: 0x1130
|
#define mmHUBP5_DCSURF_SURFACE_CONFIG 0x0a31
|
#define mmHUBP5_DCSURF_SURFACE_CONFIG_BASE_IDX 2
|
#define mmHUBP5_DCSURF_ADDR_CONFIG 0x0a32
|
#define mmHUBP5_DCSURF_ADDR_CONFIG_BASE_IDX 2
|
#define mmHUBP5_DCSURF_TILING_CONFIG 0x0a33
|
#define mmHUBP5_DCSURF_TILING_CONFIG_BASE_IDX 2
|
#define mmHUBP5_DCSURF_PRI_VIEWPORT_START 0x0a35
|
#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION 0x0a36
|
#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C 0x0a37
|
#define mmHUBP5_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0a38
|
#define mmHUBP5_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP5_DCSURF_SEC_VIEWPORT_START 0x0a39
|
#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION 0x0a3a
|
#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C 0x0a3b
|
#define mmHUBP5_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0a3c
|
#define mmHUBP5_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG 0x0a3d
|
#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
|
#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C 0x0a3e
|
#define mmHUBP5_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
|
#define mmHUBP5_DCHUBP_CNTL 0x0a3f
|
#define mmHUBP5_DCHUBP_CNTL_BASE_IDX 2
|
#define mmHUBP5_HUBP_CLK_CNTL 0x0a40
|
#define mmHUBP5_HUBP_CLK_CNTL_BASE_IDX 2
|
#define mmHUBP5_DCHUBP_VMPG_CONFIG 0x0a41
|
#define mmHUBP5_DCHUBP_VMPG_CONFIG_BASE_IDX 2
|
#define mmHUBP5_HUBPREQ_DEBUG_DB 0x0a42
|
#define mmHUBP5_HUBPREQ_DEBUG_DB_BASE_IDX 2
|
#define mmHUBP5_HUBPREQ_DEBUG 0x0a43
|
#define mmHUBP5_HUBPREQ_DEBUG_BASE_IDX 2
|
#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0a47
|
#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
|
#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0a48
|
#define mmHUBP5_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp5_dispdec_hubpreq_dispdec
|
// base address: 0x1130
|
#define mmHUBPREQ5_DCSURF_SURFACE_PITCH 0x0a53
|
#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C 0x0a54
|
#define mmHUBPREQ5_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
|
#define mmHUBPREQ5_VMID_SETTINGS_0 0x0a55
|
#define mmHUBPREQ5_VMID_SETTINGS_0_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0a56
|
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0a57
|
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0a58
|
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0a59
|
#define mmHUBPREQ5_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0a5a
|
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0a5b
|
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0a5c
|
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0a5d
|
#define mmHUBPREQ5_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0a5e
|
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0a5f
|
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0a60
|
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0a61
|
#define mmHUBPREQ5_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0a62
|
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0a63
|
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0a64
|
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0a65
|
#define mmHUBPREQ5_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SURFACE_CONTROL 0x0a66
|
#define mmHUBPREQ5_DCSURF_SURFACE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_FLIP_CONTROL 0x0a67
|
#define mmHUBPREQ5_DCSURF_FLIP_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_FLIP_CONTROL2 0x0a68
|
#define mmHUBPREQ5_DCSURF_FLIP_CONTROL2_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_QUEUE_CONTROL 0x0a69
|
#define mmHUBPREQ5_DCSURF_QUEUE_CONTROL_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_FRAME_PACING_TIME 0x0a6a
|
#define mmHUBPREQ5_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
|
#define mmHUBPREQ5_SURFACE_CURRENT_PACING_COUNTER 0x0a6b
|
#define mmHUBPREQ5_SURFACE_CURRENT_PACING_COUNTER_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT 0x0a6c
|
#define mmHUBPREQ5_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE 0x0a6d
|
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH 0x0a6e
|
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C 0x0a6f
|
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C 0x0a70
|
#define mmHUBPREQ5_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE 0x0a71
|
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0a72
|
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0a73
|
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
|
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0a74
|
#define mmHUBPREQ5_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_EXPANSION_MODE 0x0a78
|
#define mmHUBPREQ5_DCN_EXPANSION_MODE_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_TTU_QOS_WM 0x0a79
|
#define mmHUBPREQ5_DCN_TTU_QOS_WM_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL 0x0a7a
|
#define mmHUBPREQ5_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0 0x0a7b
|
#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1 0x0a7c
|
#define mmHUBPREQ5_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0 0x0a7d
|
#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1 0x0a7e
|
#define mmHUBPREQ5_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0 0x0a7f
|
#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1 0x0a80
|
#define mmHUBPREQ5_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0 0x0a81
|
#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL0_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1 0x0a82
|
#define mmHUBPREQ5_DCN_CUR1_TTU_CNTL1_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR 0x0a83
|
#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR 0x0a84
|
#define mmHUBPREQ5_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 2
|
#define mmHUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0a85
|
#define mmHUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0a86
|
#define mmHUBPREQ5_DC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x0a87
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x0a88
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0a89
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0a8a
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0a8b
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0a8c
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0a8d
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0a8e
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x0a8f
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_CNTL 0x0a90
|
#define mmHUBPREQ5_DC_VM_CONTEXT0_CNTL_BASE_IDX 2
|
#define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL 0x0a91
|
#define mmHUBPREQ5_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
|
#define mmHUBPREQ5_BLANK_OFFSET_0 0x0a92
|
#define mmHUBPREQ5_BLANK_OFFSET_0_BASE_IDX 2
|
#define mmHUBPREQ5_BLANK_OFFSET_1 0x0a93
|
#define mmHUBPREQ5_BLANK_OFFSET_1_BASE_IDX 2
|
#define mmHUBPREQ5_DST_DIMENSIONS 0x0a94
|
#define mmHUBPREQ5_DST_DIMENSIONS_BASE_IDX 2
|
#define mmHUBPREQ5_DST_AFTER_SCALER 0x0a95
|
#define mmHUBPREQ5_DST_AFTER_SCALER_BASE_IDX 2
|
#define mmHUBPREQ5_PREFETCH_SETTINGS 0x0a96
|
#define mmHUBPREQ5_PREFETCH_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ5_PREFETCH_SETTINGS_C 0x0a97
|
#define mmHUBPREQ5_PREFETCH_SETTINGS_C_BASE_IDX 2
|
#define mmHUBPREQ5_VBLANK_PARAMETERS_0 0x0a98
|
#define mmHUBPREQ5_VBLANK_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ5_VBLANK_PARAMETERS_1 0x0a99
|
#define mmHUBPREQ5_VBLANK_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ5_VBLANK_PARAMETERS_2 0x0a9a
|
#define mmHUBPREQ5_VBLANK_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ5_VBLANK_PARAMETERS_3 0x0a9b
|
#define mmHUBPREQ5_VBLANK_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ5_VBLANK_PARAMETERS_4 0x0a9c
|
#define mmHUBPREQ5_VBLANK_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ5_FLIP_PARAMETERS_0 0x0a9d
|
#define mmHUBPREQ5_FLIP_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ5_FLIP_PARAMETERS_1 0x0a9e
|
#define mmHUBPREQ5_FLIP_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ5_FLIP_PARAMETERS_2 0x0a9f
|
#define mmHUBPREQ5_FLIP_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ5_NOM_PARAMETERS_0 0x0aa0
|
#define mmHUBPREQ5_NOM_PARAMETERS_0_BASE_IDX 2
|
#define mmHUBPREQ5_NOM_PARAMETERS_1 0x0aa1
|
#define mmHUBPREQ5_NOM_PARAMETERS_1_BASE_IDX 2
|
#define mmHUBPREQ5_NOM_PARAMETERS_2 0x0aa2
|
#define mmHUBPREQ5_NOM_PARAMETERS_2_BASE_IDX 2
|
#define mmHUBPREQ5_NOM_PARAMETERS_3 0x0aa3
|
#define mmHUBPREQ5_NOM_PARAMETERS_3_BASE_IDX 2
|
#define mmHUBPREQ5_NOM_PARAMETERS_4 0x0aa4
|
#define mmHUBPREQ5_NOM_PARAMETERS_4_BASE_IDX 2
|
#define mmHUBPREQ5_NOM_PARAMETERS_5 0x0aa5
|
#define mmHUBPREQ5_NOM_PARAMETERS_5_BASE_IDX 2
|
#define mmHUBPREQ5_NOM_PARAMETERS_6 0x0aa6
|
#define mmHUBPREQ5_NOM_PARAMETERS_6_BASE_IDX 2
|
#define mmHUBPREQ5_NOM_PARAMETERS_7 0x0aa7
|
#define mmHUBPREQ5_NOM_PARAMETERS_7_BASE_IDX 2
|
#define mmHUBPREQ5_PER_LINE_DELIVERY_PRE 0x0aa8
|
#define mmHUBPREQ5_PER_LINE_DELIVERY_PRE_BASE_IDX 2
|
#define mmHUBPREQ5_PER_LINE_DELIVERY 0x0aa9
|
#define mmHUBPREQ5_PER_LINE_DELIVERY_BASE_IDX 2
|
#define mmHUBPREQ5_CURSOR_SETTINGS 0x0aaa
|
#define mmHUBPREQ5_CURSOR_SETTINGS_BASE_IDX 2
|
#define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ 0x0aab
|
#define mmHUBPREQ5_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
|
#define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT 0x0aac
|
#define mmHUBPREQ5_DST_Y_DELTA_DRQ_LIMIT_BASE_IDX 2
|
#define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL 0x0aad
|
#define mmHUBPREQ5_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS 0x0aae
|
#define mmHUBPREQ5_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp5_dispdec_hubpret_dispdec
|
// base address: 0x1130
|
#define mmHUBPRET5_HUBPRET_CONTROL 0x0ab8
|
#define mmHUBPRET5_HUBPRET_CONTROL_BASE_IDX 2
|
#define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL 0x0ab9
|
#define mmHUBPRET5_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS 0x0aba
|
#define mmHUBPRET5_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0 0x0abb
|
#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
|
#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1 0x0abc
|
#define mmHUBPRET5_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
|
#define mmHUBPRET5_HUBPRET_READ_LINE0 0x0abd
|
#define mmHUBPRET5_HUBPRET_READ_LINE0_BASE_IDX 2
|
#define mmHUBPRET5_HUBPRET_READ_LINE1 0x0abe
|
#define mmHUBPRET5_HUBPRET_READ_LINE1_BASE_IDX 2
|
#define mmHUBPRET5_HUBPRET_INTERRUPT 0x0abf
|
#define mmHUBPRET5_HUBPRET_INTERRUPT_BASE_IDX 2
|
#define mmHUBPRET5_HUBPRET_READ_LINE_VALUE 0x0ac0
|
#define mmHUBPRET5_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
|
#define mmHUBPRET5_HUBPRET_READ_LINE_STATUS 0x0ac1
|
#define mmHUBPRET5_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp5_dispdec_cursor0_dispdec
|
// base address: 0x1130
|
#define mmCURSOR0_5_CURSOR_CONTROL 0x0ac4
|
#define mmCURSOR0_5_CURSOR_CONTROL_BASE_IDX 2
|
#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS 0x0ac5
|
#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
|
#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH 0x0ac6
|
#define mmCURSOR0_5_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
|
#define mmCURSOR0_5_CURSOR_SIZE 0x0ac7
|
#define mmCURSOR0_5_CURSOR_SIZE_BASE_IDX 2
|
#define mmCURSOR0_5_CURSOR_POSITION 0x0ac8
|
#define mmCURSOR0_5_CURSOR_POSITION_BASE_IDX 2
|
#define mmCURSOR0_5_CURSOR_HOT_SPOT 0x0ac9
|
#define mmCURSOR0_5_CURSOR_HOT_SPOT_BASE_IDX 2
|
#define mmCURSOR0_5_CURSOR_STEREO_CONTROL 0x0aca
|
#define mmCURSOR0_5_CURSOR_STEREO_CONTROL_BASE_IDX 2
|
#define mmCURSOR0_5_CURSOR_DST_OFFSET 0x0acb
|
#define mmCURSOR0_5_CURSOR_DST_OFFSET_BASE_IDX 2
|
#define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL 0x0acc
|
#define mmCURSOR0_5_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS 0x0acd
|
#define mmCURSOR0_5_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCURSOR0_5_DMDATA_ADDRESS_HIGH 0x0ace
|
#define mmCURSOR0_5_DMDATA_ADDRESS_HIGH_BASE_IDX 2
|
#define mmCURSOR0_5_DMDATA_ADDRESS_LOW 0x0acf
|
#define mmCURSOR0_5_DMDATA_ADDRESS_LOW_BASE_IDX 2
|
#define mmCURSOR0_5_DMDATA_CNTL 0x0ad0
|
#define mmCURSOR0_5_DMDATA_CNTL_BASE_IDX 2
|
#define mmCURSOR0_5_DMDATA_QOS_CNTL 0x0ad1
|
#define mmCURSOR0_5_DMDATA_QOS_CNTL_BASE_IDX 2
|
#define mmCURSOR0_5_DMDATA_STATUS 0x0ad2
|
#define mmCURSOR0_5_DMDATA_STATUS_BASE_IDX 2
|
#define mmCURSOR0_5_DMDATA_SW_CNTL 0x0ad3
|
#define mmCURSOR0_5_DMDATA_SW_CNTL_BASE_IDX 2
|
#define mmCURSOR0_5_DMDATA_SW_DATA 0x0ad4
|
#define mmCURSOR0_5_DMDATA_SW_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp5_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x2ba4
|
#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0ae9
|
#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0aea
|
#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0aeb
|
#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFMON_CNTL 0x0aec
|
#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFMON_CNTL2 0x0aed
|
#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0aee
|
#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0aef
|
#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFMON_HI 0x0af0
|
#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON12_PERFMON_LOW 0x0af1
|
#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp5_dispdec_hubpxfc_dispdec
|
// base address: 0x1130
|
#define mmHUBPXFC5_HUBP_XFC_CNTL 0x0af5
|
#define mmHUBPXFC5_HUBP_XFC_CNTL_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB 0x0af6
|
#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB 0x0af7
|
#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE0_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB 0x0af8
|
#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_LSB_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB 0x0af9
|
#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_BASE1_ADDR_MSB_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_PITCH 0x0afa
|
#define mmHUBPXFC5_HUBP_XFC_XBUF_RD_PITCH_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG0 0x0afb
|
#define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG1 0x0afc
|
#define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG2 0x0afd
|
#define mmHUBPXFC5_HUBP_XFC_DELAY_CONFIG2_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS 0x0afe
|
#define mmHUBPXFC5_HUBP_XFC_UNDERFLOW_STATUS_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0 0x0aff
|
#define mmHUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1 0x0b00
|
#define mmHUBPXFC5_HUBP_XFC_SLV_VTG_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG0 0x0b01
|
#define mmHUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG0_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG1 0x0b02
|
#define mmHUBPXFC5_HUBP_XFC_SLV_SCALER_CONFIG1_BASE_IDX 2
|
#define mmHUBPXFC5_HUBP_XFC_MPC_CONFIG 0x0b03
|
#define mmHUBPXFC5_HUBP_XFC_MPC_CONFIG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
|
// base address: 0x0
|
#define mmDPP_TOP0_DPP_CONTROL 0x0cc5
|
#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2
|
#define mmDPP_TOP0_DPP_SOFT_RESET 0x0cc6
|
#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2
|
#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0cc7
|
#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2
|
#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0cc8
|
#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2
|
#define mmDPP_TOP0_DPP_CRC_CTRL 0x0cc9
|
#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2
|
#define mmDPP_TOP0_HOST_READ_CONTROL 0x0cca
|
#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
|
// base address: 0x0
|
#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0ccf
|
#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
|
#define mmCNVC_CFG0_FORMAT_CONTROL 0x0cd0
|
#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG0_FCNV_FP_BIAS_R 0x0cd1
|
#define mmCNVC_CFG0_FCNV_FP_BIAS_R_BASE_IDX 2
|
#define mmCNVC_CFG0_FCNV_FP_BIAS_G 0x0cd2
|
#define mmCNVC_CFG0_FCNV_FP_BIAS_G_BASE_IDX 2
|
#define mmCNVC_CFG0_FCNV_FP_BIAS_B 0x0cd3
|
#define mmCNVC_CFG0_FCNV_FP_BIAS_B_BASE_IDX 2
|
#define mmCNVC_CFG0_FCNV_FP_SCALE_R 0x0cd4
|
#define mmCNVC_CFG0_FCNV_FP_SCALE_R_BASE_IDX 2
|
#define mmCNVC_CFG0_FCNV_FP_SCALE_G 0x0cd5
|
#define mmCNVC_CFG0_FCNV_FP_SCALE_G_BASE_IDX 2
|
#define mmCNVC_CFG0_FCNV_FP_SCALE_B 0x0cd6
|
#define mmCNVC_CFG0_FCNV_FP_SCALE_B_BASE_IDX 2
|
#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0cd7
|
#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0cd8
|
#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2
|
#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0cd9
|
#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2
|
#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0cda
|
#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2
|
#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0cdb
|
#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2
|
#define mmCNVC_CFG0_ALPHA_2BIT_LUT 0x0cdd
|
#define mmCNVC_CFG0_ALPHA_2BIT_LUT_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
|
// base address: 0x0
|
#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0ce0
|
#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2
|
#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0ce1
|
#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2
|
#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0ce2
|
#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2
|
#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0ce3
|
#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
|
// base address: 0x0
|
#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0cea
|
#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
|
#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0ceb
|
#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmDSCL0_SCL_MODE 0x0cec
|
#define mmDSCL0_SCL_MODE_BASE_IDX 2
|
#define mmDSCL0_SCL_TAP_CONTROL 0x0ced
|
#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL0_DSCL_CONTROL 0x0cee
|
#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2
|
#define mmDSCL0_DSCL_2TAP_CONTROL 0x0cef
|
#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0cf0
|
#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
|
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0cf1
|
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0cf2
|
#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0cf3
|
#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
|
#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0cf4
|
#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
|
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0cf5
|
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0cf6
|
#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0cf7
|
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
|
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0cf8
|
#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
|
#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0cf9
|
#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
|
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0cfa
|
#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
|
#define mmDSCL0_SCL_BLACK_OFFSET 0x0cfb
|
#define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2
|
#define mmDSCL0_DSCL_UPDATE 0x0cfc
|
#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2
|
#define mmDSCL0_DSCL_AUTOCAL 0x0cfd
|
#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2
|
#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0cfe
|
#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
|
#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0cff
|
#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
|
#define mmDSCL0_OTG_H_BLANK 0x0d00
|
#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2
|
#define mmDSCL0_OTG_V_BLANK 0x0d01
|
#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2
|
#define mmDSCL0_RECOUT_START 0x0d02
|
#define mmDSCL0_RECOUT_START_BASE_IDX 2
|
#define mmDSCL0_RECOUT_SIZE 0x0d03
|
#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2
|
#define mmDSCL0_MPC_SIZE 0x0d04
|
#define mmDSCL0_MPC_SIZE_BASE_IDX 2
|
#define mmDSCL0_LB_DATA_FORMAT 0x0d05
|
#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2
|
#define mmDSCL0_LB_MEMORY_CTRL 0x0d06
|
#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2
|
#define mmDSCL0_LB_V_COUNTER 0x0d07
|
#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2
|
#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0d08
|
#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0d09
|
#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDSCL0_OBUF_CONTROL 0x0d0a
|
#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2
|
#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0d0b
|
#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
|
// base address: 0x0
|
#define mmCM0_CM_CONTROL 0x0d1a
|
#define mmCM0_CM_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_ICSC_CONTROL 0x0d1b
|
#define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_ICSC_C11_C12 0x0d1c
|
#define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2
|
#define mmCM0_CM_ICSC_C13_C14 0x0d1d
|
#define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2
|
#define mmCM0_CM_ICSC_C21_C22 0x0d1e
|
#define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2
|
#define mmCM0_CM_ICSC_C23_C24 0x0d1f
|
#define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2
|
#define mmCM0_CM_ICSC_C31_C32 0x0d20
|
#define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2
|
#define mmCM0_CM_ICSC_C33_C34 0x0d21
|
#define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2
|
#define mmCM0_CM_ICSC_B_C11_C12 0x0d22
|
#define mmCM0_CM_ICSC_B_C11_C12_BASE_IDX 2
|
#define mmCM0_CM_ICSC_B_C13_C14 0x0d23
|
#define mmCM0_CM_ICSC_B_C13_C14_BASE_IDX 2
|
#define mmCM0_CM_ICSC_B_C21_C22 0x0d24
|
#define mmCM0_CM_ICSC_B_C21_C22_BASE_IDX 2
|
#define mmCM0_CM_ICSC_B_C23_C24 0x0d25
|
#define mmCM0_CM_ICSC_B_C23_C24_BASE_IDX 2
|
#define mmCM0_CM_ICSC_B_C31_C32 0x0d26
|
#define mmCM0_CM_ICSC_B_C31_C32_BASE_IDX 2
|
#define mmCM0_CM_ICSC_B_C33_C34 0x0d27
|
#define mmCM0_CM_ICSC_B_C33_C34_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0d28
|
#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0d29
|
#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0d2a
|
#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0d2b
|
#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0d2c
|
#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0d2d
|
#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0d2e
|
#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_B_C11_C12 0x0d2f
|
#define mmCM0_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_B_C13_C14 0x0d30
|
#define mmCM0_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_B_C21_C22 0x0d31
|
#define mmCM0_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_B_C23_C24 0x0d32
|
#define mmCM0_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_B_C31_C32 0x0d33
|
#define mmCM0_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_B_C33_C34 0x0d34
|
#define mmCM0_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
|
#define mmCM0_CM_BIAS_CR_R 0x0d35
|
#define mmCM0_CM_BIAS_CR_R_BASE_IDX 2
|
#define mmCM0_CM_BIAS_Y_G_CB_B 0x0d36
|
#define mmCM0_CM_BIAS_Y_G_CB_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_CONTROL 0x0d37
|
#define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_DGAM_LUT_INDEX 0x0d38
|
#define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM0_CM_DGAM_LUT_DATA 0x0d39
|
#define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0d3a
|
#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0d3b
|
#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0d3c
|
#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0d3d
|
#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0d3e
|
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0d3f
|
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0d40
|
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0d41
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0d42
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0d43
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0d44
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0d45
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0d46
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0d47
|
#define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0d48
|
#define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0d49
|
#define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0d4a
|
#define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0d4b
|
#define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0d4c
|
#define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0d4d
|
#define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0d4e
|
#define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0d4f
|
#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0d50
|
#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0d51
|
#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0d52
|
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0d53
|
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0d54
|
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0d55
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0d56
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0d57
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0d58
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0d59
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0d5a
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0d5b
|
#define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0d5c
|
#define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0d5d
|
#define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0d5e
|
#define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0d5f
|
#define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0d60
|
#define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0d61
|
#define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0d62
|
#define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_CONTROL 0x0d63
|
#define mmCM0_CM_BLNDGAM_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_LUT_INDEX 0x0d64
|
#define mmCM0_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_LUT_DATA 0x0d65
|
#define mmCM0_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0d66
|
#define mmCM0_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B 0x0d67
|
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G 0x0d68
|
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R 0x0d69
|
#define mmCM0_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0d6a
|
#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0d6b
|
#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0d6c
|
#define mmCM0_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0d6d
|
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0d6e
|
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0d6f
|
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0d70
|
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0d71
|
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0d72
|
#define mmCM0_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1 0x0d73
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3 0x0d74
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5 0x0d75
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7 0x0d76
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9 0x0d77
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11 0x0d78
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13 0x0d79
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15 0x0d7a
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17 0x0d7b
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19 0x0d7c
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21 0x0d7d
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23 0x0d7e
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25 0x0d7f
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27 0x0d80
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29 0x0d81
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31 0x0d82
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33 0x0d83
|
#define mmCM0_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B 0x0d84
|
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G 0x0d85
|
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R 0x0d86
|
#define mmCM0_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0d87
|
#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0d88
|
#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0d89
|
#define mmCM0_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0d8a
|
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0d8b
|
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0d8c
|
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0d8d
|
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0d8e
|
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0d8f
|
#define mmCM0_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1 0x0d90
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3 0x0d91
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5 0x0d92
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7 0x0d93
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9 0x0d94
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11 0x0d95
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13 0x0d96
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15 0x0d97
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17 0x0d98
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19 0x0d99
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21 0x0d9a
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23 0x0d9b
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25 0x0d9c
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27 0x0d9d
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29 0x0d9e
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31 0x0d9f
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33 0x0da0
|
#define mmCM0_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM0_CM_HDR_MULT_COEF 0x0da1
|
#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2
|
#define mmCM0_CM_MEM_PWR_CTRL 0x0da2
|
#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCM0_CM_MEM_PWR_STATUS 0x0da3
|
#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCM0_CM_DEALPHA 0x0da5
|
#define mmCM0_CM_DEALPHA_BASE_IDX 2
|
#define mmCM0_CM_COEF_FORMAT 0x0da6
|
#define mmCM0_CM_COEF_FORMAT_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_CONTROL 0x0da7
|
#define mmCM0_CM_SHAPER_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_OFFSET_R 0x0da8
|
#define mmCM0_CM_SHAPER_OFFSET_R_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_OFFSET_G 0x0da9
|
#define mmCM0_CM_SHAPER_OFFSET_G_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_OFFSET_B 0x0daa
|
#define mmCM0_CM_SHAPER_OFFSET_B_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_SCALE_R 0x0dab
|
#define mmCM0_CM_SHAPER_SCALE_R_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_SCALE_G_B 0x0dac
|
#define mmCM0_CM_SHAPER_SCALE_G_B_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_LUT_INDEX 0x0dad
|
#define mmCM0_CM_SHAPER_LUT_INDEX_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_LUT_DATA 0x0dae
|
#define mmCM0_CM_SHAPER_LUT_DATA_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK 0x0daf
|
#define mmCM0_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B 0x0db0
|
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G 0x0db1
|
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R 0x0db2
|
#define mmCM0_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B 0x0db3
|
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G 0x0db4
|
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R 0x0db5
|
#define mmCM0_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_0_1 0x0db6
|
#define mmCM0_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_2_3 0x0db7
|
#define mmCM0_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_4_5 0x0db8
|
#define mmCM0_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_6_7 0x0db9
|
#define mmCM0_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_8_9 0x0dba
|
#define mmCM0_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_10_11 0x0dbb
|
#define mmCM0_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_12_13 0x0dbc
|
#define mmCM0_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_14_15 0x0dbd
|
#define mmCM0_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_16_17 0x0dbe
|
#define mmCM0_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_18_19 0x0dbf
|
#define mmCM0_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_20_21 0x0dc0
|
#define mmCM0_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_22_23 0x0dc1
|
#define mmCM0_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_24_25 0x0dc2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_26_27 0x0dc3
|
#define mmCM0_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_28_29 0x0dc4
|
#define mmCM0_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_30_31 0x0dc5
|
#define mmCM0_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMA_REGION_32_33 0x0dc6
|
#define mmCM0_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B 0x0dc7
|
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G 0x0dc8
|
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R 0x0dc9
|
#define mmCM0_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B 0x0dca
|
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G 0x0dcb
|
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R 0x0dcc
|
#define mmCM0_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_0_1 0x0dcd
|
#define mmCM0_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_2_3 0x0dce
|
#define mmCM0_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_4_5 0x0dcf
|
#define mmCM0_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_6_7 0x0dd0
|
#define mmCM0_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_8_9 0x0dd1
|
#define mmCM0_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_10_11 0x0dd2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_12_13 0x0dd3
|
#define mmCM0_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_14_15 0x0dd4
|
#define mmCM0_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_16_17 0x0dd5
|
#define mmCM0_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_18_19 0x0dd6
|
#define mmCM0_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_20_21 0x0dd7
|
#define mmCM0_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_22_23 0x0dd8
|
#define mmCM0_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_24_25 0x0dd9
|
#define mmCM0_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_26_27 0x0dda
|
#define mmCM0_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_28_29 0x0ddb
|
#define mmCM0_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_30_31 0x0ddc
|
#define mmCM0_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM0_CM_SHAPER_RAMB_REGION_32_33 0x0ddd
|
#define mmCM0_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM0_CM_MEM_PWR_CTRL2 0x0dde
|
#define mmCM0_CM_MEM_PWR_CTRL2_BASE_IDX 2
|
#define mmCM0_CM_MEM_PWR_STATUS2 0x0ddf
|
#define mmCM0_CM_MEM_PWR_STATUS2_BASE_IDX 2
|
#define mmCM0_CM_3DLUT_MODE 0x0de0
|
#define mmCM0_CM_3DLUT_MODE_BASE_IDX 2
|
#define mmCM0_CM_3DLUT_INDEX 0x0de1
|
#define mmCM0_CM_3DLUT_INDEX_BASE_IDX 2
|
#define mmCM0_CM_3DLUT_DATA 0x0de2
|
#define mmCM0_CM_3DLUT_DATA_BASE_IDX 2
|
#define mmCM0_CM_3DLUT_DATA_30BIT 0x0de3
|
#define mmCM0_CM_3DLUT_DATA_30BIT_BASE_IDX 2
|
#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL 0x0de4
|
#define mmCM0_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR 0x0de5
|
#define mmCM0_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
|
#define mmCM0_CM_3DLUT_OUT_OFFSET_R 0x0de6
|
#define mmCM0_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
|
#define mmCM0_CM_3DLUT_OUT_OFFSET_G 0x0de7
|
#define mmCM0_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
|
#define mmCM0_CM_3DLUT_OUT_OFFSET_B 0x0de8
|
#define mmCM0_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
|
#define mmCM0_CM_TEST_DEBUG_INDEX 0x0de9
|
#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmCM0_CM_TEST_DEBUG_DATA 0x0dea
|
#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x3890
|
#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x0e24
|
#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x0e25
|
#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x0e26
|
#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON13_PERFMON_CNTL 0x0e27
|
#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON13_PERFMON_CNTL2 0x0e28
|
#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0e29
|
#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0e2a
|
#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON13_PERFMON_HI 0x0e2b
|
#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON13_PERFMON_LOW 0x0e2c
|
#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
|
// base address: 0x5ac
|
#define mmDPP_TOP1_DPP_CONTROL 0x0e30
|
#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2
|
#define mmDPP_TOP1_DPP_SOFT_RESET 0x0e31
|
#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2
|
#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0e32
|
#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2
|
#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0e33
|
#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2
|
#define mmDPP_TOP1_DPP_CRC_CTRL 0x0e34
|
#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2
|
#define mmDPP_TOP1_HOST_READ_CONTROL 0x0e35
|
#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
|
// base address: 0x5ac
|
#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0e3a
|
#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
|
#define mmCNVC_CFG1_FORMAT_CONTROL 0x0e3b
|
#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG1_FCNV_FP_BIAS_R 0x0e3c
|
#define mmCNVC_CFG1_FCNV_FP_BIAS_R_BASE_IDX 2
|
#define mmCNVC_CFG1_FCNV_FP_BIAS_G 0x0e3d
|
#define mmCNVC_CFG1_FCNV_FP_BIAS_G_BASE_IDX 2
|
#define mmCNVC_CFG1_FCNV_FP_BIAS_B 0x0e3e
|
#define mmCNVC_CFG1_FCNV_FP_BIAS_B_BASE_IDX 2
|
#define mmCNVC_CFG1_FCNV_FP_SCALE_R 0x0e3f
|
#define mmCNVC_CFG1_FCNV_FP_SCALE_R_BASE_IDX 2
|
#define mmCNVC_CFG1_FCNV_FP_SCALE_G 0x0e40
|
#define mmCNVC_CFG1_FCNV_FP_SCALE_G_BASE_IDX 2
|
#define mmCNVC_CFG1_FCNV_FP_SCALE_B 0x0e41
|
#define mmCNVC_CFG1_FCNV_FP_SCALE_B_BASE_IDX 2
|
#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0e42
|
#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0e43
|
#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2
|
#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0e44
|
#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2
|
#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0e45
|
#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2
|
#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0e46
|
#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2
|
#define mmCNVC_CFG1_ALPHA_2BIT_LUT 0x0e48
|
#define mmCNVC_CFG1_ALPHA_2BIT_LUT_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
|
// base address: 0x5ac
|
#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0e4b
|
#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2
|
#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0e4c
|
#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2
|
#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0e4d
|
#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2
|
#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0e4e
|
#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
|
// base address: 0x5ac
|
#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0e55
|
#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
|
#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0e56
|
#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmDSCL1_SCL_MODE 0x0e57
|
#define mmDSCL1_SCL_MODE_BASE_IDX 2
|
#define mmDSCL1_SCL_TAP_CONTROL 0x0e58
|
#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL1_DSCL_CONTROL 0x0e59
|
#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2
|
#define mmDSCL1_DSCL_2TAP_CONTROL 0x0e5a
|
#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0e5b
|
#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
|
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0e5c
|
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0e5d
|
#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0e5e
|
#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
|
#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0e5f
|
#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
|
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0e60
|
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0e61
|
#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0e62
|
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
|
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0e63
|
#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
|
#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0e64
|
#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
|
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0e65
|
#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
|
#define mmDSCL1_SCL_BLACK_OFFSET 0x0e66
|
#define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2
|
#define mmDSCL1_DSCL_UPDATE 0x0e67
|
#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2
|
#define mmDSCL1_DSCL_AUTOCAL 0x0e68
|
#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2
|
#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0e69
|
#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
|
#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0e6a
|
#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
|
#define mmDSCL1_OTG_H_BLANK 0x0e6b
|
#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2
|
#define mmDSCL1_OTG_V_BLANK 0x0e6c
|
#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2
|
#define mmDSCL1_RECOUT_START 0x0e6d
|
#define mmDSCL1_RECOUT_START_BASE_IDX 2
|
#define mmDSCL1_RECOUT_SIZE 0x0e6e
|
#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2
|
#define mmDSCL1_MPC_SIZE 0x0e6f
|
#define mmDSCL1_MPC_SIZE_BASE_IDX 2
|
#define mmDSCL1_LB_DATA_FORMAT 0x0e70
|
#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2
|
#define mmDSCL1_LB_MEMORY_CTRL 0x0e71
|
#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2
|
#define mmDSCL1_LB_V_COUNTER 0x0e72
|
#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2
|
#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0e73
|
#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0e74
|
#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDSCL1_OBUF_CONTROL 0x0e75
|
#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2
|
#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0e76
|
#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
|
// base address: 0x5ac
|
#define mmCM1_CM_CONTROL 0x0e85
|
#define mmCM1_CM_CONTROL_BASE_IDX 2
|
#define mmCM1_CM_ICSC_CONTROL 0x0e86
|
#define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2
|
#define mmCM1_CM_ICSC_C11_C12 0x0e87
|
#define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2
|
#define mmCM1_CM_ICSC_C13_C14 0x0e88
|
#define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2
|
#define mmCM1_CM_ICSC_C21_C22 0x0e89
|
#define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2
|
#define mmCM1_CM_ICSC_C23_C24 0x0e8a
|
#define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2
|
#define mmCM1_CM_ICSC_C31_C32 0x0e8b
|
#define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2
|
#define mmCM1_CM_ICSC_C33_C34 0x0e8c
|
#define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2
|
#define mmCM1_CM_ICSC_B_C11_C12 0x0e8d
|
#define mmCM1_CM_ICSC_B_C11_C12_BASE_IDX 2
|
#define mmCM1_CM_ICSC_B_C13_C14 0x0e8e
|
#define mmCM1_CM_ICSC_B_C13_C14_BASE_IDX 2
|
#define mmCM1_CM_ICSC_B_C21_C22 0x0e8f
|
#define mmCM1_CM_ICSC_B_C21_C22_BASE_IDX 2
|
#define mmCM1_CM_ICSC_B_C23_C24 0x0e90
|
#define mmCM1_CM_ICSC_B_C23_C24_BASE_IDX 2
|
#define mmCM1_CM_ICSC_B_C31_C32 0x0e91
|
#define mmCM1_CM_ICSC_B_C31_C32_BASE_IDX 2
|
#define mmCM1_CM_ICSC_B_C33_C34 0x0e92
|
#define mmCM1_CM_ICSC_B_C33_C34_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0e93
|
#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0e94
|
#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0e95
|
#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0e96
|
#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0e97
|
#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0e98
|
#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0e99
|
#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_B_C11_C12 0x0e9a
|
#define mmCM1_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_B_C13_C14 0x0e9b
|
#define mmCM1_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_B_C21_C22 0x0e9c
|
#define mmCM1_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_B_C23_C24 0x0e9d
|
#define mmCM1_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_B_C31_C32 0x0e9e
|
#define mmCM1_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
|
#define mmCM1_CM_GAMUT_REMAP_B_C33_C34 0x0e9f
|
#define mmCM1_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
|
#define mmCM1_CM_BIAS_CR_R 0x0ea0
|
#define mmCM1_CM_BIAS_CR_R_BASE_IDX 2
|
#define mmCM1_CM_BIAS_Y_G_CB_B 0x0ea1
|
#define mmCM1_CM_BIAS_Y_G_CB_B_BASE_IDX 2
|
#define mmCM1_CM_DGAM_CONTROL 0x0ea2
|
#define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2
|
#define mmCM1_CM_DGAM_LUT_INDEX 0x0ea3
|
#define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM1_CM_DGAM_LUT_DATA 0x0ea4
|
#define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ea5
|
#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0ea6
|
#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0ea7
|
#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0ea8
|
#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0ea9
|
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eaa
|
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0eab
|
#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0eac
|
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0ead
|
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0eae
|
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0eaf
|
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0eb0
|
#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0eb1
|
#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0eb2
|
#define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0eb3
|
#define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0eb4
|
#define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0eb5
|
#define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0eb6
|
#define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0eb7
|
#define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0eb8
|
#define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0eb9
|
#define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0eba
|
#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0ebb
|
#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0ebc
|
#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0ebd
|
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0ebe
|
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0ebf
|
#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0ec0
|
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0ec1
|
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0ec2
|
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0ec3
|
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0ec4
|
#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0ec5
|
#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0ec6
|
#define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0ec7
|
#define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0ec8
|
#define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0ec9
|
#define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0eca
|
#define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0ecb
|
#define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0ecc
|
#define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0ecd
|
#define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_CONTROL 0x0ece
|
#define mmCM1_CM_BLNDGAM_CONTROL_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_LUT_INDEX 0x0ecf
|
#define mmCM1_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_LUT_DATA 0x0ed0
|
#define mmCM1_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x0ed1
|
#define mmCM1_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B 0x0ed2
|
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G 0x0ed3
|
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R 0x0ed4
|
#define mmCM1_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x0ed5
|
#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x0ed6
|
#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x0ed7
|
#define mmCM1_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B 0x0ed8
|
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B 0x0ed9
|
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G 0x0eda
|
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G 0x0edb
|
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R 0x0edc
|
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R 0x0edd
|
#define mmCM1_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1 0x0ede
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3 0x0edf
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5 0x0ee0
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7 0x0ee1
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9 0x0ee2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11 0x0ee3
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13 0x0ee4
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15 0x0ee5
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17 0x0ee6
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19 0x0ee7
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21 0x0ee8
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23 0x0ee9
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25 0x0eea
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27 0x0eeb
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29 0x0eec
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31 0x0eed
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33 0x0eee
|
#define mmCM1_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B 0x0eef
|
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G 0x0ef0
|
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R 0x0ef1
|
#define mmCM1_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x0ef2
|
#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x0ef3
|
#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x0ef4
|
#define mmCM1_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B 0x0ef5
|
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B 0x0ef6
|
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G 0x0ef7
|
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G 0x0ef8
|
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R 0x0ef9
|
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R 0x0efa
|
#define mmCM1_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1 0x0efb
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3 0x0efc
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5 0x0efd
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7 0x0efe
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9 0x0eff
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11 0x0f00
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13 0x0f01
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15 0x0f02
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17 0x0f03
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19 0x0f04
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21 0x0f05
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23 0x0f06
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25 0x0f07
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27 0x0f08
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29 0x0f09
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31 0x0f0a
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33 0x0f0b
|
#define mmCM1_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM1_CM_HDR_MULT_COEF 0x0f0c
|
#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2
|
#define mmCM1_CM_MEM_PWR_CTRL 0x0f0d
|
#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCM1_CM_MEM_PWR_STATUS 0x0f0e
|
#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCM1_CM_DEALPHA 0x0f10
|
#define mmCM1_CM_DEALPHA_BASE_IDX 2
|
#define mmCM1_CM_COEF_FORMAT 0x0f11
|
#define mmCM1_CM_COEF_FORMAT_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_CONTROL 0x0f12
|
#define mmCM1_CM_SHAPER_CONTROL_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_OFFSET_R 0x0f13
|
#define mmCM1_CM_SHAPER_OFFSET_R_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_OFFSET_G 0x0f14
|
#define mmCM1_CM_SHAPER_OFFSET_G_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_OFFSET_B 0x0f15
|
#define mmCM1_CM_SHAPER_OFFSET_B_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_SCALE_R 0x0f16
|
#define mmCM1_CM_SHAPER_SCALE_R_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_SCALE_G_B 0x0f17
|
#define mmCM1_CM_SHAPER_SCALE_G_B_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_LUT_INDEX 0x0f18
|
#define mmCM1_CM_SHAPER_LUT_INDEX_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_LUT_DATA 0x0f19
|
#define mmCM1_CM_SHAPER_LUT_DATA_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK 0x0f1a
|
#define mmCM1_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B 0x0f1b
|
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G 0x0f1c
|
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R 0x0f1d
|
#define mmCM1_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B 0x0f1e
|
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G 0x0f1f
|
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R 0x0f20
|
#define mmCM1_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_0_1 0x0f21
|
#define mmCM1_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_2_3 0x0f22
|
#define mmCM1_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_4_5 0x0f23
|
#define mmCM1_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_6_7 0x0f24
|
#define mmCM1_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_8_9 0x0f25
|
#define mmCM1_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_10_11 0x0f26
|
#define mmCM1_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_12_13 0x0f27
|
#define mmCM1_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_14_15 0x0f28
|
#define mmCM1_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_16_17 0x0f29
|
#define mmCM1_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_18_19 0x0f2a
|
#define mmCM1_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_20_21 0x0f2b
|
#define mmCM1_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_22_23 0x0f2c
|
#define mmCM1_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_24_25 0x0f2d
|
#define mmCM1_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_26_27 0x0f2e
|
#define mmCM1_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_28_29 0x0f2f
|
#define mmCM1_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_30_31 0x0f30
|
#define mmCM1_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMA_REGION_32_33 0x0f31
|
#define mmCM1_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B 0x0f32
|
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G 0x0f33
|
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R 0x0f34
|
#define mmCM1_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B 0x0f35
|
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G 0x0f36
|
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R 0x0f37
|
#define mmCM1_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_0_1 0x0f38
|
#define mmCM1_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_2_3 0x0f39
|
#define mmCM1_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_4_5 0x0f3a
|
#define mmCM1_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_6_7 0x0f3b
|
#define mmCM1_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_8_9 0x0f3c
|
#define mmCM1_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_10_11 0x0f3d
|
#define mmCM1_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_12_13 0x0f3e
|
#define mmCM1_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_14_15 0x0f3f
|
#define mmCM1_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_16_17 0x0f40
|
#define mmCM1_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_18_19 0x0f41
|
#define mmCM1_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_20_21 0x0f42
|
#define mmCM1_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_22_23 0x0f43
|
#define mmCM1_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_24_25 0x0f44
|
#define mmCM1_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_26_27 0x0f45
|
#define mmCM1_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_28_29 0x0f46
|
#define mmCM1_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_30_31 0x0f47
|
#define mmCM1_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM1_CM_SHAPER_RAMB_REGION_32_33 0x0f48
|
#define mmCM1_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM1_CM_MEM_PWR_CTRL2 0x0f49
|
#define mmCM1_CM_MEM_PWR_CTRL2_BASE_IDX 2
|
#define mmCM1_CM_MEM_PWR_STATUS2 0x0f4a
|
#define mmCM1_CM_MEM_PWR_STATUS2_BASE_IDX 2
|
#define mmCM1_CM_3DLUT_MODE 0x0f4b
|
#define mmCM1_CM_3DLUT_MODE_BASE_IDX 2
|
#define mmCM1_CM_3DLUT_INDEX 0x0f4c
|
#define mmCM1_CM_3DLUT_INDEX_BASE_IDX 2
|
#define mmCM1_CM_3DLUT_DATA 0x0f4d
|
#define mmCM1_CM_3DLUT_DATA_BASE_IDX 2
|
#define mmCM1_CM_3DLUT_DATA_30BIT 0x0f4e
|
#define mmCM1_CM_3DLUT_DATA_30BIT_BASE_IDX 2
|
#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL 0x0f4f
|
#define mmCM1_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
|
#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR 0x0f50
|
#define mmCM1_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
|
#define mmCM1_CM_3DLUT_OUT_OFFSET_R 0x0f51
|
#define mmCM1_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
|
#define mmCM1_CM_3DLUT_OUT_OFFSET_G 0x0f52
|
#define mmCM1_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
|
#define mmCM1_CM_3DLUT_OUT_OFFSET_B 0x0f53
|
#define mmCM1_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
|
#define mmCM1_CM_TEST_DEBUG_INDEX 0x0f54
|
#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmCM1_CM_TEST_DEBUG_DATA 0x0f55
|
#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x3e3c
|
#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x0f8f
|
#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x0f90
|
#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x0f91
|
#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON14_PERFMON_CNTL 0x0f92
|
#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON14_PERFMON_CNTL2 0x0f93
|
#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x0f94
|
#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x0f95
|
#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON14_PERFMON_HI 0x0f96
|
#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON14_PERFMON_LOW 0x0f97
|
#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
|
// base address: 0xb58
|
#define mmDPP_TOP2_DPP_CONTROL 0x0f9b
|
#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2
|
#define mmDPP_TOP2_DPP_SOFT_RESET 0x0f9c
|
#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2
|
#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0f9d
|
#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2
|
#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0f9e
|
#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2
|
#define mmDPP_TOP2_DPP_CRC_CTRL 0x0f9f
|
#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2
|
#define mmDPP_TOP2_HOST_READ_CONTROL 0x0fa0
|
#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
|
// base address: 0xb58
|
#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0fa5
|
#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
|
#define mmCNVC_CFG2_FORMAT_CONTROL 0x0fa6
|
#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG2_FCNV_FP_BIAS_R 0x0fa7
|
#define mmCNVC_CFG2_FCNV_FP_BIAS_R_BASE_IDX 2
|
#define mmCNVC_CFG2_FCNV_FP_BIAS_G 0x0fa8
|
#define mmCNVC_CFG2_FCNV_FP_BIAS_G_BASE_IDX 2
|
#define mmCNVC_CFG2_FCNV_FP_BIAS_B 0x0fa9
|
#define mmCNVC_CFG2_FCNV_FP_BIAS_B_BASE_IDX 2
|
#define mmCNVC_CFG2_FCNV_FP_SCALE_R 0x0faa
|
#define mmCNVC_CFG2_FCNV_FP_SCALE_R_BASE_IDX 2
|
#define mmCNVC_CFG2_FCNV_FP_SCALE_G 0x0fab
|
#define mmCNVC_CFG2_FCNV_FP_SCALE_G_BASE_IDX 2
|
#define mmCNVC_CFG2_FCNV_FP_SCALE_B 0x0fac
|
#define mmCNVC_CFG2_FCNV_FP_SCALE_B_BASE_IDX 2
|
#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0fad
|
#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0fae
|
#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2
|
#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0faf
|
#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2
|
#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0fb0
|
#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2
|
#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0fb1
|
#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2
|
#define mmCNVC_CFG2_ALPHA_2BIT_LUT 0x0fb3
|
#define mmCNVC_CFG2_ALPHA_2BIT_LUT_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
|
// base address: 0xb58
|
#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0fb6
|
#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2
|
#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0fb7
|
#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2
|
#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0fb8
|
#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2
|
#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0fb9
|
#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
|
// base address: 0xb58
|
#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0fc0
|
#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
|
#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0fc1
|
#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmDSCL2_SCL_MODE 0x0fc2
|
#define mmDSCL2_SCL_MODE_BASE_IDX 2
|
#define mmDSCL2_SCL_TAP_CONTROL 0x0fc3
|
#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL2_DSCL_CONTROL 0x0fc4
|
#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2
|
#define mmDSCL2_DSCL_2TAP_CONTROL 0x0fc5
|
#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0fc6
|
#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
|
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0fc7
|
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0fc8
|
#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fc9
|
#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
|
#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0fca
|
#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
|
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0fcb
|
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0fcc
|
#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0fcd
|
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
|
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fce
|
#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
|
#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0fcf
|
#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
|
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0fd0
|
#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
|
#define mmDSCL2_SCL_BLACK_OFFSET 0x0fd1
|
#define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2
|
#define mmDSCL2_DSCL_UPDATE 0x0fd2
|
#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2
|
#define mmDSCL2_DSCL_AUTOCAL 0x0fd3
|
#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2
|
#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fd4
|
#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
|
#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fd5
|
#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
|
#define mmDSCL2_OTG_H_BLANK 0x0fd6
|
#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2
|
#define mmDSCL2_OTG_V_BLANK 0x0fd7
|
#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2
|
#define mmDSCL2_RECOUT_START 0x0fd8
|
#define mmDSCL2_RECOUT_START_BASE_IDX 2
|
#define mmDSCL2_RECOUT_SIZE 0x0fd9
|
#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2
|
#define mmDSCL2_MPC_SIZE 0x0fda
|
#define mmDSCL2_MPC_SIZE_BASE_IDX 2
|
#define mmDSCL2_LB_DATA_FORMAT 0x0fdb
|
#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2
|
#define mmDSCL2_LB_MEMORY_CTRL 0x0fdc
|
#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2
|
#define mmDSCL2_LB_V_COUNTER 0x0fdd
|
#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2
|
#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0fde
|
#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0fdf
|
#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDSCL2_OBUF_CONTROL 0x0fe0
|
#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2
|
#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0fe1
|
#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
|
// base address: 0xb58
|
#define mmCM2_CM_CONTROL 0x0ff0
|
#define mmCM2_CM_CONTROL_BASE_IDX 2
|
#define mmCM2_CM_ICSC_CONTROL 0x0ff1
|
#define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2
|
#define mmCM2_CM_ICSC_C11_C12 0x0ff2
|
#define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2
|
#define mmCM2_CM_ICSC_C13_C14 0x0ff3
|
#define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2
|
#define mmCM2_CM_ICSC_C21_C22 0x0ff4
|
#define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2
|
#define mmCM2_CM_ICSC_C23_C24 0x0ff5
|
#define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2
|
#define mmCM2_CM_ICSC_C31_C32 0x0ff6
|
#define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2
|
#define mmCM2_CM_ICSC_C33_C34 0x0ff7
|
#define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2
|
#define mmCM2_CM_ICSC_B_C11_C12 0x0ff8
|
#define mmCM2_CM_ICSC_B_C11_C12_BASE_IDX 2
|
#define mmCM2_CM_ICSC_B_C13_C14 0x0ff9
|
#define mmCM2_CM_ICSC_B_C13_C14_BASE_IDX 2
|
#define mmCM2_CM_ICSC_B_C21_C22 0x0ffa
|
#define mmCM2_CM_ICSC_B_C21_C22_BASE_IDX 2
|
#define mmCM2_CM_ICSC_B_C23_C24 0x0ffb
|
#define mmCM2_CM_ICSC_B_C23_C24_BASE_IDX 2
|
#define mmCM2_CM_ICSC_B_C31_C32 0x0ffc
|
#define mmCM2_CM_ICSC_B_C31_C32_BASE_IDX 2
|
#define mmCM2_CM_ICSC_B_C33_C34 0x0ffd
|
#define mmCM2_CM_ICSC_B_C33_C34_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ffe
|
#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0fff
|
#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x1000
|
#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x1001
|
#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x1002
|
#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x1003
|
#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x1004
|
#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_B_C11_C12 0x1005
|
#define mmCM2_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_B_C13_C14 0x1006
|
#define mmCM2_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_B_C21_C22 0x1007
|
#define mmCM2_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_B_C23_C24 0x1008
|
#define mmCM2_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_B_C31_C32 0x1009
|
#define mmCM2_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
|
#define mmCM2_CM_GAMUT_REMAP_B_C33_C34 0x100a
|
#define mmCM2_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
|
#define mmCM2_CM_BIAS_CR_R 0x100b
|
#define mmCM2_CM_BIAS_CR_R_BASE_IDX 2
|
#define mmCM2_CM_BIAS_Y_G_CB_B 0x100c
|
#define mmCM2_CM_BIAS_Y_G_CB_B_BASE_IDX 2
|
#define mmCM2_CM_DGAM_CONTROL 0x100d
|
#define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2
|
#define mmCM2_CM_DGAM_LUT_INDEX 0x100e
|
#define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM2_CM_DGAM_LUT_DATA 0x100f
|
#define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x1010
|
#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x1011
|
#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x1012
|
#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x1013
|
#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1014
|
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1015
|
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1016
|
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x1017
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x1018
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x1019
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x101a
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x101b
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x101c
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x101d
|
#define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x101e
|
#define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x101f
|
#define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x1020
|
#define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x1021
|
#define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x1022
|
#define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x1023
|
#define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x1024
|
#define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x1025
|
#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x1026
|
#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x1027
|
#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1028
|
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1029
|
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102a
|
#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x102b
|
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x102c
|
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x102d
|
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x102e
|
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x102f
|
#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x1030
|
#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x1031
|
#define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x1032
|
#define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x1033
|
#define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x1034
|
#define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x1035
|
#define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x1036
|
#define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x1037
|
#define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x1038
|
#define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_CONTROL 0x1039
|
#define mmCM2_CM_BLNDGAM_CONTROL_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_LUT_INDEX 0x103a
|
#define mmCM2_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_LUT_DATA 0x103b
|
#define mmCM2_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x103c
|
#define mmCM2_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B 0x103d
|
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G 0x103e
|
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R 0x103f
|
#define mmCM2_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x1040
|
#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x1041
|
#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x1042
|
#define mmCM2_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B 0x1043
|
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B 0x1044
|
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G 0x1045
|
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G 0x1046
|
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R 0x1047
|
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R 0x1048
|
#define mmCM2_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1 0x1049
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3 0x104a
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5 0x104b
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7 0x104c
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9 0x104d
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11 0x104e
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13 0x104f
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15 0x1050
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17 0x1051
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19 0x1052
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21 0x1053
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23 0x1054
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25 0x1055
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27 0x1056
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29 0x1057
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31 0x1058
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33 0x1059
|
#define mmCM2_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B 0x105a
|
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G 0x105b
|
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R 0x105c
|
#define mmCM2_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x105d
|
#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x105e
|
#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x105f
|
#define mmCM2_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B 0x1060
|
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B 0x1061
|
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G 0x1062
|
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G 0x1063
|
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R 0x1064
|
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R 0x1065
|
#define mmCM2_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1 0x1066
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3 0x1067
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5 0x1068
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7 0x1069
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9 0x106a
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11 0x106b
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13 0x106c
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15 0x106d
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17 0x106e
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19 0x106f
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21 0x1070
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23 0x1071
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25 0x1072
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27 0x1073
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29 0x1074
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31 0x1075
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33 0x1076
|
#define mmCM2_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM2_CM_HDR_MULT_COEF 0x1077
|
#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2
|
#define mmCM2_CM_MEM_PWR_CTRL 0x1078
|
#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCM2_CM_MEM_PWR_STATUS 0x1079
|
#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCM2_CM_DEALPHA 0x107b
|
#define mmCM2_CM_DEALPHA_BASE_IDX 2
|
#define mmCM2_CM_COEF_FORMAT 0x107c
|
#define mmCM2_CM_COEF_FORMAT_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_CONTROL 0x107d
|
#define mmCM2_CM_SHAPER_CONTROL_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_OFFSET_R 0x107e
|
#define mmCM2_CM_SHAPER_OFFSET_R_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_OFFSET_G 0x107f
|
#define mmCM2_CM_SHAPER_OFFSET_G_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_OFFSET_B 0x1080
|
#define mmCM2_CM_SHAPER_OFFSET_B_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_SCALE_R 0x1081
|
#define mmCM2_CM_SHAPER_SCALE_R_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_SCALE_G_B 0x1082
|
#define mmCM2_CM_SHAPER_SCALE_G_B_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_LUT_INDEX 0x1083
|
#define mmCM2_CM_SHAPER_LUT_INDEX_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_LUT_DATA 0x1084
|
#define mmCM2_CM_SHAPER_LUT_DATA_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK 0x1085
|
#define mmCM2_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B 0x1086
|
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G 0x1087
|
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R 0x1088
|
#define mmCM2_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B 0x1089
|
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G 0x108a
|
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R 0x108b
|
#define mmCM2_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_0_1 0x108c
|
#define mmCM2_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_2_3 0x108d
|
#define mmCM2_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_4_5 0x108e
|
#define mmCM2_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_6_7 0x108f
|
#define mmCM2_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_8_9 0x1090
|
#define mmCM2_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_10_11 0x1091
|
#define mmCM2_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_12_13 0x1092
|
#define mmCM2_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_14_15 0x1093
|
#define mmCM2_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_16_17 0x1094
|
#define mmCM2_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_18_19 0x1095
|
#define mmCM2_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_20_21 0x1096
|
#define mmCM2_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_22_23 0x1097
|
#define mmCM2_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_24_25 0x1098
|
#define mmCM2_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_26_27 0x1099
|
#define mmCM2_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_28_29 0x109a
|
#define mmCM2_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_30_31 0x109b
|
#define mmCM2_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMA_REGION_32_33 0x109c
|
#define mmCM2_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B 0x109d
|
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G 0x109e
|
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R 0x109f
|
#define mmCM2_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B 0x10a0
|
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G 0x10a1
|
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R 0x10a2
|
#define mmCM2_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_0_1 0x10a3
|
#define mmCM2_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_2_3 0x10a4
|
#define mmCM2_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_4_5 0x10a5
|
#define mmCM2_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_6_7 0x10a6
|
#define mmCM2_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_8_9 0x10a7
|
#define mmCM2_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_10_11 0x10a8
|
#define mmCM2_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_12_13 0x10a9
|
#define mmCM2_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_14_15 0x10aa
|
#define mmCM2_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_16_17 0x10ab
|
#define mmCM2_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_18_19 0x10ac
|
#define mmCM2_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_20_21 0x10ad
|
#define mmCM2_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_22_23 0x10ae
|
#define mmCM2_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_24_25 0x10af
|
#define mmCM2_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_26_27 0x10b0
|
#define mmCM2_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_28_29 0x10b1
|
#define mmCM2_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_30_31 0x10b2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM2_CM_SHAPER_RAMB_REGION_32_33 0x10b3
|
#define mmCM2_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM2_CM_MEM_PWR_CTRL2 0x10b4
|
#define mmCM2_CM_MEM_PWR_CTRL2_BASE_IDX 2
|
#define mmCM2_CM_MEM_PWR_STATUS2 0x10b5
|
#define mmCM2_CM_MEM_PWR_STATUS2_BASE_IDX 2
|
#define mmCM2_CM_3DLUT_MODE 0x10b6
|
#define mmCM2_CM_3DLUT_MODE_BASE_IDX 2
|
#define mmCM2_CM_3DLUT_INDEX 0x10b7
|
#define mmCM2_CM_3DLUT_INDEX_BASE_IDX 2
|
#define mmCM2_CM_3DLUT_DATA 0x10b8
|
#define mmCM2_CM_3DLUT_DATA_BASE_IDX 2
|
#define mmCM2_CM_3DLUT_DATA_30BIT 0x10b9
|
#define mmCM2_CM_3DLUT_DATA_30BIT_BASE_IDX 2
|
#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL 0x10ba
|
#define mmCM2_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
|
#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR 0x10bb
|
#define mmCM2_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
|
#define mmCM2_CM_3DLUT_OUT_OFFSET_R 0x10bc
|
#define mmCM2_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
|
#define mmCM2_CM_3DLUT_OUT_OFFSET_G 0x10bd
|
#define mmCM2_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
|
#define mmCM2_CM_3DLUT_OUT_OFFSET_B 0x10be
|
#define mmCM2_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
|
#define mmCM2_CM_TEST_DEBUG_INDEX 0x10bf
|
#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmCM2_CM_TEST_DEBUG_DATA 0x10c0
|
#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x43e8
|
#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x10fa
|
#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x10fb
|
#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x10fc
|
#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFMON_CNTL 0x10fd
|
#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFMON_CNTL2 0x10fe
|
#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x10ff
|
#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x1100
|
#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFMON_HI 0x1101
|
#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFMON_LOW 0x1102
|
#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
|
// base address: 0x1104
|
#define mmDPP_TOP3_DPP_CONTROL 0x1106
|
#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2
|
#define mmDPP_TOP3_DPP_SOFT_RESET 0x1107
|
#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2
|
#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x1108
|
#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2
|
#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x1109
|
#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2
|
#define mmDPP_TOP3_DPP_CRC_CTRL 0x110a
|
#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2
|
#define mmDPP_TOP3_HOST_READ_CONTROL 0x110b
|
#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
|
// base address: 0x1104
|
#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x1110
|
#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
|
#define mmCNVC_CFG3_FORMAT_CONTROL 0x1111
|
#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG3_FCNV_FP_BIAS_R 0x1112
|
#define mmCNVC_CFG3_FCNV_FP_BIAS_R_BASE_IDX 2
|
#define mmCNVC_CFG3_FCNV_FP_BIAS_G 0x1113
|
#define mmCNVC_CFG3_FCNV_FP_BIAS_G_BASE_IDX 2
|
#define mmCNVC_CFG3_FCNV_FP_BIAS_B 0x1114
|
#define mmCNVC_CFG3_FCNV_FP_BIAS_B_BASE_IDX 2
|
#define mmCNVC_CFG3_FCNV_FP_SCALE_R 0x1115
|
#define mmCNVC_CFG3_FCNV_FP_SCALE_R_BASE_IDX 2
|
#define mmCNVC_CFG3_FCNV_FP_SCALE_G 0x1116
|
#define mmCNVC_CFG3_FCNV_FP_SCALE_G_BASE_IDX 2
|
#define mmCNVC_CFG3_FCNV_FP_SCALE_B 0x1117
|
#define mmCNVC_CFG3_FCNV_FP_SCALE_B_BASE_IDX 2
|
#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x1118
|
#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x1119
|
#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2
|
#define mmCNVC_CFG3_COLOR_KEYER_RED 0x111a
|
#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2
|
#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x111b
|
#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2
|
#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x111c
|
#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2
|
#define mmCNVC_CFG3_ALPHA_2BIT_LUT 0x111e
|
#define mmCNVC_CFG3_ALPHA_2BIT_LUT_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
|
// base address: 0x1104
|
#define mmCNVC_CUR3_CURSOR0_CONTROL 0x1121
|
#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2
|
#define mmCNVC_CUR3_CURSOR0_COLOR0 0x1122
|
#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2
|
#define mmCNVC_CUR3_CURSOR0_COLOR1 0x1123
|
#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2
|
#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x1124
|
#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
|
// base address: 0x1104
|
#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x112b
|
#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
|
#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x112c
|
#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmDSCL3_SCL_MODE 0x112d
|
#define mmDSCL3_SCL_MODE_BASE_IDX 2
|
#define mmDSCL3_SCL_TAP_CONTROL 0x112e
|
#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL3_DSCL_CONTROL 0x112f
|
#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2
|
#define mmDSCL3_DSCL_2TAP_CONTROL 0x1130
|
#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x1131
|
#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
|
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x1132
|
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x1133
|
#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x1134
|
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
|
#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x1135
|
#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
|
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x1136
|
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL3_SCL_VERT_FILTER_INIT 0x1137
|
#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x1138
|
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
|
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x1139
|
#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
|
#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x113a
|
#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
|
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x113b
|
#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
|
#define mmDSCL3_SCL_BLACK_OFFSET 0x113c
|
#define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2
|
#define mmDSCL3_DSCL_UPDATE 0x113d
|
#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2
|
#define mmDSCL3_DSCL_AUTOCAL 0x113e
|
#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2
|
#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x113f
|
#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
|
#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x1140
|
#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
|
#define mmDSCL3_OTG_H_BLANK 0x1141
|
#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2
|
#define mmDSCL3_OTG_V_BLANK 0x1142
|
#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2
|
#define mmDSCL3_RECOUT_START 0x1143
|
#define mmDSCL3_RECOUT_START_BASE_IDX 2
|
#define mmDSCL3_RECOUT_SIZE 0x1144
|
#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2
|
#define mmDSCL3_MPC_SIZE 0x1145
|
#define mmDSCL3_MPC_SIZE_BASE_IDX 2
|
#define mmDSCL3_LB_DATA_FORMAT 0x1146
|
#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2
|
#define mmDSCL3_LB_MEMORY_CTRL 0x1147
|
#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2
|
#define mmDSCL3_LB_V_COUNTER 0x1148
|
#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2
|
#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x1149
|
#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x114a
|
#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDSCL3_OBUF_CONTROL 0x114b
|
#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2
|
#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x114c
|
#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
|
// base address: 0x1104
|
#define mmCM3_CM_CONTROL 0x115b
|
#define mmCM3_CM_CONTROL_BASE_IDX 2
|
#define mmCM3_CM_ICSC_CONTROL 0x115c
|
#define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2
|
#define mmCM3_CM_ICSC_C11_C12 0x115d
|
#define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2
|
#define mmCM3_CM_ICSC_C13_C14 0x115e
|
#define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2
|
#define mmCM3_CM_ICSC_C21_C22 0x115f
|
#define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2
|
#define mmCM3_CM_ICSC_C23_C24 0x1160
|
#define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2
|
#define mmCM3_CM_ICSC_C31_C32 0x1161
|
#define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2
|
#define mmCM3_CM_ICSC_C33_C34 0x1162
|
#define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2
|
#define mmCM3_CM_ICSC_B_C11_C12 0x1163
|
#define mmCM3_CM_ICSC_B_C11_C12_BASE_IDX 2
|
#define mmCM3_CM_ICSC_B_C13_C14 0x1164
|
#define mmCM3_CM_ICSC_B_C13_C14_BASE_IDX 2
|
#define mmCM3_CM_ICSC_B_C21_C22 0x1165
|
#define mmCM3_CM_ICSC_B_C21_C22_BASE_IDX 2
|
#define mmCM3_CM_ICSC_B_C23_C24 0x1166
|
#define mmCM3_CM_ICSC_B_C23_C24_BASE_IDX 2
|
#define mmCM3_CM_ICSC_B_C31_C32 0x1167
|
#define mmCM3_CM_ICSC_B_C31_C32_BASE_IDX 2
|
#define mmCM3_CM_ICSC_B_C33_C34 0x1168
|
#define mmCM3_CM_ICSC_B_C33_C34_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1169
|
#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x116a
|
#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x116b
|
#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x116c
|
#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x116d
|
#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x116e
|
#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x116f
|
#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_B_C11_C12 0x1170
|
#define mmCM3_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_B_C13_C14 0x1171
|
#define mmCM3_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_B_C21_C22 0x1172
|
#define mmCM3_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_B_C23_C24 0x1173
|
#define mmCM3_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_B_C31_C32 0x1174
|
#define mmCM3_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
|
#define mmCM3_CM_GAMUT_REMAP_B_C33_C34 0x1175
|
#define mmCM3_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
|
#define mmCM3_CM_BIAS_CR_R 0x1176
|
#define mmCM3_CM_BIAS_CR_R_BASE_IDX 2
|
#define mmCM3_CM_BIAS_Y_G_CB_B 0x1177
|
#define mmCM3_CM_BIAS_Y_G_CB_B_BASE_IDX 2
|
#define mmCM3_CM_DGAM_CONTROL 0x1178
|
#define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2
|
#define mmCM3_CM_DGAM_LUT_INDEX 0x1179
|
#define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM3_CM_DGAM_LUT_DATA 0x117a
|
#define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x117b
|
#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x117c
|
#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x117d
|
#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x117e
|
#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x117f
|
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x1180
|
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x1181
|
#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x1182
|
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x1183
|
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x1184
|
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x1185
|
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1186
|
#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1187
|
#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1188
|
#define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1189
|
#define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x118a
|
#define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x118b
|
#define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x118c
|
#define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x118d
|
#define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x118e
|
#define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x118f
|
#define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x1190
|
#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x1191
|
#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x1192
|
#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x1193
|
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x1194
|
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x1195
|
#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1196
|
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1197
|
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1198
|
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1199
|
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x119a
|
#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x119b
|
#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x119c
|
#define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x119d
|
#define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x119e
|
#define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x119f
|
#define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x11a0
|
#define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x11a1
|
#define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x11a2
|
#define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x11a3
|
#define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_CONTROL 0x11a4
|
#define mmCM3_CM_BLNDGAM_CONTROL_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_LUT_INDEX 0x11a5
|
#define mmCM3_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_LUT_DATA 0x11a6
|
#define mmCM3_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x11a7
|
#define mmCM3_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B 0x11a8
|
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G 0x11a9
|
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R 0x11aa
|
#define mmCM3_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x11ab
|
#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x11ac
|
#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x11ad
|
#define mmCM3_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B 0x11ae
|
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B 0x11af
|
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G 0x11b0
|
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G 0x11b1
|
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R 0x11b2
|
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R 0x11b3
|
#define mmCM3_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1 0x11b4
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3 0x11b5
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5 0x11b6
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7 0x11b7
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9 0x11b8
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11 0x11b9
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13 0x11ba
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15 0x11bb
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17 0x11bc
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19 0x11bd
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21 0x11be
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23 0x11bf
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25 0x11c0
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27 0x11c1
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29 0x11c2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31 0x11c3
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33 0x11c4
|
#define mmCM3_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B 0x11c5
|
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G 0x11c6
|
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R 0x11c7
|
#define mmCM3_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x11c8
|
#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x11c9
|
#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x11ca
|
#define mmCM3_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B 0x11cb
|
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B 0x11cc
|
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G 0x11cd
|
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G 0x11ce
|
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R 0x11cf
|
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R 0x11d0
|
#define mmCM3_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1 0x11d1
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3 0x11d2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5 0x11d3
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7 0x11d4
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9 0x11d5
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11 0x11d6
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13 0x11d7
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15 0x11d8
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17 0x11d9
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19 0x11da
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21 0x11db
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23 0x11dc
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25 0x11dd
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27 0x11de
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29 0x11df
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31 0x11e0
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33 0x11e1
|
#define mmCM3_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM3_CM_HDR_MULT_COEF 0x11e2
|
#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2
|
#define mmCM3_CM_MEM_PWR_CTRL 0x11e3
|
#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCM3_CM_MEM_PWR_STATUS 0x11e4
|
#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCM3_CM_DEALPHA 0x11e6
|
#define mmCM3_CM_DEALPHA_BASE_IDX 2
|
#define mmCM3_CM_COEF_FORMAT 0x11e7
|
#define mmCM3_CM_COEF_FORMAT_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_CONTROL 0x11e8
|
#define mmCM3_CM_SHAPER_CONTROL_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_OFFSET_R 0x11e9
|
#define mmCM3_CM_SHAPER_OFFSET_R_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_OFFSET_G 0x11ea
|
#define mmCM3_CM_SHAPER_OFFSET_G_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_OFFSET_B 0x11eb
|
#define mmCM3_CM_SHAPER_OFFSET_B_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_SCALE_R 0x11ec
|
#define mmCM3_CM_SHAPER_SCALE_R_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_SCALE_G_B 0x11ed
|
#define mmCM3_CM_SHAPER_SCALE_G_B_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_LUT_INDEX 0x11ee
|
#define mmCM3_CM_SHAPER_LUT_INDEX_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_LUT_DATA 0x11ef
|
#define mmCM3_CM_SHAPER_LUT_DATA_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK 0x11f0
|
#define mmCM3_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B 0x11f1
|
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G 0x11f2
|
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R 0x11f3
|
#define mmCM3_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B 0x11f4
|
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G 0x11f5
|
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R 0x11f6
|
#define mmCM3_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_0_1 0x11f7
|
#define mmCM3_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_2_3 0x11f8
|
#define mmCM3_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_4_5 0x11f9
|
#define mmCM3_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_6_7 0x11fa
|
#define mmCM3_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_8_9 0x11fb
|
#define mmCM3_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_10_11 0x11fc
|
#define mmCM3_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_12_13 0x11fd
|
#define mmCM3_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_14_15 0x11fe
|
#define mmCM3_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_16_17 0x11ff
|
#define mmCM3_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_18_19 0x1200
|
#define mmCM3_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_20_21 0x1201
|
#define mmCM3_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_22_23 0x1202
|
#define mmCM3_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_24_25 0x1203
|
#define mmCM3_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_26_27 0x1204
|
#define mmCM3_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_28_29 0x1205
|
#define mmCM3_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_30_31 0x1206
|
#define mmCM3_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMA_REGION_32_33 0x1207
|
#define mmCM3_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B 0x1208
|
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G 0x1209
|
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R 0x120a
|
#define mmCM3_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B 0x120b
|
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G 0x120c
|
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R 0x120d
|
#define mmCM3_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_0_1 0x120e
|
#define mmCM3_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_2_3 0x120f
|
#define mmCM3_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_4_5 0x1210
|
#define mmCM3_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_6_7 0x1211
|
#define mmCM3_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_8_9 0x1212
|
#define mmCM3_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_10_11 0x1213
|
#define mmCM3_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_12_13 0x1214
|
#define mmCM3_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_14_15 0x1215
|
#define mmCM3_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_16_17 0x1216
|
#define mmCM3_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_18_19 0x1217
|
#define mmCM3_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_20_21 0x1218
|
#define mmCM3_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_22_23 0x1219
|
#define mmCM3_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_24_25 0x121a
|
#define mmCM3_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_26_27 0x121b
|
#define mmCM3_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_28_29 0x121c
|
#define mmCM3_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_30_31 0x121d
|
#define mmCM3_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM3_CM_SHAPER_RAMB_REGION_32_33 0x121e
|
#define mmCM3_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM3_CM_MEM_PWR_CTRL2 0x121f
|
#define mmCM3_CM_MEM_PWR_CTRL2_BASE_IDX 2
|
#define mmCM3_CM_MEM_PWR_STATUS2 0x1220
|
#define mmCM3_CM_MEM_PWR_STATUS2_BASE_IDX 2
|
#define mmCM3_CM_3DLUT_MODE 0x1221
|
#define mmCM3_CM_3DLUT_MODE_BASE_IDX 2
|
#define mmCM3_CM_3DLUT_INDEX 0x1222
|
#define mmCM3_CM_3DLUT_INDEX_BASE_IDX 2
|
#define mmCM3_CM_3DLUT_DATA 0x1223
|
#define mmCM3_CM_3DLUT_DATA_BASE_IDX 2
|
#define mmCM3_CM_3DLUT_DATA_30BIT 0x1224
|
#define mmCM3_CM_3DLUT_DATA_30BIT_BASE_IDX 2
|
#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL 0x1225
|
#define mmCM3_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
|
#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR 0x1226
|
#define mmCM3_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
|
#define mmCM3_CM_3DLUT_OUT_OFFSET_R 0x1227
|
#define mmCM3_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
|
#define mmCM3_CM_3DLUT_OUT_OFFSET_G 0x1228
|
#define mmCM3_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
|
#define mmCM3_CM_3DLUT_OUT_OFFSET_B 0x1229
|
#define mmCM3_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
|
#define mmCM3_CM_TEST_DEBUG_INDEX 0x122a
|
#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmCM3_CM_TEST_DEBUG_DATA 0x122b
|
#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x4994
|
#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x1265
|
#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x1266
|
#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x1267
|
#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_CNTL 0x1268
|
#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_CNTL2 0x1269
|
#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x126a
|
#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x126b
|
#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_HI 0x126c
|
#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_LOW 0x126d
|
#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc0_dispdec
|
// base address: 0x0
|
#define mmMPCC0_MPCC_TOP_SEL 0x1271
|
#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 2
|
#define mmMPCC0_MPCC_BOT_SEL 0x1272
|
#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 2
|
#define mmMPCC0_MPCC_OPP_ID 0x1273
|
#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 2
|
#define mmMPCC0_MPCC_CONTROL 0x1274
|
#define mmMPCC0_MPCC_CONTROL_BASE_IDX 2
|
#define mmMPCC0_MPCC_SM_CONTROL 0x1275
|
#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 2
|
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x1276
|
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
|
#define mmMPCC0_MPCC_TOP_GAIN 0x1277
|
#define mmMPCC0_MPCC_TOP_GAIN_BASE_IDX 2
|
#define mmMPCC0_MPCC_BOT_GAIN_INSIDE 0x1278
|
#define mmMPCC0_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
|
#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE 0x1279
|
#define mmMPCC0_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
|
#define mmMPCC0_MPCC_BG_R_CR 0x127a
|
#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 2
|
#define mmMPCC0_MPCC_BG_G_Y 0x127b
|
#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 2
|
#define mmMPCC0_MPCC_BG_B_CB 0x127c
|
#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 2
|
#define mmMPCC0_MPCC_MEM_PWR_CTRL 0x127d
|
#define mmMPCC0_MPCC_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmMPCC0_MPCC_STALL_STATUS 0x127e
|
#define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 2
|
#define mmMPCC0_MPCC_STATUS 0x127f
|
#define mmMPCC0_MPCC_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc1_dispdec
|
// base address: 0x6c
|
#define mmMPCC1_MPCC_TOP_SEL 0x128c
|
#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 2
|
#define mmMPCC1_MPCC_BOT_SEL 0x128d
|
#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 2
|
#define mmMPCC1_MPCC_OPP_ID 0x128e
|
#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 2
|
#define mmMPCC1_MPCC_CONTROL 0x128f
|
#define mmMPCC1_MPCC_CONTROL_BASE_IDX 2
|
#define mmMPCC1_MPCC_SM_CONTROL 0x1290
|
#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 2
|
#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x1291
|
#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
|
#define mmMPCC1_MPCC_TOP_GAIN 0x1292
|
#define mmMPCC1_MPCC_TOP_GAIN_BASE_IDX 2
|
#define mmMPCC1_MPCC_BOT_GAIN_INSIDE 0x1293
|
#define mmMPCC1_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
|
#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE 0x1294
|
#define mmMPCC1_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
|
#define mmMPCC1_MPCC_BG_R_CR 0x1295
|
#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 2
|
#define mmMPCC1_MPCC_BG_G_Y 0x1296
|
#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 2
|
#define mmMPCC1_MPCC_BG_B_CB 0x1297
|
#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 2
|
#define mmMPCC1_MPCC_MEM_PWR_CTRL 0x1298
|
#define mmMPCC1_MPCC_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmMPCC1_MPCC_STALL_STATUS 0x1299
|
#define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX 2
|
#define mmMPCC1_MPCC_STATUS 0x129a
|
#define mmMPCC1_MPCC_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc2_dispdec
|
// base address: 0xd8
|
#define mmMPCC2_MPCC_TOP_SEL 0x12a7
|
#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 2
|
#define mmMPCC2_MPCC_BOT_SEL 0x12a8
|
#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 2
|
#define mmMPCC2_MPCC_OPP_ID 0x12a9
|
#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 2
|
#define mmMPCC2_MPCC_CONTROL 0x12aa
|
#define mmMPCC2_MPCC_CONTROL_BASE_IDX 2
|
#define mmMPCC2_MPCC_SM_CONTROL 0x12ab
|
#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 2
|
#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x12ac
|
#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
|
#define mmMPCC2_MPCC_TOP_GAIN 0x12ad
|
#define mmMPCC2_MPCC_TOP_GAIN_BASE_IDX 2
|
#define mmMPCC2_MPCC_BOT_GAIN_INSIDE 0x12ae
|
#define mmMPCC2_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
|
#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE 0x12af
|
#define mmMPCC2_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
|
#define mmMPCC2_MPCC_BG_R_CR 0x12b0
|
#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 2
|
#define mmMPCC2_MPCC_BG_G_Y 0x12b1
|
#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 2
|
#define mmMPCC2_MPCC_BG_B_CB 0x12b2
|
#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 2
|
#define mmMPCC2_MPCC_MEM_PWR_CTRL 0x12b3
|
#define mmMPCC2_MPCC_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmMPCC2_MPCC_STALL_STATUS 0x12b4
|
#define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX 2
|
#define mmMPCC2_MPCC_STATUS 0x12b5
|
#define mmMPCC2_MPCC_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc3_dispdec
|
// base address: 0x144
|
#define mmMPCC3_MPCC_TOP_SEL 0x12c2
|
#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 2
|
#define mmMPCC3_MPCC_BOT_SEL 0x12c3
|
#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 2
|
#define mmMPCC3_MPCC_OPP_ID 0x12c4
|
#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 2
|
#define mmMPCC3_MPCC_CONTROL 0x12c5
|
#define mmMPCC3_MPCC_CONTROL_BASE_IDX 2
|
#define mmMPCC3_MPCC_SM_CONTROL 0x12c6
|
#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 2
|
#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x12c7
|
#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
|
#define mmMPCC3_MPCC_TOP_GAIN 0x12c8
|
#define mmMPCC3_MPCC_TOP_GAIN_BASE_IDX 2
|
#define mmMPCC3_MPCC_BOT_GAIN_INSIDE 0x12c9
|
#define mmMPCC3_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
|
#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE 0x12ca
|
#define mmMPCC3_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
|
#define mmMPCC3_MPCC_BG_R_CR 0x12cb
|
#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 2
|
#define mmMPCC3_MPCC_BG_G_Y 0x12cc
|
#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 2
|
#define mmMPCC3_MPCC_BG_B_CB 0x12cd
|
#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 2
|
#define mmMPCC3_MPCC_MEM_PWR_CTRL 0x12ce
|
#define mmMPCC3_MPCC_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmMPCC3_MPCC_STALL_STATUS 0x12cf
|
#define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX 2
|
#define mmMPCC3_MPCC_STATUS 0x12d0
|
#define mmMPCC3_MPCC_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc4_dispdec
|
// base address: 0x1b0
|
#define mmMPCC4_MPCC_TOP_SEL 0x12dd
|
#define mmMPCC4_MPCC_TOP_SEL_BASE_IDX 2
|
#define mmMPCC4_MPCC_BOT_SEL 0x12de
|
#define mmMPCC4_MPCC_BOT_SEL_BASE_IDX 2
|
#define mmMPCC4_MPCC_OPP_ID 0x12df
|
#define mmMPCC4_MPCC_OPP_ID_BASE_IDX 2
|
#define mmMPCC4_MPCC_CONTROL 0x12e0
|
#define mmMPCC4_MPCC_CONTROL_BASE_IDX 2
|
#define mmMPCC4_MPCC_SM_CONTROL 0x12e1
|
#define mmMPCC4_MPCC_SM_CONTROL_BASE_IDX 2
|
#define mmMPCC4_MPCC_UPDATE_LOCK_SEL 0x12e2
|
#define mmMPCC4_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
|
#define mmMPCC4_MPCC_TOP_GAIN 0x12e3
|
#define mmMPCC4_MPCC_TOP_GAIN_BASE_IDX 2
|
#define mmMPCC4_MPCC_BOT_GAIN_INSIDE 0x12e4
|
#define mmMPCC4_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
|
#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE 0x12e5
|
#define mmMPCC4_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
|
#define mmMPCC4_MPCC_BG_R_CR 0x12e6
|
#define mmMPCC4_MPCC_BG_R_CR_BASE_IDX 2
|
#define mmMPCC4_MPCC_BG_G_Y 0x12e7
|
#define mmMPCC4_MPCC_BG_G_Y_BASE_IDX 2
|
#define mmMPCC4_MPCC_BG_B_CB 0x12e8
|
#define mmMPCC4_MPCC_BG_B_CB_BASE_IDX 2
|
#define mmMPCC4_MPCC_MEM_PWR_CTRL 0x12e9
|
#define mmMPCC4_MPCC_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmMPCC4_MPCC_STALL_STATUS 0x12ea
|
#define mmMPCC4_MPCC_STALL_STATUS_BASE_IDX 2
|
#define mmMPCC4_MPCC_STATUS 0x12eb
|
#define mmMPCC4_MPCC_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc5_dispdec
|
// base address: 0x21c
|
#define mmMPCC5_MPCC_TOP_SEL 0x12f8
|
#define mmMPCC5_MPCC_TOP_SEL_BASE_IDX 2
|
#define mmMPCC5_MPCC_BOT_SEL 0x12f9
|
#define mmMPCC5_MPCC_BOT_SEL_BASE_IDX 2
|
#define mmMPCC5_MPCC_OPP_ID 0x12fa
|
#define mmMPCC5_MPCC_OPP_ID_BASE_IDX 2
|
#define mmMPCC5_MPCC_CONTROL 0x12fb
|
#define mmMPCC5_MPCC_CONTROL_BASE_IDX 2
|
#define mmMPCC5_MPCC_SM_CONTROL 0x12fc
|
#define mmMPCC5_MPCC_SM_CONTROL_BASE_IDX 2
|
#define mmMPCC5_MPCC_UPDATE_LOCK_SEL 0x12fd
|
#define mmMPCC5_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
|
#define mmMPCC5_MPCC_TOP_GAIN 0x12fe
|
#define mmMPCC5_MPCC_TOP_GAIN_BASE_IDX 2
|
#define mmMPCC5_MPCC_BOT_GAIN_INSIDE 0x12ff
|
#define mmMPCC5_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
|
#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE 0x1300
|
#define mmMPCC5_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
|
#define mmMPCC5_MPCC_BG_R_CR 0x1301
|
#define mmMPCC5_MPCC_BG_R_CR_BASE_IDX 2
|
#define mmMPCC5_MPCC_BG_G_Y 0x1302
|
#define mmMPCC5_MPCC_BG_G_Y_BASE_IDX 2
|
#define mmMPCC5_MPCC_BG_B_CB 0x1303
|
#define mmMPCC5_MPCC_BG_B_CB_BASE_IDX 2
|
#define mmMPCC5_MPCC_MEM_PWR_CTRL 0x1304
|
#define mmMPCC5_MPCC_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmMPCC5_MPCC_STALL_STATUS 0x1305
|
#define mmMPCC5_MPCC_STALL_STATUS_BASE_IDX 2
|
#define mmMPCC5_MPCC_STATUS 0x1306
|
#define mmMPCC5_MPCC_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc6_dispdec
|
// base address: 0x288
|
#define mmMPCC6_MPCC_TOP_SEL 0x1313
|
#define mmMPCC6_MPCC_TOP_SEL_BASE_IDX 2
|
#define mmMPCC6_MPCC_BOT_SEL 0x1314
|
#define mmMPCC6_MPCC_BOT_SEL_BASE_IDX 2
|
#define mmMPCC6_MPCC_OPP_ID 0x1315
|
#define mmMPCC6_MPCC_OPP_ID_BASE_IDX 2
|
#define mmMPCC6_MPCC_CONTROL 0x1316
|
#define mmMPCC6_MPCC_CONTROL_BASE_IDX 2
|
#define mmMPCC6_MPCC_SM_CONTROL 0x1317
|
#define mmMPCC6_MPCC_SM_CONTROL_BASE_IDX 2
|
#define mmMPCC6_MPCC_UPDATE_LOCK_SEL 0x1318
|
#define mmMPCC6_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
|
#define mmMPCC6_MPCC_TOP_GAIN 0x1319
|
#define mmMPCC6_MPCC_TOP_GAIN_BASE_IDX 2
|
#define mmMPCC6_MPCC_BOT_GAIN_INSIDE 0x131a
|
#define mmMPCC6_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
|
#define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE 0x131b
|
#define mmMPCC6_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
|
#define mmMPCC6_MPCC_BG_R_CR 0x131c
|
#define mmMPCC6_MPCC_BG_R_CR_BASE_IDX 2
|
#define mmMPCC6_MPCC_BG_G_Y 0x131d
|
#define mmMPCC6_MPCC_BG_G_Y_BASE_IDX 2
|
#define mmMPCC6_MPCC_BG_B_CB 0x131e
|
#define mmMPCC6_MPCC_BG_B_CB_BASE_IDX 2
|
#define mmMPCC6_MPCC_MEM_PWR_CTRL 0x131f
|
#define mmMPCC6_MPCC_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmMPCC6_MPCC_STALL_STATUS 0x1320
|
#define mmMPCC6_MPCC_STALL_STATUS_BASE_IDX 2
|
#define mmMPCC6_MPCC_STATUS 0x1321
|
#define mmMPCC6_MPCC_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc7_dispdec
|
// base address: 0x2f4
|
#define mmMPCC7_MPCC_TOP_SEL 0x132e
|
#define mmMPCC7_MPCC_TOP_SEL_BASE_IDX 2
|
#define mmMPCC7_MPCC_BOT_SEL 0x132f
|
#define mmMPCC7_MPCC_BOT_SEL_BASE_IDX 2
|
#define mmMPCC7_MPCC_OPP_ID 0x1330
|
#define mmMPCC7_MPCC_OPP_ID_BASE_IDX 2
|
#define mmMPCC7_MPCC_CONTROL 0x1331
|
#define mmMPCC7_MPCC_CONTROL_BASE_IDX 2
|
#define mmMPCC7_MPCC_SM_CONTROL 0x1332
|
#define mmMPCC7_MPCC_SM_CONTROL_BASE_IDX 2
|
#define mmMPCC7_MPCC_UPDATE_LOCK_SEL 0x1333
|
#define mmMPCC7_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
|
#define mmMPCC7_MPCC_TOP_GAIN 0x1334
|
#define mmMPCC7_MPCC_TOP_GAIN_BASE_IDX 2
|
#define mmMPCC7_MPCC_BOT_GAIN_INSIDE 0x1335
|
#define mmMPCC7_MPCC_BOT_GAIN_INSIDE_BASE_IDX 2
|
#define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE 0x1336
|
#define mmMPCC7_MPCC_BOT_GAIN_OUTSIDE_BASE_IDX 2
|
#define mmMPCC7_MPCC_BG_R_CR 0x1337
|
#define mmMPCC7_MPCC_BG_R_CR_BASE_IDX 2
|
#define mmMPCC7_MPCC_BG_G_Y 0x1338
|
#define mmMPCC7_MPCC_BG_G_Y_BASE_IDX 2
|
#define mmMPCC7_MPCC_BG_B_CB 0x1339
|
#define mmMPCC7_MPCC_BG_B_CB_BASE_IDX 2
|
#define mmMPCC7_MPCC_MEM_PWR_CTRL 0x133a
|
#define mmMPCC7_MPCC_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmMPCC7_MPCC_STALL_STATUS 0x133b
|
#define mmMPCC7_MPCC_STALL_STATUS_BASE_IDX 2
|
#define mmMPCC7_MPCC_STATUS 0x133c
|
#define mmMPCC7_MPCC_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
|
// base address: 0x0
|
#define mmMPC_CLOCK_CONTROL 0x1349
|
#define mmMPC_CLOCK_CONTROL_BASE_IDX 2
|
#define mmMPC_SOFT_RESET 0x134a
|
#define mmMPC_SOFT_RESET_BASE_IDX 2
|
#define mmMPC_CRC_CTRL 0x134b
|
#define mmMPC_CRC_CTRL_BASE_IDX 2
|
#define mmMPC_CRC_SEL_CONTROL 0x134c
|
#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 2
|
#define mmMPC_CRC_RESULT_AR 0x134d
|
#define mmMPC_CRC_RESULT_AR_BASE_IDX 2
|
#define mmMPC_CRC_RESULT_GB 0x134e
|
#define mmMPC_CRC_RESULT_GB_BASE_IDX 2
|
#define mmMPC_CRC_RESULT_C 0x134f
|
#define mmMPC_CRC_RESULT_C_BASE_IDX 2
|
#define mmMPC_PERFMON_EVENT_CTRL 0x1352
|
#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 2
|
#define mmMPC_BYPASS_BG_AR 0x1353
|
#define mmMPC_BYPASS_BG_AR_BASE_IDX 2
|
#define mmMPC_BYPASS_BG_GB 0x1354
|
#define mmMPC_BYPASS_BG_GB_BASE_IDX 2
|
#define mmMPC_STALL_GRACE_WINDOW 0x1355
|
#define mmMPC_STALL_GRACE_WINDOW_BASE_IDX 2
|
#define mmMPC_HOST_READ_CONTROL 0x1356
|
#define mmMPC_HOST_READ_CONTROL_BASE_IDX 2
|
#define mmMPC_PENDING_TAKEN_STATUS_REG1 0x1357
|
#define mmMPC_PENDING_TAKEN_STATUS_REG1_BASE_IDX 2
|
#define mmMPC_PENDING_TAKEN_STATUS_REG2 0x1358
|
#define mmMPC_PENDING_TAKEN_STATUS_REG2_BASE_IDX 2
|
#define mmMPC_PENDING_TAKEN_STATUS_REG3 0x1359
|
#define mmMPC_PENDING_TAKEN_STATUS_REG3_BASE_IDX 2
|
#define mmMPC_UPDATE_ACK_REG5 0x135b
|
#define mmMPC_UPDATE_ACK_REG5_BASE_IDX 2
|
#define mmMPC_UPDATE_ACK_REG6 0x135c
|
#define mmMPC_UPDATE_ACK_REG6_BASE_IDX 2
|
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0 0x135d
|
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET0_BASE_IDX 2
|
#define mmADR_CFG_VUPDATE_LOCK_SET0 0x135e
|
#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 2
|
#define mmADR_VUPDATE_LOCK_SET0 0x135f
|
#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 2
|
#define mmCFG_VUPDATE_LOCK_SET0 0x1360
|
#define mmCFG_VUPDATE_LOCK_SET0_BASE_IDX 2
|
#define mmCUR_VUPDATE_LOCK_SET0 0x1361
|
#define mmCUR_VUPDATE_LOCK_SET0_BASE_IDX 2
|
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1 0x1362
|
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET1_BASE_IDX 2
|
#define mmADR_CFG_VUPDATE_LOCK_SET1 0x1363
|
#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 2
|
#define mmADR_VUPDATE_LOCK_SET1 0x1364
|
#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 2
|
#define mmCFG_VUPDATE_LOCK_SET1 0x1365
|
#define mmCFG_VUPDATE_LOCK_SET1_BASE_IDX 2
|
#define mmCUR_VUPDATE_LOCK_SET1 0x1366
|
#define mmCUR_VUPDATE_LOCK_SET1_BASE_IDX 2
|
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2 0x1367
|
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET2_BASE_IDX 2
|
#define mmADR_CFG_VUPDATE_LOCK_SET2 0x1368
|
#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 2
|
#define mmADR_VUPDATE_LOCK_SET2 0x1369
|
#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 2
|
#define mmCFG_VUPDATE_LOCK_SET2 0x136a
|
#define mmCFG_VUPDATE_LOCK_SET2_BASE_IDX 2
|
#define mmCUR_VUPDATE_LOCK_SET2 0x136b
|
#define mmCUR_VUPDATE_LOCK_SET2_BASE_IDX 2
|
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3 0x136c
|
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET3_BASE_IDX 2
|
#define mmADR_CFG_VUPDATE_LOCK_SET3 0x136d
|
#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 2
|
#define mmADR_VUPDATE_LOCK_SET3 0x136e
|
#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 2
|
#define mmCFG_VUPDATE_LOCK_SET3 0x136f
|
#define mmCFG_VUPDATE_LOCK_SET3_BASE_IDX 2
|
#define mmCUR_VUPDATE_LOCK_SET3 0x1370
|
#define mmCUR_VUPDATE_LOCK_SET3_BASE_IDX 2
|
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET4 0x1371
|
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET4_BASE_IDX 2
|
#define mmADR_CFG_VUPDATE_LOCK_SET4 0x1372
|
#define mmADR_CFG_VUPDATE_LOCK_SET4_BASE_IDX 2
|
#define mmADR_VUPDATE_LOCK_SET4 0x1373
|
#define mmADR_VUPDATE_LOCK_SET4_BASE_IDX 2
|
#define mmCFG_VUPDATE_LOCK_SET4 0x1374
|
#define mmCFG_VUPDATE_LOCK_SET4_BASE_IDX 2
|
#define mmCUR_VUPDATE_LOCK_SET4 0x1375
|
#define mmCUR_VUPDATE_LOCK_SET4_BASE_IDX 2
|
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET5 0x1376
|
#define mmADR_CFG_CUR_VUPDATE_LOCK_SET5_BASE_IDX 2
|
#define mmADR_CFG_VUPDATE_LOCK_SET5 0x1377
|
#define mmADR_CFG_VUPDATE_LOCK_SET5_BASE_IDX 2
|
#define mmADR_VUPDATE_LOCK_SET5 0x1378
|
#define mmADR_VUPDATE_LOCK_SET5_BASE_IDX 2
|
#define mmCFG_VUPDATE_LOCK_SET5 0x1379
|
#define mmCFG_VUPDATE_LOCK_SET5_BASE_IDX 2
|
#define mmCUR_VUPDATE_LOCK_SET5 0x137a
|
#define mmCUR_VUPDATE_LOCK_SET5_BASE_IDX 2
|
#define mmMPC_OUT0_MUX 0x1385
|
#define mmMPC_OUT0_MUX_BASE_IDX 2
|
#define mmMPC_OUT0_DENORM_CONTROL 0x1386
|
#define mmMPC_OUT0_DENORM_CONTROL_BASE_IDX 2
|
#define mmMPC_OUT0_DENORM_CLAMP_G_Y 0x1387
|
#define mmMPC_OUT0_DENORM_CLAMP_G_Y_BASE_IDX 2
|
#define mmMPC_OUT0_DENORM_CLAMP_B_CB 0x1388
|
#define mmMPC_OUT0_DENORM_CLAMP_B_CB_BASE_IDX 2
|
#define mmMPC_OUT1_MUX 0x1389
|
#define mmMPC_OUT1_MUX_BASE_IDX 2
|
#define mmMPC_OUT1_DENORM_CONTROL 0x138a
|
#define mmMPC_OUT1_DENORM_CONTROL_BASE_IDX 2
|
#define mmMPC_OUT1_DENORM_CLAMP_G_Y 0x138b
|
#define mmMPC_OUT1_DENORM_CLAMP_G_Y_BASE_IDX 2
|
#define mmMPC_OUT1_DENORM_CLAMP_B_CB 0x138c
|
#define mmMPC_OUT1_DENORM_CLAMP_B_CB_BASE_IDX 2
|
#define mmMPC_OUT2_MUX 0x138d
|
#define mmMPC_OUT2_MUX_BASE_IDX 2
|
#define mmMPC_OUT2_DENORM_CONTROL 0x138e
|
#define mmMPC_OUT2_DENORM_CONTROL_BASE_IDX 2
|
#define mmMPC_OUT2_DENORM_CLAMP_G_Y 0x138f
|
#define mmMPC_OUT2_DENORM_CLAMP_G_Y_BASE_IDX 2
|
#define mmMPC_OUT2_DENORM_CLAMP_B_CB 0x1390
|
#define mmMPC_OUT2_DENORM_CLAMP_B_CB_BASE_IDX 2
|
#define mmMPC_OUT3_MUX 0x1391
|
#define mmMPC_OUT3_MUX_BASE_IDX 2
|
#define mmMPC_OUT3_DENORM_CONTROL 0x1392
|
#define mmMPC_OUT3_DENORM_CONTROL_BASE_IDX 2
|
#define mmMPC_OUT3_DENORM_CLAMP_G_Y 0x1393
|
#define mmMPC_OUT3_DENORM_CLAMP_G_Y_BASE_IDX 2
|
#define mmMPC_OUT3_DENORM_CLAMP_B_CB 0x1394
|
#define mmMPC_OUT3_DENORM_CLAMP_B_CB_BASE_IDX 2
|
#define mmMPC_OUT4_MUX 0x1395
|
#define mmMPC_OUT4_MUX_BASE_IDX 2
|
#define mmMPC_OUT4_DENORM_CONTROL 0x1396
|
#define mmMPC_OUT4_DENORM_CONTROL_BASE_IDX 2
|
#define mmMPC_OUT4_DENORM_CLAMP_G_Y 0x1397
|
#define mmMPC_OUT4_DENORM_CLAMP_G_Y_BASE_IDX 2
|
#define mmMPC_OUT4_DENORM_CLAMP_B_CB 0x1398
|
#define mmMPC_OUT4_DENORM_CLAMP_B_CB_BASE_IDX 2
|
#define mmMPC_OUT5_MUX 0x1399
|
#define mmMPC_OUT5_MUX_BASE_IDX 2
|
#define mmMPC_OUT5_DENORM_CONTROL 0x139a
|
#define mmMPC_OUT5_DENORM_CONTROL_BASE_IDX 2
|
#define mmMPC_OUT5_DENORM_CLAMP_G_Y 0x139b
|
#define mmMPC_OUT5_DENORM_CLAMP_G_Y_BASE_IDX 2
|
#define mmMPC_OUT5_DENORM_CLAMP_B_CB 0x139c
|
#define mmMPC_OUT5_DENORM_CLAMP_B_CB_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc_ogam0_dispdec
|
// base address: 0x0
|
#define mmMPCC_OGAM0_MPCC_OGAM_MODE 0x13ae
|
#define mmMPCC_OGAM0_MPCC_OGAM_MODE_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX 0x13af
|
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA 0x13b0
|
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_DATA_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL 0x13b1
|
#define mmMPCC_OGAM0_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B 0x13b2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G 0x13b3
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R 0x13b4
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13b5
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13b6
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13b7
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B 0x13b8
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B 0x13b9
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G 0x13ba
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G 0x13bb
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R 0x13bc
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R 0x13bd
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1 0x13be
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3 0x13bf
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5 0x13c0
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7 0x13c1
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9 0x13c2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11 0x13c3
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13 0x13c4
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15 0x13c5
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17 0x13c6
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19 0x13c7
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21 0x13c8
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23 0x13c9
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25 0x13ca
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27 0x13cb
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29 0x13cc
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31 0x13cd
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33 0x13ce
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B 0x13cf
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G 0x13d0
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R 0x13d1
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x13d2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x13d3
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x13d4
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B 0x13d5
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B 0x13d6
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G 0x13d7
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G 0x13d8
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R 0x13d9
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R 0x13da
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1 0x13db
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3 0x13dc
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5 0x13dd
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7 0x13de
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9 0x13df
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11 0x13e0
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13 0x13e1
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15 0x13e2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17 0x13e3
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19 0x13e4
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21 0x13e5
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23 0x13e6
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25 0x13e7
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27 0x13e8
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29 0x13e9
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31 0x13ea
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33 0x13eb
|
#define mmMPCC_OGAM0_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc_ogam1_dispdec
|
// base address: 0x104
|
#define mmMPCC_OGAM1_MPCC_OGAM_MODE 0x13ef
|
#define mmMPCC_OGAM1_MPCC_OGAM_MODE_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX 0x13f0
|
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA 0x13f1
|
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_DATA_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL 0x13f2
|
#define mmMPCC_OGAM1_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B 0x13f3
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G 0x13f4
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R 0x13f5
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x13f6
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x13f7
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x13f8
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B 0x13f9
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B 0x13fa
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G 0x13fb
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G 0x13fc
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R 0x13fd
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R 0x13fe
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1 0x13ff
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3 0x1400
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5 0x1401
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7 0x1402
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9 0x1403
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11 0x1404
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13 0x1405
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15 0x1406
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17 0x1407
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19 0x1408
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21 0x1409
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23 0x140a
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25 0x140b
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27 0x140c
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29 0x140d
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31 0x140e
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33 0x140f
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B 0x1410
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G 0x1411
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R 0x1412
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1413
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1414
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1415
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B 0x1416
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B 0x1417
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G 0x1418
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G 0x1419
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R 0x141a
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R 0x141b
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1 0x141c
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3 0x141d
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5 0x141e
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7 0x141f
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9 0x1420
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11 0x1421
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13 0x1422
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15 0x1423
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17 0x1424
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19 0x1425
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21 0x1426
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23 0x1427
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25 0x1428
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27 0x1429
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29 0x142a
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31 0x142b
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33 0x142c
|
#define mmMPCC_OGAM1_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc_ogam2_dispdec
|
// base address: 0x208
|
#define mmMPCC_OGAM2_MPCC_OGAM_MODE 0x1430
|
#define mmMPCC_OGAM2_MPCC_OGAM_MODE_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX 0x1431
|
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA 0x1432
|
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_DATA_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL 0x1433
|
#define mmMPCC_OGAM2_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B 0x1434
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G 0x1435
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R 0x1436
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1437
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1438
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x1439
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B 0x143a
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B 0x143b
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G 0x143c
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G 0x143d
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R 0x143e
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R 0x143f
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1 0x1440
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3 0x1441
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5 0x1442
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7 0x1443
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9 0x1444
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11 0x1445
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13 0x1446
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15 0x1447
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17 0x1448
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19 0x1449
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21 0x144a
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23 0x144b
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25 0x144c
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27 0x144d
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29 0x144e
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31 0x144f
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33 0x1450
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B 0x1451
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G 0x1452
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R 0x1453
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1454
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1455
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1456
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B 0x1457
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B 0x1458
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G 0x1459
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G 0x145a
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R 0x145b
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R 0x145c
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1 0x145d
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3 0x145e
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5 0x145f
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7 0x1460
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9 0x1461
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11 0x1462
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13 0x1463
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15 0x1464
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17 0x1465
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19 0x1466
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21 0x1467
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23 0x1468
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25 0x1469
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27 0x146a
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29 0x146b
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31 0x146c
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33 0x146d
|
#define mmMPCC_OGAM2_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc_ogam3_dispdec
|
// base address: 0x30c
|
#define mmMPCC_OGAM3_MPCC_OGAM_MODE 0x1471
|
#define mmMPCC_OGAM3_MPCC_OGAM_MODE_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX 0x1472
|
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA 0x1473
|
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_DATA_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL 0x1474
|
#define mmMPCC_OGAM3_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B 0x1475
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G 0x1476
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R 0x1477
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x1478
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x1479
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x147a
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B 0x147b
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B 0x147c
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G 0x147d
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G 0x147e
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R 0x147f
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R 0x1480
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1 0x1481
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3 0x1482
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5 0x1483
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7 0x1484
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9 0x1485
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11 0x1486
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13 0x1487
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15 0x1488
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17 0x1489
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19 0x148a
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21 0x148b
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23 0x148c
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25 0x148d
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27 0x148e
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29 0x148f
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31 0x1490
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33 0x1491
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B 0x1492
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G 0x1493
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R 0x1494
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1495
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1496
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1497
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B 0x1498
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B 0x1499
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G 0x149a
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G 0x149b
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R 0x149c
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R 0x149d
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1 0x149e
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3 0x149f
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5 0x14a0
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7 0x14a1
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9 0x14a2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11 0x14a3
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13 0x14a4
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15 0x14a5
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17 0x14a6
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19 0x14a7
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21 0x14a8
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23 0x14a9
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25 0x14aa
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27 0x14ab
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29 0x14ac
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31 0x14ad
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33 0x14ae
|
#define mmMPCC_OGAM3_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc_ogam4_dispdec
|
// base address: 0x410
|
#define mmMPCC_OGAM4_MPCC_OGAM_MODE 0x14b2
|
#define mmMPCC_OGAM4_MPCC_OGAM_MODE_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX 0x14b3
|
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA 0x14b4
|
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_DATA_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL 0x14b5
|
#define mmMPCC_OGAM4_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B 0x14b6
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G 0x14b7
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R 0x14b8
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x14b9
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x14ba
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x14bb
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B 0x14bc
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B 0x14bd
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G 0x14be
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G 0x14bf
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R 0x14c0
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R 0x14c1
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1 0x14c2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3 0x14c3
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5 0x14c4
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7 0x14c5
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9 0x14c6
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11 0x14c7
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13 0x14c8
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15 0x14c9
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17 0x14ca
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19 0x14cb
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21 0x14cc
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23 0x14cd
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25 0x14ce
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27 0x14cf
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29 0x14d0
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31 0x14d1
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33 0x14d2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B 0x14d3
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G 0x14d4
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R 0x14d5
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x14d6
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x14d7
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x14d8
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B 0x14d9
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B 0x14da
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G 0x14db
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G 0x14dc
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R 0x14dd
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R 0x14de
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1 0x14df
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3 0x14e0
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5 0x14e1
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7 0x14e2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9 0x14e3
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11 0x14e4
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13 0x14e5
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15 0x14e6
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17 0x14e7
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19 0x14e8
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21 0x14e9
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23 0x14ea
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25 0x14eb
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27 0x14ec
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29 0x14ed
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31 0x14ee
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33 0x14ef
|
#define mmMPCC_OGAM4_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc_ogam5_dispdec
|
// base address: 0x514
|
#define mmMPCC_OGAM5_MPCC_OGAM_MODE 0x14f3
|
#define mmMPCC_OGAM5_MPCC_OGAM_MODE_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX 0x14f4
|
#define mmMPCC_OGAM5_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA 0x14f5
|
#define mmMPCC_OGAM5_MPCC_OGAM_LUT_DATA_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL 0x14f6
|
#define mmMPCC_OGAM5_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B 0x14f7
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G 0x14f8
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R 0x14f9
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x14fa
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x14fb
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x14fc
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B 0x14fd
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B 0x14fe
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G 0x14ff
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G 0x1500
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R 0x1501
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R 0x1502
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1 0x1503
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3 0x1504
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5 0x1505
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7 0x1506
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9 0x1507
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11 0x1508
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13 0x1509
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15 0x150a
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17 0x150b
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19 0x150c
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21 0x150d
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23 0x150e
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25 0x150f
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27 0x1510
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29 0x1511
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31 0x1512
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33 0x1513
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B 0x1514
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G 0x1515
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R 0x1516
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1517
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1518
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x1519
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B 0x151a
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B 0x151b
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G 0x151c
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G 0x151d
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R 0x151e
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R 0x151f
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1 0x1520
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3 0x1521
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5 0x1522
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7 0x1523
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9 0x1524
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11 0x1525
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13 0x1526
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15 0x1527
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17 0x1528
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19 0x1529
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21 0x152a
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23 0x152b
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25 0x152c
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27 0x152d
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29 0x152e
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31 0x152f
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33 0x1530
|
#define mmMPCC_OGAM5_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc_ogam6_dispdec
|
// base address: 0x618
|
#define mmMPCC_OGAM6_MPCC_OGAM_MODE 0x1534
|
#define mmMPCC_OGAM6_MPCC_OGAM_MODE_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX 0x1535
|
#define mmMPCC_OGAM6_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA 0x1536
|
#define mmMPCC_OGAM6_MPCC_OGAM_LUT_DATA_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL 0x1537
|
#define mmMPCC_OGAM6_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B 0x1538
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G 0x1539
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R 0x153a
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x153b
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x153c
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x153d
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B 0x153e
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B 0x153f
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G 0x1540
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G 0x1541
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R 0x1542
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R 0x1543
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1 0x1544
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3 0x1545
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5 0x1546
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7 0x1547
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9 0x1548
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11 0x1549
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13 0x154a
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15 0x154b
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17 0x154c
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19 0x154d
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21 0x154e
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23 0x154f
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25 0x1550
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27 0x1551
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29 0x1552
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31 0x1553
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33 0x1554
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B 0x1555
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G 0x1556
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R 0x1557
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1558
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x1559
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x155a
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B 0x155b
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B 0x155c
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G 0x155d
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G 0x155e
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R 0x155f
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R 0x1560
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1 0x1561
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3 0x1562
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5 0x1563
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7 0x1564
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9 0x1565
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11 0x1566
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13 0x1567
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15 0x1568
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17 0x1569
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19 0x156a
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21 0x156b
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23 0x156c
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25 0x156d
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27 0x156e
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29 0x156f
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31 0x1570
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33 0x1571
|
#define mmMPCC_OGAM6_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc_ogam7_dispdec
|
// base address: 0x71c
|
#define mmMPCC_OGAM7_MPCC_OGAM_MODE 0x1575
|
#define mmMPCC_OGAM7_MPCC_OGAM_MODE_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX 0x1576
|
#define mmMPCC_OGAM7_MPCC_OGAM_LUT_INDEX_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA 0x1577
|
#define mmMPCC_OGAM7_MPCC_OGAM_LUT_DATA_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL 0x1578
|
#define mmMPCC_OGAM7_MPCC_OGAM_LUT_RAM_CONTROL_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B 0x1579
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G 0x157a
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R 0x157b
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B 0x157c
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G 0x157d
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R 0x157e
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B 0x157f
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B 0x1580
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G 0x1581
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G 0x1582
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R 0x1583
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R 0x1584
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1 0x1585
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3 0x1586
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5 0x1587
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7 0x1588
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9 0x1589
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11 0x158a
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13 0x158b
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15 0x158c
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17 0x158d
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19 0x158e
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21 0x158f
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23 0x1590
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25 0x1591
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27 0x1592
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29 0x1593
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31 0x1594
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33 0x1595
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B 0x1596
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G 0x1597
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R 0x1598
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B 0x1599
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G 0x159a
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R 0x159b
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B 0x159c
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B 0x159d
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G 0x159e
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G 0x159f
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R 0x15a0
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R 0x15a1
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1 0x15a2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3 0x15a3
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5 0x15a4
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7 0x15a5
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9 0x15a6
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11 0x15a7
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13 0x15a8
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15 0x15a9
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17 0x15aa
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19 0x15ab
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21 0x15ac
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23 0x15ad
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25 0x15ae
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27 0x15af
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29 0x15b0
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31 0x15b1
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33 0x15b2
|
#define mmMPCC_OGAM7_MPCC_OGAM_RAMB_REGION_32_33_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpc_ocsc_dispdec
|
// base address: 0x0
|
#define mmMPC_OUT_CSC_COEF_FORMAT 0x15b6
|
#define mmMPC_OUT_CSC_COEF_FORMAT_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_MODE 0x15b7
|
#define mmMPC_OUT0_CSC_MODE_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_C11_C12_A 0x15b8
|
#define mmMPC_OUT0_CSC_C11_C12_A_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_C13_C14_A 0x15b9
|
#define mmMPC_OUT0_CSC_C13_C14_A_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_C21_C22_A 0x15ba
|
#define mmMPC_OUT0_CSC_C21_C22_A_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_C23_C24_A 0x15bb
|
#define mmMPC_OUT0_CSC_C23_C24_A_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_C31_C32_A 0x15bc
|
#define mmMPC_OUT0_CSC_C31_C32_A_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_C33_C34_A 0x15bd
|
#define mmMPC_OUT0_CSC_C33_C34_A_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_C11_C12_B 0x15be
|
#define mmMPC_OUT0_CSC_C11_C12_B_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_C13_C14_B 0x15bf
|
#define mmMPC_OUT0_CSC_C13_C14_B_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_C21_C22_B 0x15c0
|
#define mmMPC_OUT0_CSC_C21_C22_B_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_C23_C24_B 0x15c1
|
#define mmMPC_OUT0_CSC_C23_C24_B_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_C31_C32_B 0x15c2
|
#define mmMPC_OUT0_CSC_C31_C32_B_BASE_IDX 2
|
#define mmMPC_OUT0_CSC_C33_C34_B 0x15c3
|
#define mmMPC_OUT0_CSC_C33_C34_B_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_MODE 0x15c4
|
#define mmMPC_OUT1_CSC_MODE_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_C11_C12_A 0x15c5
|
#define mmMPC_OUT1_CSC_C11_C12_A_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_C13_C14_A 0x15c6
|
#define mmMPC_OUT1_CSC_C13_C14_A_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_C21_C22_A 0x15c7
|
#define mmMPC_OUT1_CSC_C21_C22_A_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_C23_C24_A 0x15c8
|
#define mmMPC_OUT1_CSC_C23_C24_A_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_C31_C32_A 0x15c9
|
#define mmMPC_OUT1_CSC_C31_C32_A_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_C33_C34_A 0x15ca
|
#define mmMPC_OUT1_CSC_C33_C34_A_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_C11_C12_B 0x15cb
|
#define mmMPC_OUT1_CSC_C11_C12_B_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_C13_C14_B 0x15cc
|
#define mmMPC_OUT1_CSC_C13_C14_B_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_C21_C22_B 0x15cd
|
#define mmMPC_OUT1_CSC_C21_C22_B_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_C23_C24_B 0x15ce
|
#define mmMPC_OUT1_CSC_C23_C24_B_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_C31_C32_B 0x15cf
|
#define mmMPC_OUT1_CSC_C31_C32_B_BASE_IDX 2
|
#define mmMPC_OUT1_CSC_C33_C34_B 0x15d0
|
#define mmMPC_OUT1_CSC_C33_C34_B_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_MODE 0x15d1
|
#define mmMPC_OUT2_CSC_MODE_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_C11_C12_A 0x15d2
|
#define mmMPC_OUT2_CSC_C11_C12_A_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_C13_C14_A 0x15d3
|
#define mmMPC_OUT2_CSC_C13_C14_A_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_C21_C22_A 0x15d4
|
#define mmMPC_OUT2_CSC_C21_C22_A_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_C23_C24_A 0x15d5
|
#define mmMPC_OUT2_CSC_C23_C24_A_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_C31_C32_A 0x15d6
|
#define mmMPC_OUT2_CSC_C31_C32_A_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_C33_C34_A 0x15d7
|
#define mmMPC_OUT2_CSC_C33_C34_A_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_C11_C12_B 0x15d8
|
#define mmMPC_OUT2_CSC_C11_C12_B_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_C13_C14_B 0x15d9
|
#define mmMPC_OUT2_CSC_C13_C14_B_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_C21_C22_B 0x15da
|
#define mmMPC_OUT2_CSC_C21_C22_B_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_C23_C24_B 0x15db
|
#define mmMPC_OUT2_CSC_C23_C24_B_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_C31_C32_B 0x15dc
|
#define mmMPC_OUT2_CSC_C31_C32_B_BASE_IDX 2
|
#define mmMPC_OUT2_CSC_C33_C34_B 0x15dd
|
#define mmMPC_OUT2_CSC_C33_C34_B_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_MODE 0x15de
|
#define mmMPC_OUT3_CSC_MODE_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_C11_C12_A 0x15df
|
#define mmMPC_OUT3_CSC_C11_C12_A_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_C13_C14_A 0x15e0
|
#define mmMPC_OUT3_CSC_C13_C14_A_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_C21_C22_A 0x15e1
|
#define mmMPC_OUT3_CSC_C21_C22_A_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_C23_C24_A 0x15e2
|
#define mmMPC_OUT3_CSC_C23_C24_A_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_C31_C32_A 0x15e3
|
#define mmMPC_OUT3_CSC_C31_C32_A_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_C33_C34_A 0x15e4
|
#define mmMPC_OUT3_CSC_C33_C34_A_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_C11_C12_B 0x15e5
|
#define mmMPC_OUT3_CSC_C11_C12_B_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_C13_C14_B 0x15e6
|
#define mmMPC_OUT3_CSC_C13_C14_B_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_C21_C22_B 0x15e7
|
#define mmMPC_OUT3_CSC_C21_C22_B_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_C23_C24_B 0x15e8
|
#define mmMPC_OUT3_CSC_C23_C24_B_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_C31_C32_B 0x15e9
|
#define mmMPC_OUT3_CSC_C31_C32_B_BASE_IDX 2
|
#define mmMPC_OUT3_CSC_C33_C34_B 0x15ea
|
#define mmMPC_OUT3_CSC_C33_C34_B_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_MODE 0x15eb
|
#define mmMPC_OUT4_CSC_MODE_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_C11_C12_A 0x15ec
|
#define mmMPC_OUT4_CSC_C11_C12_A_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_C13_C14_A 0x15ed
|
#define mmMPC_OUT4_CSC_C13_C14_A_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_C21_C22_A 0x15ee
|
#define mmMPC_OUT4_CSC_C21_C22_A_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_C23_C24_A 0x15ef
|
#define mmMPC_OUT4_CSC_C23_C24_A_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_C31_C32_A 0x15f0
|
#define mmMPC_OUT4_CSC_C31_C32_A_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_C33_C34_A 0x15f1
|
#define mmMPC_OUT4_CSC_C33_C34_A_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_C11_C12_B 0x15f2
|
#define mmMPC_OUT4_CSC_C11_C12_B_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_C13_C14_B 0x15f3
|
#define mmMPC_OUT4_CSC_C13_C14_B_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_C21_C22_B 0x15f4
|
#define mmMPC_OUT4_CSC_C21_C22_B_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_C23_C24_B 0x15f5
|
#define mmMPC_OUT4_CSC_C23_C24_B_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_C31_C32_B 0x15f6
|
#define mmMPC_OUT4_CSC_C31_C32_B_BASE_IDX 2
|
#define mmMPC_OUT4_CSC_C33_C34_B 0x15f7
|
#define mmMPC_OUT4_CSC_C33_C34_B_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_MODE 0x15f8
|
#define mmMPC_OUT5_CSC_MODE_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_C11_C12_A 0x15f9
|
#define mmMPC_OUT5_CSC_C11_C12_A_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_C13_C14_A 0x15fa
|
#define mmMPC_OUT5_CSC_C13_C14_A_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_C21_C22_A 0x15fb
|
#define mmMPC_OUT5_CSC_C21_C22_A_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_C23_C24_A 0x15fc
|
#define mmMPC_OUT5_CSC_C23_C24_A_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_C31_C32_A 0x15fd
|
#define mmMPC_OUT5_CSC_C31_C32_A_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_C33_C34_A 0x15fe
|
#define mmMPC_OUT5_CSC_C33_C34_A_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_C11_C12_B 0x15ff
|
#define mmMPC_OUT5_CSC_C11_C12_B_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_C13_C14_B 0x1600
|
#define mmMPC_OUT5_CSC_C13_C14_B_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_C21_C22_B 0x1601
|
#define mmMPC_OUT5_CSC_C21_C22_B_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_C23_C24_B 0x1602
|
#define mmMPC_OUT5_CSC_C23_C24_B_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_C31_C32_B 0x1603
|
#define mmMPC_OUT5_CSC_C31_C32_B_BASE_IDX 2
|
#define mmMPC_OUT5_CSC_C33_C34_B 0x1604
|
#define mmMPC_OUT5_CSC_C33_C34_B_BASE_IDX 2
|
|
#define mmMPC_OCSC_TEST_DEBUG_INDEX 0x163b
|
#define mmMPC_OCSC_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmMPC_OCSC_TEST_DEBUG_DATA_BASE_IDX 2
|
#define mmMPC_OCSC_TEST_DEBUG_DATA 0x163c
|
|
// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x5964
|
#define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x1659
|
#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x165a
|
#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFCOUNTER_STATE 0x165b
|
#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_CNTL 0x165c
|
#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_CNTL2 0x165d
|
#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x165e
|
#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x165f
|
#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_HI 0x1660
|
#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_LOW 0x1661
|
#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_abm0_dispdec
|
// base address: 0x0
|
#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x17b0
|
#define mmBL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
|
#define mmBL1_PWM_USER_LEVEL 0x17b1
|
#define mmBL1_PWM_USER_LEVEL_BASE_IDX 2
|
#define mmBL1_PWM_TARGET_ABM_LEVEL 0x17b2
|
#define mmBL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
|
#define mmBL1_PWM_CURRENT_ABM_LEVEL 0x17b3
|
#define mmBL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
|
#define mmBL1_PWM_FINAL_DUTY_CYCLE 0x17b4
|
#define mmBL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
|
#define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x17b5
|
#define mmBL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
|
#define mmBL1_PWM_ABM_CNTL 0x17b6
|
#define mmBL1_PWM_ABM_CNTL_BASE_IDX 2
|
#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17b7
|
#define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
|
#define mmBL1_PWM_GRP2_REG_LOCK 0x17b8
|
#define mmBL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
|
#define mmDC_ABM1_CNTL 0x17b9
|
#define mmDC_ABM1_CNTL_BASE_IDX 2
|
#define mmDC_ABM1_IPCSC_COEFF_SEL 0x17ba
|
#define mmDC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
|
#define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x17bb
|
#define mmDC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
|
#define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x17bc
|
#define mmDC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
|
#define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x17bd
|
#define mmDC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
|
#define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x17be
|
#define mmDC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
|
#define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x17bf
|
#define mmDC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
|
#define mmDC_ABM1_ACE_THRES_12 0x17c0
|
#define mmDC_ABM1_ACE_THRES_12_BASE_IDX 2
|
#define mmDC_ABM1_ACE_THRES_34 0x17c1
|
#define mmDC_ABM1_ACE_THRES_34_BASE_IDX 2
|
#define mmDC_ABM1_ACE_CNTL_MISC 0x17c2
|
#define mmDC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
|
#define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x17c4
|
#define mmDC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
|
#define mmDC_ABM1_HG_MISC_CTRL 0x17c5
|
#define mmDC_ABM1_HG_MISC_CTRL_BASE_IDX 2
|
#define mmDC_ABM1_LS_SUM_OF_LUMA 0x17c6
|
#define mmDC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
|
#define mmDC_ABM1_LS_MIN_MAX_LUMA 0x17c7
|
#define mmDC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
|
#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x17c8
|
#define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
|
#define mmDC_ABM1_LS_PIXEL_COUNT 0x17c9
|
#define mmDC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
|
#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x17ca
|
#define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
|
#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x17cb
|
#define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
|
#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x17cc
|
#define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
|
#define mmDC_ABM1_HG_SAMPLE_RATE 0x17cd
|
#define mmDC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
|
#define mmDC_ABM1_LS_SAMPLE_RATE 0x17ce
|
#define mmDC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
|
#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x17cf
|
#define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
|
#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x17d0
|
#define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
|
#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x17d1
|
#define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
|
#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x17d2
|
#define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
|
#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x17d3
|
#define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_1 0x17d4
|
#define mmDC_ABM1_HG_RESULT_1_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_2 0x17d5
|
#define mmDC_ABM1_HG_RESULT_2_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_3 0x17d6
|
#define mmDC_ABM1_HG_RESULT_3_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_4 0x17d7
|
#define mmDC_ABM1_HG_RESULT_4_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_5 0x17d8
|
#define mmDC_ABM1_HG_RESULT_5_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_6 0x17d9
|
#define mmDC_ABM1_HG_RESULT_6_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_7 0x17da
|
#define mmDC_ABM1_HG_RESULT_7_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_8 0x17db
|
#define mmDC_ABM1_HG_RESULT_8_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_9 0x17dc
|
#define mmDC_ABM1_HG_RESULT_9_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_10 0x17dd
|
#define mmDC_ABM1_HG_RESULT_10_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_11 0x17de
|
#define mmDC_ABM1_HG_RESULT_11_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_12 0x17df
|
#define mmDC_ABM1_HG_RESULT_12_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_13 0x17e0
|
#define mmDC_ABM1_HG_RESULT_13_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_14 0x17e1
|
#define mmDC_ABM1_HG_RESULT_14_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_15 0x17e2
|
#define mmDC_ABM1_HG_RESULT_15_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_16 0x17e3
|
#define mmDC_ABM1_HG_RESULT_16_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_17 0x17e4
|
#define mmDC_ABM1_HG_RESULT_17_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_18 0x17e5
|
#define mmDC_ABM1_HG_RESULT_18_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_19 0x17e6
|
#define mmDC_ABM1_HG_RESULT_19_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_20 0x17e7
|
#define mmDC_ABM1_HG_RESULT_20_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_21 0x17e8
|
#define mmDC_ABM1_HG_RESULT_21_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_22 0x17e9
|
#define mmDC_ABM1_HG_RESULT_22_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_23 0x17ea
|
#define mmDC_ABM1_HG_RESULT_23_BASE_IDX 2
|
#define mmDC_ABM1_HG_RESULT_24 0x17eb
|
#define mmDC_ABM1_HG_RESULT_24_BASE_IDX 2
|
#define mmDC_ABM1_BL_MASTER_LOCK 0x17ec
|
#define mmDC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_fmt0_dispdec
|
// base address: 0x0
|
#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c
|
#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d
|
#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e
|
#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f
|
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT0_FMT_CONTROL 0x1840
|
#define mmFMT0_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841
|
#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842
|
#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843
|
#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844
|
#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT0_FMT_CLAMP_CNTL 0x1845
|
#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1846
|
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x1847
|
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
#define mmFMT0_FMT_422_CONTROL 0x1849
|
#define mmFMT0_FMT_422_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dpg0_dispdec
|
// base address: 0x0
|
#define mmDPG0_DPG_CONTROL 0x1854
|
#define mmDPG0_DPG_CONTROL_BASE_IDX 2
|
#define mmDPG0_DPG_RAMP_CONTROL 0x1855
|
#define mmDPG0_DPG_RAMP_CONTROL_BASE_IDX 2
|
#define mmDPG0_DPG_DIMENSIONS 0x1856
|
#define mmDPG0_DPG_DIMENSIONS_BASE_IDX 2
|
#define mmDPG0_DPG_COLOUR_R_CR 0x1857
|
#define mmDPG0_DPG_COLOUR_R_CR_BASE_IDX 2
|
#define mmDPG0_DPG_COLOUR_G_Y 0x1858
|
#define mmDPG0_DPG_COLOUR_G_Y_BASE_IDX 2
|
#define mmDPG0_DPG_COLOUR_B_CB 0x1859
|
#define mmDPG0_DPG_COLOUR_B_CB_BASE_IDX 2
|
#define mmDPG0_DPG_OFFSET_SEGMENT 0x185a
|
#define mmDPG0_DPG_OFFSET_SEGMENT_BASE_IDX 2
|
#define mmDPG0_DPG_STATUS 0x185b
|
#define mmDPG0_DPG_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_oppbuf0_dispdec
|
// base address: 0x0
|
#define mmOPPBUF0_OPPBUF_CONTROL 0x1884
|
#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885
|
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886
|
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
|
#define mmOPPBUF0_OPPBUF_CONTROL1 0x1889
|
#define mmOPPBUF0_OPPBUF_CONTROL1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe0_dispdec
|
// base address: 0x0
|
#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c
|
#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
|
// base address: 0x0
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_fmt1_dispdec
|
// base address: 0x168
|
#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896
|
#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897
|
#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898
|
#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899
|
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT1_FMT_CONTROL 0x189a
|
#define mmFMT1_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b
|
#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c
|
#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d
|
#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e
|
#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT1_FMT_CLAMP_CNTL 0x189f
|
#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a0
|
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a1
|
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
#define mmFMT1_FMT_422_CONTROL 0x18a3
|
#define mmFMT1_FMT_422_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dpg1_dispdec
|
// base address: 0x168
|
#define mmDPG1_DPG_CONTROL 0x18ae
|
#define mmDPG1_DPG_CONTROL_BASE_IDX 2
|
#define mmDPG1_DPG_RAMP_CONTROL 0x18af
|
#define mmDPG1_DPG_RAMP_CONTROL_BASE_IDX 2
|
#define mmDPG1_DPG_DIMENSIONS 0x18b0
|
#define mmDPG1_DPG_DIMENSIONS_BASE_IDX 2
|
#define mmDPG1_DPG_COLOUR_R_CR 0x18b1
|
#define mmDPG1_DPG_COLOUR_R_CR_BASE_IDX 2
|
#define mmDPG1_DPG_COLOUR_G_Y 0x18b2
|
#define mmDPG1_DPG_COLOUR_G_Y_BASE_IDX 2
|
#define mmDPG1_DPG_COLOUR_B_CB 0x18b3
|
#define mmDPG1_DPG_COLOUR_B_CB_BASE_IDX 2
|
#define mmDPG1_DPG_OFFSET_SEGMENT 0x18b4
|
#define mmDPG1_DPG_OFFSET_SEGMENT_BASE_IDX 2
|
#define mmDPG1_DPG_STATUS 0x18b5
|
#define mmDPG1_DPG_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_oppbuf1_dispdec
|
// base address: 0x168
|
#define mmOPPBUF1_OPPBUF_CONTROL 0x18de
|
#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df
|
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0
|
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
|
#define mmOPPBUF1_OPPBUF_CONTROL1 0x18e3
|
#define mmOPPBUF1_OPPBUF_CONTROL1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe1_dispdec
|
// base address: 0x168
|
#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6
|
#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
|
// base address: 0x168
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_fmt2_dispdec
|
// base address: 0x2d0
|
#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0
|
#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1
|
#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2
|
#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3
|
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT2_FMT_CONTROL 0x18f4
|
#define mmFMT2_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5
|
#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6
|
#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7
|
#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8
|
#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT2_FMT_CLAMP_CNTL 0x18f9
|
#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fa
|
#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fb
|
#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
#define mmFMT2_FMT_422_CONTROL 0x18fd
|
#define mmFMT2_FMT_422_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dpg2_dispdec
|
// base address: 0x2d0
|
#define mmDPG2_DPG_CONTROL 0x1908
|
#define mmDPG2_DPG_CONTROL_BASE_IDX 2
|
#define mmDPG2_DPG_RAMP_CONTROL 0x1909
|
#define mmDPG2_DPG_RAMP_CONTROL_BASE_IDX 2
|
#define mmDPG2_DPG_DIMENSIONS 0x190a
|
#define mmDPG2_DPG_DIMENSIONS_BASE_IDX 2
|
#define mmDPG2_DPG_COLOUR_R_CR 0x190b
|
#define mmDPG2_DPG_COLOUR_R_CR_BASE_IDX 2
|
#define mmDPG2_DPG_COLOUR_G_Y 0x190c
|
#define mmDPG2_DPG_COLOUR_G_Y_BASE_IDX 2
|
#define mmDPG2_DPG_COLOUR_B_CB 0x190d
|
#define mmDPG2_DPG_COLOUR_B_CB_BASE_IDX 2
|
#define mmDPG2_DPG_OFFSET_SEGMENT 0x190e
|
#define mmDPG2_DPG_OFFSET_SEGMENT_BASE_IDX 2
|
#define mmDPG2_DPG_STATUS 0x190f
|
#define mmDPG2_DPG_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_oppbuf2_dispdec
|
// base address: 0x2d0
|
#define mmOPPBUF2_OPPBUF_CONTROL 0x1938
|
#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939
|
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a
|
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
|
#define mmOPPBUF2_OPPBUF_CONTROL1 0x193d
|
#define mmOPPBUF2_OPPBUF_CONTROL1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe2_dispdec
|
// base address: 0x2d0
|
#define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940
|
#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
|
// base address: 0x2d0
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_fmt3_dispdec
|
// base address: 0x438
|
#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a
|
#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b
|
#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c
|
#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d
|
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT3_FMT_CONTROL 0x194e
|
#define mmFMT3_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f
|
#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950
|
#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951
|
#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952
|
#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT3_FMT_CLAMP_CNTL 0x1953
|
#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1954
|
#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1955
|
#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
#define mmFMT3_FMT_422_CONTROL 0x1957
|
#define mmFMT3_FMT_422_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dpg3_dispdec
|
// base address: 0x438
|
#define mmDPG3_DPG_CONTROL 0x1962
|
#define mmDPG3_DPG_CONTROL_BASE_IDX 2
|
#define mmDPG3_DPG_RAMP_CONTROL 0x1963
|
#define mmDPG3_DPG_RAMP_CONTROL_BASE_IDX 2
|
#define mmDPG3_DPG_DIMENSIONS 0x1964
|
#define mmDPG3_DPG_DIMENSIONS_BASE_IDX 2
|
#define mmDPG3_DPG_COLOUR_R_CR 0x1965
|
#define mmDPG3_DPG_COLOUR_R_CR_BASE_IDX 2
|
#define mmDPG3_DPG_COLOUR_G_Y 0x1966
|
#define mmDPG3_DPG_COLOUR_G_Y_BASE_IDX 2
|
#define mmDPG3_DPG_COLOUR_B_CB 0x1967
|
#define mmDPG3_DPG_COLOUR_B_CB_BASE_IDX 2
|
#define mmDPG3_DPG_OFFSET_SEGMENT 0x1968
|
#define mmDPG3_DPG_OFFSET_SEGMENT_BASE_IDX 2
|
#define mmDPG3_DPG_STATUS 0x1969
|
#define mmDPG3_DPG_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_oppbuf3_dispdec
|
// base address: 0x438
|
#define mmOPPBUF3_OPPBUF_CONTROL 0x1992
|
#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993
|
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994
|
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
|
#define mmOPPBUF3_OPPBUF_CONTROL1 0x1997
|
#define mmOPPBUF3_OPPBUF_CONTROL1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe3_dispdec
|
// base address: 0x438
|
#define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a
|
#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
|
// base address: 0x438
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_fmt4_dispdec
|
// base address: 0x5a0
|
#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4
|
#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5
|
#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6
|
#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7
|
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT4_FMT_CONTROL 0x19a8
|
#define mmFMT4_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9
|
#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa
|
#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab
|
#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac
|
#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT4_FMT_CLAMP_CNTL 0x19ad
|
#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19ae
|
#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19af
|
#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
#define mmFMT4_FMT_422_CONTROL 0x19b1
|
#define mmFMT4_FMT_422_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dpg4_dispdec
|
// base address: 0x5a0
|
#define mmDPG4_DPG_CONTROL 0x19bc
|
#define mmDPG4_DPG_CONTROL_BASE_IDX 2
|
#define mmDPG4_DPG_RAMP_CONTROL 0x19bd
|
#define mmDPG4_DPG_RAMP_CONTROL_BASE_IDX 2
|
#define mmDPG4_DPG_DIMENSIONS 0x19be
|
#define mmDPG4_DPG_DIMENSIONS_BASE_IDX 2
|
#define mmDPG4_DPG_COLOUR_R_CR 0x19bf
|
#define mmDPG4_DPG_COLOUR_R_CR_BASE_IDX 2
|
#define mmDPG4_DPG_COLOUR_G_Y 0x19c0
|
#define mmDPG4_DPG_COLOUR_G_Y_BASE_IDX 2
|
#define mmDPG4_DPG_COLOUR_B_CB 0x19c1
|
#define mmDPG4_DPG_COLOUR_B_CB_BASE_IDX 2
|
#define mmDPG4_DPG_OFFSET_SEGMENT 0x19c2
|
#define mmDPG4_DPG_OFFSET_SEGMENT_BASE_IDX 2
|
#define mmDPG4_DPG_STATUS 0x19c3
|
#define mmDPG4_DPG_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_oppbuf4_dispdec
|
// base address: 0x5a0
|
#define mmOPPBUF4_OPPBUF_CONTROL 0x19ec
|
#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed
|
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee
|
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
|
#define mmOPPBUF4_OPPBUF_CONTROL1 0x19f1
|
#define mmOPPBUF4_OPPBUF_CONTROL1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe4_dispdec
|
// base address: 0x5a0
|
#define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4
|
#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
|
// base address: 0x5a0
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_fmt5_dispdec
|
// base address: 0x708
|
#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe
|
#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff
|
#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00
|
#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01
|
#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT5_FMT_CONTROL 0x1a02
|
#define mmFMT5_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03
|
#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04
|
#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05
|
#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06
|
#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT5_FMT_CLAMP_CNTL 0x1a07
|
#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a08
|
#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a09
|
#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
#define mmFMT5_FMT_422_CONTROL 0x1a0b
|
#define mmFMT5_FMT_422_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dpg5_dispdec
|
// base address: 0x708
|
#define mmDPG5_DPG_CONTROL 0x1a16
|
#define mmDPG5_DPG_CONTROL_BASE_IDX 2
|
#define mmDPG5_DPG_RAMP_CONTROL 0x1a17
|
#define mmDPG5_DPG_RAMP_CONTROL_BASE_IDX 2
|
#define mmDPG5_DPG_DIMENSIONS 0x1a18
|
#define mmDPG5_DPG_DIMENSIONS_BASE_IDX 2
|
#define mmDPG5_DPG_COLOUR_R_CR 0x1a19
|
#define mmDPG5_DPG_COLOUR_R_CR_BASE_IDX 2
|
#define mmDPG5_DPG_COLOUR_G_Y 0x1a1a
|
#define mmDPG5_DPG_COLOUR_G_Y_BASE_IDX 2
|
#define mmDPG5_DPG_COLOUR_B_CB 0x1a1b
|
#define mmDPG5_DPG_COLOUR_B_CB_BASE_IDX 2
|
#define mmDPG5_DPG_OFFSET_SEGMENT 0x1a1c
|
#define mmDPG5_DPG_OFFSET_SEGMENT_BASE_IDX 2
|
#define mmDPG5_DPG_STATUS 0x1a1d
|
#define mmDPG5_DPG_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_oppbuf5_dispdec
|
// base address: 0x708
|
#define mmOPPBUF5_OPPBUF_CONTROL 0x1a46
|
#define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47
|
#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48
|
#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
|
#define mmOPPBUF5_OPPBUF_CONTROL1 0x1a4b
|
#define mmOPPBUF5_OPPBUF_CONTROL1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe5_dispdec
|
// base address: 0x708
|
#define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e
|
#define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
|
// base address: 0x708
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_top_dispdec
|
// base address: 0x0
|
#define mmOPP_TOP_CLK_CONTROL 0x1a5e
|
#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dscrm0_dispdec
|
// base address: 0x0
|
#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG 0x1a64
|
#define mmDSCRM0_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dscrm1_dispdec
|
// base address: 0x4
|
#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG 0x1a65
|
#define mmDSCRM1_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dscrm2_dispdec
|
// base address: 0x8
|
#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG 0x1a66
|
#define mmDSCRM2_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dscrm3_dispdec
|
// base address: 0xc
|
#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG 0x1a67
|
#define mmDSCRM3_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dscrm4_dispdec
|
// base address: 0x10
|
#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG 0x1a68
|
#define mmDSCRM4_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_dscrm5_dispdec
|
// base address: 0x14
|
#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG 0x1a69
|
#define mmDSCRM5_DSCRM_DSC_FORWARD_CONFIG_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x6af8
|
#define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1abe
|
#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1abf
|
#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1ac0
|
#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON18_PERFMON_CNTL 0x1ac1
|
#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON18_PERFMON_CNTL2 0x1ac2
|
#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1ac3
|
#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1ac4
|
#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON18_PERFMON_HI 0x1ac5
|
#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON18_PERFMON_LOW 0x1ac6
|
#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_odm0_dispdec
|
// base address: 0x0
|
#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca
|
#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
|
#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb
|
#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
|
#define mmODM0_OPTC_DATA_FORMAT_CONTROL 0x1acc
|
#define mmODM0_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
|
#define mmODM0_OPTC_BYTES_PER_PIXEL 0x1acd
|
#define mmODM0_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmODM0_OPTC_WIDTH_CONTROL 0x1ace
|
#define mmODM0_OPTC_WIDTH_CONTROL_BASE_IDX 2
|
#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acf
|
#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
|
#define mmODM0_OPTC_MEMORY_CONFIG 0x1ad0
|
#define mmODM0_OPTC_MEMORY_CONFIG_BASE_IDX 2
|
#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1ad1
|
#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_odm1_dispdec
|
// base address: 0x40
|
#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada
|
#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
|
#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb
|
#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
|
#define mmODM1_OPTC_DATA_FORMAT_CONTROL 0x1adc
|
#define mmODM1_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
|
#define mmODM1_OPTC_BYTES_PER_PIXEL 0x1add
|
#define mmODM1_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmODM1_OPTC_WIDTH_CONTROL 0x1ade
|
#define mmODM1_OPTC_WIDTH_CONTROL_BASE_IDX 2
|
#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1adf
|
#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
|
#define mmODM1_OPTC_MEMORY_CONFIG 0x1ae0
|
#define mmODM1_OPTC_MEMORY_CONFIG_BASE_IDX 2
|
#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1ae1
|
#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_odm2_dispdec
|
// base address: 0x80
|
#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea
|
#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
|
#define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb
|
#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
|
#define mmODM2_OPTC_DATA_FORMAT_CONTROL 0x1aec
|
#define mmODM2_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
|
#define mmODM2_OPTC_BYTES_PER_PIXEL 0x1aed
|
#define mmODM2_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmODM2_OPTC_WIDTH_CONTROL 0x1aee
|
#define mmODM2_OPTC_WIDTH_CONTROL_BASE_IDX 2
|
#define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aef
|
#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
|
#define mmODM2_OPTC_MEMORY_CONFIG 0x1af0
|
#define mmODM2_OPTC_MEMORY_CONFIG_BASE_IDX 2
|
#define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1af1
|
#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_odm3_dispdec
|
// base address: 0xc0
|
#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa
|
#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
|
#define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb
|
#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
|
#define mmODM3_OPTC_DATA_FORMAT_CONTROL 0x1afc
|
#define mmODM3_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
|
#define mmODM3_OPTC_BYTES_PER_PIXEL 0x1afd
|
#define mmODM3_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmODM3_OPTC_WIDTH_CONTROL 0x1afe
|
#define mmODM3_OPTC_WIDTH_CONTROL_BASE_IDX 2
|
#define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1aff
|
#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
|
#define mmODM3_OPTC_MEMORY_CONFIG 0x1b00
|
#define mmODM3_OPTC_MEMORY_CONFIG_BASE_IDX 2
|
#define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1b01
|
#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_odm4_dispdec
|
// base address: 0x100
|
#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a
|
#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
|
#define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b
|
#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
|
#define mmODM4_OPTC_DATA_FORMAT_CONTROL 0x1b0c
|
#define mmODM4_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
|
#define mmODM4_OPTC_BYTES_PER_PIXEL 0x1b0d
|
#define mmODM4_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmODM4_OPTC_WIDTH_CONTROL 0x1b0e
|
#define mmODM4_OPTC_WIDTH_CONTROL_BASE_IDX 2
|
#define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0f
|
#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
|
#define mmODM4_OPTC_MEMORY_CONFIG 0x1b10
|
#define mmODM4_OPTC_MEMORY_CONFIG_BASE_IDX 2
|
#define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b11
|
#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_odm5_dispdec
|
// base address: 0x140
|
#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a
|
#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
|
#define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b
|
#define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
|
#define mmODM5_OPTC_DATA_FORMAT_CONTROL 0x1b1c
|
#define mmODM5_OPTC_DATA_FORMAT_CONTROL_BASE_IDX 2
|
#define mmODM5_OPTC_BYTES_PER_PIXEL 0x1b1d
|
#define mmODM5_OPTC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmODM5_OPTC_WIDTH_CONTROL 0x1b1e
|
#define mmODM5_OPTC_WIDTH_CONTROL_BASE_IDX 2
|
#define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1f
|
#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
|
#define mmODM5_OPTC_MEMORY_CONFIG 0x1b20
|
#define mmODM5_OPTC_MEMORY_CONFIG_BASE_IDX 2
|
#define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b21
|
#define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_otg0_dispdec
|
// base address: 0x0
|
#define mmOTG0_OTG_H_TOTAL 0x1b2a
|
#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2
|
#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b
|
#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2
|
#define mmOTG0_OTG_H_SYNC_A 0x1b2c
|
#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2
|
#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d
|
#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e
|
#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2
|
#define mmOTG0_OTG_V_TOTAL 0x1b2f
|
#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2
|
#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30
|
#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2
|
#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31
|
#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2
|
#define mmOTG0_OTG_V_TOTAL_MID 0x1b32
|
#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2
|
#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33
|
#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34
|
#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
|
#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35
|
#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
|
#define mmOTG0_OTG_V_BLANK_START_END 0x1b36
|
#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2
|
#define mmOTG0_OTG_V_SYNC_A 0x1b37
|
#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2
|
#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38
|
#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG0_OTG_TRIGA_CNTL 0x1b39
|
#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2
|
#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a
|
#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b
|
#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2
|
#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c
|
#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d
|
#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
|
#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e
|
#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f
|
#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
|
#define mmOTG0_OTG_CONTROL 0x1b41
|
#define mmOTG0_OTG_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_BLANK_CONTROL 0x1b42
|
#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_PIPE_ABORT_CONTROL 0x1b43
|
#define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44
|
#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45
|
#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2
|
#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47
|
#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
|
#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48
|
#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
|
#define mmOTG0_OTG_STATUS 0x1b49
|
#define mmOTG0_OTG_STATUS_BASE_IDX 2
|
#define mmOTG0_OTG_STATUS_POSITION 0x1b4a
|
#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2
|
#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b
|
#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2
|
#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c
|
#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
|
#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d
|
#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2
|
#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e
|
#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2
|
#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f
|
#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_COUNT_RESET 0x1b50
|
#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2
|
#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51
|
#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
|
#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52
|
#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_STEREO_STATUS 0x1b53
|
#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2
|
#define mmOTG0_OTG_STEREO_CONTROL 0x1b54
|
#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55
|
#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2
|
#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56
|
#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57
|
#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2
|
#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58
|
#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2
|
#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59
|
#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a
|
#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2
|
#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b
|
#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_MASTER_EN 0x1b5c
|
#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2
|
#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b5e
|
#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2
|
#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b5f
|
#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
|
#define mmOTG0_OTG_BLACK_COLOR 0x1b60
|
#define mmOTG0_OTG_BLACK_COLOR_BASE_IDX 2
|
#define mmOTG0_OTG_BLACK_COLOR_EXT 0x1b61
|
#define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX 2
|
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b62
|
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
|
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b63
|
#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b64
|
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
|
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b65
|
#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b66
|
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
|
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b67
|
#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_CRC_CNTL 0x1b68
|
#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2
|
#define mmOTG0_OTG_CRC_CNTL2 0x1b69
|
#define mmOTG0_OTG_CRC_CNTL2_BASE_IDX 2
|
#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6a
|
#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6b
|
#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6c
|
#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6d
|
#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_CRC0_DATA_RG 0x1b6e
|
#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2
|
#define mmOTG0_OTG_CRC0_DATA_B 0x1b6f
|
#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2
|
#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b70
|
#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b71
|
#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b72
|
#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b73
|
#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_CRC1_DATA_RG 0x1b74
|
#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2
|
#define mmOTG0_OTG_CRC1_DATA_B 0x1b75
|
#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2
|
#define mmOTG0_OTG_CRC2_DATA_RG 0x1b76
|
#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2
|
#define mmOTG0_OTG_CRC2_DATA_B 0x1b77
|
#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2
|
#define mmOTG0_OTG_CRC3_DATA_RG 0x1b78
|
#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2
|
#define mmOTG0_OTG_CRC3_DATA_B 0x1b79
|
#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2
|
#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7a
|
#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
|
#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7b
|
#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
|
#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b82
|
#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b83
|
#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b84
|
#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2
|
#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b85
|
#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
|
#define mmOTG0_OTG_CLOCK_CONTROL 0x1b86
|
#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b87
|
#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2
|
#define mmOTG0_OTG_VUPDATE_PARAM 0x1b88
|
#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2
|
#define mmOTG0_OTG_VREADY_PARAM 0x1b89
|
#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2
|
#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8a
|
#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
|
#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8b
|
#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
|
#define mmOTG0_OTG_GSL_CONTROL 0x1b8c
|
#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8d
|
#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2
|
#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b8e
|
#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2
|
#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b8f
|
#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
|
#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b90
|
#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2
|
#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b91
|
#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2
|
#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b92
|
#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2
|
#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b93
|
#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2
|
#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b94
|
#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b95
|
#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS 0x1b96
|
#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
|
#define mmOTG0_OTG_DRR_CONTROL 0x1b97
|
#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_REQUEST_CONTROL 0x1b98
|
#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2
|
#define mmOTG0_OTG_DSC_START_POSITION 0x1b99
|
#define mmOTG0_OTG_DSC_START_POSITION_BASE_IDX 2
|
#define mmOTG0_OTG_PIPE_UPDATE_STATUS 0x1b9a
|
#define mmOTG0_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
|
#define mmOTG0_OTG_SPARE_REGISTER 0x1b9c
|
#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_otg1_dispdec
|
// base address: 0x200
|
#define mmOTG1_OTG_H_TOTAL 0x1baa
|
#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2
|
#define mmOTG1_OTG_H_BLANK_START_END 0x1bab
|
#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2
|
#define mmOTG1_OTG_H_SYNC_A 0x1bac
|
#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2
|
#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad
|
#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae
|
#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2
|
#define mmOTG1_OTG_V_TOTAL 0x1baf
|
#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2
|
#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0
|
#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2
|
#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1
|
#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2
|
#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2
|
#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2
|
#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3
|
#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4
|
#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
|
#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5
|
#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
|
#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6
|
#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2
|
#define mmOTG1_OTG_V_SYNC_A 0x1bb7
|
#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2
|
#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8
|
#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9
|
#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2
|
#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba
|
#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb
|
#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2
|
#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc
|
#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd
|
#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
|
#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe
|
#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf
|
#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
|
#define mmOTG1_OTG_CONTROL 0x1bc1
|
#define mmOTG1_OTG_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2
|
#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_PIPE_ABORT_CONTROL 0x1bc3
|
#define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4
|
#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5
|
#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2
|
#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7
|
#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
|
#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8
|
#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
|
#define mmOTG1_OTG_STATUS 0x1bc9
|
#define mmOTG1_OTG_STATUS_BASE_IDX 2
|
#define mmOTG1_OTG_STATUS_POSITION 0x1bca
|
#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2
|
#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb
|
#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2
|
#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc
|
#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
|
#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd
|
#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2
|
#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce
|
#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2
|
#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf
|
#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_COUNT_RESET 0x1bd0
|
#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2
|
#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1
|
#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
|
#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2
|
#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_STEREO_STATUS 0x1bd3
|
#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2
|
#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4
|
#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5
|
#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2
|
#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6
|
#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7
|
#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2
|
#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8
|
#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2
|
#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9
|
#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_UPDATE_LOCK 0x1bda
|
#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2
|
#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb
|
#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_MASTER_EN 0x1bdc
|
#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2
|
#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1bde
|
#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2
|
#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1bdf
|
#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
|
#define mmOTG1_OTG_BLACK_COLOR 0x1be0
|
#define mmOTG1_OTG_BLACK_COLOR_BASE_IDX 2
|
#define mmOTG1_OTG_BLACK_COLOR_EXT 0x1be1
|
#define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX 2
|
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be2
|
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
|
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be3
|
#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be4
|
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
|
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be5
|
#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be6
|
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
|
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1be7
|
#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_CRC_CNTL 0x1be8
|
#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2
|
#define mmOTG1_OTG_CRC_CNTL2 0x1be9
|
#define mmOTG1_OTG_CRC_CNTL2_BASE_IDX 2
|
#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bea
|
#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1beb
|
#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bec
|
#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bed
|
#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_CRC0_DATA_RG 0x1bee
|
#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2
|
#define mmOTG1_OTG_CRC0_DATA_B 0x1bef
|
#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2
|
#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf0
|
#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf1
|
#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf2
|
#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf3
|
#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf4
|
#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2
|
#define mmOTG1_OTG_CRC1_DATA_B 0x1bf5
|
#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2
|
#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf6
|
#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2
|
#define mmOTG1_OTG_CRC2_DATA_B 0x1bf7
|
#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2
|
#define mmOTG1_OTG_CRC3_DATA_RG 0x1bf8
|
#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2
|
#define mmOTG1_OTG_CRC3_DATA_B 0x1bf9
|
#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2
|
#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfa
|
#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
|
#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfb
|
#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
|
#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c02
|
#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c03
|
#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c04
|
#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2
|
#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c05
|
#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
|
#define mmOTG1_OTG_CLOCK_CONTROL 0x1c06
|
#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c07
|
#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2
|
#define mmOTG1_OTG_VUPDATE_PARAM 0x1c08
|
#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2
|
#define mmOTG1_OTG_VREADY_PARAM 0x1c09
|
#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2
|
#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0a
|
#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
|
#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0b
|
#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
|
#define mmOTG1_OTG_GSL_CONTROL 0x1c0c
|
#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0d
|
#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2
|
#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c0e
|
#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2
|
#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c0f
|
#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
|
#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c10
|
#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2
|
#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c11
|
#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2
|
#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c12
|
#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2
|
#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c13
|
#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2
|
#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c14
|
#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c15
|
#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS 0x1c16
|
#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
|
#define mmOTG1_OTG_DRR_CONTROL 0x1c17
|
#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_REQUEST_CONTROL 0x1c18
|
#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_DSC_START_POSITION 0x1c19
|
#define mmOTG1_OTG_DSC_START_POSITION_BASE_IDX 2
|
#define mmOTG1_OTG_PIPE_UPDATE_STATUS 0x1c1a
|
#define mmOTG1_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
|
#define mmOTG1_OTG_SPARE_REGISTER 0x1c1c
|
#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_otg2_dispdec
|
// base address: 0x400
|
#define mmOTG2_OTG_H_TOTAL 0x1c2a
|
#define mmOTG2_OTG_H_TOTAL_BASE_IDX 2
|
#define mmOTG2_OTG_H_BLANK_START_END 0x1c2b
|
#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2
|
#define mmOTG2_OTG_H_SYNC_A 0x1c2c
|
#define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2
|
#define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d
|
#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e
|
#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2
|
#define mmOTG2_OTG_V_TOTAL 0x1c2f
|
#define mmOTG2_OTG_V_TOTAL_BASE_IDX 2
|
#define mmOTG2_OTG_V_TOTAL_MIN 0x1c30
|
#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2
|
#define mmOTG2_OTG_V_TOTAL_MAX 0x1c31
|
#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2
|
#define mmOTG2_OTG_V_TOTAL_MID 0x1c32
|
#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2
|
#define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33
|
#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34
|
#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
|
#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35
|
#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
|
#define mmOTG2_OTG_V_BLANK_START_END 0x1c36
|
#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2
|
#define mmOTG2_OTG_V_SYNC_A 0x1c37
|
#define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2
|
#define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38
|
#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG2_OTG_TRIGA_CNTL 0x1c39
|
#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2
|
#define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a
|
#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG2_OTG_TRIGB_CNTL 0x1c3b
|
#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2
|
#define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c
|
#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d
|
#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
|
#define mmOTG2_OTG_FLOW_CONTROL 0x1c3e
|
#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f
|
#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
|
#define mmOTG2_OTG_CONTROL 0x1c41
|
#define mmOTG2_OTG_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_BLANK_CONTROL 0x1c42
|
#define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_PIPE_ABORT_CONTROL 0x1c43
|
#define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44
|
#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_INTERLACE_STATUS 0x1c45
|
#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2
|
#define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47
|
#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
|
#define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48
|
#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
|
#define mmOTG2_OTG_STATUS 0x1c49
|
#define mmOTG2_OTG_STATUS_BASE_IDX 2
|
#define mmOTG2_OTG_STATUS_POSITION 0x1c4a
|
#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2
|
#define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b
|
#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2
|
#define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c
|
#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
|
#define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d
|
#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2
|
#define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e
|
#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2
|
#define mmOTG2_OTG_COUNT_CONTROL 0x1c4f
|
#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_COUNT_RESET 0x1c50
|
#define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2
|
#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51
|
#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
|
#define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52
|
#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_STEREO_STATUS 0x1c53
|
#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2
|
#define mmOTG2_OTG_STEREO_CONTROL 0x1c54
|
#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55
|
#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2
|
#define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56
|
#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57
|
#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2
|
#define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58
|
#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2
|
#define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59
|
#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_UPDATE_LOCK 0x1c5a
|
#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2
|
#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b
|
#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_MASTER_EN 0x1c5c
|
#define mmOTG2_OTG_MASTER_EN_BASE_IDX 2
|
#define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c5e
|
#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2
|
#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c5f
|
#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
|
#define mmOTG2_OTG_BLACK_COLOR 0x1c60
|
#define mmOTG2_OTG_BLACK_COLOR_BASE_IDX 2
|
#define mmOTG2_OTG_BLACK_COLOR_EXT 0x1c61
|
#define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX 2
|
#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c62
|
#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
|
#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c63
|
#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c64
|
#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
|
#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c65
|
#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c66
|
#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
|
#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c67
|
#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_CRC_CNTL 0x1c68
|
#define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2
|
#define mmOTG2_OTG_CRC_CNTL2 0x1c69
|
#define mmOTG2_OTG_CRC_CNTL2_BASE_IDX 2
|
#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6a
|
#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6b
|
#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6c
|
#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6d
|
#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_CRC0_DATA_RG 0x1c6e
|
#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2
|
#define mmOTG2_OTG_CRC0_DATA_B 0x1c6f
|
#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2
|
#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c70
|
#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c71
|
#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c72
|
#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c73
|
#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_CRC1_DATA_RG 0x1c74
|
#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2
|
#define mmOTG2_OTG_CRC1_DATA_B 0x1c75
|
#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2
|
#define mmOTG2_OTG_CRC2_DATA_RG 0x1c76
|
#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2
|
#define mmOTG2_OTG_CRC2_DATA_B 0x1c77
|
#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2
|
#define mmOTG2_OTG_CRC3_DATA_RG 0x1c78
|
#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2
|
#define mmOTG2_OTG_CRC3_DATA_B 0x1c79
|
#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2
|
#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7a
|
#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
|
#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7b
|
#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
|
#define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c82
|
#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c83
|
#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c84
|
#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2
|
#define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c85
|
#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
|
#define mmOTG2_OTG_CLOCK_CONTROL 0x1c86
|
#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_VSTARTUP_PARAM 0x1c87
|
#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2
|
#define mmOTG2_OTG_VUPDATE_PARAM 0x1c88
|
#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2
|
#define mmOTG2_OTG_VREADY_PARAM 0x1c89
|
#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2
|
#define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8a
|
#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
|
#define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8b
|
#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
|
#define mmOTG2_OTG_GSL_CONTROL 0x1c8c
|
#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_GSL_WINDOW_X 0x1c8d
|
#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2
|
#define mmOTG2_OTG_GSL_WINDOW_Y 0x1c8e
|
#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2
|
#define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c8f
|
#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
|
#define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c90
|
#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2
|
#define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c91
|
#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2
|
#define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c92
|
#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2
|
#define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c93
|
#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2
|
#define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c94
|
#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c95
|
#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS 0x1c96
|
#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
|
#define mmOTG2_OTG_DRR_CONTROL 0x1c97
|
#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_REQUEST_CONTROL 0x1c98
|
#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2
|
#define mmOTG2_OTG_DSC_START_POSITION 0x1c99
|
#define mmOTG2_OTG_DSC_START_POSITION_BASE_IDX 2
|
#define mmOTG2_OTG_PIPE_UPDATE_STATUS 0x1c9a
|
#define mmOTG2_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
|
#define mmOTG2_OTG_SPARE_REGISTER 0x1c9c
|
#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_otg3_dispdec
|
// base address: 0x600
|
#define mmOTG3_OTG_H_TOTAL 0x1caa
|
#define mmOTG3_OTG_H_TOTAL_BASE_IDX 2
|
#define mmOTG3_OTG_H_BLANK_START_END 0x1cab
|
#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2
|
#define mmOTG3_OTG_H_SYNC_A 0x1cac
|
#define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2
|
#define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad
|
#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG3_OTG_H_TIMING_CNTL 0x1cae
|
#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2
|
#define mmOTG3_OTG_V_TOTAL 0x1caf
|
#define mmOTG3_OTG_V_TOTAL_BASE_IDX 2
|
#define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0
|
#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2
|
#define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1
|
#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2
|
#define mmOTG3_OTG_V_TOTAL_MID 0x1cb2
|
#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2
|
#define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3
|
#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4
|
#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
|
#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5
|
#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
|
#define mmOTG3_OTG_V_BLANK_START_END 0x1cb6
|
#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2
|
#define mmOTG3_OTG_V_SYNC_A 0x1cb7
|
#define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2
|
#define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8
|
#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG3_OTG_TRIGA_CNTL 0x1cb9
|
#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2
|
#define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba
|
#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG3_OTG_TRIGB_CNTL 0x1cbb
|
#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2
|
#define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc
|
#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd
|
#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
|
#define mmOTG3_OTG_FLOW_CONTROL 0x1cbe
|
#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf
|
#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
|
#define mmOTG3_OTG_CONTROL 0x1cc1
|
#define mmOTG3_OTG_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_BLANK_CONTROL 0x1cc2
|
#define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_PIPE_ABORT_CONTROL 0x1cc3
|
#define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4
|
#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5
|
#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2
|
#define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7
|
#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
|
#define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8
|
#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
|
#define mmOTG3_OTG_STATUS 0x1cc9
|
#define mmOTG3_OTG_STATUS_BASE_IDX 2
|
#define mmOTG3_OTG_STATUS_POSITION 0x1cca
|
#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2
|
#define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb
|
#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2
|
#define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc
|
#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
|
#define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd
|
#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2
|
#define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce
|
#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2
|
#define mmOTG3_OTG_COUNT_CONTROL 0x1ccf
|
#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_COUNT_RESET 0x1cd0
|
#define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2
|
#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1
|
#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
|
#define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2
|
#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_STEREO_STATUS 0x1cd3
|
#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2
|
#define mmOTG3_OTG_STEREO_CONTROL 0x1cd4
|
#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5
|
#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2
|
#define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6
|
#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7
|
#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2
|
#define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8
|
#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2
|
#define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9
|
#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_UPDATE_LOCK 0x1cda
|
#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2
|
#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb
|
#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_MASTER_EN 0x1cdc
|
#define mmOTG3_OTG_MASTER_EN_BASE_IDX 2
|
#define mmOTG3_OTG_BLANK_DATA_COLOR 0x1cde
|
#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2
|
#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1cdf
|
#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
|
#define mmOTG3_OTG_BLACK_COLOR 0x1ce0
|
#define mmOTG3_OTG_BLACK_COLOR_BASE_IDX 2
|
#define mmOTG3_OTG_BLACK_COLOR_EXT 0x1ce1
|
#define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX 2
|
#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce2
|
#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
|
#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce3
|
#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce4
|
#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
|
#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce5
|
#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce6
|
#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
|
#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1ce7
|
#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_CRC_CNTL 0x1ce8
|
#define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2
|
#define mmOTG3_OTG_CRC_CNTL2 0x1ce9
|
#define mmOTG3_OTG_CRC_CNTL2_BASE_IDX 2
|
#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cea
|
#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ceb
|
#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cec
|
#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ced
|
#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_CRC0_DATA_RG 0x1cee
|
#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2
|
#define mmOTG3_OTG_CRC0_DATA_B 0x1cef
|
#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2
|
#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf0
|
#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf1
|
#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf2
|
#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf3
|
#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_CRC1_DATA_RG 0x1cf4
|
#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2
|
#define mmOTG3_OTG_CRC1_DATA_B 0x1cf5
|
#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2
|
#define mmOTG3_OTG_CRC2_DATA_RG 0x1cf6
|
#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2
|
#define mmOTG3_OTG_CRC2_DATA_B 0x1cf7
|
#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2
|
#define mmOTG3_OTG_CRC3_DATA_RG 0x1cf8
|
#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2
|
#define mmOTG3_OTG_CRC3_DATA_B 0x1cf9
|
#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2
|
#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfa
|
#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
|
#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfb
|
#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
|
#define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d02
|
#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d03
|
#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d04
|
#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2
|
#define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d05
|
#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
|
#define mmOTG3_OTG_CLOCK_CONTROL 0x1d06
|
#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_VSTARTUP_PARAM 0x1d07
|
#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2
|
#define mmOTG3_OTG_VUPDATE_PARAM 0x1d08
|
#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2
|
#define mmOTG3_OTG_VREADY_PARAM 0x1d09
|
#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2
|
#define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0a
|
#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
|
#define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0b
|
#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
|
#define mmOTG3_OTG_GSL_CONTROL 0x1d0c
|
#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_GSL_WINDOW_X 0x1d0d
|
#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2
|
#define mmOTG3_OTG_GSL_WINDOW_Y 0x1d0e
|
#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2
|
#define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d0f
|
#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
|
#define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d10
|
#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2
|
#define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d11
|
#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2
|
#define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d12
|
#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2
|
#define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d13
|
#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2
|
#define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d14
|
#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d15
|
#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS 0x1d16
|
#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
|
#define mmOTG3_OTG_DRR_CONTROL 0x1d17
|
#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_REQUEST_CONTROL 0x1d18
|
#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2
|
#define mmOTG3_OTG_DSC_START_POSITION 0x1d19
|
#define mmOTG3_OTG_DSC_START_POSITION_BASE_IDX 2
|
#define mmOTG3_OTG_PIPE_UPDATE_STATUS 0x1d1a
|
#define mmOTG3_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
|
#define mmOTG3_OTG_SPARE_REGISTER 0x1d1c
|
#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_otg4_dispdec
|
// base address: 0x800
|
#define mmOTG4_OTG_H_TOTAL 0x1d2a
|
#define mmOTG4_OTG_H_TOTAL_BASE_IDX 2
|
#define mmOTG4_OTG_H_BLANK_START_END 0x1d2b
|
#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2
|
#define mmOTG4_OTG_H_SYNC_A 0x1d2c
|
#define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2
|
#define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d
|
#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e
|
#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2
|
#define mmOTG4_OTG_V_TOTAL 0x1d2f
|
#define mmOTG4_OTG_V_TOTAL_BASE_IDX 2
|
#define mmOTG4_OTG_V_TOTAL_MIN 0x1d30
|
#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2
|
#define mmOTG4_OTG_V_TOTAL_MAX 0x1d31
|
#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2
|
#define mmOTG4_OTG_V_TOTAL_MID 0x1d32
|
#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2
|
#define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33
|
#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34
|
#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
|
#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35
|
#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
|
#define mmOTG4_OTG_V_BLANK_START_END 0x1d36
|
#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2
|
#define mmOTG4_OTG_V_SYNC_A 0x1d37
|
#define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2
|
#define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38
|
#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG4_OTG_TRIGA_CNTL 0x1d39
|
#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2
|
#define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a
|
#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG4_OTG_TRIGB_CNTL 0x1d3b
|
#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2
|
#define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c
|
#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d
|
#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
|
#define mmOTG4_OTG_FLOW_CONTROL 0x1d3e
|
#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f
|
#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
|
#define mmOTG4_OTG_CONTROL 0x1d41
|
#define mmOTG4_OTG_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_BLANK_CONTROL 0x1d42
|
#define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_PIPE_ABORT_CONTROL 0x1d43
|
#define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44
|
#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_INTERLACE_STATUS 0x1d45
|
#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2
|
#define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47
|
#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
|
#define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48
|
#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
|
#define mmOTG4_OTG_STATUS 0x1d49
|
#define mmOTG4_OTG_STATUS_BASE_IDX 2
|
#define mmOTG4_OTG_STATUS_POSITION 0x1d4a
|
#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2
|
#define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b
|
#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2
|
#define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c
|
#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
|
#define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d
|
#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2
|
#define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e
|
#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2
|
#define mmOTG4_OTG_COUNT_CONTROL 0x1d4f
|
#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_COUNT_RESET 0x1d50
|
#define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2
|
#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51
|
#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
|
#define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52
|
#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_STEREO_STATUS 0x1d53
|
#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2
|
#define mmOTG4_OTG_STEREO_CONTROL 0x1d54
|
#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55
|
#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2
|
#define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56
|
#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57
|
#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2
|
#define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58
|
#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2
|
#define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59
|
#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_UPDATE_LOCK 0x1d5a
|
#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2
|
#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b
|
#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_MASTER_EN 0x1d5c
|
#define mmOTG4_OTG_MASTER_EN_BASE_IDX 2
|
#define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d5e
|
#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2
|
#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d5f
|
#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
|
#define mmOTG4_OTG_BLACK_COLOR 0x1d60
|
#define mmOTG4_OTG_BLACK_COLOR_BASE_IDX 2
|
#define mmOTG4_OTG_BLACK_COLOR_EXT 0x1d61
|
#define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX 2
|
#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d62
|
#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
|
#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d63
|
#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d64
|
#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
|
#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d65
|
#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d66
|
#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
|
#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d67
|
#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_CRC_CNTL 0x1d68
|
#define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2
|
#define mmOTG4_OTG_CRC_CNTL2 0x1d69
|
#define mmOTG4_OTG_CRC_CNTL2_BASE_IDX 2
|
#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6a
|
#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6b
|
#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6c
|
#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6d
|
#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_CRC0_DATA_RG 0x1d6e
|
#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2
|
#define mmOTG4_OTG_CRC0_DATA_B 0x1d6f
|
#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2
|
#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d70
|
#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d71
|
#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d72
|
#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d73
|
#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_CRC1_DATA_RG 0x1d74
|
#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2
|
#define mmOTG4_OTG_CRC1_DATA_B 0x1d75
|
#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2
|
#define mmOTG4_OTG_CRC2_DATA_RG 0x1d76
|
#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2
|
#define mmOTG4_OTG_CRC2_DATA_B 0x1d77
|
#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2
|
#define mmOTG4_OTG_CRC3_DATA_RG 0x1d78
|
#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2
|
#define mmOTG4_OTG_CRC3_DATA_B 0x1d79
|
#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2
|
#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7a
|
#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
|
#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7b
|
#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
|
#define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d82
|
#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d83
|
#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d84
|
#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2
|
#define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d85
|
#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
|
#define mmOTG4_OTG_CLOCK_CONTROL 0x1d86
|
#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_VSTARTUP_PARAM 0x1d87
|
#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2
|
#define mmOTG4_OTG_VUPDATE_PARAM 0x1d88
|
#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2
|
#define mmOTG4_OTG_VREADY_PARAM 0x1d89
|
#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2
|
#define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8a
|
#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
|
#define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8b
|
#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
|
#define mmOTG4_OTG_GSL_CONTROL 0x1d8c
|
#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_GSL_WINDOW_X 0x1d8d
|
#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2
|
#define mmOTG4_OTG_GSL_WINDOW_Y 0x1d8e
|
#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2
|
#define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d8f
|
#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
|
#define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d90
|
#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2
|
#define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d91
|
#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2
|
#define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d92
|
#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2
|
#define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d93
|
#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2
|
#define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d94
|
#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d95
|
#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS 0x1d96
|
#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
|
#define mmOTG4_OTG_DRR_CONTROL 0x1d97
|
#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_REQUEST_CONTROL 0x1d98
|
#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2
|
#define mmOTG4_OTG_DSC_START_POSITION 0x1d99
|
#define mmOTG4_OTG_DSC_START_POSITION_BASE_IDX 2
|
#define mmOTG4_OTG_PIPE_UPDATE_STATUS 0x1d9a
|
#define mmOTG4_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
|
#define mmOTG4_OTG_SPARE_REGISTER 0x1d9c
|
#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_otg5_dispdec
|
// base address: 0xa00
|
#define mmOTG5_OTG_H_TOTAL 0x1daa
|
#define mmOTG5_OTG_H_TOTAL_BASE_IDX 2
|
#define mmOTG5_OTG_H_BLANK_START_END 0x1dab
|
#define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2
|
#define mmOTG5_OTG_H_SYNC_A 0x1dac
|
#define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2
|
#define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad
|
#define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG5_OTG_H_TIMING_CNTL 0x1dae
|
#define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2
|
#define mmOTG5_OTG_V_TOTAL 0x1daf
|
#define mmOTG5_OTG_V_TOTAL_BASE_IDX 2
|
#define mmOTG5_OTG_V_TOTAL_MIN 0x1db0
|
#define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2
|
#define mmOTG5_OTG_V_TOTAL_MAX 0x1db1
|
#define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2
|
#define mmOTG5_OTG_V_TOTAL_MID 0x1db2
|
#define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2
|
#define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3
|
#define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4
|
#define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
|
#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5
|
#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
|
#define mmOTG5_OTG_V_BLANK_START_END 0x1db6
|
#define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2
|
#define mmOTG5_OTG_V_SYNC_A 0x1db7
|
#define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2
|
#define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8
|
#define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG5_OTG_TRIGA_CNTL 0x1db9
|
#define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2
|
#define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba
|
#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG5_OTG_TRIGB_CNTL 0x1dbb
|
#define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2
|
#define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc
|
#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd
|
#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
|
#define mmOTG5_OTG_FLOW_CONTROL 0x1dbe
|
#define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf
|
#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
|
#define mmOTG5_OTG_CONTROL 0x1dc1
|
#define mmOTG5_OTG_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_BLANK_CONTROL 0x1dc2
|
#define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_PIPE_ABORT_CONTROL 0x1dc3
|
#define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4
|
#define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5
|
#define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2
|
#define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7
|
#define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
|
#define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8
|
#define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
|
#define mmOTG5_OTG_STATUS 0x1dc9
|
#define mmOTG5_OTG_STATUS_BASE_IDX 2
|
#define mmOTG5_OTG_STATUS_POSITION 0x1dca
|
#define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2
|
#define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb
|
#define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2
|
#define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc
|
#define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
|
#define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd
|
#define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2
|
#define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce
|
#define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2
|
#define mmOTG5_OTG_COUNT_CONTROL 0x1dcf
|
#define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_COUNT_RESET 0x1dd0
|
#define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2
|
#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1
|
#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
|
#define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2
|
#define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_STEREO_STATUS 0x1dd3
|
#define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2
|
#define mmOTG5_OTG_STEREO_CONTROL 0x1dd4
|
#define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5
|
#define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2
|
#define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6
|
#define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7
|
#define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2
|
#define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8
|
#define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2
|
#define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9
|
#define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_UPDATE_LOCK 0x1dda
|
#define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2
|
#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb
|
#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_MASTER_EN 0x1ddc
|
#define mmOTG5_OTG_MASTER_EN_BASE_IDX 2
|
#define mmOTG5_OTG_BLANK_DATA_COLOR 0x1dde
|
#define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2
|
#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1ddf
|
#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
|
#define mmOTG5_OTG_BLACK_COLOR 0x1de0
|
#define mmOTG5_OTG_BLACK_COLOR_BASE_IDX 2
|
#define mmOTG5_OTG_BLACK_COLOR_EXT 0x1de1
|
#define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX 2
|
#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de2
|
#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
|
#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de3
|
#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de4
|
#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
|
#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de5
|
#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de6
|
#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
|
#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1de7
|
#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_CRC_CNTL 0x1de8
|
#define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2
|
#define mmOTG5_OTG_CRC_CNTL2 0x1de9
|
#define mmOTG5_OTG_CRC_CNTL2_BASE_IDX 2
|
#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dea
|
#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1deb
|
#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dec
|
#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1ded
|
#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_CRC0_DATA_RG 0x1dee
|
#define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2
|
#define mmOTG5_OTG_CRC0_DATA_B 0x1def
|
#define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2
|
#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df0
|
#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df1
|
#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df2
|
#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df3
|
#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_CRC1_DATA_RG 0x1df4
|
#define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2
|
#define mmOTG5_OTG_CRC1_DATA_B 0x1df5
|
#define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2
|
#define mmOTG5_OTG_CRC2_DATA_RG 0x1df6
|
#define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2
|
#define mmOTG5_OTG_CRC2_DATA_B 0x1df7
|
#define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2
|
#define mmOTG5_OTG_CRC3_DATA_RG 0x1df8
|
#define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2
|
#define mmOTG5_OTG_CRC3_DATA_B 0x1df9
|
#define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2
|
#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfa
|
#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
|
#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfb
|
#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
|
#define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e02
|
#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e03
|
#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e04
|
#define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2
|
#define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e05
|
#define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
|
#define mmOTG5_OTG_CLOCK_CONTROL 0x1e06
|
#define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_VSTARTUP_PARAM 0x1e07
|
#define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2
|
#define mmOTG5_OTG_VUPDATE_PARAM 0x1e08
|
#define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2
|
#define mmOTG5_OTG_VREADY_PARAM 0x1e09
|
#define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2
|
#define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0a
|
#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
|
#define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0b
|
#define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
|
#define mmOTG5_OTG_GSL_CONTROL 0x1e0c
|
#define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_GSL_WINDOW_X 0x1e0d
|
#define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2
|
#define mmOTG5_OTG_GSL_WINDOW_Y 0x1e0e
|
#define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2
|
#define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e0f
|
#define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
|
#define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e10
|
#define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2
|
#define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e11
|
#define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2
|
#define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e12
|
#define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2
|
#define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e13
|
#define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2
|
#define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e14
|
#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e15
|
#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS 0x1e16
|
#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
|
#define mmOTG5_OTG_DRR_CONTROL 0x1e17
|
#define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_REQUEST_CONTROL 0x1e18
|
#define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_DSC_START_POSITION 0x1e19
|
#define mmOTG5_OTG_DSC_START_POSITION_BASE_IDX 2
|
#define mmOTG5_OTG_PIPE_UPDATE_STATUS 0x1e1a
|
#define mmOTG5_OTG_PIPE_UPDATE_STATUS_BASE_IDX 2
|
#define mmOTG5_OTG_SPARE_REGISTER 0x1e1c
|
#define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_optc_misc_dispdec
|
// base address: 0x0
|
#define mmDWB_SOURCE_SELECT 0x1e2a
|
#define mmDWB_SOURCE_SELECT_BASE_IDX 2
|
#define mmGSL_SOURCE_SELECT 0x1e2b
|
#define mmGSL_SOURCE_SELECT_BASE_IDX 2
|
#define mmOPTC_CLOCK_CONTROL 0x1e2c
|
#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2
|
#define mmODM_MEM_PWR_CTRL 0x1e2d
|
#define mmODM_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmODM_MEM_PWR_CTRL2 0x1e2e
|
#define mmODM_MEM_PWR_CTRL2_BASE_IDX 2
|
#define mmODM_MEM_PWR_CTRL3 0x1e2f
|
#define mmODM_MEM_PWR_CTRL3_BASE_IDX 2
|
#define mmODM_MEM_PWR_STATUS 0x1e30
|
#define mmODM_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmOPTC_MISC_SPARE_REGISTER 0x1e31
|
#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x79a8
|
#define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x1e6a
|
#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x1e6b
|
#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON19_PERFCOUNTER_STATE 0x1e6c
|
#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON19_PERFMON_CNTL 0x1e6d
|
#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON19_PERFMON_CNTL2 0x1e6e
|
#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x1e6f
|
#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x1e70
|
#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON19_PERFMON_HI 0x1e71
|
#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON19_PERFMON_LOW 0x1e72
|
#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dout_i2c_dispdec
|
// base address: 0x0
|
#define mmDC_I2C_CONTROL 0x1e98
|
#define mmDC_I2C_CONTROL_BASE_IDX 2
|
#define mmDC_I2C_ARBITRATION 0x1e99
|
#define mmDC_I2C_ARBITRATION_BASE_IDX 2
|
#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a
|
#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDC_I2C_SW_STATUS 0x1e9b
|
#define mmDC_I2C_SW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c
|
#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d
|
#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC3_HW_STATUS 0x1e9e
|
#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC4_HW_STATUS 0x1e9f
|
#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC5_HW_STATUS 0x1ea0
|
#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC6_HW_STATUS 0x1ea1
|
#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC1_SPEED 0x1ea2
|
#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
|
#define mmDC_I2C_DDC1_SETUP 0x1ea3
|
#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
|
#define mmDC_I2C_DDC2_SPEED 0x1ea4
|
#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
|
#define mmDC_I2C_DDC2_SETUP 0x1ea5
|
#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
|
#define mmDC_I2C_DDC3_SPEED 0x1ea6
|
#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
|
#define mmDC_I2C_DDC3_SETUP 0x1ea7
|
#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
|
#define mmDC_I2C_DDC4_SPEED 0x1ea8
|
#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
|
#define mmDC_I2C_DDC4_SETUP 0x1ea9
|
#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
|
#define mmDC_I2C_DDC5_SPEED 0x1eaa
|
#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
|
#define mmDC_I2C_DDC5_SETUP 0x1eab
|
#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
|
#define mmDC_I2C_DDC6_SPEED 0x1eac
|
#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
|
#define mmDC_I2C_DDC6_SETUP 0x1ead
|
#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
|
#define mmDC_I2C_TRANSACTION0 0x1eae
|
#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
|
#define mmDC_I2C_TRANSACTION1 0x1eaf
|
#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
|
#define mmDC_I2C_TRANSACTION2 0x1eb0
|
#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
|
#define mmDC_I2C_TRANSACTION3 0x1eb1
|
#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
|
#define mmDC_I2C_DATA 0x1eb2
|
#define mmDC_I2C_DATA_BASE_IDX 2
|
#define mmDC_I2C_DDCVGA_SETUP 0x1eb5
|
#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2
|
#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6
|
#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
|
#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7
|
#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dio_misc_dispdec
|
// base address: 0x0
|
#define mmDIO_SCRATCH0 0x1eca
|
#define mmDIO_SCRATCH0_BASE_IDX 2
|
#define mmDIO_SCRATCH1 0x1ecb
|
#define mmDIO_SCRATCH1_BASE_IDX 2
|
#define mmDIO_SCRATCH2 0x1ecc
|
#define mmDIO_SCRATCH2_BASE_IDX 2
|
#define mmDIO_SCRATCH3 0x1ecd
|
#define mmDIO_SCRATCH3_BASE_IDX 2
|
#define mmDIO_SCRATCH4 0x1ece
|
#define mmDIO_SCRATCH4_BASE_IDX 2
|
#define mmDIO_SCRATCH5 0x1ecf
|
#define mmDIO_SCRATCH5_BASE_IDX 2
|
#define mmDIO_SCRATCH6 0x1ed0
|
#define mmDIO_SCRATCH6_BASE_IDX 2
|
#define mmDIO_SCRATCH7 0x1ed1
|
#define mmDIO_SCRATCH7_BASE_IDX 2
|
#define mmDCE_VCE_CONTROL 0x1ed2
|
#define mmDCE_VCE_CONTROL_BASE_IDX 2
|
#define mmDIO_MEM_PWR_STATUS 0x1edd
|
#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDIO_MEM_PWR_CTRL 0x1ede
|
#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDIO_MEM_PWR_CTRL2 0x1edf
|
#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2
|
#define mmDIO_CLK_CNTL 0x1ee0
|
#define mmDIO_CLK_CNTL_BASE_IDX 2
|
#define mmDIO_MEM_PWR_CTRL3 0x1ee1
|
#define mmDIO_MEM_PWR_CTRL3_BASE_IDX 2
|
#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4
|
#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
|
#define mmDIG_SOFT_RESET 0x1eee
|
#define mmDIG_SOFT_RESET_BASE_IDX 2
|
#define mmDIO_MEM_PWR_STATUS1 0x1ef0
|
#define mmDIO_MEM_PWR_STATUS1_BASE_IDX 2
|
#define mmDIO_CLK_CNTL2 0x1ef2
|
#define mmDIO_CLK_CNTL2_BASE_IDX 2
|
#define mmDIO_CLK_CNTL3 0x1ef3
|
#define mmDIO_CLK_CNTL3_BASE_IDX 2
|
#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff
|
#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
|
#define mmDIO_PSP_INTERRUPT_STATUS 0x1f00
|
#define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDIO_PSP_INTERRUPT_CLEAR 0x1f01
|
#define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
|
#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02
|
#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
|
#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03
|
#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_hpd0_dispdec
|
// base address: 0x0
|
#define mmHPD0_DC_HPD_INT_STATUS 0x1f14
|
#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
|
#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15
|
#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
|
#define mmHPD0_DC_HPD_CONTROL 0x1f16
|
#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
|
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17
|
#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
|
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18
|
#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_hpd1_dispdec
|
// base address: 0x20
|
#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c
|
#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
|
#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d
|
#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
|
#define mmHPD1_DC_HPD_CONTROL 0x1f1e
|
#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
|
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f
|
#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
|
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20
|
#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_hpd2_dispdec
|
// base address: 0x40
|
#define mmHPD2_DC_HPD_INT_STATUS 0x1f24
|
#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
|
#define mmHPD2_DC_HPD_INT_CONTROL 0x1f25
|
#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
|
#define mmHPD2_DC_HPD_CONTROL 0x1f26
|
#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
|
#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27
|
#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
|
#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28
|
#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_hpd3_dispdec
|
// base address: 0x60
|
#define mmHPD3_DC_HPD_INT_STATUS 0x1f2c
|
#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
|
#define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d
|
#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
|
#define mmHPD3_DC_HPD_CONTROL 0x1f2e
|
#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
|
#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f
|
#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
|
#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30
|
#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_hpd4_dispdec
|
// base address: 0x80
|
#define mmHPD4_DC_HPD_INT_STATUS 0x1f34
|
#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
|
#define mmHPD4_DC_HPD_INT_CONTROL 0x1f35
|
#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
|
#define mmHPD4_DC_HPD_CONTROL 0x1f36
|
#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
|
#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37
|
#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
|
#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38
|
#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_hpd5_dispdec
|
// base address: 0xa0
|
#define mmHPD5_DC_HPD_INT_STATUS 0x1f3c
|
#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2
|
#define mmHPD5_DC_HPD_INT_CONTROL 0x1f3d
|
#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2
|
#define mmHPD5_DC_HPD_CONTROL 0x1f3e
|
#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2
|
#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x1f3f
|
#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
|
#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x1f40
|
#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x7d10
|
#define mmDC_PERFMON20_PERFCOUNTER_CNTL 0x1f44
|
#define mmDC_PERFMON20_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFCOUNTER_CNTL2 0x1f45
|
#define mmDC_PERFMON20_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFCOUNTER_STATE 0x1f46
|
#define mmDC_PERFMON20_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFMON_CNTL 0x1f47
|
#define mmDC_PERFMON20_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFMON_CNTL2 0x1f48
|
#define mmDC_PERFMON20_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC 0x1f49
|
#define mmDC_PERFMON20_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFMON_CVALUE_LOW 0x1f4a
|
#define mmDC_PERFMON20_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFMON_HI 0x1f4b
|
#define mmDC_PERFMON20_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON20_PERFMON_LOW 0x1f4c
|
#define mmDC_PERFMON20_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp_aux0_dispdec
|
// base address: 0x0
|
#define mmDP_AUX0_AUX_CONTROL 0x1f50
|
#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51
|
#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52
|
#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53
|
#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_SW_STATUS 0x1f54
|
#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX0_AUX_LS_STATUS 0x1f55
|
#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX0_AUX_SW_DATA 0x1f56
|
#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
|
#define mmDP_AUX0_AUX_LS_DATA 0x1f57
|
#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58
|
#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59
|
#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a
|
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b
|
#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c
|
#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d
|
#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
|
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x1f5e
|
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f
|
#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
|
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60
|
#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61
|
#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
#define mmDP_AUX0_AUX_PHY_WAKE_CNTL 0x1f66
|
#define mmDP_AUX0_AUX_PHY_WAKE_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp_aux1_dispdec
|
// base address: 0x70
|
#define mmDP_AUX1_AUX_CONTROL 0x1f6c
|
#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d
|
#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
|
#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e
|
#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
|
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f
|
#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDP_AUX1_AUX_SW_STATUS 0x1f70
|
#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_LS_STATUS 0x1f71
|
#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_SW_DATA 0x1f72
|
#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
|
#define mmDP_AUX1_AUX_LS_DATA 0x1f73
|
#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
|
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74
|
#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75
|
#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76
|
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
|
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77
|
#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78
|
#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79
|
#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x1f7a
|
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
|
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b
|
#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
|
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c
|
#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d
|
#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
#define mmDP_AUX1_AUX_PHY_WAKE_CNTL 0x1f82
|
#define mmDP_AUX1_AUX_PHY_WAKE_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp_aux2_dispdec
|
// base address: 0xe0
|
#define mmDP_AUX2_AUX_CONTROL 0x1f88
|
#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_SW_CONTROL 0x1f89
|
#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a
|
#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b
|
#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_SW_STATUS 0x1f8c
|
#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_LS_STATUS 0x1f8d
|
#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_SW_DATA 0x1f8e
|
#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
|
#define mmDP_AUX2_AUX_LS_DATA 0x1f8f
|
#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90
|
#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91
|
#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92
|
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93
|
#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94
|
#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95
|
#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x1f96
|
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97
|
#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
|
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98
|
#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99
|
#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
#define mmDP_AUX2_AUX_PHY_WAKE_CNTL 0x1f9e
|
#define mmDP_AUX2_AUX_PHY_WAKE_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp_aux3_dispdec
|
// base address: 0x150
|
#define mmDP_AUX3_AUX_CONTROL 0x1fa4
|
#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5
|
#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6
|
#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7
|
#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_SW_STATUS 0x1fa8
|
#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_LS_STATUS 0x1fa9
|
#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_SW_DATA 0x1faa
|
#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
|
#define mmDP_AUX3_AUX_LS_DATA 0x1fab
|
#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
|
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac
|
#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad
|
#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae
|
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
|
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf
|
#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0
|
#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1
|
#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x1fb2
|
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3
|
#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
|
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4
|
#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5
|
#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
#define mmDP_AUX3_AUX_PHY_WAKE_CNTL 0x1fba
|
#define mmDP_AUX3_AUX_PHY_WAKE_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp_aux4_dispdec
|
// base address: 0x1c0
|
#define mmDP_AUX4_AUX_CONTROL 0x1fc0
|
#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1
|
#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2
|
#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3
|
#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_SW_STATUS 0x1fc4
|
#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX4_AUX_LS_STATUS 0x1fc5
|
#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX4_AUX_SW_DATA 0x1fc6
|
#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
|
#define mmDP_AUX4_AUX_LS_DATA 0x1fc7
|
#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
|
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8
|
#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9
|
#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca
|
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
|
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb
|
#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc
|
#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd
|
#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
|
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x1fce
|
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf
|
#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
|
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0
|
#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1
|
#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
#define mmDP_AUX4_AUX_PHY_WAKE_CNTL 0x1fd6
|
#define mmDP_AUX4_AUX_PHY_WAKE_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp_aux5_dispdec
|
// base address: 0x230
|
#define mmDP_AUX5_AUX_CONTROL 0x1fdc
|
#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_SW_CONTROL 0x1fdd
|
#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_ARB_CONTROL 0x1fde
|
#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x1fdf
|
#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_SW_STATUS 0x1fe0
|
#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2
|
#define mmDP_AUX5_AUX_LS_STATUS 0x1fe1
|
#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2
|
#define mmDP_AUX5_AUX_SW_DATA 0x1fe2
|
#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2
|
#define mmDP_AUX5_AUX_LS_DATA 0x1fe3
|
#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x1fe4
|
#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x1fe5
|
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x1fe6
|
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x1fe7
|
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x1fe8
|
#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x1fe9
|
#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2
|
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x1fea
|
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1feb
|
#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fec
|
#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
|
#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1fed
|
#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2
|
#define mmDP_AUX5_AUX_PHY_WAKE_CNTL 0x1ff2
|
#define mmDP_AUX5_AUX_PHY_WAKE_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dig0_dispdec
|
// base address: 0x0
|
#define mmDIG0_DIG_FE_CNTL 0x2068
|
#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
|
#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x2069
|
#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
|
#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x206a
|
#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
|
#define mmDIG0_DIG_CLOCK_PATTERN 0x206b
|
#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
|
#define mmDIG0_DIG_TEST_PATTERN 0x206c
|
#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
|
#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x206d
|
#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
|
#define mmDIG0_DIG_FIFO_STATUS 0x206e
|
#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
|
#define mmDIG0_HDMI_METADATA_PACKET_CONTROL 0x206f
|
#define mmDIG0_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4 0x2070
|
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
|
#define mmDIG0_HDMI_CONTROL 0x2071
|
#define mmDIG0_HDMI_CONTROL_BASE_IDX 2
|
#define mmDIG0_HDMI_STATUS 0x2072
|
#define mmDIG0_HDMI_STATUS_BASE_IDX 2
|
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2073
|
#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2074
|
#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2075
|
#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2076
|
#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2077
|
#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
|
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x2078
|
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
|
#define mmDIG0_AFMT_INTERRUPT_STATUS 0x2079
|
#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDIG0_HDMI_GC 0x207b
|
#define mmDIG0_HDMI_GC_BASE_IDX 2
|
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x207c
|
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG0_AFMT_ISRC1_0 0x207d
|
#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2
|
#define mmDIG0_AFMT_ISRC1_1 0x207e
|
#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2
|
#define mmDIG0_AFMT_ISRC1_2 0x207f
|
#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2
|
#define mmDIG0_AFMT_ISRC1_3 0x2080
|
#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2
|
#define mmDIG0_AFMT_ISRC1_4 0x2081
|
#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2
|
#define mmDIG0_AFMT_ISRC2_0 0x2082
|
#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2
|
#define mmDIG0_AFMT_ISRC2_1 0x2083
|
#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2
|
#define mmDIG0_AFMT_ISRC2_2 0x2084
|
#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2
|
#define mmDIG0_AFMT_ISRC2_3 0x2085
|
#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2
|
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x2086
|
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x2087
|
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
|
#define mmDIG0_HDMI_DB_CONTROL 0x2088
|
#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2
|
#define mmDIG0_DME_CONTROL 0x2089
|
#define mmDIG0_DME_CONTROL_BASE_IDX 2
|
#define mmDIG0_AFMT_MPEG_INFO0 0x208a
|
#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2
|
#define mmDIG0_AFMT_MPEG_INFO1 0x208b
|
#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2
|
#define mmDIG0_AFMT_GENERIC_HDR 0x208c
|
#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2
|
#define mmDIG0_AFMT_GENERIC_0 0x208d
|
#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2
|
#define mmDIG0_AFMT_GENERIC_1 0x208e
|
#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2
|
#define mmDIG0_AFMT_GENERIC_2 0x208f
|
#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2
|
#define mmDIG0_AFMT_GENERIC_3 0x2090
|
#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2
|
#define mmDIG0_AFMT_GENERIC_4 0x2091
|
#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2
|
#define mmDIG0_AFMT_GENERIC_5 0x2092
|
#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2
|
#define mmDIG0_AFMT_GENERIC_6 0x2093
|
#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2
|
#define mmDIG0_AFMT_GENERIC_7 0x2094
|
#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2
|
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x2095
|
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG0_HDMI_ACR_32_0 0x2096
|
#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
|
#define mmDIG0_HDMI_ACR_32_1 0x2097
|
#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
|
#define mmDIG0_HDMI_ACR_44_0 0x2098
|
#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
|
#define mmDIG0_HDMI_ACR_44_1 0x2099
|
#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
|
#define mmDIG0_HDMI_ACR_48_0 0x209a
|
#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
|
#define mmDIG0_HDMI_ACR_48_1 0x209b
|
#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
|
#define mmDIG0_HDMI_ACR_STATUS_0 0x209c
|
#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
|
#define mmDIG0_HDMI_ACR_STATUS_1 0x209d
|
#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
|
#define mmDIG0_AFMT_AUDIO_INFO0 0x209e
|
#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2
|
#define mmDIG0_AFMT_AUDIO_INFO1 0x209f
|
#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2
|
#define mmDIG0_AFMT_60958_0 0x20a0
|
#define mmDIG0_AFMT_60958_0_BASE_IDX 2
|
#define mmDIG0_AFMT_60958_1 0x20a1
|
#define mmDIG0_AFMT_60958_1_BASE_IDX 2
|
#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x20a2
|
#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
|
#define mmDIG0_AFMT_RAMP_CONTROL0 0x20a3
|
#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2
|
#define mmDIG0_AFMT_RAMP_CONTROL1 0x20a4
|
#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2
|
#define mmDIG0_AFMT_RAMP_CONTROL2 0x20a5
|
#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2
|
#define mmDIG0_AFMT_RAMP_CONTROL3 0x20a6
|
#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2
|
#define mmDIG0_AFMT_60958_2 0x20a7
|
#define mmDIG0_AFMT_60958_2_BASE_IDX 2
|
#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x20a8
|
#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
|
#define mmDIG0_AFMT_STATUS 0x20a9
|
#define mmDIG0_AFMT_STATUS_BASE_IDX 2
|
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x20aa
|
#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x20ab
|
#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x20ac
|
#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x20ad
|
#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
|
#define mmDIG0_DIG_BE_CNTL 0x20af
|
#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
|
#define mmDIG0_DIG_BE_EN_CNTL 0x20b0
|
#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
|
#define mmDIG0_TMDS_CNTL 0x20d3
|
#define mmDIG0_TMDS_CNTL_BASE_IDX 2
|
#define mmDIG0_TMDS_CONTROL_CHAR 0x20d4
|
#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
|
#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d5
|
#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
|
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20d6
|
#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
|
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20d7
|
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
|
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20d8
|
#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
|
#define mmDIG0_TMDS_CTL_BITS 0x20da
|
#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
|
#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20db
|
#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
|
#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR 0x20dc
|
#define mmDIG0_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
|
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20dd
|
#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
|
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20de
|
#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
|
#define mmDIG0_DIG_VERSION 0x20e0
|
#define mmDIG0_DIG_VERSION_BASE_IDX 2
|
#define mmDIG0_DIG_LANE_ENABLE 0x20e1
|
#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
|
#define mmDIG0_AFMT_CNTL 0x20e6
|
#define mmDIG0_AFMT_CNTL_BASE_IDX 2
|
#define mmDIG0_AFMT_VBI_PACKET_CONTROL1 0x20e7
|
#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5 0x20f6
|
#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
|
#define mmDIG0_FORCE_DIG_DISABLE 0x20f7
|
#define mmDIG0_FORCE_DIG_DISABLE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp0_dispdec
|
// base address: 0x0
|
#define mmDP0_DP_LINK_CNTL 0x2108
|
#define mmDP0_DP_LINK_CNTL_BASE_IDX 2
|
#define mmDP0_DP_PIXEL_FORMAT 0x2109
|
#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
|
#define mmDP0_DP_MSA_COLORIMETRY 0x210a
|
#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
|
#define mmDP0_DP_CONFIG 0x210b
|
#define mmDP0_DP_CONFIG_BASE_IDX 2
|
#define mmDP0_DP_VID_STREAM_CNTL 0x210c
|
#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
|
#define mmDP0_DP_STEER_FIFO 0x210d
|
#define mmDP0_DP_STEER_FIFO_BASE_IDX 2
|
#define mmDP0_DP_MSA_MISC 0x210e
|
#define mmDP0_DP_MSA_MISC_BASE_IDX 2
|
#define mmDP0_DP_VID_TIMING 0x2110
|
#define mmDP0_DP_VID_TIMING_BASE_IDX 2
|
#define mmDP0_DP_VID_N 0x2111
|
#define mmDP0_DP_VID_N_BASE_IDX 2
|
#define mmDP0_DP_VID_M 0x2112
|
#define mmDP0_DP_VID_M_BASE_IDX 2
|
#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113
|
#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
|
#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114
|
#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
|
#define mmDP0_DP_VID_MSA_VBID 0x2115
|
#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
|
#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116
|
#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_CNTL 0x2117
|
#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118
|
#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_SYM0 0x2119
|
#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
|
#define mmDP0_DP_DPHY_SYM1 0x211a
|
#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
|
#define mmDP0_DP_DPHY_SYM2 0x211b
|
#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
|
#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c
|
#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d
|
#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e
|
#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_CRC_EN 0x211f
|
#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
|
#define mmDP0_DP_DPHY_CRC_CNTL 0x2120
|
#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_CRC_RESULT 0x2121
|
#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
|
#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122
|
#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123
|
#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
|
#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124
|
#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
|
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125
|
#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
|
#define mmDP0_DP_SEC_CNTL 0x212b
|
#define mmDP0_DP_SEC_CNTL_BASE_IDX 2
|
#define mmDP0_DP_SEC_CNTL1 0x212c
|
#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
|
#define mmDP0_DP_SEC_FRAMING1 0x212d
|
#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
|
#define mmDP0_DP_SEC_FRAMING2 0x212e
|
#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
|
#define mmDP0_DP_SEC_FRAMING3 0x212f
|
#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
|
#define mmDP0_DP_SEC_FRAMING4 0x2130
|
#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
|
#define mmDP0_DP_SEC_AUD_N 0x2131
|
#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
|
#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132
|
#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
|
#define mmDP0_DP_SEC_AUD_M 0x2133
|
#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
|
#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134
|
#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
|
#define mmDP0_DP_SEC_TIMESTAMP 0x2135
|
#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
|
#define mmDP0_DP_SEC_PACKET_CNTL 0x2136
|
#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
|
#define mmDP0_DP_MSE_RATE_CNTL 0x2137
|
#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
|
#define mmDP0_DP_MSE_RATE_UPDATE 0x2139
|
#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
|
#define mmDP0_DP_MSE_SAT0 0x213a
|
#define mmDP0_DP_MSE_SAT0_BASE_IDX 2
|
#define mmDP0_DP_MSE_SAT1 0x213b
|
#define mmDP0_DP_MSE_SAT1_BASE_IDX 2
|
#define mmDP0_DP_MSE_SAT2 0x213c
|
#define mmDP0_DP_MSE_SAT2_BASE_IDX 2
|
#define mmDP0_DP_MSE_SAT_UPDATE 0x213d
|
#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
|
#define mmDP0_DP_MSE_LINK_TIMING 0x213e
|
#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
|
#define mmDP0_DP_MSE_MISC_CNTL 0x213f
|
#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144
|
#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
|
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145
|
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
|
#define mmDP0_DP_MSE_SAT0_STATUS 0x2147
|
#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
|
#define mmDP0_DP_MSE_SAT1_STATUS 0x2148
|
#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
|
#define mmDP0_DP_MSE_SAT2_STATUS 0x2149
|
#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
|
#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c
|
#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2
|
#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d
|
#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2
|
#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e
|
#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2
|
#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f
|
#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2
|
#define mmDP0_DP_MSO_CNTL 0x2150
|
#define mmDP0_DP_MSO_CNTL_BASE_IDX 2
|
#define mmDP0_DP_MSO_CNTL1 0x2151
|
#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2
|
#define mmDP0_DP_DSC_CNTL 0x2152
|
#define mmDP0_DP_DSC_CNTL_BASE_IDX 2
|
#define mmDP0_DP_SEC_CNTL2 0x2153
|
#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2
|
#define mmDP0_DP_SEC_CNTL3 0x2154
|
#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2
|
#define mmDP0_DP_SEC_CNTL4 0x2155
|
#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2
|
#define mmDP0_DP_SEC_CNTL5 0x2156
|
#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2
|
#define mmDP0_DP_SEC_CNTL6 0x2157
|
#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2
|
#define mmDP0_DP_SEC_CNTL7 0x2158
|
#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2
|
#define mmDP0_DP_DB_CNTL 0x2159
|
#define mmDP0_DP_DB_CNTL_BASE_IDX 2
|
#define mmDP0_DP_MSA_VBID_MISC 0x215a
|
#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2
|
#define mmDP0_DP_SEC_METADATA_TRANSMISSION 0x215b
|
#define mmDP0_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
|
#define mmDP0_DP_DSC_BYTES_PER_PIXEL 0x215c
|
#define mmDP0_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmDP0_DP_ALPM_CNTL 0x215d
|
#define mmDP0_DP_ALPM_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dig1_dispdec
|
// base address: 0x400
|
#define mmDIG1_DIG_FE_CNTL 0x2168
|
#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
|
#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x2169
|
#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
|
#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x216a
|
#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
|
#define mmDIG1_DIG_CLOCK_PATTERN 0x216b
|
#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
|
#define mmDIG1_DIG_TEST_PATTERN 0x216c
|
#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
|
#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x216d
|
#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
|
#define mmDIG1_DIG_FIFO_STATUS 0x216e
|
#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
|
#define mmDIG1_HDMI_METADATA_PACKET_CONTROL 0x216f
|
#define mmDIG1_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4 0x2170
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
|
#define mmDIG1_HDMI_CONTROL 0x2171
|
#define mmDIG1_HDMI_CONTROL_BASE_IDX 2
|
#define mmDIG1_HDMI_STATUS 0x2172
|
#define mmDIG1_HDMI_STATUS_BASE_IDX 2
|
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2173
|
#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2174
|
#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2175
|
#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2176
|
#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2177
|
#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x2178
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
|
#define mmDIG1_AFMT_INTERRUPT_STATUS 0x2179
|
#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDIG1_HDMI_GC 0x217b
|
#define mmDIG1_HDMI_GC_BASE_IDX 2
|
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x217c
|
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG1_AFMT_ISRC1_0 0x217d
|
#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2
|
#define mmDIG1_AFMT_ISRC1_1 0x217e
|
#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2
|
#define mmDIG1_AFMT_ISRC1_2 0x217f
|
#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2
|
#define mmDIG1_AFMT_ISRC1_3 0x2180
|
#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2
|
#define mmDIG1_AFMT_ISRC1_4 0x2181
|
#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2
|
#define mmDIG1_AFMT_ISRC2_0 0x2182
|
#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2
|
#define mmDIG1_AFMT_ISRC2_1 0x2183
|
#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2
|
#define mmDIG1_AFMT_ISRC2_2 0x2184
|
#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2
|
#define mmDIG1_AFMT_ISRC2_3 0x2185
|
#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x2186
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x2187
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
|
#define mmDIG1_HDMI_DB_CONTROL 0x2188
|
#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2
|
#define mmDIG1_DME_CONTROL 0x2189
|
#define mmDIG1_DME_CONTROL_BASE_IDX 2
|
#define mmDIG1_AFMT_MPEG_INFO0 0x218a
|
#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2
|
#define mmDIG1_AFMT_MPEG_INFO1 0x218b
|
#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2
|
#define mmDIG1_AFMT_GENERIC_HDR 0x218c
|
#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2
|
#define mmDIG1_AFMT_GENERIC_0 0x218d
|
#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2
|
#define mmDIG1_AFMT_GENERIC_1 0x218e
|
#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2
|
#define mmDIG1_AFMT_GENERIC_2 0x218f
|
#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2
|
#define mmDIG1_AFMT_GENERIC_3 0x2190
|
#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2
|
#define mmDIG1_AFMT_GENERIC_4 0x2191
|
#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2
|
#define mmDIG1_AFMT_GENERIC_5 0x2192
|
#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2
|
#define mmDIG1_AFMT_GENERIC_6 0x2193
|
#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2
|
#define mmDIG1_AFMT_GENERIC_7 0x2194
|
#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x2195
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG1_HDMI_ACR_32_0 0x2196
|
#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
|
#define mmDIG1_HDMI_ACR_32_1 0x2197
|
#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
|
#define mmDIG1_HDMI_ACR_44_0 0x2198
|
#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
|
#define mmDIG1_HDMI_ACR_44_1 0x2199
|
#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
|
#define mmDIG1_HDMI_ACR_48_0 0x219a
|
#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
|
#define mmDIG1_HDMI_ACR_48_1 0x219b
|
#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
|
#define mmDIG1_HDMI_ACR_STATUS_0 0x219c
|
#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
|
#define mmDIG1_HDMI_ACR_STATUS_1 0x219d
|
#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
|
#define mmDIG1_AFMT_AUDIO_INFO0 0x219e
|
#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2
|
#define mmDIG1_AFMT_AUDIO_INFO1 0x219f
|
#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2
|
#define mmDIG1_AFMT_60958_0 0x21a0
|
#define mmDIG1_AFMT_60958_0_BASE_IDX 2
|
#define mmDIG1_AFMT_60958_1 0x21a1
|
#define mmDIG1_AFMT_60958_1_BASE_IDX 2
|
#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x21a2
|
#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
|
#define mmDIG1_AFMT_RAMP_CONTROL0 0x21a3
|
#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2
|
#define mmDIG1_AFMT_RAMP_CONTROL1 0x21a4
|
#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2
|
#define mmDIG1_AFMT_RAMP_CONTROL2 0x21a5
|
#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2
|
#define mmDIG1_AFMT_RAMP_CONTROL3 0x21a6
|
#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2
|
#define mmDIG1_AFMT_60958_2 0x21a7
|
#define mmDIG1_AFMT_60958_2_BASE_IDX 2
|
#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x21a8
|
#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
|
#define mmDIG1_AFMT_STATUS 0x21a9
|
#define mmDIG1_AFMT_STATUS_BASE_IDX 2
|
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x21aa
|
#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x21ab
|
#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x21ac
|
#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x21ad
|
#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
|
#define mmDIG1_DIG_BE_CNTL 0x21af
|
#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
|
#define mmDIG1_DIG_BE_EN_CNTL 0x21b0
|
#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
|
#define mmDIG1_TMDS_CNTL 0x21d3
|
#define mmDIG1_TMDS_CNTL_BASE_IDX 2
|
#define mmDIG1_TMDS_CONTROL_CHAR 0x21d4
|
#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
|
#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d5
|
#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
|
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21d6
|
#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
|
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21d7
|
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
|
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21d8
|
#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
|
#define mmDIG1_TMDS_CTL_BITS 0x21da
|
#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
|
#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21db
|
#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
|
#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR 0x21dc
|
#define mmDIG1_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
|
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21dd
|
#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
|
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21de
|
#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
|
#define mmDIG1_DIG_VERSION 0x21e0
|
#define mmDIG1_DIG_VERSION_BASE_IDX 2
|
#define mmDIG1_DIG_LANE_ENABLE 0x21e1
|
#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
|
#define mmDIG1_AFMT_CNTL 0x21e6
|
#define mmDIG1_AFMT_CNTL_BASE_IDX 2
|
#define mmDIG1_AFMT_VBI_PACKET_CONTROL1 0x21e7
|
#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5 0x21f6
|
#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
|
#define mmDIG1_FORCE_DIG_DISABLE 0x21f7
|
#define mmDIG1_FORCE_DIG_DISABLE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp1_dispdec
|
// base address: 0x400
|
#define mmDP1_DP_LINK_CNTL 0x2208
|
#define mmDP1_DP_LINK_CNTL_BASE_IDX 2
|
#define mmDP1_DP_PIXEL_FORMAT 0x2209
|
#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
|
#define mmDP1_DP_MSA_COLORIMETRY 0x220a
|
#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
|
#define mmDP1_DP_CONFIG 0x220b
|
#define mmDP1_DP_CONFIG_BASE_IDX 2
|
#define mmDP1_DP_VID_STREAM_CNTL 0x220c
|
#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
|
#define mmDP1_DP_STEER_FIFO 0x220d
|
#define mmDP1_DP_STEER_FIFO_BASE_IDX 2
|
#define mmDP1_DP_MSA_MISC 0x220e
|
#define mmDP1_DP_MSA_MISC_BASE_IDX 2
|
#define mmDP1_DP_VID_TIMING 0x2210
|
#define mmDP1_DP_VID_TIMING_BASE_IDX 2
|
#define mmDP1_DP_VID_N 0x2211
|
#define mmDP1_DP_VID_N_BASE_IDX 2
|
#define mmDP1_DP_VID_M 0x2212
|
#define mmDP1_DP_VID_M_BASE_IDX 2
|
#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213
|
#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
|
#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214
|
#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
|
#define mmDP1_DP_VID_MSA_VBID 0x2215
|
#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
|
#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216
|
#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CNTL 0x2217
|
#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218
|
#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_SYM0 0x2219
|
#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
|
#define mmDP1_DP_DPHY_SYM1 0x221a
|
#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
|
#define mmDP1_DP_DPHY_SYM2 0x221b
|
#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
|
#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c
|
#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d
|
#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e
|
#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_EN 0x221f
|
#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_CNTL 0x2220
|
#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_RESULT 0x2221
|
#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222
|
#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223
|
#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
|
#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224
|
#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
|
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225
|
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL 0x222b
|
#define mmDP1_DP_SEC_CNTL_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL1 0x222c
|
#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
|
#define mmDP1_DP_SEC_FRAMING1 0x222d
|
#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
|
#define mmDP1_DP_SEC_FRAMING2 0x222e
|
#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
|
#define mmDP1_DP_SEC_FRAMING3 0x222f
|
#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
|
#define mmDP1_DP_SEC_FRAMING4 0x2230
|
#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
|
#define mmDP1_DP_SEC_AUD_N 0x2231
|
#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
|
#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232
|
#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
|
#define mmDP1_DP_SEC_AUD_M 0x2233
|
#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
|
#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234
|
#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
|
#define mmDP1_DP_SEC_TIMESTAMP 0x2235
|
#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
|
#define mmDP1_DP_SEC_PACKET_CNTL 0x2236
|
#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
|
#define mmDP1_DP_MSE_RATE_CNTL 0x2237
|
#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
|
#define mmDP1_DP_MSE_RATE_UPDATE 0x2239
|
#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT0 0x223a
|
#define mmDP1_DP_MSE_SAT0_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT1 0x223b
|
#define mmDP1_DP_MSE_SAT1_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT2 0x223c
|
#define mmDP1_DP_MSE_SAT2_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT_UPDATE 0x223d
|
#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
|
#define mmDP1_DP_MSE_LINK_TIMING 0x223e
|
#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
|
#define mmDP1_DP_MSE_MISC_CNTL 0x223f
|
#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244
|
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245
|
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT0_STATUS 0x2247
|
#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT1_STATUS 0x2248
|
#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT2_STATUS 0x2249
|
#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
|
#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c
|
#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2
|
#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d
|
#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2
|
#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e
|
#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2
|
#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f
|
#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2
|
#define mmDP1_DP_MSO_CNTL 0x2250
|
#define mmDP1_DP_MSO_CNTL_BASE_IDX 2
|
#define mmDP1_DP_MSO_CNTL1 0x2251
|
#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2
|
#define mmDP1_DP_DSC_CNTL 0x2252
|
#define mmDP1_DP_DSC_CNTL_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL2 0x2253
|
#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL3 0x2254
|
#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL4 0x2255
|
#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL5 0x2256
|
#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL6 0x2257
|
#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL7 0x2258
|
#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2
|
#define mmDP1_DP_DB_CNTL 0x2259
|
#define mmDP1_DP_DB_CNTL_BASE_IDX 2
|
#define mmDP1_DP_MSA_VBID_MISC 0x225a
|
#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2
|
#define mmDP1_DP_SEC_METADATA_TRANSMISSION 0x225b
|
#define mmDP1_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
|
#define mmDP1_DP_DSC_BYTES_PER_PIXEL 0x225c
|
#define mmDP1_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmDP1_DP_ALPM_CNTL 0x225d
|
#define mmDP1_DP_ALPM_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dig2_dispdec
|
// base address: 0x800
|
#define mmDIG2_DIG_FE_CNTL 0x2268
|
#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
|
#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x2269
|
#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
|
#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x226a
|
#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
|
#define mmDIG2_DIG_CLOCK_PATTERN 0x226b
|
#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
|
#define mmDIG2_DIG_TEST_PATTERN 0x226c
|
#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
|
#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x226d
|
#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
|
#define mmDIG2_DIG_FIFO_STATUS 0x226e
|
#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
|
#define mmDIG2_HDMI_METADATA_PACKET_CONTROL 0x226f
|
#define mmDIG2_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4 0x2270
|
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
|
#define mmDIG2_HDMI_CONTROL 0x2271
|
#define mmDIG2_HDMI_CONTROL_BASE_IDX 2
|
#define mmDIG2_HDMI_STATUS 0x2272
|
#define mmDIG2_HDMI_STATUS_BASE_IDX 2
|
#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2273
|
#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2274
|
#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2275
|
#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2276
|
#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2277
|
#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
|
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x2278
|
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
|
#define mmDIG2_AFMT_INTERRUPT_STATUS 0x2279
|
#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDIG2_HDMI_GC 0x227b
|
#define mmDIG2_HDMI_GC_BASE_IDX 2
|
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x227c
|
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG2_AFMT_ISRC1_0 0x227d
|
#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2
|
#define mmDIG2_AFMT_ISRC1_1 0x227e
|
#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2
|
#define mmDIG2_AFMT_ISRC1_2 0x227f
|
#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2
|
#define mmDIG2_AFMT_ISRC1_3 0x2280
|
#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2
|
#define mmDIG2_AFMT_ISRC1_4 0x2281
|
#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2
|
#define mmDIG2_AFMT_ISRC2_0 0x2282
|
#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2
|
#define mmDIG2_AFMT_ISRC2_1 0x2283
|
#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2
|
#define mmDIG2_AFMT_ISRC2_2 0x2284
|
#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2
|
#define mmDIG2_AFMT_ISRC2_3 0x2285
|
#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2
|
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x2286
|
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x2287
|
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
|
#define mmDIG2_HDMI_DB_CONTROL 0x2288
|
#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2
|
#define mmDIG2_DME_CONTROL 0x2289
|
#define mmDIG2_DME_CONTROL_BASE_IDX 2
|
#define mmDIG2_AFMT_MPEG_INFO0 0x228a
|
#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2
|
#define mmDIG2_AFMT_MPEG_INFO1 0x228b
|
#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2
|
#define mmDIG2_AFMT_GENERIC_HDR 0x228c
|
#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2
|
#define mmDIG2_AFMT_GENERIC_0 0x228d
|
#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2
|
#define mmDIG2_AFMT_GENERIC_1 0x228e
|
#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2
|
#define mmDIG2_AFMT_GENERIC_2 0x228f
|
#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2
|
#define mmDIG2_AFMT_GENERIC_3 0x2290
|
#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2
|
#define mmDIG2_AFMT_GENERIC_4 0x2291
|
#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2
|
#define mmDIG2_AFMT_GENERIC_5 0x2292
|
#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2
|
#define mmDIG2_AFMT_GENERIC_6 0x2293
|
#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2
|
#define mmDIG2_AFMT_GENERIC_7 0x2294
|
#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2
|
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x2295
|
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG2_HDMI_ACR_32_0 0x2296
|
#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
|
#define mmDIG2_HDMI_ACR_32_1 0x2297
|
#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
|
#define mmDIG2_HDMI_ACR_44_0 0x2298
|
#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
|
#define mmDIG2_HDMI_ACR_44_1 0x2299
|
#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
|
#define mmDIG2_HDMI_ACR_48_0 0x229a
|
#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
|
#define mmDIG2_HDMI_ACR_48_1 0x229b
|
#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
|
#define mmDIG2_HDMI_ACR_STATUS_0 0x229c
|
#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
|
#define mmDIG2_HDMI_ACR_STATUS_1 0x229d
|
#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
|
#define mmDIG2_AFMT_AUDIO_INFO0 0x229e
|
#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2
|
#define mmDIG2_AFMT_AUDIO_INFO1 0x229f
|
#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2
|
#define mmDIG2_AFMT_60958_0 0x22a0
|
#define mmDIG2_AFMT_60958_0_BASE_IDX 2
|
#define mmDIG2_AFMT_60958_1 0x22a1
|
#define mmDIG2_AFMT_60958_1_BASE_IDX 2
|
#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x22a2
|
#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
|
#define mmDIG2_AFMT_RAMP_CONTROL0 0x22a3
|
#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2
|
#define mmDIG2_AFMT_RAMP_CONTROL1 0x22a4
|
#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2
|
#define mmDIG2_AFMT_RAMP_CONTROL2 0x22a5
|
#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2
|
#define mmDIG2_AFMT_RAMP_CONTROL3 0x22a6
|
#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2
|
#define mmDIG2_AFMT_60958_2 0x22a7
|
#define mmDIG2_AFMT_60958_2_BASE_IDX 2
|
#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x22a8
|
#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
|
#define mmDIG2_AFMT_STATUS 0x22a9
|
#define mmDIG2_AFMT_STATUS_BASE_IDX 2
|
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x22aa
|
#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x22ab
|
#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x22ac
|
#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x22ad
|
#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
|
#define mmDIG2_DIG_BE_CNTL 0x22af
|
#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
|
#define mmDIG2_DIG_BE_EN_CNTL 0x22b0
|
#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
|
#define mmDIG2_TMDS_CNTL 0x22d3
|
#define mmDIG2_TMDS_CNTL_BASE_IDX 2
|
#define mmDIG2_TMDS_CONTROL_CHAR 0x22d4
|
#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
|
#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d5
|
#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
|
#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22d6
|
#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
|
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22d7
|
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
|
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22d8
|
#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
|
#define mmDIG2_TMDS_CTL_BITS 0x22da
|
#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
|
#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22db
|
#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
|
#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR 0x22dc
|
#define mmDIG2_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
|
#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22dd
|
#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
|
#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22de
|
#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
|
#define mmDIG2_DIG_VERSION 0x22e0
|
#define mmDIG2_DIG_VERSION_BASE_IDX 2
|
#define mmDIG2_DIG_LANE_ENABLE 0x22e1
|
#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
|
#define mmDIG2_AFMT_CNTL 0x22e6
|
#define mmDIG2_AFMT_CNTL_BASE_IDX 2
|
#define mmDIG2_AFMT_VBI_PACKET_CONTROL1 0x22e7
|
#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5 0x22f6
|
#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
|
#define mmDIG2_FORCE_DIG_DISABLE 0x22f7
|
#define mmDIG2_FORCE_DIG_DISABLE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp2_dispdec
|
// base address: 0x800
|
#define mmDP2_DP_LINK_CNTL 0x2308
|
#define mmDP2_DP_LINK_CNTL_BASE_IDX 2
|
#define mmDP2_DP_PIXEL_FORMAT 0x2309
|
#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
|
#define mmDP2_DP_MSA_COLORIMETRY 0x230a
|
#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
|
#define mmDP2_DP_CONFIG 0x230b
|
#define mmDP2_DP_CONFIG_BASE_IDX 2
|
#define mmDP2_DP_VID_STREAM_CNTL 0x230c
|
#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
|
#define mmDP2_DP_STEER_FIFO 0x230d
|
#define mmDP2_DP_STEER_FIFO_BASE_IDX 2
|
#define mmDP2_DP_MSA_MISC 0x230e
|
#define mmDP2_DP_MSA_MISC_BASE_IDX 2
|
#define mmDP2_DP_VID_TIMING 0x2310
|
#define mmDP2_DP_VID_TIMING_BASE_IDX 2
|
#define mmDP2_DP_VID_N 0x2311
|
#define mmDP2_DP_VID_N_BASE_IDX 2
|
#define mmDP2_DP_VID_M 0x2312
|
#define mmDP2_DP_VID_M_BASE_IDX 2
|
#define mmDP2_DP_LINK_FRAMING_CNTL 0x2313
|
#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
|
#define mmDP2_DP_HBR2_EYE_PATTERN 0x2314
|
#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
|
#define mmDP2_DP_VID_MSA_VBID 0x2315
|
#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
|
#define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316
|
#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmDP2_DP_DPHY_CNTL 0x2317
|
#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
|
#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318
|
#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
|
#define mmDP2_DP_DPHY_SYM0 0x2319
|
#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
|
#define mmDP2_DP_DPHY_SYM1 0x231a
|
#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
|
#define mmDP2_DP_DPHY_SYM2 0x231b
|
#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
|
#define mmDP2_DP_DPHY_8B10B_CNTL 0x231c
|
#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
|
#define mmDP2_DP_DPHY_PRBS_CNTL 0x231d
|
#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
|
#define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e
|
#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
|
#define mmDP2_DP_DPHY_CRC_EN 0x231f
|
#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
|
#define mmDP2_DP_DPHY_CRC_CNTL 0x2320
|
#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
|
#define mmDP2_DP_DPHY_CRC_RESULT 0x2321
|
#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
|
#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322
|
#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
|
#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323
|
#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
|
#define mmDP2_DP_DPHY_FAST_TRAINING 0x2324
|
#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
|
#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325
|
#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
|
#define mmDP2_DP_SEC_CNTL 0x232b
|
#define mmDP2_DP_SEC_CNTL_BASE_IDX 2
|
#define mmDP2_DP_SEC_CNTL1 0x232c
|
#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
|
#define mmDP2_DP_SEC_FRAMING1 0x232d
|
#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
|
#define mmDP2_DP_SEC_FRAMING2 0x232e
|
#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
|
#define mmDP2_DP_SEC_FRAMING3 0x232f
|
#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
|
#define mmDP2_DP_SEC_FRAMING4 0x2330
|
#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
|
#define mmDP2_DP_SEC_AUD_N 0x2331
|
#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
|
#define mmDP2_DP_SEC_AUD_N_READBACK 0x2332
|
#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
|
#define mmDP2_DP_SEC_AUD_M 0x2333
|
#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
|
#define mmDP2_DP_SEC_AUD_M_READBACK 0x2334
|
#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
|
#define mmDP2_DP_SEC_TIMESTAMP 0x2335
|
#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
|
#define mmDP2_DP_SEC_PACKET_CNTL 0x2336
|
#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
|
#define mmDP2_DP_MSE_RATE_CNTL 0x2337
|
#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
|
#define mmDP2_DP_MSE_RATE_UPDATE 0x2339
|
#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
|
#define mmDP2_DP_MSE_SAT0 0x233a
|
#define mmDP2_DP_MSE_SAT0_BASE_IDX 2
|
#define mmDP2_DP_MSE_SAT1 0x233b
|
#define mmDP2_DP_MSE_SAT1_BASE_IDX 2
|
#define mmDP2_DP_MSE_SAT2 0x233c
|
#define mmDP2_DP_MSE_SAT2_BASE_IDX 2
|
#define mmDP2_DP_MSE_SAT_UPDATE 0x233d
|
#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
|
#define mmDP2_DP_MSE_LINK_TIMING 0x233e
|
#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
|
#define mmDP2_DP_MSE_MISC_CNTL 0x233f
|
#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
|
#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344
|
#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
|
#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345
|
#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
|
#define mmDP2_DP_MSE_SAT0_STATUS 0x2347
|
#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
|
#define mmDP2_DP_MSE_SAT1_STATUS 0x2348
|
#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
|
#define mmDP2_DP_MSE_SAT2_STATUS 0x2349
|
#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
|
#define mmDP2_DP_MSA_TIMING_PARAM1 0x234c
|
#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2
|
#define mmDP2_DP_MSA_TIMING_PARAM2 0x234d
|
#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2
|
#define mmDP2_DP_MSA_TIMING_PARAM3 0x234e
|
#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2
|
#define mmDP2_DP_MSA_TIMING_PARAM4 0x234f
|
#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2
|
#define mmDP2_DP_MSO_CNTL 0x2350
|
#define mmDP2_DP_MSO_CNTL_BASE_IDX 2
|
#define mmDP2_DP_MSO_CNTL1 0x2351
|
#define mmDP2_DP_MSO_CNTL1_BASE_IDX 2
|
#define mmDP2_DP_DSC_CNTL 0x2352
|
#define mmDP2_DP_DSC_CNTL_BASE_IDX 2
|
#define mmDP2_DP_SEC_CNTL2 0x2353
|
#define mmDP2_DP_SEC_CNTL2_BASE_IDX 2
|
#define mmDP2_DP_SEC_CNTL3 0x2354
|
#define mmDP2_DP_SEC_CNTL3_BASE_IDX 2
|
#define mmDP2_DP_SEC_CNTL4 0x2355
|
#define mmDP2_DP_SEC_CNTL4_BASE_IDX 2
|
#define mmDP2_DP_SEC_CNTL5 0x2356
|
#define mmDP2_DP_SEC_CNTL5_BASE_IDX 2
|
#define mmDP2_DP_SEC_CNTL6 0x2357
|
#define mmDP2_DP_SEC_CNTL6_BASE_IDX 2
|
#define mmDP2_DP_SEC_CNTL7 0x2358
|
#define mmDP2_DP_SEC_CNTL7_BASE_IDX 2
|
#define mmDP2_DP_DB_CNTL 0x2359
|
#define mmDP2_DP_DB_CNTL_BASE_IDX 2
|
#define mmDP2_DP_MSA_VBID_MISC 0x235a
|
#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2
|
#define mmDP2_DP_SEC_METADATA_TRANSMISSION 0x235b
|
#define mmDP2_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
|
#define mmDP2_DP_DSC_BYTES_PER_PIXEL 0x235c
|
#define mmDP2_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmDP2_DP_ALPM_CNTL 0x235d
|
#define mmDP2_DP_ALPM_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dig3_dispdec
|
// base address: 0xc00
|
#define mmDIG3_DIG_FE_CNTL 0x2368
|
#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
|
#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x2369
|
#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
|
#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x236a
|
#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
|
#define mmDIG3_DIG_CLOCK_PATTERN 0x236b
|
#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
|
#define mmDIG3_DIG_TEST_PATTERN 0x236c
|
#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
|
#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x236d
|
#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
|
#define mmDIG3_DIG_FIFO_STATUS 0x236e
|
#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
|
#define mmDIG3_HDMI_METADATA_PACKET_CONTROL 0x236f
|
#define mmDIG3_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4 0x2370
|
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
|
#define mmDIG3_HDMI_CONTROL 0x2371
|
#define mmDIG3_HDMI_CONTROL_BASE_IDX 2
|
#define mmDIG3_HDMI_STATUS 0x2372
|
#define mmDIG3_HDMI_STATUS_BASE_IDX 2
|
#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2373
|
#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2374
|
#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2375
|
#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2376
|
#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2377
|
#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
|
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2378
|
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
|
#define mmDIG3_AFMT_INTERRUPT_STATUS 0x2379
|
#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDIG3_HDMI_GC 0x237b
|
#define mmDIG3_HDMI_GC_BASE_IDX 2
|
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x237c
|
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG3_AFMT_ISRC1_0 0x237d
|
#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2
|
#define mmDIG3_AFMT_ISRC1_1 0x237e
|
#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2
|
#define mmDIG3_AFMT_ISRC1_2 0x237f
|
#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2
|
#define mmDIG3_AFMT_ISRC1_3 0x2380
|
#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2
|
#define mmDIG3_AFMT_ISRC1_4 0x2381
|
#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2
|
#define mmDIG3_AFMT_ISRC2_0 0x2382
|
#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2
|
#define mmDIG3_AFMT_ISRC2_1 0x2383
|
#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2
|
#define mmDIG3_AFMT_ISRC2_2 0x2384
|
#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2
|
#define mmDIG3_AFMT_ISRC2_3 0x2385
|
#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2
|
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2386
|
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2387
|
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
|
#define mmDIG3_HDMI_DB_CONTROL 0x2388
|
#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2
|
#define mmDIG3_DME_CONTROL 0x2389
|
#define mmDIG3_DME_CONTROL_BASE_IDX 2
|
#define mmDIG3_AFMT_MPEG_INFO0 0x238a
|
#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2
|
#define mmDIG3_AFMT_MPEG_INFO1 0x238b
|
#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2
|
#define mmDIG3_AFMT_GENERIC_HDR 0x238c
|
#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2
|
#define mmDIG3_AFMT_GENERIC_0 0x238d
|
#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2
|
#define mmDIG3_AFMT_GENERIC_1 0x238e
|
#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2
|
#define mmDIG3_AFMT_GENERIC_2 0x238f
|
#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2
|
#define mmDIG3_AFMT_GENERIC_3 0x2390
|
#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2
|
#define mmDIG3_AFMT_GENERIC_4 0x2391
|
#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2
|
#define mmDIG3_AFMT_GENERIC_5 0x2392
|
#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2
|
#define mmDIG3_AFMT_GENERIC_6 0x2393
|
#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2
|
#define mmDIG3_AFMT_GENERIC_7 0x2394
|
#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2
|
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2395
|
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG3_HDMI_ACR_32_0 0x2396
|
#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
|
#define mmDIG3_HDMI_ACR_32_1 0x2397
|
#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
|
#define mmDIG3_HDMI_ACR_44_0 0x2398
|
#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
|
#define mmDIG3_HDMI_ACR_44_1 0x2399
|
#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
|
#define mmDIG3_HDMI_ACR_48_0 0x239a
|
#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
|
#define mmDIG3_HDMI_ACR_48_1 0x239b
|
#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
|
#define mmDIG3_HDMI_ACR_STATUS_0 0x239c
|
#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
|
#define mmDIG3_HDMI_ACR_STATUS_1 0x239d
|
#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
|
#define mmDIG3_AFMT_AUDIO_INFO0 0x239e
|
#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2
|
#define mmDIG3_AFMT_AUDIO_INFO1 0x239f
|
#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2
|
#define mmDIG3_AFMT_60958_0 0x23a0
|
#define mmDIG3_AFMT_60958_0_BASE_IDX 2
|
#define mmDIG3_AFMT_60958_1 0x23a1
|
#define mmDIG3_AFMT_60958_1_BASE_IDX 2
|
#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x23a2
|
#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
|
#define mmDIG3_AFMT_RAMP_CONTROL0 0x23a3
|
#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2
|
#define mmDIG3_AFMT_RAMP_CONTROL1 0x23a4
|
#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2
|
#define mmDIG3_AFMT_RAMP_CONTROL2 0x23a5
|
#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2
|
#define mmDIG3_AFMT_RAMP_CONTROL3 0x23a6
|
#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2
|
#define mmDIG3_AFMT_60958_2 0x23a7
|
#define mmDIG3_AFMT_60958_2_BASE_IDX 2
|
#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x23a8
|
#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
|
#define mmDIG3_AFMT_STATUS 0x23a9
|
#define mmDIG3_AFMT_STATUS_BASE_IDX 2
|
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x23aa
|
#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x23ab
|
#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x23ac
|
#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x23ad
|
#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
|
#define mmDIG3_DIG_BE_CNTL 0x23af
|
#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
|
#define mmDIG3_DIG_BE_EN_CNTL 0x23b0
|
#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
|
#define mmDIG3_TMDS_CNTL 0x23d3
|
#define mmDIG3_TMDS_CNTL_BASE_IDX 2
|
#define mmDIG3_TMDS_CONTROL_CHAR 0x23d4
|
#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
|
#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d5
|
#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
|
#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23d6
|
#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
|
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23d7
|
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
|
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23d8
|
#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
|
#define mmDIG3_TMDS_CTL_BITS 0x23da
|
#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
|
#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23db
|
#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
|
#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR 0x23dc
|
#define mmDIG3_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
|
#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23dd
|
#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
|
#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23de
|
#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
|
#define mmDIG3_DIG_VERSION 0x23e0
|
#define mmDIG3_DIG_VERSION_BASE_IDX 2
|
#define mmDIG3_DIG_LANE_ENABLE 0x23e1
|
#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
|
#define mmDIG3_AFMT_CNTL 0x23e6
|
#define mmDIG3_AFMT_CNTL_BASE_IDX 2
|
#define mmDIG3_AFMT_VBI_PACKET_CONTROL1 0x23e7
|
#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5 0x23f6
|
#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
|
#define mmDIG3_FORCE_DIG_DISABLE 0x23f7
|
#define mmDIG3_FORCE_DIG_DISABLE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp3_dispdec
|
// base address: 0xc00
|
#define mmDP3_DP_LINK_CNTL 0x2408
|
#define mmDP3_DP_LINK_CNTL_BASE_IDX 2
|
#define mmDP3_DP_PIXEL_FORMAT 0x2409
|
#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
|
#define mmDP3_DP_MSA_COLORIMETRY 0x240a
|
#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
|
#define mmDP3_DP_CONFIG 0x240b
|
#define mmDP3_DP_CONFIG_BASE_IDX 2
|
#define mmDP3_DP_VID_STREAM_CNTL 0x240c
|
#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
|
#define mmDP3_DP_STEER_FIFO 0x240d
|
#define mmDP3_DP_STEER_FIFO_BASE_IDX 2
|
#define mmDP3_DP_MSA_MISC 0x240e
|
#define mmDP3_DP_MSA_MISC_BASE_IDX 2
|
#define mmDP3_DP_VID_TIMING 0x2410
|
#define mmDP3_DP_VID_TIMING_BASE_IDX 2
|
#define mmDP3_DP_VID_N 0x2411
|
#define mmDP3_DP_VID_N_BASE_IDX 2
|
#define mmDP3_DP_VID_M 0x2412
|
#define mmDP3_DP_VID_M_BASE_IDX 2
|
#define mmDP3_DP_LINK_FRAMING_CNTL 0x2413
|
#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
|
#define mmDP3_DP_HBR2_EYE_PATTERN 0x2414
|
#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
|
#define mmDP3_DP_VID_MSA_VBID 0x2415
|
#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
|
#define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416
|
#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmDP3_DP_DPHY_CNTL 0x2417
|
#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
|
#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418
|
#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
|
#define mmDP3_DP_DPHY_SYM0 0x2419
|
#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
|
#define mmDP3_DP_DPHY_SYM1 0x241a
|
#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
|
#define mmDP3_DP_DPHY_SYM2 0x241b
|
#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
|
#define mmDP3_DP_DPHY_8B10B_CNTL 0x241c
|
#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
|
#define mmDP3_DP_DPHY_PRBS_CNTL 0x241d
|
#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
|
#define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e
|
#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
|
#define mmDP3_DP_DPHY_CRC_EN 0x241f
|
#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
|
#define mmDP3_DP_DPHY_CRC_CNTL 0x2420
|
#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
|
#define mmDP3_DP_DPHY_CRC_RESULT 0x2421
|
#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
|
#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422
|
#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
|
#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423
|
#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
|
#define mmDP3_DP_DPHY_FAST_TRAINING 0x2424
|
#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
|
#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425
|
#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
|
#define mmDP3_DP_SEC_CNTL 0x242b
|
#define mmDP3_DP_SEC_CNTL_BASE_IDX 2
|
#define mmDP3_DP_SEC_CNTL1 0x242c
|
#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
|
#define mmDP3_DP_SEC_FRAMING1 0x242d
|
#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
|
#define mmDP3_DP_SEC_FRAMING2 0x242e
|
#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
|
#define mmDP3_DP_SEC_FRAMING3 0x242f
|
#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
|
#define mmDP3_DP_SEC_FRAMING4 0x2430
|
#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
|
#define mmDP3_DP_SEC_AUD_N 0x2431
|
#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
|
#define mmDP3_DP_SEC_AUD_N_READBACK 0x2432
|
#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
|
#define mmDP3_DP_SEC_AUD_M 0x2433
|
#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
|
#define mmDP3_DP_SEC_AUD_M_READBACK 0x2434
|
#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
|
#define mmDP3_DP_SEC_TIMESTAMP 0x2435
|
#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
|
#define mmDP3_DP_SEC_PACKET_CNTL 0x2436
|
#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
|
#define mmDP3_DP_MSE_RATE_CNTL 0x2437
|
#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
|
#define mmDP3_DP_MSE_RATE_UPDATE 0x2439
|
#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
|
#define mmDP3_DP_MSE_SAT0 0x243a
|
#define mmDP3_DP_MSE_SAT0_BASE_IDX 2
|
#define mmDP3_DP_MSE_SAT1 0x243b
|
#define mmDP3_DP_MSE_SAT1_BASE_IDX 2
|
#define mmDP3_DP_MSE_SAT2 0x243c
|
#define mmDP3_DP_MSE_SAT2_BASE_IDX 2
|
#define mmDP3_DP_MSE_SAT_UPDATE 0x243d
|
#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
|
#define mmDP3_DP_MSE_LINK_TIMING 0x243e
|
#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
|
#define mmDP3_DP_MSE_MISC_CNTL 0x243f
|
#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
|
#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444
|
#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
|
#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445
|
#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
|
#define mmDP3_DP_MSE_SAT0_STATUS 0x2447
|
#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
|
#define mmDP3_DP_MSE_SAT1_STATUS 0x2448
|
#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
|
#define mmDP3_DP_MSE_SAT2_STATUS 0x2449
|
#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
|
#define mmDP3_DP_MSA_TIMING_PARAM1 0x244c
|
#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2
|
#define mmDP3_DP_MSA_TIMING_PARAM2 0x244d
|
#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2
|
#define mmDP3_DP_MSA_TIMING_PARAM3 0x244e
|
#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2
|
#define mmDP3_DP_MSA_TIMING_PARAM4 0x244f
|
#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2
|
#define mmDP3_DP_MSO_CNTL 0x2450
|
#define mmDP3_DP_MSO_CNTL_BASE_IDX 2
|
#define mmDP3_DP_MSO_CNTL1 0x2451
|
#define mmDP3_DP_MSO_CNTL1_BASE_IDX 2
|
#define mmDP3_DP_DSC_CNTL 0x2452
|
#define mmDP3_DP_DSC_CNTL_BASE_IDX 2
|
#define mmDP3_DP_SEC_CNTL2 0x2453
|
#define mmDP3_DP_SEC_CNTL2_BASE_IDX 2
|
#define mmDP3_DP_SEC_CNTL3 0x2454
|
#define mmDP3_DP_SEC_CNTL3_BASE_IDX 2
|
#define mmDP3_DP_SEC_CNTL4 0x2455
|
#define mmDP3_DP_SEC_CNTL4_BASE_IDX 2
|
#define mmDP3_DP_SEC_CNTL5 0x2456
|
#define mmDP3_DP_SEC_CNTL5_BASE_IDX 2
|
#define mmDP3_DP_SEC_CNTL6 0x2457
|
#define mmDP3_DP_SEC_CNTL6_BASE_IDX 2
|
#define mmDP3_DP_SEC_CNTL7 0x2458
|
#define mmDP3_DP_SEC_CNTL7_BASE_IDX 2
|
#define mmDP3_DP_DB_CNTL 0x2459
|
#define mmDP3_DP_DB_CNTL_BASE_IDX 2
|
#define mmDP3_DP_MSA_VBID_MISC 0x245a
|
#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2
|
#define mmDP3_DP_SEC_METADATA_TRANSMISSION 0x245b
|
#define mmDP3_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
|
#define mmDP3_DP_DSC_BYTES_PER_PIXEL 0x245c
|
#define mmDP3_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmDP3_DP_ALPM_CNTL 0x245d
|
#define mmDP3_DP_ALPM_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dig4_dispdec
|
// base address: 0x1000
|
#define mmDIG4_DIG_FE_CNTL 0x2468
|
#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
|
#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x2469
|
#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
|
#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x246a
|
#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
|
#define mmDIG4_DIG_CLOCK_PATTERN 0x246b
|
#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
|
#define mmDIG4_DIG_TEST_PATTERN 0x246c
|
#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
|
#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x246d
|
#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
|
#define mmDIG4_DIG_FIFO_STATUS 0x246e
|
#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
|
#define mmDIG4_HDMI_METADATA_PACKET_CONTROL 0x246f
|
#define mmDIG4_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4 0x2470
|
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
|
#define mmDIG4_HDMI_CONTROL 0x2471
|
#define mmDIG4_HDMI_CONTROL_BASE_IDX 2
|
#define mmDIG4_HDMI_STATUS 0x2472
|
#define mmDIG4_HDMI_STATUS_BASE_IDX 2
|
#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2473
|
#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2474
|
#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2475
|
#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2476
|
#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2477
|
#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
|
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2478
|
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
|
#define mmDIG4_AFMT_INTERRUPT_STATUS 0x2479
|
#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDIG4_HDMI_GC 0x247b
|
#define mmDIG4_HDMI_GC_BASE_IDX 2
|
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x247c
|
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG4_AFMT_ISRC1_0 0x247d
|
#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2
|
#define mmDIG4_AFMT_ISRC1_1 0x247e
|
#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2
|
#define mmDIG4_AFMT_ISRC1_2 0x247f
|
#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2
|
#define mmDIG4_AFMT_ISRC1_3 0x2480
|
#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2
|
#define mmDIG4_AFMT_ISRC1_4 0x2481
|
#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2
|
#define mmDIG4_AFMT_ISRC2_0 0x2482
|
#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2
|
#define mmDIG4_AFMT_ISRC2_1 0x2483
|
#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2
|
#define mmDIG4_AFMT_ISRC2_2 0x2484
|
#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2
|
#define mmDIG4_AFMT_ISRC2_3 0x2485
|
#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2
|
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x2486
|
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x2487
|
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
|
#define mmDIG4_HDMI_DB_CONTROL 0x2488
|
#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2
|
#define mmDIG4_DME_CONTROL 0x2489
|
#define mmDIG4_DME_CONTROL_BASE_IDX 2
|
#define mmDIG4_AFMT_MPEG_INFO0 0x248a
|
#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2
|
#define mmDIG4_AFMT_MPEG_INFO1 0x248b
|
#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2
|
#define mmDIG4_AFMT_GENERIC_HDR 0x248c
|
#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2
|
#define mmDIG4_AFMT_GENERIC_0 0x248d
|
#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2
|
#define mmDIG4_AFMT_GENERIC_1 0x248e
|
#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2
|
#define mmDIG4_AFMT_GENERIC_2 0x248f
|
#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2
|
#define mmDIG4_AFMT_GENERIC_3 0x2490
|
#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2
|
#define mmDIG4_AFMT_GENERIC_4 0x2491
|
#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2
|
#define mmDIG4_AFMT_GENERIC_5 0x2492
|
#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2
|
#define mmDIG4_AFMT_GENERIC_6 0x2493
|
#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2
|
#define mmDIG4_AFMT_GENERIC_7 0x2494
|
#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2
|
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2495
|
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG4_HDMI_ACR_32_0 0x2496
|
#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
|
#define mmDIG4_HDMI_ACR_32_1 0x2497
|
#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
|
#define mmDIG4_HDMI_ACR_44_0 0x2498
|
#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
|
#define mmDIG4_HDMI_ACR_44_1 0x2499
|
#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
|
#define mmDIG4_HDMI_ACR_48_0 0x249a
|
#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
|
#define mmDIG4_HDMI_ACR_48_1 0x249b
|
#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
|
#define mmDIG4_HDMI_ACR_STATUS_0 0x249c
|
#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
|
#define mmDIG4_HDMI_ACR_STATUS_1 0x249d
|
#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
|
#define mmDIG4_AFMT_AUDIO_INFO0 0x249e
|
#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2
|
#define mmDIG4_AFMT_AUDIO_INFO1 0x249f
|
#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2
|
#define mmDIG4_AFMT_60958_0 0x24a0
|
#define mmDIG4_AFMT_60958_0_BASE_IDX 2
|
#define mmDIG4_AFMT_60958_1 0x24a1
|
#define mmDIG4_AFMT_60958_1_BASE_IDX 2
|
#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x24a2
|
#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
|
#define mmDIG4_AFMT_RAMP_CONTROL0 0x24a3
|
#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2
|
#define mmDIG4_AFMT_RAMP_CONTROL1 0x24a4
|
#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2
|
#define mmDIG4_AFMT_RAMP_CONTROL2 0x24a5
|
#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2
|
#define mmDIG4_AFMT_RAMP_CONTROL3 0x24a6
|
#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2
|
#define mmDIG4_AFMT_60958_2 0x24a7
|
#define mmDIG4_AFMT_60958_2_BASE_IDX 2
|
#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x24a8
|
#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
|
#define mmDIG4_AFMT_STATUS 0x24a9
|
#define mmDIG4_AFMT_STATUS_BASE_IDX 2
|
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x24aa
|
#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x24ab
|
#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x24ac
|
#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x24ad
|
#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
|
#define mmDIG4_DIG_BE_CNTL 0x24af
|
#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
|
#define mmDIG4_DIG_BE_EN_CNTL 0x24b0
|
#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
|
#define mmDIG4_TMDS_CNTL 0x24d3
|
#define mmDIG4_TMDS_CNTL_BASE_IDX 2
|
#define mmDIG4_TMDS_CONTROL_CHAR 0x24d4
|
#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
|
#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d5
|
#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
|
#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24d6
|
#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
|
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24d7
|
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
|
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24d8
|
#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
|
#define mmDIG4_TMDS_CTL_BITS 0x24da
|
#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
|
#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24db
|
#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
|
#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR 0x24dc
|
#define mmDIG4_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
|
#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24dd
|
#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
|
#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24de
|
#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
|
#define mmDIG4_DIG_VERSION 0x24e0
|
#define mmDIG4_DIG_VERSION_BASE_IDX 2
|
#define mmDIG4_DIG_LANE_ENABLE 0x24e1
|
#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
|
#define mmDIG4_AFMT_CNTL 0x24e6
|
#define mmDIG4_AFMT_CNTL_BASE_IDX 2
|
#define mmDIG4_AFMT_VBI_PACKET_CONTROL1 0x24e7
|
#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5 0x24f6
|
#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
|
#define mmDIG4_FORCE_DIG_DISABLE 0x24f7
|
#define mmDIG4_FORCE_DIG_DISABLE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp4_dispdec
|
// base address: 0x1000
|
#define mmDP4_DP_LINK_CNTL 0x2508
|
#define mmDP4_DP_LINK_CNTL_BASE_IDX 2
|
#define mmDP4_DP_PIXEL_FORMAT 0x2509
|
#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
|
#define mmDP4_DP_MSA_COLORIMETRY 0x250a
|
#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
|
#define mmDP4_DP_CONFIG 0x250b
|
#define mmDP4_DP_CONFIG_BASE_IDX 2
|
#define mmDP4_DP_VID_STREAM_CNTL 0x250c
|
#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
|
#define mmDP4_DP_STEER_FIFO 0x250d
|
#define mmDP4_DP_STEER_FIFO_BASE_IDX 2
|
#define mmDP4_DP_MSA_MISC 0x250e
|
#define mmDP4_DP_MSA_MISC_BASE_IDX 2
|
#define mmDP4_DP_VID_TIMING 0x2510
|
#define mmDP4_DP_VID_TIMING_BASE_IDX 2
|
#define mmDP4_DP_VID_N 0x2511
|
#define mmDP4_DP_VID_N_BASE_IDX 2
|
#define mmDP4_DP_VID_M 0x2512
|
#define mmDP4_DP_VID_M_BASE_IDX 2
|
#define mmDP4_DP_LINK_FRAMING_CNTL 0x2513
|
#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
|
#define mmDP4_DP_HBR2_EYE_PATTERN 0x2514
|
#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
|
#define mmDP4_DP_VID_MSA_VBID 0x2515
|
#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
|
#define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516
|
#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmDP4_DP_DPHY_CNTL 0x2517
|
#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
|
#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518
|
#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
|
#define mmDP4_DP_DPHY_SYM0 0x2519
|
#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
|
#define mmDP4_DP_DPHY_SYM1 0x251a
|
#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
|
#define mmDP4_DP_DPHY_SYM2 0x251b
|
#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
|
#define mmDP4_DP_DPHY_8B10B_CNTL 0x251c
|
#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
|
#define mmDP4_DP_DPHY_PRBS_CNTL 0x251d
|
#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
|
#define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e
|
#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
|
#define mmDP4_DP_DPHY_CRC_EN 0x251f
|
#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
|
#define mmDP4_DP_DPHY_CRC_CNTL 0x2520
|
#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
|
#define mmDP4_DP_DPHY_CRC_RESULT 0x2521
|
#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
|
#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522
|
#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
|
#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523
|
#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
|
#define mmDP4_DP_DPHY_FAST_TRAINING 0x2524
|
#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
|
#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525
|
#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
|
#define mmDP4_DP_SEC_CNTL 0x252b
|
#define mmDP4_DP_SEC_CNTL_BASE_IDX 2
|
#define mmDP4_DP_SEC_CNTL1 0x252c
|
#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
|
#define mmDP4_DP_SEC_FRAMING1 0x252d
|
#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
|
#define mmDP4_DP_SEC_FRAMING2 0x252e
|
#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
|
#define mmDP4_DP_SEC_FRAMING3 0x252f
|
#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
|
#define mmDP4_DP_SEC_FRAMING4 0x2530
|
#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
|
#define mmDP4_DP_SEC_AUD_N 0x2531
|
#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
|
#define mmDP4_DP_SEC_AUD_N_READBACK 0x2532
|
#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
|
#define mmDP4_DP_SEC_AUD_M 0x2533
|
#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
|
#define mmDP4_DP_SEC_AUD_M_READBACK 0x2534
|
#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
|
#define mmDP4_DP_SEC_TIMESTAMP 0x2535
|
#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
|
#define mmDP4_DP_SEC_PACKET_CNTL 0x2536
|
#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
|
#define mmDP4_DP_MSE_RATE_CNTL 0x2537
|
#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
|
#define mmDP4_DP_MSE_RATE_UPDATE 0x2539
|
#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
|
#define mmDP4_DP_MSE_SAT0 0x253a
|
#define mmDP4_DP_MSE_SAT0_BASE_IDX 2
|
#define mmDP4_DP_MSE_SAT1 0x253b
|
#define mmDP4_DP_MSE_SAT1_BASE_IDX 2
|
#define mmDP4_DP_MSE_SAT2 0x253c
|
#define mmDP4_DP_MSE_SAT2_BASE_IDX 2
|
#define mmDP4_DP_MSE_SAT_UPDATE 0x253d
|
#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
|
#define mmDP4_DP_MSE_LINK_TIMING 0x253e
|
#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
|
#define mmDP4_DP_MSE_MISC_CNTL 0x253f
|
#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
|
#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544
|
#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
|
#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545
|
#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
|
#define mmDP4_DP_MSE_SAT0_STATUS 0x2547
|
#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
|
#define mmDP4_DP_MSE_SAT1_STATUS 0x2548
|
#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
|
#define mmDP4_DP_MSE_SAT2_STATUS 0x2549
|
#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
|
#define mmDP4_DP_MSA_TIMING_PARAM1 0x254c
|
#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2
|
#define mmDP4_DP_MSA_TIMING_PARAM2 0x254d
|
#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2
|
#define mmDP4_DP_MSA_TIMING_PARAM3 0x254e
|
#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2
|
#define mmDP4_DP_MSA_TIMING_PARAM4 0x254f
|
#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2
|
#define mmDP4_DP_MSO_CNTL 0x2550
|
#define mmDP4_DP_MSO_CNTL_BASE_IDX 2
|
#define mmDP4_DP_MSO_CNTL1 0x2551
|
#define mmDP4_DP_MSO_CNTL1_BASE_IDX 2
|
#define mmDP4_DP_DSC_CNTL 0x2552
|
#define mmDP4_DP_DSC_CNTL_BASE_IDX 2
|
#define mmDP4_DP_SEC_CNTL2 0x2553
|
#define mmDP4_DP_SEC_CNTL2_BASE_IDX 2
|
#define mmDP4_DP_SEC_CNTL3 0x2554
|
#define mmDP4_DP_SEC_CNTL3_BASE_IDX 2
|
#define mmDP4_DP_SEC_CNTL4 0x2555
|
#define mmDP4_DP_SEC_CNTL4_BASE_IDX 2
|
#define mmDP4_DP_SEC_CNTL5 0x2556
|
#define mmDP4_DP_SEC_CNTL5_BASE_IDX 2
|
#define mmDP4_DP_SEC_CNTL6 0x2557
|
#define mmDP4_DP_SEC_CNTL6_BASE_IDX 2
|
#define mmDP4_DP_SEC_CNTL7 0x2558
|
#define mmDP4_DP_SEC_CNTL7_BASE_IDX 2
|
#define mmDP4_DP_DB_CNTL 0x2559
|
#define mmDP4_DP_DB_CNTL_BASE_IDX 2
|
#define mmDP4_DP_MSA_VBID_MISC 0x255a
|
#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2
|
#define mmDP4_DP_SEC_METADATA_TRANSMISSION 0x255b
|
#define mmDP4_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
|
#define mmDP4_DP_DSC_BYTES_PER_PIXEL 0x255c
|
#define mmDP4_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmDP4_DP_ALPM_CNTL 0x255d
|
#define mmDP4_DP_ALPM_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dig5_dispdec
|
// base address: 0x1400
|
#define mmDIG5_DIG_FE_CNTL 0x2568
|
#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
|
#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x2569
|
#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
|
#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x256a
|
#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
|
#define mmDIG5_DIG_CLOCK_PATTERN 0x256b
|
#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
|
#define mmDIG5_DIG_TEST_PATTERN 0x256c
|
#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
|
#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x256d
|
#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
|
#define mmDIG5_DIG_FIFO_STATUS 0x256e
|
#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
|
#define mmDIG5_HDMI_METADATA_PACKET_CONTROL 0x256f
|
#define mmDIG5_HDMI_METADATA_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4 0x2570
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL4_BASE_IDX 2
|
#define mmDIG5_HDMI_CONTROL 0x2571
|
#define mmDIG5_HDMI_CONTROL_BASE_IDX 2
|
#define mmDIG5_HDMI_STATUS 0x2572
|
#define mmDIG5_HDMI_STATUS_BASE_IDX 2
|
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x2573
|
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x2574
|
#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x2575
|
#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x2576
|
#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x2577
|
#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x2578
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
|
#define mmDIG5_AFMT_INTERRUPT_STATUS 0x2579
|
#define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDIG5_HDMI_GC 0x257b
|
#define mmDIG5_HDMI_GC_BASE_IDX 2
|
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x257c
|
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC1_0 0x257d
|
#define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC1_1 0x257e
|
#define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC1_2 0x257f
|
#define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC1_3 0x2580
|
#define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC1_4 0x2581
|
#define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC2_0 0x2582
|
#define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC2_1 0x2583
|
#define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC2_2 0x2584
|
#define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC2_3 0x2585
|
#define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0x2586
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0x2587
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
|
#define mmDIG5_HDMI_DB_CONTROL 0x2588
|
#define mmDIG5_HDMI_DB_CONTROL_BASE_IDX 2
|
#define mmDIG5_DME_CONTROL 0x2589
|
#define mmDIG5_DME_CONTROL_BASE_IDX 2
|
#define mmDIG5_AFMT_MPEG_INFO0 0x258a
|
#define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2
|
#define mmDIG5_AFMT_MPEG_INFO1 0x258b
|
#define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_HDR 0x258c
|
#define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_0 0x258d
|
#define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_1 0x258e
|
#define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_2 0x258f
|
#define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_3 0x2590
|
#define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_4 0x2591
|
#define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_5 0x2592
|
#define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_6 0x2593
|
#define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_7 0x2594
|
#define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x2595
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_32_0 0x2596
|
#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_32_1 0x2597
|
#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_44_0 0x2598
|
#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_44_1 0x2599
|
#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_48_0 0x259a
|
#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_48_1 0x259b
|
#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_STATUS_0 0x259c
|
#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_STATUS_1 0x259d
|
#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
|
#define mmDIG5_AFMT_AUDIO_INFO0 0x259e
|
#define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2
|
#define mmDIG5_AFMT_AUDIO_INFO1 0x259f
|
#define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2
|
#define mmDIG5_AFMT_60958_0 0x25a0
|
#define mmDIG5_AFMT_60958_0_BASE_IDX 2
|
#define mmDIG5_AFMT_60958_1 0x25a1
|
#define mmDIG5_AFMT_60958_1_BASE_IDX 2
|
#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x25a2
|
#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
|
#define mmDIG5_AFMT_RAMP_CONTROL0 0x25a3
|
#define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2
|
#define mmDIG5_AFMT_RAMP_CONTROL1 0x25a4
|
#define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2
|
#define mmDIG5_AFMT_RAMP_CONTROL2 0x25a5
|
#define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2
|
#define mmDIG5_AFMT_RAMP_CONTROL3 0x25a6
|
#define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2
|
#define mmDIG5_AFMT_60958_2 0x25a7
|
#define mmDIG5_AFMT_60958_2_BASE_IDX 2
|
#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x25a8
|
#define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
|
#define mmDIG5_AFMT_STATUS 0x25a9
|
#define mmDIG5_AFMT_STATUS_BASE_IDX 2
|
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x25aa
|
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x25ab
|
#define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x25ac
|
#define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x25ad
|
#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
|
#define mmDIG5_DIG_BE_CNTL 0x25af
|
#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
|
#define mmDIG5_DIG_BE_EN_CNTL 0x25b0
|
#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
|
#define mmDIG5_TMDS_CNTL 0x25d3
|
#define mmDIG5_TMDS_CNTL_BASE_IDX 2
|
#define mmDIG5_TMDS_CONTROL_CHAR 0x25d4
|
#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
|
#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x25d5
|
#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
|
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x25d6
|
#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
|
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x25d7
|
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
|
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x25d8
|
#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
|
#define mmDIG5_TMDS_CTL_BITS 0x25da
|
#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
|
#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x25db
|
#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
|
#define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR 0x25dc
|
#define mmDIG5_TMDS_SYNC_DCBALANCE_CHAR_BASE_IDX 2
|
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x25dd
|
#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
|
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x25de
|
#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
|
#define mmDIG5_DIG_VERSION 0x25e0
|
#define mmDIG5_DIG_VERSION_BASE_IDX 2
|
#define mmDIG5_DIG_LANE_ENABLE 0x25e1
|
#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
|
#define mmDIG5_AFMT_CNTL 0x25e6
|
#define mmDIG5_AFMT_CNTL_BASE_IDX 2
|
#define mmDIG5_AFMT_VBI_PACKET_CONTROL1 0x25e7
|
#define mmDIG5_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5 0x25f6
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL5_BASE_IDX 2
|
#define mmDIG5_FORCE_DIG_DISABLE 0x25f7
|
#define mmDIG5_FORCE_DIG_DISABLE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp5_dispdec
|
// base address: 0x1400
|
#define mmDP5_DP_LINK_CNTL 0x2608
|
#define mmDP5_DP_LINK_CNTL_BASE_IDX 2
|
#define mmDP5_DP_PIXEL_FORMAT 0x2609
|
#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
|
#define mmDP5_DP_MSA_COLORIMETRY 0x260a
|
#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
|
#define mmDP5_DP_CONFIG 0x260b
|
#define mmDP5_DP_CONFIG_BASE_IDX 2
|
#define mmDP5_DP_VID_STREAM_CNTL 0x260c
|
#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
|
#define mmDP5_DP_STEER_FIFO 0x260d
|
#define mmDP5_DP_STEER_FIFO_BASE_IDX 2
|
#define mmDP5_DP_MSA_MISC 0x260e
|
#define mmDP5_DP_MSA_MISC_BASE_IDX 2
|
#define mmDP5_DP_VID_TIMING 0x2610
|
#define mmDP5_DP_VID_TIMING_BASE_IDX 2
|
#define mmDP5_DP_VID_N 0x2611
|
#define mmDP5_DP_VID_N_BASE_IDX 2
|
#define mmDP5_DP_VID_M 0x2612
|
#define mmDP5_DP_VID_M_BASE_IDX 2
|
#define mmDP5_DP_LINK_FRAMING_CNTL 0x2613
|
#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
|
#define mmDP5_DP_HBR2_EYE_PATTERN 0x2614
|
#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
|
#define mmDP5_DP_VID_MSA_VBID 0x2615
|
#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
|
#define mmDP5_DP_VID_INTERRUPT_CNTL 0x2616
|
#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CNTL 0x2617
|
#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x2618
|
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_SYM0 0x2619
|
#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
|
#define mmDP5_DP_DPHY_SYM1 0x261a
|
#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
|
#define mmDP5_DP_DPHY_SYM2 0x261b
|
#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
|
#define mmDP5_DP_DPHY_8B10B_CNTL 0x261c
|
#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_PRBS_CNTL 0x261d
|
#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_SCRAM_CNTL 0x261e
|
#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_EN 0x261f
|
#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_CNTL 0x2620
|
#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_RESULT 0x2621
|
#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x2622
|
#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x2623
|
#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
|
#define mmDP5_DP_DPHY_FAST_TRAINING 0x2624
|
#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
|
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x2625
|
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL 0x262b
|
#define mmDP5_DP_SEC_CNTL_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL1 0x262c
|
#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
|
#define mmDP5_DP_SEC_FRAMING1 0x262d
|
#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
|
#define mmDP5_DP_SEC_FRAMING2 0x262e
|
#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
|
#define mmDP5_DP_SEC_FRAMING3 0x262f
|
#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
|
#define mmDP5_DP_SEC_FRAMING4 0x2630
|
#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
|
#define mmDP5_DP_SEC_AUD_N 0x2631
|
#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
|
#define mmDP5_DP_SEC_AUD_N_READBACK 0x2632
|
#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
|
#define mmDP5_DP_SEC_AUD_M 0x2633
|
#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
|
#define mmDP5_DP_SEC_AUD_M_READBACK 0x2634
|
#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
|
#define mmDP5_DP_SEC_TIMESTAMP 0x2635
|
#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
|
#define mmDP5_DP_SEC_PACKET_CNTL 0x2636
|
#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
|
#define mmDP5_DP_MSE_RATE_CNTL 0x2637
|
#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
|
#define mmDP5_DP_MSE_RATE_UPDATE 0x2639
|
#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT0 0x263a
|
#define mmDP5_DP_MSE_SAT0_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT1 0x263b
|
#define mmDP5_DP_MSE_SAT1_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT2 0x263c
|
#define mmDP5_DP_MSE_SAT2_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT_UPDATE 0x263d
|
#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
|
#define mmDP5_DP_MSE_LINK_TIMING 0x263e
|
#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
|
#define mmDP5_DP_MSE_MISC_CNTL 0x263f
|
#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x2644
|
#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x2645
|
#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT0_STATUS 0x2647
|
#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT1_STATUS 0x2648
|
#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
|
#define mmDP5_DP_MSE_SAT2_STATUS 0x2649
|
#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
|
#define mmDP5_DP_MSA_TIMING_PARAM1 0x264c
|
#define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 2
|
#define mmDP5_DP_MSA_TIMING_PARAM2 0x264d
|
#define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX 2
|
#define mmDP5_DP_MSA_TIMING_PARAM3 0x264e
|
#define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX 2
|
#define mmDP5_DP_MSA_TIMING_PARAM4 0x264f
|
#define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX 2
|
#define mmDP5_DP_MSO_CNTL 0x2650
|
#define mmDP5_DP_MSO_CNTL_BASE_IDX 2
|
#define mmDP5_DP_MSO_CNTL1 0x2651
|
#define mmDP5_DP_MSO_CNTL1_BASE_IDX 2
|
#define mmDP5_DP_DSC_CNTL 0x2652
|
#define mmDP5_DP_DSC_CNTL_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL2 0x2653
|
#define mmDP5_DP_SEC_CNTL2_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL3 0x2654
|
#define mmDP5_DP_SEC_CNTL3_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL4 0x2655
|
#define mmDP5_DP_SEC_CNTL4_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL5 0x2656
|
#define mmDP5_DP_SEC_CNTL5_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL6 0x2657
|
#define mmDP5_DP_SEC_CNTL6_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL7 0x2658
|
#define mmDP5_DP_SEC_CNTL7_BASE_IDX 2
|
#define mmDP5_DP_DB_CNTL 0x2659
|
#define mmDP5_DP_DB_CNTL_BASE_IDX 2
|
#define mmDP5_DP_MSA_VBID_MISC 0x265a
|
#define mmDP5_DP_MSA_VBID_MISC_BASE_IDX 2
|
#define mmDP5_DP_SEC_METADATA_TRANSMISSION 0x265b
|
#define mmDP5_DP_SEC_METADATA_TRANSMISSION_BASE_IDX 2
|
#define mmDP5_DP_DSC_BYTES_PER_PIXEL 0x265c
|
#define mmDP5_DP_DSC_BYTES_PER_PIXEL_BASE_IDX 2
|
#define mmDP5_DP_ALPM_CNTL 0x265d
|
#define mmDP5_DP_ALPM_CNTL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcio_dcio_dispdec
|
// base address: 0x0
|
#define mmDC_GENERICA 0x2868
|
#define mmDC_GENERICA_BASE_IDX 2
|
#define mmDC_GENERICB 0x2869
|
#define mmDC_GENERICB_BASE_IDX 2
|
#define mmDC_REF_CLK_CNTL 0x286b
|
#define mmDC_REF_CLK_CNTL_BASE_IDX 2
|
#define mmUNIPHYA_LINK_CNTL 0x286d
|
#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
|
#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYB_LINK_CNTL 0x286f
|
#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
|
#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYC_LINK_CNTL 0x2871
|
#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
|
#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYD_LINK_CNTL 0x2873
|
#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
|
#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYE_LINK_CNTL 0x2875
|
#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
|
#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYF_LINK_CNTL 0x2877
|
#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x2878
|
#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmDCIO_WRCMD_DELAY 0x287e
|
#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
|
#define mmDC_PINSTRAPS 0x2880
|
#define mmDC_PINSTRAPS_BASE_IDX 2
|
#define mmLVTMA_PWRSEQ_CNTL 0x2883
|
#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
|
#define mmLVTMA_PWRSEQ_STATE 0x2884
|
#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
|
#define mmLVTMA_PWRSEQ_REF_DIV 0x2885
|
#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
|
#define mmLVTMA_PWRSEQ_DELAY1 0x2886
|
#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
|
#define mmLVTMA_PWRSEQ_DELAY2 0x2887
|
#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
|
#define mmBL_PWM_CNTL 0x2888
|
#define mmBL_PWM_CNTL_BASE_IDX 2
|
#define mmBL_PWM_CNTL2 0x2889
|
#define mmBL_PWM_CNTL2_BASE_IDX 2
|
#define mmBL_PWM_PERIOD_CNTL 0x288a
|
#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
|
#define mmBL_PWM_GRP1_REG_LOCK 0x288b
|
#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
|
#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c
|
#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
|
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
|
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
|
#define mmDCIO_CLOCK_CNTL 0x2895
|
#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
|
#define mmDCIO_SOFT_RESET 0x289e
|
#define mmDCIO_SOFT_RESET_BASE_IDX 2
|
#define mmAUXP_IMPCAL 0x28a3
|
#define mmAUXP_IMPCAL_BASE_IDX 2
|
#define mmAUXN_IMPCAL 0x28a4
|
#define mmAUXN_IMPCAL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcio_dcio_chip_dispdec
|
// base address: 0x0
|
#define mmDC_GPIO_GENERIC_MASK 0x28c8
|
#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
|
#define mmDC_GPIO_GENERIC_A 0x28c9
|
#define mmDC_GPIO_GENERIC_A_BASE_IDX 2
|
#define mmDC_GPIO_GENERIC_EN 0x28ca
|
#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
|
#define mmDC_GPIO_GENERIC_Y 0x28cb
|
#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
|
#define mmDC_GPIO_DDC1_MASK 0x28d0
|
#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
|
#define mmDC_GPIO_DDC1_A 0x28d1
|
#define mmDC_GPIO_DDC1_A_BASE_IDX 2
|
#define mmDC_GPIO_DDC1_EN 0x28d2
|
#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
|
#define mmDC_GPIO_DDC1_Y 0x28d3
|
#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
|
#define mmDC_GPIO_DDC2_MASK 0x28d4
|
#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
|
#define mmDC_GPIO_DDC2_A 0x28d5
|
#define mmDC_GPIO_DDC2_A_BASE_IDX 2
|
#define mmDC_GPIO_DDC2_EN 0x28d6
|
#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
|
#define mmDC_GPIO_DDC2_Y 0x28d7
|
#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
|
#define mmDC_GPIO_DDC3_MASK 0x28d8
|
#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
|
#define mmDC_GPIO_DDC3_A 0x28d9
|
#define mmDC_GPIO_DDC3_A_BASE_IDX 2
|
#define mmDC_GPIO_DDC3_EN 0x28da
|
#define mmDC_GPIO_DDC3_EN_BASE_IDX 2
|
#define mmDC_GPIO_DDC3_Y 0x28db
|
#define mmDC_GPIO_DDC3_Y_BASE_IDX 2
|
#define mmDC_GPIO_DDC4_MASK 0x28dc
|
#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
|
#define mmDC_GPIO_DDC4_A 0x28dd
|
#define mmDC_GPIO_DDC4_A_BASE_IDX 2
|
#define mmDC_GPIO_DDC4_EN 0x28de
|
#define mmDC_GPIO_DDC4_EN_BASE_IDX 2
|
#define mmDC_GPIO_DDC4_Y 0x28df
|
#define mmDC_GPIO_DDC4_Y_BASE_IDX 2
|
#define mmDC_GPIO_DDC5_MASK 0x28e0
|
#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
|
#define mmDC_GPIO_DDC5_A 0x28e1
|
#define mmDC_GPIO_DDC5_A_BASE_IDX 2
|
#define mmDC_GPIO_DDC5_EN 0x28e2
|
#define mmDC_GPIO_DDC5_EN_BASE_IDX 2
|
#define mmDC_GPIO_DDC5_Y 0x28e3
|
#define mmDC_GPIO_DDC5_Y_BASE_IDX 2
|
#define mmDC_GPIO_DDC6_MASK 0x28e4
|
#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
|
#define mmDC_GPIO_DDC6_A 0x28e5
|
#define mmDC_GPIO_DDC6_A_BASE_IDX 2
|
#define mmDC_GPIO_DDC6_EN 0x28e6
|
#define mmDC_GPIO_DDC6_EN_BASE_IDX 2
|
#define mmDC_GPIO_DDC6_Y 0x28e7
|
#define mmDC_GPIO_DDC6_Y_BASE_IDX 2
|
#define mmDC_GPIO_DDCVGA_MASK 0x28e8
|
#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
|
#define mmDC_GPIO_DDCVGA_A 0x28e9
|
#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
|
#define mmDC_GPIO_DDCVGA_EN 0x28ea
|
#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
|
#define mmDC_GPIO_DDCVGA_Y 0x28eb
|
#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
|
#define mmDC_GPIO_GENLK_MASK 0x28f0
|
#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
|
#define mmDC_GPIO_GENLK_A 0x28f1
|
#define mmDC_GPIO_GENLK_A_BASE_IDX 2
|
#define mmDC_GPIO_GENLK_EN 0x28f2
|
#define mmDC_GPIO_GENLK_EN_BASE_IDX 2
|
#define mmDC_GPIO_GENLK_Y 0x28f3
|
#define mmDC_GPIO_GENLK_Y_BASE_IDX 2
|
#define mmDC_GPIO_HPD_MASK 0x28f4
|
#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
|
#define mmDC_GPIO_HPD_A 0x28f5
|
#define mmDC_GPIO_HPD_A_BASE_IDX 2
|
#define mmDC_GPIO_HPD_EN 0x28f6
|
#define mmDC_GPIO_HPD_EN_BASE_IDX 2
|
#define mmDC_GPIO_HPD_Y 0x28f7
|
#define mmDC_GPIO_HPD_Y_BASE_IDX 2
|
#define mmDC_GPIO_PWRSEQ_MASK 0x28f8
|
#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
|
#define mmDC_GPIO_PWRSEQ_A 0x28f9
|
#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
|
#define mmDC_GPIO_PWRSEQ_EN 0x28fa
|
#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
|
#define mmDC_GPIO_PWRSEQ_Y 0x28fb
|
#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
|
#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc
|
#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
|
#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd
|
#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
|
#define mmPHY_AUX_CNTL 0x28ff
|
#define mmPHY_AUX_CNTL_BASE_IDX 2
|
#define mmDC_GPIO_TX12_EN 0x2915
|
#define mmDC_GPIO_TX12_EN_BASE_IDX 2
|
#define mmDC_GPIO_AUX_CTRL_0 0x2916
|
#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
|
#define mmDC_GPIO_AUX_CTRL_1 0x2917
|
#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
|
#define mmDC_GPIO_AUX_CTRL_2 0x2918
|
#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
|
#define mmDC_GPIO_RXEN 0x2919
|
#define mmDC_GPIO_RXEN_BASE_IDX 2
|
#define mmDC_GPIO_PULLUPEN 0x291a
|
#define mmDC_GPIO_PULLUPEN_BASE_IDX 2
|
#define mmDC_GPIO_AUX_CTRL_3 0x291b
|
#define mmDC_GPIO_AUX_CTRL_3_BASE_IDX 2
|
#define mmDC_GPIO_AUX_CTRL_4 0x291c
|
#define mmDC_GPIO_AUX_CTRL_4_BASE_IDX 2
|
#define mmDC_GPIO_AUX_CTRL_5 0x291d
|
#define mmDC_GPIO_AUX_CTRL_5_BASE_IDX 2
|
#define mmAUXI2C_PAD_ALL_PWR_OK 0x291e
|
#define mmAUXI2C_PAD_ALL_PWR_OK_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
|
// base address: 0x0
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957
|
#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
|
// base address: 0x360
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
|
// base address: 0x6c0
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07
|
#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
|
// base address: 0xa20
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf
|
#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcio_dcio_uniphy4_dispdec
|
// base address: 0xd80
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0 0x2c88
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1 0x2c89
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2 0x2c8a
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3 0x2c8b
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4 0x2c8c
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5 0x2c8d
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6 0x2c8e
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7 0x2c8f
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8 0x2c90
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9 0x2c91
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10 0x2c92
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11 0x2c93
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12 0x2c94
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13 0x2c95
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14 0x2c96
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15 0x2c97
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16 0x2c98
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17 0x2c99
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18 0x2c9a
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19 0x2c9b
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20 0x2c9c
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21 0x2c9d
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22 0x2c9e
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23 0x2c9f
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24 0x2ca0
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25 0x2ca1
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26 0x2ca2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27 0x2ca3
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28 0x2ca4
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29 0x2ca5
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30 0x2ca6
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31 0x2ca7
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32 0x2ca8
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33 0x2ca9
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34 0x2caa
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35 0x2cab
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36 0x2cac
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37 0x2cad
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38 0x2cae
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39 0x2caf
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40 0x2cb0
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41 0x2cb1
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42 0x2cb2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43 0x2cb3
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44 0x2cb4
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45 0x2cb5
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46 0x2cb6
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47 0x2cb7
|
#define mmDCIO_UNIPHY4_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcio_dcio_uniphy5_dispdec
|
// base address: 0x10e0
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0 0x2d60
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1 0x2d61
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2 0x2d62
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3 0x2d63
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4 0x2d64
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5 0x2d65
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6 0x2d66
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7 0x2d67
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8 0x2d68
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9 0x2d69
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10 0x2d6a
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11 0x2d6b
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12 0x2d6c
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13 0x2d6d
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14 0x2d6e
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15 0x2d6f
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16 0x2d70
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17 0x2d71
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18 0x2d72
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19 0x2d73
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20 0x2d74
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21 0x2d75
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22 0x2d76
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23 0x2d77
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24 0x2d78
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25 0x2d79
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26 0x2d7a
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27 0x2d7b
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28 0x2d7c
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29 0x2d7d
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30 0x2d7e
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31 0x2d7f
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32 0x2d80
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33 0x2d81
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34 0x2d82
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35 0x2d83
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36 0x2d84
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37 0x2d85
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38 0x2d86
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39 0x2d87
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40 0x2d88
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41 0x2d89
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42 0x2d8a
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43 0x2d8b
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44 0x2d8c
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45 0x2d8d
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46 0x2d8e
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47 0x2d8f
|
#define mmDCIO_UNIPHY5_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcio_dcio_uniphy6_dispdec
|
// base address: 0x1440
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0 0x2e38
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1 0x2e39
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2 0x2e3a
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3 0x2e3b
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4 0x2e3c
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5 0x2e3d
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6 0x2e3e
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7 0x2e3f
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8 0x2e40
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9 0x2e41
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10 0x2e42
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11 0x2e43
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12 0x2e44
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13 0x2e45
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14 0x2e46
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15 0x2e47
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16 0x2e48
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17 0x2e49
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18 0x2e4a
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19 0x2e4b
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20 0x2e4c
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21 0x2e4d
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22 0x2e4e
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23 0x2e4f
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24 0x2e50
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25 0x2e51
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26 0x2e52
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27 0x2e53
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28 0x2e54
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29 0x2e55
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30 0x2e56
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31 0x2e57
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32 0x2e58
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33 0x2e59
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34 0x2e5a
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35 0x2e5b
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36 0x2e5c
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37 0x2e5d
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38 0x2e5e
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39 0x2e5f
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40 0x2e60
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41 0x2e61
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42 0x2e62
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43 0x2e63
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44 0x2e64
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45 0x2e65
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46 0x2e66
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47 0x2e67
|
#define mmDCIO_UNIPHY6_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc0_dispdec_dsc_top_dispdec
|
// base address: 0x0
|
#define mmDSC_TOP0_DSC_TOP_CONTROL 0x3000
|
#define mmDSC_TOP0_DSC_TOP_CONTROL_BASE_IDX 2
|
#define mmDSC_TOP0_DSC_DEBUG_CONTROL 0x3001
|
#define mmDSC_TOP0_DSC_DEBUG_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
|
// base address: 0x0
|
#define mmDSCCIF0_DSCCIF_CONFIG0 0x3005
|
#define mmDSCCIF0_DSCCIF_CONFIG0_BASE_IDX 2
|
#define mmDSCCIF0_DSCCIF_CONFIG1 0x3006
|
#define mmDSCCIF0_DSCCIF_CONFIG1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc0_dispdec_dscc_dispdec
|
// base address: 0x0
|
#define mmDSCC0_DSCC_CONFIG0 0x300a
|
#define mmDSCC0_DSCC_CONFIG0_BASE_IDX 2
|
#define mmDSCC0_DSCC_CONFIG1 0x300b
|
#define mmDSCC0_DSCC_CONFIG1_BASE_IDX 2
|
#define mmDSCC0_DSCC_STATUS 0x300c
|
#define mmDSCC0_DSCC_STATUS_BASE_IDX 2
|
#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS 0x300d
|
#define mmDSCC0_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG0 0x300e
|
#define mmDSCC0_DSCC_PPS_CONFIG0_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG1 0x300f
|
#define mmDSCC0_DSCC_PPS_CONFIG1_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG2 0x3010
|
#define mmDSCC0_DSCC_PPS_CONFIG2_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG3 0x3011
|
#define mmDSCC0_DSCC_PPS_CONFIG3_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG4 0x3012
|
#define mmDSCC0_DSCC_PPS_CONFIG4_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG5 0x3013
|
#define mmDSCC0_DSCC_PPS_CONFIG5_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG6 0x3014
|
#define mmDSCC0_DSCC_PPS_CONFIG6_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG7 0x3015
|
#define mmDSCC0_DSCC_PPS_CONFIG7_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG8 0x3016
|
#define mmDSCC0_DSCC_PPS_CONFIG8_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG9 0x3017
|
#define mmDSCC0_DSCC_PPS_CONFIG9_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG10 0x3018
|
#define mmDSCC0_DSCC_PPS_CONFIG10_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG11 0x3019
|
#define mmDSCC0_DSCC_PPS_CONFIG11_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG12 0x301a
|
#define mmDSCC0_DSCC_PPS_CONFIG12_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG13 0x301b
|
#define mmDSCC0_DSCC_PPS_CONFIG13_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG14 0x301c
|
#define mmDSCC0_DSCC_PPS_CONFIG14_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG15 0x301d
|
#define mmDSCC0_DSCC_PPS_CONFIG15_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG16 0x301e
|
#define mmDSCC0_DSCC_PPS_CONFIG16_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG17 0x301f
|
#define mmDSCC0_DSCC_PPS_CONFIG17_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG18 0x3020
|
#define mmDSCC0_DSCC_PPS_CONFIG18_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG19 0x3021
|
#define mmDSCC0_DSCC_PPS_CONFIG19_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG20 0x3022
|
#define mmDSCC0_DSCC_PPS_CONFIG20_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG21 0x3023
|
#define mmDSCC0_DSCC_PPS_CONFIG21_BASE_IDX 2
|
#define mmDSCC0_DSCC_PPS_CONFIG22 0x3024
|
#define mmDSCC0_DSCC_PPS_CONFIG22_BASE_IDX 2
|
#define mmDSCC0_DSCC_MEM_POWER_CONTROL 0x3025
|
#define mmDSCC0_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
|
#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3026
|
#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3027
|
#define mmDSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3028
|
#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3029
|
#define mmDSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER 0x302a
|
#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER 0x302b
|
#define mmDSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC0_DSCC_MAX_ABS_ERROR0 0x302c
|
#define mmDSCC0_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
|
#define mmDSCC0_DSCC_MAX_ABS_ERROR1 0x302d
|
#define mmDSCC0_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
|
#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x302e
|
#define mmDSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x302f
|
#define mmDSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3030
|
#define mmDSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3031
|
#define mmDSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3032
|
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3033
|
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3034
|
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3035
|
#define mmDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE 0x303a
|
#define mmDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc0_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xc140
|
#define mmDC_PERFMON21_PERFCOUNTER_CNTL 0x3050
|
#define mmDC_PERFMON21_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON21_PERFCOUNTER_CNTL2 0x3051
|
#define mmDC_PERFMON21_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON21_PERFCOUNTER_STATE 0x3052
|
#define mmDC_PERFMON21_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON21_PERFMON_CNTL 0x3053
|
#define mmDC_PERFMON21_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON21_PERFMON_CNTL2 0x3054
|
#define mmDC_PERFMON21_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC 0x3055
|
#define mmDC_PERFMON21_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON21_PERFMON_CVALUE_LOW 0x3056
|
#define mmDC_PERFMON21_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON21_PERFMON_HI 0x3057
|
#define mmDC_PERFMON21_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON21_PERFMON_LOW 0x3058
|
#define mmDC_PERFMON21_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc1_dispdec_dsc_top_dispdec
|
// base address: 0x170
|
#define mmDSC_TOP1_DSC_TOP_CONTROL 0x305c
|
#define mmDSC_TOP1_DSC_TOP_CONTROL_BASE_IDX 2
|
#define mmDSC_TOP1_DSC_DEBUG_CONTROL 0x305d
|
#define mmDSC_TOP1_DSC_DEBUG_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
|
// base address: 0x170
|
#define mmDSCCIF1_DSCCIF_CONFIG0 0x3061
|
#define mmDSCCIF1_DSCCIF_CONFIG0_BASE_IDX 2
|
#define mmDSCCIF1_DSCCIF_CONFIG1 0x3062
|
#define mmDSCCIF1_DSCCIF_CONFIG1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
|
// base address: 0x170
|
#define mmDSCC1_DSCC_CONFIG0 0x3066
|
#define mmDSCC1_DSCC_CONFIG0_BASE_IDX 2
|
#define mmDSCC1_DSCC_CONFIG1 0x3067
|
#define mmDSCC1_DSCC_CONFIG1_BASE_IDX 2
|
#define mmDSCC1_DSCC_STATUS 0x3068
|
#define mmDSCC1_DSCC_STATUS_BASE_IDX 2
|
#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS 0x3069
|
#define mmDSCC1_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG0 0x306a
|
#define mmDSCC1_DSCC_PPS_CONFIG0_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG1 0x306b
|
#define mmDSCC1_DSCC_PPS_CONFIG1_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG2 0x306c
|
#define mmDSCC1_DSCC_PPS_CONFIG2_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG3 0x306d
|
#define mmDSCC1_DSCC_PPS_CONFIG3_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG4 0x306e
|
#define mmDSCC1_DSCC_PPS_CONFIG4_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG5 0x306f
|
#define mmDSCC1_DSCC_PPS_CONFIG5_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG6 0x3070
|
#define mmDSCC1_DSCC_PPS_CONFIG6_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG7 0x3071
|
#define mmDSCC1_DSCC_PPS_CONFIG7_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG8 0x3072
|
#define mmDSCC1_DSCC_PPS_CONFIG8_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG9 0x3073
|
#define mmDSCC1_DSCC_PPS_CONFIG9_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG10 0x3074
|
#define mmDSCC1_DSCC_PPS_CONFIG10_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG11 0x3075
|
#define mmDSCC1_DSCC_PPS_CONFIG11_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG12 0x3076
|
#define mmDSCC1_DSCC_PPS_CONFIG12_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG13 0x3077
|
#define mmDSCC1_DSCC_PPS_CONFIG13_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG14 0x3078
|
#define mmDSCC1_DSCC_PPS_CONFIG14_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG15 0x3079
|
#define mmDSCC1_DSCC_PPS_CONFIG15_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG16 0x307a
|
#define mmDSCC1_DSCC_PPS_CONFIG16_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG17 0x307b
|
#define mmDSCC1_DSCC_PPS_CONFIG17_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG18 0x307c
|
#define mmDSCC1_DSCC_PPS_CONFIG18_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG19 0x307d
|
#define mmDSCC1_DSCC_PPS_CONFIG19_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG20 0x307e
|
#define mmDSCC1_DSCC_PPS_CONFIG20_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG21 0x307f
|
#define mmDSCC1_DSCC_PPS_CONFIG21_BASE_IDX 2
|
#define mmDSCC1_DSCC_PPS_CONFIG22 0x3080
|
#define mmDSCC1_DSCC_PPS_CONFIG22_BASE_IDX 2
|
#define mmDSCC1_DSCC_MEM_POWER_CONTROL 0x3081
|
#define mmDSCC1_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
|
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3082
|
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3083
|
#define mmDSCC1_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3084
|
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3085
|
#define mmDSCC1_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER 0x3086
|
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER 0x3087
|
#define mmDSCC1_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC1_DSCC_MAX_ABS_ERROR0 0x3088
|
#define mmDSCC1_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
|
#define mmDSCC1_DSCC_MAX_ABS_ERROR1 0x3089
|
#define mmDSCC1_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x308a
|
#define mmDSCC1_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x308b
|
#define mmDSCC1_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x308c
|
#define mmDSCC1_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x308d
|
#define mmDSCC1_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x308e
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x308f
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3090
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3091
|
#define mmDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE 0x3096
|
#define mmDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc1_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xc2b0
|
#define mmDC_PERFMON22_PERFCOUNTER_CNTL 0x30ac
|
#define mmDC_PERFMON22_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFCOUNTER_CNTL2 0x30ad
|
#define mmDC_PERFMON22_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFCOUNTER_STATE 0x30ae
|
#define mmDC_PERFMON22_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFMON_CNTL 0x30af
|
#define mmDC_PERFMON22_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFMON_CNTL2 0x30b0
|
#define mmDC_PERFMON22_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC 0x30b1
|
#define mmDC_PERFMON22_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFMON_CVALUE_LOW 0x30b2
|
#define mmDC_PERFMON22_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFMON_HI 0x30b3
|
#define mmDC_PERFMON22_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON22_PERFMON_LOW 0x30b4
|
#define mmDC_PERFMON22_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc2_dispdec_dsc_top_dispdec
|
// base address: 0x2e0
|
#define mmDSC_TOP2_DSC_TOP_CONTROL 0x30b8
|
#define mmDSC_TOP2_DSC_TOP_CONTROL_BASE_IDX 2
|
#define mmDSC_TOP2_DSC_DEBUG_CONTROL 0x30b9
|
#define mmDSC_TOP2_DSC_DEBUG_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
|
// base address: 0x2e0
|
#define mmDSCCIF2_DSCCIF_CONFIG0 0x30bd
|
#define mmDSCCIF2_DSCCIF_CONFIG0_BASE_IDX 2
|
#define mmDSCCIF2_DSCCIF_CONFIG1 0x30be
|
#define mmDSCCIF2_DSCCIF_CONFIG1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc2_dispdec_dscc_dispdec
|
// base address: 0x2e0
|
#define mmDSCC2_DSCC_CONFIG0 0x30c2
|
#define mmDSCC2_DSCC_CONFIG0_BASE_IDX 2
|
#define mmDSCC2_DSCC_CONFIG1 0x30c3
|
#define mmDSCC2_DSCC_CONFIG1_BASE_IDX 2
|
#define mmDSCC2_DSCC_STATUS 0x30c4
|
#define mmDSCC2_DSCC_STATUS_BASE_IDX 2
|
#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS 0x30c5
|
#define mmDSCC2_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG0 0x30c6
|
#define mmDSCC2_DSCC_PPS_CONFIG0_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG1 0x30c7
|
#define mmDSCC2_DSCC_PPS_CONFIG1_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG2 0x30c8
|
#define mmDSCC2_DSCC_PPS_CONFIG2_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG3 0x30c9
|
#define mmDSCC2_DSCC_PPS_CONFIG3_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG4 0x30ca
|
#define mmDSCC2_DSCC_PPS_CONFIG4_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG5 0x30cb
|
#define mmDSCC2_DSCC_PPS_CONFIG5_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG6 0x30cc
|
#define mmDSCC2_DSCC_PPS_CONFIG6_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG7 0x30cd
|
#define mmDSCC2_DSCC_PPS_CONFIG7_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG8 0x30ce
|
#define mmDSCC2_DSCC_PPS_CONFIG8_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG9 0x30cf
|
#define mmDSCC2_DSCC_PPS_CONFIG9_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG10 0x30d0
|
#define mmDSCC2_DSCC_PPS_CONFIG10_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG11 0x30d1
|
#define mmDSCC2_DSCC_PPS_CONFIG11_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG12 0x30d2
|
#define mmDSCC2_DSCC_PPS_CONFIG12_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG13 0x30d3
|
#define mmDSCC2_DSCC_PPS_CONFIG13_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG14 0x30d4
|
#define mmDSCC2_DSCC_PPS_CONFIG14_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG15 0x30d5
|
#define mmDSCC2_DSCC_PPS_CONFIG15_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG16 0x30d6
|
#define mmDSCC2_DSCC_PPS_CONFIG16_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG17 0x30d7
|
#define mmDSCC2_DSCC_PPS_CONFIG17_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG18 0x30d8
|
#define mmDSCC2_DSCC_PPS_CONFIG18_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG19 0x30d9
|
#define mmDSCC2_DSCC_PPS_CONFIG19_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG20 0x30da
|
#define mmDSCC2_DSCC_PPS_CONFIG20_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG21 0x30db
|
#define mmDSCC2_DSCC_PPS_CONFIG21_BASE_IDX 2
|
#define mmDSCC2_DSCC_PPS_CONFIG22 0x30dc
|
#define mmDSCC2_DSCC_PPS_CONFIG22_BASE_IDX 2
|
#define mmDSCC2_DSCC_MEM_POWER_CONTROL 0x30dd
|
#define mmDSCC2_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
|
#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER 0x30de
|
#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER 0x30df
|
#define mmDSCC2_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER 0x30e0
|
#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER 0x30e1
|
#define mmDSCC2_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER 0x30e2
|
#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER 0x30e3
|
#define mmDSCC2_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC2_DSCC_MAX_ABS_ERROR0 0x30e4
|
#define mmDSCC2_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
|
#define mmDSCC2_DSCC_MAX_ABS_ERROR1 0x30e5
|
#define mmDSCC2_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x30e6
|
#define mmDSCC2_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x30e7
|
#define mmDSCC2_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x30e8
|
#define mmDSCC2_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x30e9
|
#define mmDSCC2_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x30ea
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x30eb
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x30ec
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x30ed
|
#define mmDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE 0x30f2
|
#define mmDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc2_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xc420
|
#define mmDC_PERFMON23_PERFCOUNTER_CNTL 0x3108
|
#define mmDC_PERFMON23_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFCOUNTER_CNTL2 0x3109
|
#define mmDC_PERFMON23_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFCOUNTER_STATE 0x310a
|
#define mmDC_PERFMON23_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFMON_CNTL 0x310b
|
#define mmDC_PERFMON23_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFMON_CNTL2 0x310c
|
#define mmDC_PERFMON23_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC 0x310d
|
#define mmDC_PERFMON23_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFMON_CVALUE_LOW 0x310e
|
#define mmDC_PERFMON23_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFMON_HI 0x310f
|
#define mmDC_PERFMON23_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON23_PERFMON_LOW 0x3110
|
#define mmDC_PERFMON23_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc3_dispdec_dsc_top_dispdec
|
// base address: 0x450
|
#define mmDSC_TOP3_DSC_TOP_CONTROL 0x3114
|
#define mmDSC_TOP3_DSC_TOP_CONTROL_BASE_IDX 2
|
#define mmDSC_TOP3_DSC_DEBUG_CONTROL 0x3115
|
#define mmDSC_TOP3_DSC_DEBUG_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
|
// base address: 0x450
|
#define mmDSCCIF3_DSCCIF_CONFIG0 0x3119
|
#define mmDSCCIF3_DSCCIF_CONFIG0_BASE_IDX 2
|
#define mmDSCCIF3_DSCCIF_CONFIG1 0x311a
|
#define mmDSCCIF3_DSCCIF_CONFIG1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc3_dispdec_dscc_dispdec
|
// base address: 0x450
|
#define mmDSCC3_DSCC_CONFIG0 0x311e
|
#define mmDSCC3_DSCC_CONFIG0_BASE_IDX 2
|
#define mmDSCC3_DSCC_CONFIG1 0x311f
|
#define mmDSCC3_DSCC_CONFIG1_BASE_IDX 2
|
#define mmDSCC3_DSCC_STATUS 0x3120
|
#define mmDSCC3_DSCC_STATUS_BASE_IDX 2
|
#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS 0x3121
|
#define mmDSCC3_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG0 0x3122
|
#define mmDSCC3_DSCC_PPS_CONFIG0_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG1 0x3123
|
#define mmDSCC3_DSCC_PPS_CONFIG1_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG2 0x3124
|
#define mmDSCC3_DSCC_PPS_CONFIG2_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG3 0x3125
|
#define mmDSCC3_DSCC_PPS_CONFIG3_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG4 0x3126
|
#define mmDSCC3_DSCC_PPS_CONFIG4_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG5 0x3127
|
#define mmDSCC3_DSCC_PPS_CONFIG5_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG6 0x3128
|
#define mmDSCC3_DSCC_PPS_CONFIG6_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG7 0x3129
|
#define mmDSCC3_DSCC_PPS_CONFIG7_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG8 0x312a
|
#define mmDSCC3_DSCC_PPS_CONFIG8_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG9 0x312b
|
#define mmDSCC3_DSCC_PPS_CONFIG9_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG10 0x312c
|
#define mmDSCC3_DSCC_PPS_CONFIG10_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG11 0x312d
|
#define mmDSCC3_DSCC_PPS_CONFIG11_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG12 0x312e
|
#define mmDSCC3_DSCC_PPS_CONFIG12_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG13 0x312f
|
#define mmDSCC3_DSCC_PPS_CONFIG13_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG14 0x3130
|
#define mmDSCC3_DSCC_PPS_CONFIG14_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG15 0x3131
|
#define mmDSCC3_DSCC_PPS_CONFIG15_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG16 0x3132
|
#define mmDSCC3_DSCC_PPS_CONFIG16_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG17 0x3133
|
#define mmDSCC3_DSCC_PPS_CONFIG17_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG18 0x3134
|
#define mmDSCC3_DSCC_PPS_CONFIG18_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG19 0x3135
|
#define mmDSCC3_DSCC_PPS_CONFIG19_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG20 0x3136
|
#define mmDSCC3_DSCC_PPS_CONFIG20_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG21 0x3137
|
#define mmDSCC3_DSCC_PPS_CONFIG21_BASE_IDX 2
|
#define mmDSCC3_DSCC_PPS_CONFIG22 0x3138
|
#define mmDSCC3_DSCC_PPS_CONFIG22_BASE_IDX 2
|
#define mmDSCC3_DSCC_MEM_POWER_CONTROL 0x3139
|
#define mmDSCC3_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
|
#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER 0x313a
|
#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER 0x313b
|
#define mmDSCC3_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER 0x313c
|
#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER 0x313d
|
#define mmDSCC3_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER 0x313e
|
#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER 0x313f
|
#define mmDSCC3_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC3_DSCC_MAX_ABS_ERROR0 0x3140
|
#define mmDSCC3_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
|
#define mmDSCC3_DSCC_MAX_ABS_ERROR1 0x3141
|
#define mmDSCC3_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x3142
|
#define mmDSCC3_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x3143
|
#define mmDSCC3_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x3144
|
#define mmDSCC3_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x3145
|
#define mmDSCC3_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x3146
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x3147
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3148
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3149
|
#define mmDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE 0x314e
|
#define mmDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc3_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xc590
|
#define mmDC_PERFMON24_PERFCOUNTER_CNTL 0x3164
|
#define mmDC_PERFMON24_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFCOUNTER_CNTL2 0x3165
|
#define mmDC_PERFMON24_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFCOUNTER_STATE 0x3166
|
#define mmDC_PERFMON24_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFMON_CNTL 0x3167
|
#define mmDC_PERFMON24_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFMON_CNTL2 0x3168
|
#define mmDC_PERFMON24_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC 0x3169
|
#define mmDC_PERFMON24_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFMON_CVALUE_LOW 0x316a
|
#define mmDC_PERFMON24_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFMON_HI 0x316b
|
#define mmDC_PERFMON24_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON24_PERFMON_LOW 0x316c
|
#define mmDC_PERFMON24_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc4_dispdec_dsc_top_dispdec
|
// base address: 0x5c0
|
#define mmDSC_TOP4_DSC_TOP_CONTROL 0x3170
|
#define mmDSC_TOP4_DSC_TOP_CONTROL_BASE_IDX 2
|
#define mmDSC_TOP4_DSC_DEBUG_CONTROL 0x3171
|
#define mmDSC_TOP4_DSC_DEBUG_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc4_dispdec_dsccif_dispdec
|
// base address: 0x5c0
|
#define mmDSCCIF4_DSCCIF_CONFIG0 0x3175
|
#define mmDSCCIF4_DSCCIF_CONFIG0_BASE_IDX 2
|
#define mmDSCCIF4_DSCCIF_CONFIG1 0x3176
|
#define mmDSCCIF4_DSCCIF_CONFIG1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc4_dispdec_dscc_dispdec
|
// base address: 0x5c0
|
#define mmDSCC4_DSCC_CONFIG0 0x317a
|
#define mmDSCC4_DSCC_CONFIG0_BASE_IDX 2
|
#define mmDSCC4_DSCC_CONFIG1 0x317b
|
#define mmDSCC4_DSCC_CONFIG1_BASE_IDX 2
|
#define mmDSCC4_DSCC_STATUS 0x317c
|
#define mmDSCC4_DSCC_STATUS_BASE_IDX 2
|
#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS 0x317d
|
#define mmDSCC4_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG0 0x317e
|
#define mmDSCC4_DSCC_PPS_CONFIG0_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG1 0x317f
|
#define mmDSCC4_DSCC_PPS_CONFIG1_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG2 0x3180
|
#define mmDSCC4_DSCC_PPS_CONFIG2_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG3 0x3181
|
#define mmDSCC4_DSCC_PPS_CONFIG3_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG4 0x3182
|
#define mmDSCC4_DSCC_PPS_CONFIG4_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG5 0x3183
|
#define mmDSCC4_DSCC_PPS_CONFIG5_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG6 0x3184
|
#define mmDSCC4_DSCC_PPS_CONFIG6_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG7 0x3185
|
#define mmDSCC4_DSCC_PPS_CONFIG7_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG8 0x3186
|
#define mmDSCC4_DSCC_PPS_CONFIG8_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG9 0x3187
|
#define mmDSCC4_DSCC_PPS_CONFIG9_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG10 0x3188
|
#define mmDSCC4_DSCC_PPS_CONFIG10_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG11 0x3189
|
#define mmDSCC4_DSCC_PPS_CONFIG11_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG12 0x318a
|
#define mmDSCC4_DSCC_PPS_CONFIG12_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG13 0x318b
|
#define mmDSCC4_DSCC_PPS_CONFIG13_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG14 0x318c
|
#define mmDSCC4_DSCC_PPS_CONFIG14_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG15 0x318d
|
#define mmDSCC4_DSCC_PPS_CONFIG15_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG16 0x318e
|
#define mmDSCC4_DSCC_PPS_CONFIG16_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG17 0x318f
|
#define mmDSCC4_DSCC_PPS_CONFIG17_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG18 0x3190
|
#define mmDSCC4_DSCC_PPS_CONFIG18_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG19 0x3191
|
#define mmDSCC4_DSCC_PPS_CONFIG19_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG20 0x3192
|
#define mmDSCC4_DSCC_PPS_CONFIG20_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG21 0x3193
|
#define mmDSCC4_DSCC_PPS_CONFIG21_BASE_IDX 2
|
#define mmDSCC4_DSCC_PPS_CONFIG22 0x3194
|
#define mmDSCC4_DSCC_PPS_CONFIG22_BASE_IDX 2
|
#define mmDSCC4_DSCC_MEM_POWER_CONTROL 0x3195
|
#define mmDSCC4_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
|
#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER 0x3196
|
#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER 0x3197
|
#define mmDSCC4_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER 0x3198
|
#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER 0x3199
|
#define mmDSCC4_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER 0x319a
|
#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER 0x319b
|
#define mmDSCC4_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC4_DSCC_MAX_ABS_ERROR0 0x319c
|
#define mmDSCC4_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
|
#define mmDSCC4_DSCC_MAX_ABS_ERROR1 0x319d
|
#define mmDSCC4_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x319e
|
#define mmDSCC4_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x319f
|
#define mmDSCC4_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31a0
|
#define mmDSCC4_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31a1
|
#define mmDSCC4_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31a2
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31a3
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x31a4
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x31a5
|
#define mmDSCC4_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE 0x31aa
|
#define mmDSCC4_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc4_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xc700
|
#define mmDC_PERFMON25_PERFCOUNTER_CNTL 0x31c0
|
#define mmDC_PERFMON25_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFCOUNTER_CNTL2 0x31c1
|
#define mmDC_PERFMON25_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFCOUNTER_STATE 0x31c2
|
#define mmDC_PERFMON25_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFMON_CNTL 0x31c3
|
#define mmDC_PERFMON25_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFMON_CNTL2 0x31c4
|
#define mmDC_PERFMON25_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC 0x31c5
|
#define mmDC_PERFMON25_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFMON_CVALUE_LOW 0x31c6
|
#define mmDC_PERFMON25_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFMON_HI 0x31c7
|
#define mmDC_PERFMON25_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON25_PERFMON_LOW 0x31c8
|
#define mmDC_PERFMON25_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc5_dispdec_dsc_top_dispdec
|
// base address: 0x730
|
#define mmDSC_TOP5_DSC_TOP_CONTROL 0x31cc
|
#define mmDSC_TOP5_DSC_TOP_CONTROL_BASE_IDX 2
|
#define mmDSC_TOP5_DSC_DEBUG_CONTROL 0x31cd
|
#define mmDSC_TOP5_DSC_DEBUG_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc5_dispdec_dsccif_dispdec
|
// base address: 0x730
|
#define mmDSCCIF5_DSCCIF_CONFIG0 0x31d1
|
#define mmDSCCIF5_DSCCIF_CONFIG0_BASE_IDX 2
|
#define mmDSCCIF5_DSCCIF_CONFIG1 0x31d2
|
#define mmDSCCIF5_DSCCIF_CONFIG1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc5_dispdec_dscc_dispdec
|
// base address: 0x730
|
#define mmDSCC5_DSCC_CONFIG0 0x31d6
|
#define mmDSCC5_DSCC_CONFIG0_BASE_IDX 2
|
#define mmDSCC5_DSCC_CONFIG1 0x31d7
|
#define mmDSCC5_DSCC_CONFIG1_BASE_IDX 2
|
#define mmDSCC5_DSCC_STATUS 0x31d8
|
#define mmDSCC5_DSCC_STATUS_BASE_IDX 2
|
#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS 0x31d9
|
#define mmDSCC5_DSCC_INTERRUPT_CONTROL_STATUS_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG0 0x31da
|
#define mmDSCC5_DSCC_PPS_CONFIG0_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG1 0x31db
|
#define mmDSCC5_DSCC_PPS_CONFIG1_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG2 0x31dc
|
#define mmDSCC5_DSCC_PPS_CONFIG2_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG3 0x31dd
|
#define mmDSCC5_DSCC_PPS_CONFIG3_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG4 0x31de
|
#define mmDSCC5_DSCC_PPS_CONFIG4_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG5 0x31df
|
#define mmDSCC5_DSCC_PPS_CONFIG5_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG6 0x31e0
|
#define mmDSCC5_DSCC_PPS_CONFIG6_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG7 0x31e1
|
#define mmDSCC5_DSCC_PPS_CONFIG7_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG8 0x31e2
|
#define mmDSCC5_DSCC_PPS_CONFIG8_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG9 0x31e3
|
#define mmDSCC5_DSCC_PPS_CONFIG9_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG10 0x31e4
|
#define mmDSCC5_DSCC_PPS_CONFIG10_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG11 0x31e5
|
#define mmDSCC5_DSCC_PPS_CONFIG11_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG12 0x31e6
|
#define mmDSCC5_DSCC_PPS_CONFIG12_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG13 0x31e7
|
#define mmDSCC5_DSCC_PPS_CONFIG13_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG14 0x31e8
|
#define mmDSCC5_DSCC_PPS_CONFIG14_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG15 0x31e9
|
#define mmDSCC5_DSCC_PPS_CONFIG15_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG16 0x31ea
|
#define mmDSCC5_DSCC_PPS_CONFIG16_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG17 0x31eb
|
#define mmDSCC5_DSCC_PPS_CONFIG17_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG18 0x31ec
|
#define mmDSCC5_DSCC_PPS_CONFIG18_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG19 0x31ed
|
#define mmDSCC5_DSCC_PPS_CONFIG19_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG20 0x31ee
|
#define mmDSCC5_DSCC_PPS_CONFIG20_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG21 0x31ef
|
#define mmDSCC5_DSCC_PPS_CONFIG21_BASE_IDX 2
|
#define mmDSCC5_DSCC_PPS_CONFIG22 0x31f0
|
#define mmDSCC5_DSCC_PPS_CONFIG22_BASE_IDX 2
|
#define mmDSCC5_DSCC_MEM_POWER_CONTROL 0x31f1
|
#define mmDSCC5_DSCC_MEM_POWER_CONTROL_BASE_IDX 2
|
#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER 0x31f2
|
#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER 0x31f3
|
#define mmDSCC5_DSCC_R_Y_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER 0x31f4
|
#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER 0x31f5
|
#define mmDSCC5_DSCC_G_CB_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER 0x31f6
|
#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_LOWER_BASE_IDX 2
|
#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER 0x31f7
|
#define mmDSCC5_DSCC_B_CR_SQUARED_ERROR_UPPER_BASE_IDX 2
|
#define mmDSCC5_DSCC_MAX_ABS_ERROR0 0x31f8
|
#define mmDSCC5_DSCC_MAX_ABS_ERROR0_BASE_IDX 2
|
#define mmDSCC5_DSCC_MAX_ABS_ERROR1 0x31f9
|
#define mmDSCC5_DSCC_MAX_ABS_ERROR1_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL 0x31fa
|
#define mmDSCC5_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL 0x31fb
|
#define mmDSCC5_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL 0x31fc
|
#define mmDSCC5_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL 0x31fd
|
#define mmDSCC5_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL 0x31fe
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL 0x31ff
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL 0x3200
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL 0x3201
|
#define mmDSCC5_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX 2
|
#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE 0x3206
|
#define mmDSCC5_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dsc5_dispdec_dsc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xc870
|
#define mmDC_PERFMON26_PERFCOUNTER_CNTL 0x321c
|
#define mmDC_PERFMON26_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFCOUNTER_CNTL2 0x321d
|
#define mmDC_PERFMON26_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFCOUNTER_STATE 0x321e
|
#define mmDC_PERFMON26_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFMON_CNTL 0x321f
|
#define mmDC_PERFMON26_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFMON_CNTL2 0x3220
|
#define mmDC_PERFMON26_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC 0x3221
|
#define mmDC_PERFMON26_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFMON_CVALUE_LOW 0x3222
|
#define mmDC_PERFMON26_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFMON_HI 0x3223
|
#define mmDC_PERFMON26_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON26_PERFMON_LOW 0x3224
|
#define mmDC_PERFMON26_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dmu_dmcub_dispdec
|
// base address: 0x0
|
#define mmDMCUB_REGION0_OFFSET 0x3238
|
#define mmDMCUB_REGION0_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION0_OFFSET_HIGH 0x3239
|
#define mmDMCUB_REGION0_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION1_OFFSET 0x323a
|
#define mmDMCUB_REGION1_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION1_OFFSET_HIGH 0x323b
|
#define mmDMCUB_REGION1_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION2_OFFSET 0x323c
|
#define mmDMCUB_REGION2_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION2_OFFSET_HIGH 0x323d
|
#define mmDMCUB_REGION2_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION4_OFFSET 0x3240
|
#define mmDMCUB_REGION4_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION4_OFFSET_HIGH 0x3241
|
#define mmDMCUB_REGION4_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION5_OFFSET 0x3242
|
#define mmDMCUB_REGION5_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION5_OFFSET_HIGH 0x3243
|
#define mmDMCUB_REGION5_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION6_OFFSET 0x3244
|
#define mmDMCUB_REGION6_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION6_OFFSET_HIGH 0x3245
|
#define mmDMCUB_REGION6_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION7_OFFSET 0x3246
|
#define mmDMCUB_REGION7_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION7_OFFSET_HIGH 0x3247
|
#define mmDMCUB_REGION7_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION0_TOP_ADDRESS 0x3248
|
#define mmDMCUB_REGION0_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION1_TOP_ADDRESS 0x3249
|
#define mmDMCUB_REGION1_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION2_TOP_ADDRESS 0x324a
|
#define mmDMCUB_REGION2_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION4_TOP_ADDRESS 0x324b
|
#define mmDMCUB_REGION4_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION5_TOP_ADDRESS 0x324c
|
#define mmDMCUB_REGION5_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION6_TOP_ADDRESS 0x324d
|
#define mmDMCUB_REGION6_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION7_TOP_ADDRESS 0x324e
|
#define mmDMCUB_REGION7_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW0_BASE_ADDRESS 0x324f
|
#define mmDMCUB_REGION3_CW0_BASE_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW1_BASE_ADDRESS 0x3250
|
#define mmDMCUB_REGION3_CW1_BASE_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW2_BASE_ADDRESS 0x3251
|
#define mmDMCUB_REGION3_CW2_BASE_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW3_BASE_ADDRESS 0x3252
|
#define mmDMCUB_REGION3_CW3_BASE_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW4_BASE_ADDRESS 0x3253
|
#define mmDMCUB_REGION3_CW4_BASE_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW5_BASE_ADDRESS 0x3254
|
#define mmDMCUB_REGION3_CW5_BASE_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW6_BASE_ADDRESS 0x3255
|
#define mmDMCUB_REGION3_CW6_BASE_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW7_BASE_ADDRESS 0x3256
|
#define mmDMCUB_REGION3_CW7_BASE_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW0_TOP_ADDRESS 0x3257
|
#define mmDMCUB_REGION3_CW0_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW1_TOP_ADDRESS 0x3258
|
#define mmDMCUB_REGION3_CW1_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW2_TOP_ADDRESS 0x3259
|
#define mmDMCUB_REGION3_CW2_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW3_TOP_ADDRESS 0x325a
|
#define mmDMCUB_REGION3_CW3_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW4_TOP_ADDRESS 0x325b
|
#define mmDMCUB_REGION3_CW4_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW5_TOP_ADDRESS 0x325c
|
#define mmDMCUB_REGION3_CW5_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW6_TOP_ADDRESS 0x325d
|
#define mmDMCUB_REGION3_CW6_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW7_TOP_ADDRESS 0x325e
|
#define mmDMCUB_REGION3_CW7_TOP_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW0_OFFSET 0x325f
|
#define mmDMCUB_REGION3_CW0_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW0_OFFSET_HIGH 0x3260
|
#define mmDMCUB_REGION3_CW0_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW1_OFFSET 0x3261
|
#define mmDMCUB_REGION3_CW1_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW1_OFFSET_HIGH 0x3262
|
#define mmDMCUB_REGION3_CW1_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW2_OFFSET 0x3263
|
#define mmDMCUB_REGION3_CW2_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW2_OFFSET_HIGH 0x3264
|
#define mmDMCUB_REGION3_CW2_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW3_OFFSET 0x3265
|
#define mmDMCUB_REGION3_CW3_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW3_OFFSET_HIGH 0x3266
|
#define mmDMCUB_REGION3_CW3_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW4_OFFSET 0x3267
|
#define mmDMCUB_REGION3_CW4_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW4_OFFSET_HIGH 0x3268
|
#define mmDMCUB_REGION3_CW4_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW5_OFFSET 0x3269
|
#define mmDMCUB_REGION3_CW5_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW5_OFFSET_HIGH 0x326a
|
#define mmDMCUB_REGION3_CW5_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW6_OFFSET 0x326b
|
#define mmDMCUB_REGION3_CW6_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW6_OFFSET_HIGH 0x326c
|
#define mmDMCUB_REGION3_CW6_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW7_OFFSET 0x326d
|
#define mmDMCUB_REGION3_CW7_OFFSET_BASE_IDX 2
|
#define mmDMCUB_REGION3_CW7_OFFSET_HIGH 0x326e
|
#define mmDMCUB_REGION3_CW7_OFFSET_HIGH_BASE_IDX 2
|
#define mmDMCUB_INTERRUPT_ENABLE 0x326f
|
#define mmDMCUB_INTERRUPT_ENABLE_BASE_IDX 2
|
#define mmDMCUB_INTERRUPT_ACK 0x3270
|
#define mmDMCUB_INTERRUPT_ACK_BASE_IDX 2
|
#define mmDMCUB_INTERRUPT_STATUS 0x3271
|
#define mmDMCUB_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDMCUB_INTERRUPT_TYPE 0x3272
|
#define mmDMCUB_INTERRUPT_TYPE_BASE_IDX 2
|
#define mmDMCUB_EXT_INTERRUPT_STATUS 0x3273
|
#define mmDMCUB_EXT_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDMCUB_EXT_INTERRUPT_CTXID 0x3274
|
#define mmDMCUB_EXT_INTERRUPT_CTXID_BASE_IDX 2
|
#define mmDMCUB_EXT_INTERRUPT_ACK 0x3275
|
#define mmDMCUB_EXT_INTERRUPT_ACK_BASE_IDX 2
|
#define mmDMCUB_INST_FETCH_FAULT_ADDR 0x3276
|
#define mmDMCUB_INST_FETCH_FAULT_ADDR_BASE_IDX 2
|
#define mmDMCUB_DATA_WRITE_FAULT_ADDR 0x3277
|
#define mmDMCUB_DATA_WRITE_FAULT_ADDR_BASE_IDX 2
|
#define mmDMCUB_SEC_CNTL 0x3278
|
#define mmDMCUB_SEC_CNTL_BASE_IDX 2
|
#define mmDMCUB_MEM_CNTL 0x3279
|
#define mmDMCUB_MEM_CNTL_BASE_IDX 2
|
#define mmDMCUB_INBOX0_BASE_ADDRESS 0x327a
|
#define mmDMCUB_INBOX0_BASE_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_INBOX0_SIZE 0x327b
|
#define mmDMCUB_INBOX0_SIZE_BASE_IDX 2
|
#define mmDMCUB_INBOX0_WPTR 0x327c
|
#define mmDMCUB_INBOX0_WPTR_BASE_IDX 2
|
#define mmDMCUB_INBOX0_RPTR 0x327d
|
#define mmDMCUB_INBOX0_RPTR_BASE_IDX 2
|
#define mmDMCUB_INBOX1_BASE_ADDRESS 0x327e
|
#define mmDMCUB_INBOX1_BASE_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_INBOX1_SIZE 0x327f
|
#define mmDMCUB_INBOX1_SIZE_BASE_IDX 2
|
#define mmDMCUB_INBOX1_WPTR 0x3280
|
#define mmDMCUB_INBOX1_WPTR_BASE_IDX 2
|
#define mmDMCUB_INBOX1_RPTR 0x3281
|
#define mmDMCUB_INBOX1_RPTR_BASE_IDX 2
|
#define mmDMCUB_OUTBOX0_BASE_ADDRESS 0x3282
|
#define mmDMCUB_OUTBOX0_BASE_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_OUTBOX0_SIZE 0x3283
|
#define mmDMCUB_OUTBOX0_SIZE_BASE_IDX 2
|
#define mmDMCUB_OUTBOX0_WPTR 0x3284
|
#define mmDMCUB_OUTBOX0_WPTR_BASE_IDX 2
|
#define mmDMCUB_OUTBOX0_RPTR 0x3285
|
#define mmDMCUB_OUTBOX0_RPTR_BASE_IDX 2
|
#define mmDMCUB_OUTBOX1_BASE_ADDRESS 0x3286
|
#define mmDMCUB_OUTBOX1_BASE_ADDRESS_BASE_IDX 2
|
#define mmDMCUB_OUTBOX1_SIZE 0x3287
|
#define mmDMCUB_OUTBOX1_SIZE_BASE_IDX 2
|
#define mmDMCUB_OUTBOX1_WPTR 0x3288
|
#define mmDMCUB_OUTBOX1_WPTR_BASE_IDX 2
|
#define mmDMCUB_OUTBOX1_RPTR 0x3289
|
#define mmDMCUB_OUTBOX1_RPTR_BASE_IDX 2
|
#define mmDMCUB_TIMER_TRIGGER0 0x328a
|
#define mmDMCUB_TIMER_TRIGGER0_BASE_IDX 2
|
#define mmDMCUB_TIMER_TRIGGER1 0x328b
|
#define mmDMCUB_TIMER_TRIGGER1_BASE_IDX 2
|
#define mmDMCUB_TIMER_WINDOW 0x328c
|
#define mmDMCUB_TIMER_WINDOW_BASE_IDX 2
|
#define mmDMCUB_SCRATCH0 0x328d
|
#define mmDMCUB_SCRATCH0_BASE_IDX 2
|
#define mmDMCUB_SCRATCH1 0x328e
|
#define mmDMCUB_SCRATCH1_BASE_IDX 2
|
#define mmDMCUB_SCRATCH2 0x328f
|
#define mmDMCUB_SCRATCH2_BASE_IDX 2
|
#define mmDMCUB_SCRATCH3 0x3290
|
#define mmDMCUB_SCRATCH3_BASE_IDX 2
|
#define mmDMCUB_SCRATCH4 0x3291
|
#define mmDMCUB_SCRATCH4_BASE_IDX 2
|
#define mmDMCUB_SCRATCH5 0x3292
|
#define mmDMCUB_SCRATCH5_BASE_IDX 2
|
#define mmDMCUB_SCRATCH6 0x3293
|
#define mmDMCUB_SCRATCH6_BASE_IDX 2
|
#define mmDMCUB_SCRATCH7 0x3294
|
#define mmDMCUB_SCRATCH7_BASE_IDX 2
|
#define mmDMCUB_SCRATCH8 0x3295
|
#define mmDMCUB_SCRATCH8_BASE_IDX 2
|
#define mmDMCUB_SCRATCH9 0x3296
|
#define mmDMCUB_SCRATCH9_BASE_IDX 2
|
#define mmDMCUB_SCRATCH10 0x3297
|
#define mmDMCUB_SCRATCH10_BASE_IDX 2
|
#define mmDMCUB_SCRATCH11 0x3298
|
#define mmDMCUB_SCRATCH11_BASE_IDX 2
|
#define mmDMCUB_SCRATCH12 0x3299
|
#define mmDMCUB_SCRATCH12_BASE_IDX 2
|
#define mmDMCUB_SCRATCH13 0x329a
|
#define mmDMCUB_SCRATCH13_BASE_IDX 2
|
#define mmDMCUB_SCRATCH14 0x329b
|
#define mmDMCUB_SCRATCH14_BASE_IDX 2
|
#define mmDMCUB_SCRATCH15 0x329c
|
#define mmDMCUB_SCRATCH15_BASE_IDX 2
|
#define mmDMCUB_CNTL 0x32a0
|
#define mmDMCUB_CNTL_BASE_IDX 2
|
#define mmDMCUB_GPINT_DATAIN0 0x32a1
|
#define mmDMCUB_GPINT_DATAIN0_BASE_IDX 2
|
#define mmDMCUB_GPINT_DATAIN1 0x32a2
|
#define mmDMCUB_GPINT_DATAIN1_BASE_IDX 2
|
#define mmDMCUB_GPINT_DATAOUT 0x32a3
|
#define mmDMCUB_GPINT_DATAOUT_BASE_IDX 2
|
#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR 0x32a4
|
#define mmDMCUB_UNDEFINED_ADDRESS_FAULT_ADDR_BASE_IDX 2
|
#define mmDMCUB_LS_WAKE_INT_ENABLE 0x32a5
|
#define mmDMCUB_LS_WAKE_INT_ENABLE_BASE_IDX 2
|
#define mmDMCUB_MEM_PWR_CNTL 0x32a6
|
#define mmDMCUB_MEM_PWR_CNTL_BASE_IDX 2
|
#define mmDMCUB_TIMER_CURRENT 0x32a7
|
#define mmDMCUB_TIMER_CURRENT_BASE_IDX 2
|
#define mmDMCUB_PROC_ID 0x32a9
|
#define mmDMCUB_PROC_ID_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_mcif_wb2_dispdec
|
// base address: 0xc6b8
|
#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL 0x3460
|
#define mmMCIF_WB2_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R 0x3461
|
#define mmMCIF_WB2_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS 0x3462
|
#define mmMCIF_WB2_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_PITCH 0x3463
|
#define mmMCIF_WB2_MCIF_WB_BUF_PITCH_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS 0x3464
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2 0x3465
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS 0x3466
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2 0x3467
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS 0x3468
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2 0x3469
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS 0x346a
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2 0x346b
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL 0x346c
|
#define mmMCIF_WB2_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE 0x346d
|
#define mmMCIF_WB2_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX 0x346e
|
#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA 0x346f
|
#define mmMCIF_WB2_MCIF_WB_TEST_DEBUG_DATA_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y 0x3470
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x3471
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C 0x3472
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x3473
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y 0x3474
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x3475
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C 0x3476
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x3477
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y 0x3478
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x3479
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C 0x347a
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x347b
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y 0x347c
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x347d
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C 0x347e
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x347f
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL 0x3480
|
#define mmMCIF_WB2_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x3481
|
#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL 0x3482
|
#define mmMCIF_WB2_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_WATERMARK 0x3483
|
#define mmMCIF_WB2_MCIF_WB_WATERMARK_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL 0x3484
|
#define mmMCIF_WB2_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL 0x3485
|
#define mmMCIF_WB2_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL 0x3486
|
#define mmMCIF_WB2_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
|
#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL 0x3487
|
#define mmMCIF_WB2_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE 0x3489
|
#define mmMCIF_WB2_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE 0x348a
|
#define mmMCIF_WB2_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH 0x348b
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_Y_HIGH_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH 0x348c
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_ADDR_C_HIGH_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH 0x348d
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_Y_HIGH_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH 0x348e
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_ADDR_C_HIGH_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH 0x348f
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_Y_HIGH_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH 0x3490
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_ADDR_C_HIGH_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH 0x3491
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_Y_HIGH_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH 0x3492
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_ADDR_C_HIGH_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION 0x3493
|
#define mmMCIF_WB2_MCIF_WB_BUF_1_RESOLUTION_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION 0x3494
|
#define mmMCIF_WB2_MCIF_WB_BUF_2_RESOLUTION_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION 0x3495
|
#define mmMCIF_WB2_MCIF_WB_BUF_3_RESOLUTION_BASE_IDX 2
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION 0x3496
|
#define mmMCIF_WB2_MCIF_WB_BUF_4_RESOLUTION_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_xfcp0_dispdec
|
// base address: 0x0
|
#define mmXFCP0_MMHUBBUB_XFC_CNTL 0x34a0
|
#define mmXFCP0_MMHUBBUB_XFC_CNTL_BASE_IDX 2
|
#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x34a1
|
#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
|
#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x34a2
|
#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
|
#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x34a3
|
#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
|
#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x34a4
|
#define mmXFCP0_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
|
#define mmXFCP0_MMHUBBUB_XFC_XBUF_CONFIG 0x34a5
|
#define mmXFCP0_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
|
#define mmXFCP0_MMHUBBUB_XFC_XBUF_SIZE 0x34a6
|
#define mmXFCP0_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_xfcp1_dispdec
|
// base address: 0x80
|
#define mmXFCP1_MMHUBBUB_XFC_CNTL 0x34c0
|
#define mmXFCP1_MMHUBBUB_XFC_CNTL_BASE_IDX 2
|
#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x34c1
|
#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
|
#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x34c2
|
#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
|
#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x34c3
|
#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
|
#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x34c4
|
#define mmXFCP1_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
|
#define mmXFCP1_MMHUBBUB_XFC_XBUF_CONFIG 0x34c5
|
#define mmXFCP1_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
|
#define mmXFCP1_MMHUBBUB_XFC_XBUF_SIZE 0x34c6
|
#define mmXFCP1_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_xfcp2_dispdec
|
// base address: 0x100
|
#define mmXFCP2_MMHUBBUB_XFC_CNTL 0x34e0
|
#define mmXFCP2_MMHUBBUB_XFC_CNTL_BASE_IDX 2
|
#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x34e1
|
#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
|
#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x34e2
|
#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
|
#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x34e3
|
#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
|
#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x34e4
|
#define mmXFCP2_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
|
#define mmXFCP2_MMHUBBUB_XFC_XBUF_CONFIG 0x34e5
|
#define mmXFCP2_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
|
#define mmXFCP2_MMHUBBUB_XFC_XBUF_SIZE 0x34e6
|
#define mmXFCP2_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_xfcp3_dispdec
|
// base address: 0x180
|
#define mmXFCP3_MMHUBBUB_XFC_CNTL 0x3500
|
#define mmXFCP3_MMHUBBUB_XFC_CNTL_BASE_IDX 2
|
#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x3501
|
#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
|
#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x3502
|
#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
|
#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x3503
|
#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
|
#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x3504
|
#define mmXFCP3_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
|
#define mmXFCP3_MMHUBBUB_XFC_XBUF_CONFIG 0x3505
|
#define mmXFCP3_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
|
#define mmXFCP3_MMHUBBUB_XFC_XBUF_SIZE 0x3506
|
#define mmXFCP3_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_xfcp4_dispdec
|
// base address: 0x200
|
#define mmXFCP4_MMHUBBUB_XFC_CNTL 0x3520
|
#define mmXFCP4_MMHUBBUB_XFC_CNTL_BASE_IDX 2
|
#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x3521
|
#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
|
#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x3522
|
#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
|
#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x3523
|
#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
|
#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x3524
|
#define mmXFCP4_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
|
#define mmXFCP4_MMHUBBUB_XFC_XBUF_CONFIG 0x3525
|
#define mmXFCP4_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
|
#define mmXFCP4_MMHUBBUB_XFC_XBUF_SIZE 0x3526
|
#define mmXFCP4_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_xfcp5_dispdec
|
// base address: 0x280
|
#define mmXFCP5_MMHUBBUB_XFC_CNTL 0x3540
|
#define mmXFCP5_MMHUBBUB_XFC_CNTL_BASE_IDX 2
|
#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB 0x3541
|
#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_LSB_BASE_IDX 2
|
#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB 0x3542
|
#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE0_ADDR_MSB_BASE_IDX 2
|
#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB 0x3543
|
#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_LSB_BASE_IDX 2
|
#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB 0x3544
|
#define mmXFCP5_MMHUBBUB_XFC_XBUF_WR_BASE1_ADDR_MSB_BASE_IDX 2
|
#define mmXFCP5_MMHUBBUB_XFC_XBUF_CONFIG 0x3545
|
#define mmXFCP5_MMHUBBUB_XFC_XBUF_CONFIG_BASE_IDX 2
|
#define mmXFCP5_MMHUBBUB_XFC_XBUF_SIZE 0x3546
|
#define mmXFCP5_MMHUBBUB_XFC_XBUF_SIZE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mmhubbub_xfc_dispdec
|
// base address: 0x0
|
#define mmXFC_MEM_PWR_CNTL 0x35a0
|
#define mmXFC_MEM_PWR_CNTL_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_XBUF_WR_SURF_CONFIG 0x35a1
|
#define mmMMHUBBUB_XFC_XBUF_WR_SURF_CONFIG_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_XBUF_WR_CONFIG 0x35a2
|
#define mmMMHUBBUB_XFC_XBUF_WR_CONFIG_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_IO_BACKPRESSURE_RELEASE_TIMER 0x35a3
|
#define mmMMHUBBUB_XFC_IO_BACKPRESSURE_RELEASE_TIMER_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_GPU_CTRL 0x35a4
|
#define mmMMHUBBUB_XFC_GPU_CTRL_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_XBUF_VM_CTRL 0x35a5
|
#define mmMMHUBBUB_XFC_XBUF_VM_CTRL_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_LSB 0x35a6
|
#define mmMMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_LSB_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_MSB 0x35a7
|
#define mmMMHUBBUB_XFC_XBUF_VM_INIT_BASE_ADDR_MSB_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_LSB 0x35a8
|
#define mmMMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_LSB_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_MSB 0x35a9
|
#define mmMMHUBBUB_XFC_XBUF_VM_INIT_PIXEL_VALUE_MSB_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_GPU0_BASE_ADDR 0x35aa
|
#define mmMMHUBBUB_XFC_GPU0_BASE_ADDR_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_GPU1_BASE_ADDR 0x35ab
|
#define mmMMHUBBUB_XFC_GPU1_BASE_ADDR_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_GPU2_BASE_ADDR 0x35ac
|
#define mmMMHUBBUB_XFC_GPU2_BASE_ADDR_BASE_IDX 2
|
#define mmMMHUBBUB_XFC_GPU3_BASE_ADDR 0x35ad
|
#define mmMMHUBBUB_XFC_GPU3_BASE_ADDR_BASE_IDX 2
|
#define mmMMHUBBUB_XFCMON_CTRL 0x35ae
|
#define mmMMHUBBUB_XFCMON_CTRL_BASE_IDX 2
|
#define mmMMHUBBUB_XFCMON_TIMER 0x35af
|
#define mmMMHUBBUB_XFCMON_TIMER_BASE_IDX 2
|
#define mmMMHUBBUB_XFCMON_STAT_REQUESTS 0x35b0
|
#define mmMMHUBBUB_XFCMON_STAT_REQUESTS_BASE_IDX 2
|
#define mmMMHUBBUB_XFCMON_STAT_BACKPRESSURE 0x35b1
|
#define mmMMHUBBUB_XFCMON_STAT_BACKPRESSURE_BASE_IDX 2
|
#define mmMMHUBBUB_XFCMON_STAT_MAX_REQUESTS 0x35b2
|
#define mmMMHUBBUB_XFCMON_STAT_MAX_REQUESTS_BASE_IDX 2
|
#define mmMMHUBBUB_XFCMON_STAT_BACKPRESSURE_AT_MAX_REQUESTS 0x35b3
|
#define mmMMHUBBUB_XFCMON_STAT_BACKPRESSURE_AT_MAX_REQUESTS_BASE_IDX 2
|
#define mmMMHUBBUB_XFCMON_STAT_MAX_BACKPRESSURE 0x35b4
|
#define mmMMHUBBUB_XFCMON_STAT_MAX_BACKPRESSURE_BASE_IDX 2
|
#define mmMMHUBBUB_XFCMON_STAT_REQUESTS_AT_MAX_BACKPRESSURE 0x35b5
|
#define mmMMHUBBUB_XFCMON_STAT_REQUESTS_AT_MAX_BACKPRESSURE_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp4_dispdec_dpp_top_dispdec
|
// base address: 0xa42c
|
#define mmDPP_TOP4_DPP_CONTROL 0x35d0
|
#define mmDPP_TOP4_DPP_CONTROL_BASE_IDX 2
|
#define mmDPP_TOP4_DPP_SOFT_RESET 0x35d1
|
#define mmDPP_TOP4_DPP_SOFT_RESET_BASE_IDX 2
|
#define mmDPP_TOP4_DPP_CRC_VAL_R_G 0x35d2
|
#define mmDPP_TOP4_DPP_CRC_VAL_R_G_BASE_IDX 2
|
#define mmDPP_TOP4_DPP_CRC_VAL_B_A 0x35d3
|
#define mmDPP_TOP4_DPP_CRC_VAL_B_A_BASE_IDX 2
|
#define mmDPP_TOP4_DPP_CRC_CTRL 0x35d4
|
#define mmDPP_TOP4_DPP_CRC_CTRL_BASE_IDX 2
|
#define mmDPP_TOP4_HOST_READ_CONTROL 0x35d5
|
#define mmDPP_TOP4_HOST_READ_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp4_dispdec_cnvc_cfg_dispdec
|
// base address: 0xa42c
|
#define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT 0x35da
|
#define mmCNVC_CFG4_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
|
#define mmCNVC_CFG4_FORMAT_CONTROL 0x35db
|
#define mmCNVC_CFG4_FORMAT_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG4_FCNV_FP_BIAS_R 0x35dc
|
#define mmCNVC_CFG4_FCNV_FP_BIAS_R_BASE_IDX 2
|
#define mmCNVC_CFG4_FCNV_FP_BIAS_G 0x35dd
|
#define mmCNVC_CFG4_FCNV_FP_BIAS_G_BASE_IDX 2
|
#define mmCNVC_CFG4_FCNV_FP_BIAS_B 0x35de
|
#define mmCNVC_CFG4_FCNV_FP_BIAS_B_BASE_IDX 2
|
#define mmCNVC_CFG4_FCNV_FP_SCALE_R 0x35df
|
#define mmCNVC_CFG4_FCNV_FP_SCALE_R_BASE_IDX 2
|
#define mmCNVC_CFG4_FCNV_FP_SCALE_G 0x35e0
|
#define mmCNVC_CFG4_FCNV_FP_SCALE_G_BASE_IDX 2
|
#define mmCNVC_CFG4_FCNV_FP_SCALE_B 0x35e1
|
#define mmCNVC_CFG4_FCNV_FP_SCALE_B_BASE_IDX 2
|
#define mmCNVC_CFG4_COLOR_KEYER_CONTROL 0x35e2
|
#define mmCNVC_CFG4_COLOR_KEYER_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG4_COLOR_KEYER_ALPHA 0x35e3
|
#define mmCNVC_CFG4_COLOR_KEYER_ALPHA_BASE_IDX 2
|
#define mmCNVC_CFG4_COLOR_KEYER_RED 0x35e4
|
#define mmCNVC_CFG4_COLOR_KEYER_RED_BASE_IDX 2
|
#define mmCNVC_CFG4_COLOR_KEYER_GREEN 0x35e5
|
#define mmCNVC_CFG4_COLOR_KEYER_GREEN_BASE_IDX 2
|
#define mmCNVC_CFG4_COLOR_KEYER_BLUE 0x35e6
|
#define mmCNVC_CFG4_COLOR_KEYER_BLUE_BASE_IDX 2
|
#define mmCNVC_CFG4_ALPHA_2BIT_LUT 0x35e8
|
#define mmCNVC_CFG4_ALPHA_2BIT_LUT_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp4_dispdec_cnvc_cur_dispdec
|
// base address: 0xa42c
|
#define mmCNVC_CUR4_CURSOR0_CONTROL 0x35eb
|
#define mmCNVC_CUR4_CURSOR0_CONTROL_BASE_IDX 2
|
#define mmCNVC_CUR4_CURSOR0_COLOR0 0x35ec
|
#define mmCNVC_CUR4_CURSOR0_COLOR0_BASE_IDX 2
|
#define mmCNVC_CUR4_CURSOR0_COLOR1 0x35ed
|
#define mmCNVC_CUR4_CURSOR0_COLOR1_BASE_IDX 2
|
#define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS 0x35ee
|
#define mmCNVC_CUR4_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp4_dispdec_dscl_dispdec
|
// base address: 0xa42c
|
#define mmDSCL4_SCL_COEF_RAM_TAP_SELECT 0x35f5
|
#define mmDSCL4_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
|
#define mmDSCL4_SCL_COEF_RAM_TAP_DATA 0x35f6
|
#define mmDSCL4_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmDSCL4_SCL_MODE 0x35f7
|
#define mmDSCL4_SCL_MODE_BASE_IDX 2
|
#define mmDSCL4_SCL_TAP_CONTROL 0x35f8
|
#define mmDSCL4_SCL_TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL4_DSCL_CONTROL 0x35f9
|
#define mmDSCL4_DSCL_CONTROL_BASE_IDX 2
|
#define mmDSCL4_DSCL_2TAP_CONTROL 0x35fa
|
#define mmDSCL4_DSCL_2TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x35fb
|
#define mmDSCL4_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
|
#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x35fc
|
#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL4_SCL_HORZ_FILTER_INIT 0x35fd
|
#define mmDSCL4_SCL_HORZ_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C 0x35fe
|
#define mmDSCL4_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
|
#define mmDSCL4_SCL_HORZ_FILTER_INIT_C 0x35ff
|
#define mmDSCL4_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
|
#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x3600
|
#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL4_SCL_VERT_FILTER_INIT 0x3601
|
#define mmDSCL4_SCL_VERT_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT 0x3602
|
#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
|
#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C 0x3603
|
#define mmDSCL4_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
|
#define mmDSCL4_SCL_VERT_FILTER_INIT_C 0x3604
|
#define mmDSCL4_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
|
#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C 0x3605
|
#define mmDSCL4_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
|
#define mmDSCL4_SCL_BLACK_OFFSET 0x3606
|
#define mmDSCL4_SCL_BLACK_OFFSET_BASE_IDX 2
|
#define mmDSCL4_DSCL_UPDATE 0x3607
|
#define mmDSCL4_DSCL_UPDATE_BASE_IDX 2
|
#define mmDSCL4_DSCL_AUTOCAL 0x3608
|
#define mmDSCL4_DSCL_AUTOCAL_BASE_IDX 2
|
#define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x3609
|
#define mmDSCL4_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
|
#define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x360a
|
#define mmDSCL4_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
|
#define mmDSCL4_OTG_H_BLANK 0x360b
|
#define mmDSCL4_OTG_H_BLANK_BASE_IDX 2
|
#define mmDSCL4_OTG_V_BLANK 0x360c
|
#define mmDSCL4_OTG_V_BLANK_BASE_IDX 2
|
#define mmDSCL4_RECOUT_START 0x360d
|
#define mmDSCL4_RECOUT_START_BASE_IDX 2
|
#define mmDSCL4_RECOUT_SIZE 0x360e
|
#define mmDSCL4_RECOUT_SIZE_BASE_IDX 2
|
#define mmDSCL4_MPC_SIZE 0x360f
|
#define mmDSCL4_MPC_SIZE_BASE_IDX 2
|
#define mmDSCL4_LB_DATA_FORMAT 0x3610
|
#define mmDSCL4_LB_DATA_FORMAT_BASE_IDX 2
|
#define mmDSCL4_LB_MEMORY_CTRL 0x3611
|
#define mmDSCL4_LB_MEMORY_CTRL_BASE_IDX 2
|
#define mmDSCL4_LB_V_COUNTER 0x3612
|
#define mmDSCL4_LB_V_COUNTER_BASE_IDX 2
|
#define mmDSCL4_DSCL_MEM_PWR_CTRL 0x3613
|
#define mmDSCL4_DSCL_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDSCL4_DSCL_MEM_PWR_STATUS 0x3614
|
#define mmDSCL4_DSCL_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDSCL4_OBUF_CONTROL 0x3615
|
#define mmDSCL4_OBUF_CONTROL_BASE_IDX 2
|
#define mmDSCL4_OBUF_MEM_PWR_CTRL 0x3616
|
#define mmDSCL4_OBUF_MEM_PWR_CTRL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp4_dispdec_cm_dispdec
|
// base address: 0xa42c
|
#define mmCM4_CM_CONTROL 0x3625
|
#define mmCM4_CM_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_ICSC_CONTROL 0x3626
|
#define mmCM4_CM_ICSC_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_ICSC_C11_C12 0x3627
|
#define mmCM4_CM_ICSC_C11_C12_BASE_IDX 2
|
#define mmCM4_CM_ICSC_C13_C14 0x3628
|
#define mmCM4_CM_ICSC_C13_C14_BASE_IDX 2
|
#define mmCM4_CM_ICSC_C21_C22 0x3629
|
#define mmCM4_CM_ICSC_C21_C22_BASE_IDX 2
|
#define mmCM4_CM_ICSC_C23_C24 0x362a
|
#define mmCM4_CM_ICSC_C23_C24_BASE_IDX 2
|
#define mmCM4_CM_ICSC_C31_C32 0x362b
|
#define mmCM4_CM_ICSC_C31_C32_BASE_IDX 2
|
#define mmCM4_CM_ICSC_C33_C34 0x362c
|
#define mmCM4_CM_ICSC_C33_C34_BASE_IDX 2
|
#define mmCM4_CM_ICSC_B_C11_C12 0x362d
|
#define mmCM4_CM_ICSC_B_C11_C12_BASE_IDX 2
|
#define mmCM4_CM_ICSC_B_C13_C14 0x362e
|
#define mmCM4_CM_ICSC_B_C13_C14_BASE_IDX 2
|
#define mmCM4_CM_ICSC_B_C21_C22 0x362f
|
#define mmCM4_CM_ICSC_B_C21_C22_BASE_IDX 2
|
#define mmCM4_CM_ICSC_B_C23_C24 0x3630
|
#define mmCM4_CM_ICSC_B_C23_C24_BASE_IDX 2
|
#define mmCM4_CM_ICSC_B_C31_C32 0x3631
|
#define mmCM4_CM_ICSC_B_C31_C32_BASE_IDX 2
|
#define mmCM4_CM_ICSC_B_C33_C34 0x3632
|
#define mmCM4_CM_ICSC_B_C33_C34_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_CONTROL 0x3633
|
#define mmCM4_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_C11_C12 0x3634
|
#define mmCM4_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_C13_C14 0x3635
|
#define mmCM4_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_C21_C22 0x3636
|
#define mmCM4_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_C23_C24 0x3637
|
#define mmCM4_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_C31_C32 0x3638
|
#define mmCM4_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_C33_C34 0x3639
|
#define mmCM4_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_B_C11_C12 0x363a
|
#define mmCM4_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_B_C13_C14 0x363b
|
#define mmCM4_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_B_C21_C22 0x363c
|
#define mmCM4_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_B_C23_C24 0x363d
|
#define mmCM4_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_B_C31_C32 0x363e
|
#define mmCM4_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
|
#define mmCM4_CM_GAMUT_REMAP_B_C33_C34 0x363f
|
#define mmCM4_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
|
#define mmCM4_CM_BIAS_CR_R 0x3640
|
#define mmCM4_CM_BIAS_CR_R_BASE_IDX 2
|
#define mmCM4_CM_BIAS_Y_G_CB_B 0x3641
|
#define mmCM4_CM_BIAS_Y_G_CB_B_BASE_IDX 2
|
#define mmCM4_CM_DGAM_CONTROL 0x3642
|
#define mmCM4_CM_DGAM_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_DGAM_LUT_INDEX 0x3643
|
#define mmCM4_CM_DGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM4_CM_DGAM_LUT_DATA 0x3644
|
#define mmCM4_CM_DGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM4_CM_DGAM_LUT_WRITE_EN_MASK 0x3645
|
#define mmCM4_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_START_CNTL_B 0x3646
|
#define mmCM4_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_START_CNTL_G 0x3647
|
#define mmCM4_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_START_CNTL_R 0x3648
|
#define mmCM4_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_B 0x3649
|
#define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_G 0x364a
|
#define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_R 0x364b
|
#define mmCM4_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_END_CNTL1_B 0x364c
|
#define mmCM4_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_END_CNTL2_B 0x364d
|
#define mmCM4_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_END_CNTL1_G 0x364e
|
#define mmCM4_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_END_CNTL2_G 0x364f
|
#define mmCM4_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_END_CNTL1_R 0x3650
|
#define mmCM4_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_END_CNTL2_R 0x3651
|
#define mmCM4_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_REGION_0_1 0x3652
|
#define mmCM4_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_REGION_2_3 0x3653
|
#define mmCM4_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_REGION_4_5 0x3654
|
#define mmCM4_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_REGION_6_7 0x3655
|
#define mmCM4_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_REGION_8_9 0x3656
|
#define mmCM4_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_REGION_10_11 0x3657
|
#define mmCM4_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_REGION_12_13 0x3658
|
#define mmCM4_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMA_REGION_14_15 0x3659
|
#define mmCM4_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_START_CNTL_B 0x365a
|
#define mmCM4_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_START_CNTL_G 0x365b
|
#define mmCM4_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_START_CNTL_R 0x365c
|
#define mmCM4_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_B 0x365d
|
#define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_G 0x365e
|
#define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_R 0x365f
|
#define mmCM4_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_END_CNTL1_B 0x3660
|
#define mmCM4_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_END_CNTL2_B 0x3661
|
#define mmCM4_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_END_CNTL1_G 0x3662
|
#define mmCM4_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_END_CNTL2_G 0x3663
|
#define mmCM4_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_END_CNTL1_R 0x3664
|
#define mmCM4_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_END_CNTL2_R 0x3665
|
#define mmCM4_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_REGION_0_1 0x3666
|
#define mmCM4_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_REGION_2_3 0x3667
|
#define mmCM4_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_REGION_4_5 0x3668
|
#define mmCM4_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_REGION_6_7 0x3669
|
#define mmCM4_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_REGION_8_9 0x366a
|
#define mmCM4_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_REGION_10_11 0x366b
|
#define mmCM4_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_REGION_12_13 0x366c
|
#define mmCM4_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM4_CM_DGAM_RAMB_REGION_14_15 0x366d
|
#define mmCM4_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_CONTROL 0x366e
|
#define mmCM4_CM_BLNDGAM_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_LUT_INDEX 0x366f
|
#define mmCM4_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_LUT_DATA 0x3670
|
#define mmCM4_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x3671
|
#define mmCM4_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B 0x3672
|
#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G 0x3673
|
#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R 0x3674
|
#define mmCM4_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x3675
|
#define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x3676
|
#define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x3677
|
#define mmCM4_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B 0x3678
|
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B 0x3679
|
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G 0x367a
|
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G 0x367b
|
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R 0x367c
|
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R 0x367d
|
#define mmCM4_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1 0x367e
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3 0x367f
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5 0x3680
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7 0x3681
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9 0x3682
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11 0x3683
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13 0x3684
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15 0x3685
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17 0x3686
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19 0x3687
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21 0x3688
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23 0x3689
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25 0x368a
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27 0x368b
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29 0x368c
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31 0x368d
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33 0x368e
|
#define mmCM4_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B 0x368f
|
#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G 0x3690
|
#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R 0x3691
|
#define mmCM4_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x3692
|
#define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x3693
|
#define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x3694
|
#define mmCM4_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B 0x3695
|
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B 0x3696
|
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G 0x3697
|
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G 0x3698
|
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R 0x3699
|
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R 0x369a
|
#define mmCM4_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1 0x369b
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3 0x369c
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5 0x369d
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7 0x369e
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9 0x369f
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11 0x36a0
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13 0x36a1
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15 0x36a2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17 0x36a3
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19 0x36a4
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21 0x36a5
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23 0x36a6
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25 0x36a7
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27 0x36a8
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29 0x36a9
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31 0x36aa
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33 0x36ab
|
#define mmCM4_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM4_CM_HDR_MULT_COEF 0x36ac
|
#define mmCM4_CM_HDR_MULT_COEF_BASE_IDX 2
|
#define mmCM4_CM_MEM_PWR_CTRL 0x36ad
|
#define mmCM4_CM_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCM4_CM_MEM_PWR_STATUS 0x36ae
|
#define mmCM4_CM_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCM4_CM_DEALPHA 0x36b0
|
#define mmCM4_CM_DEALPHA_BASE_IDX 2
|
#define mmCM4_CM_COEF_FORMAT 0x36b1
|
#define mmCM4_CM_COEF_FORMAT_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_CONTROL 0x36b2
|
#define mmCM4_CM_SHAPER_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_OFFSET_R 0x36b3
|
#define mmCM4_CM_SHAPER_OFFSET_R_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_OFFSET_G 0x36b4
|
#define mmCM4_CM_SHAPER_OFFSET_G_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_OFFSET_B 0x36b5
|
#define mmCM4_CM_SHAPER_OFFSET_B_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_SCALE_R 0x36b6
|
#define mmCM4_CM_SHAPER_SCALE_R_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_SCALE_G_B 0x36b7
|
#define mmCM4_CM_SHAPER_SCALE_G_B_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_LUT_INDEX 0x36b8
|
#define mmCM4_CM_SHAPER_LUT_INDEX_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_LUT_DATA 0x36b9
|
#define mmCM4_CM_SHAPER_LUT_DATA_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK 0x36ba
|
#define mmCM4_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_B 0x36bb
|
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_G 0x36bc
|
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_R 0x36bd
|
#define mmCM4_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_B 0x36be
|
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_G 0x36bf
|
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_R 0x36c0
|
#define mmCM4_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_0_1 0x36c1
|
#define mmCM4_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_2_3 0x36c2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_4_5 0x36c3
|
#define mmCM4_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_6_7 0x36c4
|
#define mmCM4_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_8_9 0x36c5
|
#define mmCM4_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_10_11 0x36c6
|
#define mmCM4_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_12_13 0x36c7
|
#define mmCM4_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_14_15 0x36c8
|
#define mmCM4_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_16_17 0x36c9
|
#define mmCM4_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_18_19 0x36ca
|
#define mmCM4_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_20_21 0x36cb
|
#define mmCM4_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_22_23 0x36cc
|
#define mmCM4_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_24_25 0x36cd
|
#define mmCM4_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_26_27 0x36ce
|
#define mmCM4_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_28_29 0x36cf
|
#define mmCM4_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_30_31 0x36d0
|
#define mmCM4_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMA_REGION_32_33 0x36d1
|
#define mmCM4_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_B 0x36d2
|
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_G 0x36d3
|
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_R 0x36d4
|
#define mmCM4_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_B 0x36d5
|
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_G 0x36d6
|
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_R 0x36d7
|
#define mmCM4_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_0_1 0x36d8
|
#define mmCM4_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_2_3 0x36d9
|
#define mmCM4_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_4_5 0x36da
|
#define mmCM4_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_6_7 0x36db
|
#define mmCM4_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_8_9 0x36dc
|
#define mmCM4_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_10_11 0x36dd
|
#define mmCM4_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_12_13 0x36de
|
#define mmCM4_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_14_15 0x36df
|
#define mmCM4_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_16_17 0x36e0
|
#define mmCM4_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_18_19 0x36e1
|
#define mmCM4_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_20_21 0x36e2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_22_23 0x36e3
|
#define mmCM4_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_24_25 0x36e4
|
#define mmCM4_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_26_27 0x36e5
|
#define mmCM4_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_28_29 0x36e6
|
#define mmCM4_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_30_31 0x36e7
|
#define mmCM4_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM4_CM_SHAPER_RAMB_REGION_32_33 0x36e8
|
#define mmCM4_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM4_CM_MEM_PWR_CTRL2 0x36e9
|
#define mmCM4_CM_MEM_PWR_CTRL2_BASE_IDX 2
|
#define mmCM4_CM_MEM_PWR_STATUS2 0x36ea
|
#define mmCM4_CM_MEM_PWR_STATUS2_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_MODE 0x36eb
|
#define mmCM4_CM_3DLUT_MODE_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_INDEX 0x36ec
|
#define mmCM4_CM_3DLUT_INDEX_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_DATA 0x36ed
|
#define mmCM4_CM_3DLUT_DATA_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_DATA_30BIT 0x36ee
|
#define mmCM4_CM_3DLUT_DATA_30BIT_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_READ_WRITE_CONTROL 0x36ef
|
#define mmCM4_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_OUT_NORM_FACTOR 0x36f0
|
#define mmCM4_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_OUT_OFFSET_R 0x36f1
|
#define mmCM4_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_OUT_OFFSET_G 0x36f2
|
#define mmCM4_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
|
#define mmCM4_CM_3DLUT_OUT_OFFSET_B 0x36f3
|
#define mmCM4_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
|
#define mmCM4_CM_TEST_DEBUG_INDEX 0x36f4
|
#define mmCM4_CM_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmCM4_CM_TEST_DEBUG_DATA 0x36f5
|
#define mmCM4_CM_TEST_DEBUG_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp4_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xdcbc
|
#define mmDC_PERFMON27_PERFCOUNTER_CNTL 0x372f
|
#define mmDC_PERFMON27_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFCOUNTER_CNTL2 0x3730
|
#define mmDC_PERFMON27_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFCOUNTER_STATE 0x3731
|
#define mmDC_PERFMON27_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFMON_CNTL 0x3732
|
#define mmDC_PERFMON27_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFMON_CNTL2 0x3733
|
#define mmDC_PERFMON27_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFMON_CVALUE_INT_MISC 0x3734
|
#define mmDC_PERFMON27_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFMON_CVALUE_LOW 0x3735
|
#define mmDC_PERFMON27_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFMON_HI 0x3736
|
#define mmDC_PERFMON27_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON27_PERFMON_LOW 0x3737
|
#define mmDC_PERFMON27_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp5_dispdec_dpp_top_dispdec
|
// base address: 0xa9d8
|
#define mmDPP_TOP5_DPP_CONTROL 0x373b
|
#define mmDPP_TOP5_DPP_CONTROL_BASE_IDX 2
|
#define mmDPP_TOP5_DPP_SOFT_RESET 0x373c
|
#define mmDPP_TOP5_DPP_SOFT_RESET_BASE_IDX 2
|
#define mmDPP_TOP5_DPP_CRC_VAL_R_G 0x373d
|
#define mmDPP_TOP5_DPP_CRC_VAL_R_G_BASE_IDX 2
|
#define mmDPP_TOP5_DPP_CRC_VAL_B_A 0x373e
|
#define mmDPP_TOP5_DPP_CRC_VAL_B_A_BASE_IDX 2
|
#define mmDPP_TOP5_DPP_CRC_CTRL 0x373f
|
#define mmDPP_TOP5_DPP_CRC_CTRL_BASE_IDX 2
|
#define mmDPP_TOP5_HOST_READ_CONTROL 0x3740
|
#define mmDPP_TOP5_HOST_READ_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp5_dispdec_cnvc_cfg_dispdec
|
// base address: 0xa9d8
|
#define mmCNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT 0x3745
|
#define mmCNVC_CFG5_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
|
#define mmCNVC_CFG5_FORMAT_CONTROL 0x3746
|
#define mmCNVC_CFG5_FORMAT_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG5_FCNV_FP_BIAS_R 0x3747
|
#define mmCNVC_CFG5_FCNV_FP_BIAS_R_BASE_IDX 2
|
#define mmCNVC_CFG5_FCNV_FP_BIAS_G 0x3748
|
#define mmCNVC_CFG5_FCNV_FP_BIAS_G_BASE_IDX 2
|
#define mmCNVC_CFG5_FCNV_FP_BIAS_B 0x3749
|
#define mmCNVC_CFG5_FCNV_FP_BIAS_B_BASE_IDX 2
|
#define mmCNVC_CFG5_FCNV_FP_SCALE_R 0x374a
|
#define mmCNVC_CFG5_FCNV_FP_SCALE_R_BASE_IDX 2
|
#define mmCNVC_CFG5_FCNV_FP_SCALE_G 0x374b
|
#define mmCNVC_CFG5_FCNV_FP_SCALE_G_BASE_IDX 2
|
#define mmCNVC_CFG5_FCNV_FP_SCALE_B 0x374c
|
#define mmCNVC_CFG5_FCNV_FP_SCALE_B_BASE_IDX 2
|
#define mmCNVC_CFG5_COLOR_KEYER_CONTROL 0x374d
|
#define mmCNVC_CFG5_COLOR_KEYER_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG5_COLOR_KEYER_ALPHA 0x374e
|
#define mmCNVC_CFG5_COLOR_KEYER_ALPHA_BASE_IDX 2
|
#define mmCNVC_CFG5_COLOR_KEYER_RED 0x374f
|
#define mmCNVC_CFG5_COLOR_KEYER_RED_BASE_IDX 2
|
#define mmCNVC_CFG5_COLOR_KEYER_GREEN 0x3750
|
#define mmCNVC_CFG5_COLOR_KEYER_GREEN_BASE_IDX 2
|
#define mmCNVC_CFG5_COLOR_KEYER_BLUE 0x3751
|
#define mmCNVC_CFG5_COLOR_KEYER_BLUE_BASE_IDX 2
|
#define mmCNVC_CFG5_ALPHA_2BIT_LUT 0x3753
|
#define mmCNVC_CFG5_ALPHA_2BIT_LUT_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp5_dispdec_cnvc_cur_dispdec
|
// base address: 0xa9d8
|
#define mmCNVC_CUR5_CURSOR0_CONTROL 0x3756
|
#define mmCNVC_CUR5_CURSOR0_CONTROL_BASE_IDX 2
|
#define mmCNVC_CUR5_CURSOR0_COLOR0 0x3757
|
#define mmCNVC_CUR5_CURSOR0_COLOR0_BASE_IDX 2
|
#define mmCNVC_CUR5_CURSOR0_COLOR1 0x3758
|
#define mmCNVC_CUR5_CURSOR0_COLOR1_BASE_IDX 2
|
#define mmCNVC_CUR5_CURSOR0_FP_SCALE_BIAS 0x3759
|
#define mmCNVC_CUR5_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp5_dispdec_dscl_dispdec
|
// base address: 0xa9d8
|
#define mmDSCL5_SCL_COEF_RAM_TAP_SELECT 0x3760
|
#define mmDSCL5_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
|
#define mmDSCL5_SCL_COEF_RAM_TAP_DATA 0x3761
|
#define mmDSCL5_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmDSCL5_SCL_MODE 0x3762
|
#define mmDSCL5_SCL_MODE_BASE_IDX 2
|
#define mmDSCL5_SCL_TAP_CONTROL 0x3763
|
#define mmDSCL5_SCL_TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL5_DSCL_CONTROL 0x3764
|
#define mmDSCL5_DSCL_CONTROL_BASE_IDX 2
|
#define mmDSCL5_DSCL_2TAP_CONTROL 0x3765
|
#define mmDSCL5_DSCL_2TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x3766
|
#define mmDSCL5_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
|
#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x3767
|
#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL5_SCL_HORZ_FILTER_INIT 0x3768
|
#define mmDSCL5_SCL_HORZ_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C 0x3769
|
#define mmDSCL5_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
|
#define mmDSCL5_SCL_HORZ_FILTER_INIT_C 0x376a
|
#define mmDSCL5_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
|
#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x376b
|
#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL5_SCL_VERT_FILTER_INIT 0x376c
|
#define mmDSCL5_SCL_VERT_FILTER_INIT_BASE_IDX 2
|
#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT 0x376d
|
#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
|
#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_C 0x376e
|
#define mmDSCL5_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
|
#define mmDSCL5_SCL_VERT_FILTER_INIT_C 0x376f
|
#define mmDSCL5_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
|
#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_C 0x3770
|
#define mmDSCL5_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
|
#define mmDSCL5_SCL_BLACK_OFFSET 0x3771
|
#define mmDSCL5_SCL_BLACK_OFFSET_BASE_IDX 2
|
#define mmDSCL5_DSCL_UPDATE 0x3772
|
#define mmDSCL5_DSCL_UPDATE_BASE_IDX 2
|
#define mmDSCL5_DSCL_AUTOCAL 0x3773
|
#define mmDSCL5_DSCL_AUTOCAL_BASE_IDX 2
|
#define mmDSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x3774
|
#define mmDSCL5_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
|
#define mmDSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x3775
|
#define mmDSCL5_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
|
#define mmDSCL5_OTG_H_BLANK 0x3776
|
#define mmDSCL5_OTG_H_BLANK_BASE_IDX 2
|
#define mmDSCL5_OTG_V_BLANK 0x3777
|
#define mmDSCL5_OTG_V_BLANK_BASE_IDX 2
|
#define mmDSCL5_RECOUT_START 0x3778
|
#define mmDSCL5_RECOUT_START_BASE_IDX 2
|
#define mmDSCL5_RECOUT_SIZE 0x3779
|
#define mmDSCL5_RECOUT_SIZE_BASE_IDX 2
|
#define mmDSCL5_MPC_SIZE 0x377a
|
#define mmDSCL5_MPC_SIZE_BASE_IDX 2
|
#define mmDSCL5_LB_DATA_FORMAT 0x377b
|
#define mmDSCL5_LB_DATA_FORMAT_BASE_IDX 2
|
#define mmDSCL5_LB_MEMORY_CTRL 0x377c
|
#define mmDSCL5_LB_MEMORY_CTRL_BASE_IDX 2
|
#define mmDSCL5_LB_V_COUNTER 0x377d
|
#define mmDSCL5_LB_V_COUNTER_BASE_IDX 2
|
#define mmDSCL5_DSCL_MEM_PWR_CTRL 0x377e
|
#define mmDSCL5_DSCL_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDSCL5_DSCL_MEM_PWR_STATUS 0x377f
|
#define mmDSCL5_DSCL_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDSCL5_OBUF_CONTROL 0x3780
|
#define mmDSCL5_OBUF_CONTROL_BASE_IDX 2
|
#define mmDSCL5_OBUF_MEM_PWR_CTRL 0x3781
|
#define mmDSCL5_OBUF_MEM_PWR_CTRL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp5_dispdec_cm_dispdec
|
// base address: 0xa9d8
|
#define mmCM5_CM_CONTROL 0x3790
|
#define mmCM5_CM_CONTROL_BASE_IDX 2
|
#define mmCM5_CM_ICSC_CONTROL 0x3791
|
#define mmCM5_CM_ICSC_CONTROL_BASE_IDX 2
|
#define mmCM5_CM_ICSC_C11_C12 0x3792
|
#define mmCM5_CM_ICSC_C11_C12_BASE_IDX 2
|
#define mmCM5_CM_ICSC_C13_C14 0x3793
|
#define mmCM5_CM_ICSC_C13_C14_BASE_IDX 2
|
#define mmCM5_CM_ICSC_C21_C22 0x3794
|
#define mmCM5_CM_ICSC_C21_C22_BASE_IDX 2
|
#define mmCM5_CM_ICSC_C23_C24 0x3795
|
#define mmCM5_CM_ICSC_C23_C24_BASE_IDX 2
|
#define mmCM5_CM_ICSC_C31_C32 0x3796
|
#define mmCM5_CM_ICSC_C31_C32_BASE_IDX 2
|
#define mmCM5_CM_ICSC_C33_C34 0x3797
|
#define mmCM5_CM_ICSC_C33_C34_BASE_IDX 2
|
#define mmCM5_CM_ICSC_B_C11_C12 0x3798
|
#define mmCM5_CM_ICSC_B_C11_C12_BASE_IDX 2
|
#define mmCM5_CM_ICSC_B_C13_C14 0x3799
|
#define mmCM5_CM_ICSC_B_C13_C14_BASE_IDX 2
|
#define mmCM5_CM_ICSC_B_C21_C22 0x379a
|
#define mmCM5_CM_ICSC_B_C21_C22_BASE_IDX 2
|
#define mmCM5_CM_ICSC_B_C23_C24 0x379b
|
#define mmCM5_CM_ICSC_B_C23_C24_BASE_IDX 2
|
#define mmCM5_CM_ICSC_B_C31_C32 0x379c
|
#define mmCM5_CM_ICSC_B_C31_C32_BASE_IDX 2
|
#define mmCM5_CM_ICSC_B_C33_C34 0x379d
|
#define mmCM5_CM_ICSC_B_C33_C34_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_CONTROL 0x379e
|
#define mmCM5_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_C11_C12 0x379f
|
#define mmCM5_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_C13_C14 0x37a0
|
#define mmCM5_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_C21_C22 0x37a1
|
#define mmCM5_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_C23_C24 0x37a2
|
#define mmCM5_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_C31_C32 0x37a3
|
#define mmCM5_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_C33_C34 0x37a4
|
#define mmCM5_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_B_C11_C12 0x37a5
|
#define mmCM5_CM_GAMUT_REMAP_B_C11_C12_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_B_C13_C14 0x37a6
|
#define mmCM5_CM_GAMUT_REMAP_B_C13_C14_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_B_C21_C22 0x37a7
|
#define mmCM5_CM_GAMUT_REMAP_B_C21_C22_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_B_C23_C24 0x37a8
|
#define mmCM5_CM_GAMUT_REMAP_B_C23_C24_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_B_C31_C32 0x37a9
|
#define mmCM5_CM_GAMUT_REMAP_B_C31_C32_BASE_IDX 2
|
#define mmCM5_CM_GAMUT_REMAP_B_C33_C34 0x37aa
|
#define mmCM5_CM_GAMUT_REMAP_B_C33_C34_BASE_IDX 2
|
#define mmCM5_CM_BIAS_CR_R 0x37ab
|
#define mmCM5_CM_BIAS_CR_R_BASE_IDX 2
|
#define mmCM5_CM_BIAS_Y_G_CB_B 0x37ac
|
#define mmCM5_CM_BIAS_Y_G_CB_B_BASE_IDX 2
|
#define mmCM5_CM_DGAM_CONTROL 0x37ad
|
#define mmCM5_CM_DGAM_CONTROL_BASE_IDX 2
|
#define mmCM5_CM_DGAM_LUT_INDEX 0x37ae
|
#define mmCM5_CM_DGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM5_CM_DGAM_LUT_DATA 0x37af
|
#define mmCM5_CM_DGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM5_CM_DGAM_LUT_WRITE_EN_MASK 0x37b0
|
#define mmCM5_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_START_CNTL_B 0x37b1
|
#define mmCM5_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_START_CNTL_G 0x37b2
|
#define mmCM5_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_START_CNTL_R 0x37b3
|
#define mmCM5_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_B 0x37b4
|
#define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_G 0x37b5
|
#define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_R 0x37b6
|
#define mmCM5_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_END_CNTL1_B 0x37b7
|
#define mmCM5_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_END_CNTL2_B 0x37b8
|
#define mmCM5_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_END_CNTL1_G 0x37b9
|
#define mmCM5_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_END_CNTL2_G 0x37ba
|
#define mmCM5_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_END_CNTL1_R 0x37bb
|
#define mmCM5_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_END_CNTL2_R 0x37bc
|
#define mmCM5_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_REGION_0_1 0x37bd
|
#define mmCM5_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_REGION_2_3 0x37be
|
#define mmCM5_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_REGION_4_5 0x37bf
|
#define mmCM5_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_REGION_6_7 0x37c0
|
#define mmCM5_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_REGION_8_9 0x37c1
|
#define mmCM5_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_REGION_10_11 0x37c2
|
#define mmCM5_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_REGION_12_13 0x37c3
|
#define mmCM5_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMA_REGION_14_15 0x37c4
|
#define mmCM5_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_START_CNTL_B 0x37c5
|
#define mmCM5_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_START_CNTL_G 0x37c6
|
#define mmCM5_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_START_CNTL_R 0x37c7
|
#define mmCM5_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_B 0x37c8
|
#define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_G 0x37c9
|
#define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_R 0x37ca
|
#define mmCM5_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_END_CNTL1_B 0x37cb
|
#define mmCM5_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_END_CNTL2_B 0x37cc
|
#define mmCM5_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_END_CNTL1_G 0x37cd
|
#define mmCM5_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_END_CNTL2_G 0x37ce
|
#define mmCM5_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_END_CNTL1_R 0x37cf
|
#define mmCM5_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_END_CNTL2_R 0x37d0
|
#define mmCM5_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_REGION_0_1 0x37d1
|
#define mmCM5_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_REGION_2_3 0x37d2
|
#define mmCM5_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_REGION_4_5 0x37d3
|
#define mmCM5_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_REGION_6_7 0x37d4
|
#define mmCM5_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_REGION_8_9 0x37d5
|
#define mmCM5_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_REGION_10_11 0x37d6
|
#define mmCM5_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_REGION_12_13 0x37d7
|
#define mmCM5_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM5_CM_DGAM_RAMB_REGION_14_15 0x37d8
|
#define mmCM5_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_CONTROL 0x37d9
|
#define mmCM5_CM_BLNDGAM_CONTROL_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_LUT_INDEX 0x37da
|
#define mmCM5_CM_BLNDGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_LUT_DATA 0x37db
|
#define mmCM5_CM_BLNDGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_LUT_WRITE_EN_MASK 0x37dc
|
#define mmCM5_CM_BLNDGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_B 0x37dd
|
#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_G 0x37de
|
#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_R 0x37df
|
#define mmCM5_CM_BLNDGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_B 0x37e0
|
#define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_G 0x37e1
|
#define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_R 0x37e2
|
#define mmCM5_CM_BLNDGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_B 0x37e3
|
#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_B 0x37e4
|
#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_G 0x37e5
|
#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_G 0x37e6
|
#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_R 0x37e7
|
#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_R 0x37e8
|
#define mmCM5_CM_BLNDGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_0_1 0x37e9
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_2_3 0x37ea
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_4_5 0x37eb
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_6_7 0x37ec
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_8_9 0x37ed
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_10_11 0x37ee
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_12_13 0x37ef
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_14_15 0x37f0
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_16_17 0x37f1
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_18_19 0x37f2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_20_21 0x37f3
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_22_23 0x37f4
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_24_25 0x37f5
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_26_27 0x37f6
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_28_29 0x37f7
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_30_31 0x37f8
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_32_33 0x37f9
|
#define mmCM5_CM_BLNDGAM_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_B 0x37fa
|
#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_G 0x37fb
|
#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_R 0x37fc
|
#define mmCM5_CM_BLNDGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_B 0x37fd
|
#define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_G 0x37fe
|
#define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_R 0x37ff
|
#define mmCM5_CM_BLNDGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_B 0x3800
|
#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_B 0x3801
|
#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_G 0x3802
|
#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_G 0x3803
|
#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_R 0x3804
|
#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_R 0x3805
|
#define mmCM5_CM_BLNDGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_0_1 0x3806
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_2_3 0x3807
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_4_5 0x3808
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_6_7 0x3809
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_8_9 0x380a
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_10_11 0x380b
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_12_13 0x380c
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_14_15 0x380d
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_16_17 0x380e
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_18_19 0x380f
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_20_21 0x3810
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_22_23 0x3811
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_24_25 0x3812
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_26_27 0x3813
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_28_29 0x3814
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_30_31 0x3815
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_32_33 0x3816
|
#define mmCM5_CM_BLNDGAM_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM5_CM_HDR_MULT_COEF 0x3817
|
#define mmCM5_CM_HDR_MULT_COEF_BASE_IDX 2
|
#define mmCM5_CM_MEM_PWR_CTRL 0x3818
|
#define mmCM5_CM_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmCM5_CM_MEM_PWR_STATUS 0x3819
|
#define mmCM5_CM_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCM5_CM_DEALPHA 0x381b
|
#define mmCM5_CM_DEALPHA_BASE_IDX 2
|
#define mmCM5_CM_COEF_FORMAT 0x381c
|
#define mmCM5_CM_COEF_FORMAT_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_CONTROL 0x381d
|
#define mmCM5_CM_SHAPER_CONTROL_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_OFFSET_R 0x381e
|
#define mmCM5_CM_SHAPER_OFFSET_R_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_OFFSET_G 0x381f
|
#define mmCM5_CM_SHAPER_OFFSET_G_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_OFFSET_B 0x3820
|
#define mmCM5_CM_SHAPER_OFFSET_B_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_SCALE_R 0x3821
|
#define mmCM5_CM_SHAPER_SCALE_R_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_SCALE_G_B 0x3822
|
#define mmCM5_CM_SHAPER_SCALE_G_B_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_LUT_INDEX 0x3823
|
#define mmCM5_CM_SHAPER_LUT_INDEX_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_LUT_DATA 0x3824
|
#define mmCM5_CM_SHAPER_LUT_DATA_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_LUT_WRITE_EN_MASK 0x3825
|
#define mmCM5_CM_SHAPER_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_START_CNTL_B 0x3826
|
#define mmCM5_CM_SHAPER_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_START_CNTL_G 0x3827
|
#define mmCM5_CM_SHAPER_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_START_CNTL_R 0x3828
|
#define mmCM5_CM_SHAPER_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_END_CNTL_B 0x3829
|
#define mmCM5_CM_SHAPER_RAMA_END_CNTL_B_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_END_CNTL_G 0x382a
|
#define mmCM5_CM_SHAPER_RAMA_END_CNTL_G_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_END_CNTL_R 0x382b
|
#define mmCM5_CM_SHAPER_RAMA_END_CNTL_R_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_0_1 0x382c
|
#define mmCM5_CM_SHAPER_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_2_3 0x382d
|
#define mmCM5_CM_SHAPER_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_4_5 0x382e
|
#define mmCM5_CM_SHAPER_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_6_7 0x382f
|
#define mmCM5_CM_SHAPER_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_8_9 0x3830
|
#define mmCM5_CM_SHAPER_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_10_11 0x3831
|
#define mmCM5_CM_SHAPER_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_12_13 0x3832
|
#define mmCM5_CM_SHAPER_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_14_15 0x3833
|
#define mmCM5_CM_SHAPER_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_16_17 0x3834
|
#define mmCM5_CM_SHAPER_RAMA_REGION_16_17_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_18_19 0x3835
|
#define mmCM5_CM_SHAPER_RAMA_REGION_18_19_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_20_21 0x3836
|
#define mmCM5_CM_SHAPER_RAMA_REGION_20_21_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_22_23 0x3837
|
#define mmCM5_CM_SHAPER_RAMA_REGION_22_23_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_24_25 0x3838
|
#define mmCM5_CM_SHAPER_RAMA_REGION_24_25_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_26_27 0x3839
|
#define mmCM5_CM_SHAPER_RAMA_REGION_26_27_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_28_29 0x383a
|
#define mmCM5_CM_SHAPER_RAMA_REGION_28_29_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_30_31 0x383b
|
#define mmCM5_CM_SHAPER_RAMA_REGION_30_31_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMA_REGION_32_33 0x383c
|
#define mmCM5_CM_SHAPER_RAMA_REGION_32_33_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_START_CNTL_B 0x383d
|
#define mmCM5_CM_SHAPER_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_START_CNTL_G 0x383e
|
#define mmCM5_CM_SHAPER_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_START_CNTL_R 0x383f
|
#define mmCM5_CM_SHAPER_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_END_CNTL_B 0x3840
|
#define mmCM5_CM_SHAPER_RAMB_END_CNTL_B_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_END_CNTL_G 0x3841
|
#define mmCM5_CM_SHAPER_RAMB_END_CNTL_G_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_END_CNTL_R 0x3842
|
#define mmCM5_CM_SHAPER_RAMB_END_CNTL_R_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_0_1 0x3843
|
#define mmCM5_CM_SHAPER_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_2_3 0x3844
|
#define mmCM5_CM_SHAPER_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_4_5 0x3845
|
#define mmCM5_CM_SHAPER_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_6_7 0x3846
|
#define mmCM5_CM_SHAPER_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_8_9 0x3847
|
#define mmCM5_CM_SHAPER_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_10_11 0x3848
|
#define mmCM5_CM_SHAPER_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_12_13 0x3849
|
#define mmCM5_CM_SHAPER_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_14_15 0x384a
|
#define mmCM5_CM_SHAPER_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_16_17 0x384b
|
#define mmCM5_CM_SHAPER_RAMB_REGION_16_17_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_18_19 0x384c
|
#define mmCM5_CM_SHAPER_RAMB_REGION_18_19_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_20_21 0x384d
|
#define mmCM5_CM_SHAPER_RAMB_REGION_20_21_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_22_23 0x384e
|
#define mmCM5_CM_SHAPER_RAMB_REGION_22_23_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_24_25 0x384f
|
#define mmCM5_CM_SHAPER_RAMB_REGION_24_25_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_26_27 0x3850
|
#define mmCM5_CM_SHAPER_RAMB_REGION_26_27_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_28_29 0x3851
|
#define mmCM5_CM_SHAPER_RAMB_REGION_28_29_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_30_31 0x3852
|
#define mmCM5_CM_SHAPER_RAMB_REGION_30_31_BASE_IDX 2
|
#define mmCM5_CM_SHAPER_RAMB_REGION_32_33 0x3853
|
#define mmCM5_CM_SHAPER_RAMB_REGION_32_33_BASE_IDX 2
|
#define mmCM5_CM_MEM_PWR_CTRL2 0x3854
|
#define mmCM5_CM_MEM_PWR_CTRL2_BASE_IDX 2
|
#define mmCM5_CM_MEM_PWR_STATUS2 0x3855
|
#define mmCM5_CM_MEM_PWR_STATUS2_BASE_IDX 2
|
#define mmCM5_CM_3DLUT_MODE 0x3856
|
#define mmCM5_CM_3DLUT_MODE_BASE_IDX 2
|
#define mmCM5_CM_3DLUT_INDEX 0x3857
|
#define mmCM5_CM_3DLUT_INDEX_BASE_IDX 2
|
#define mmCM5_CM_3DLUT_DATA 0x3858
|
#define mmCM5_CM_3DLUT_DATA_BASE_IDX 2
|
#define mmCM5_CM_3DLUT_DATA_30BIT 0x3859
|
#define mmCM5_CM_3DLUT_DATA_30BIT_BASE_IDX 2
|
#define mmCM5_CM_3DLUT_READ_WRITE_CONTROL 0x385a
|
#define mmCM5_CM_3DLUT_READ_WRITE_CONTROL_BASE_IDX 2
|
#define mmCM5_CM_3DLUT_OUT_NORM_FACTOR 0x385b
|
#define mmCM5_CM_3DLUT_OUT_NORM_FACTOR_BASE_IDX 2
|
#define mmCM5_CM_3DLUT_OUT_OFFSET_R 0x385c
|
#define mmCM5_CM_3DLUT_OUT_OFFSET_R_BASE_IDX 2
|
#define mmCM5_CM_3DLUT_OUT_OFFSET_G 0x385d
|
#define mmCM5_CM_3DLUT_OUT_OFFSET_G_BASE_IDX 2
|
#define mmCM5_CM_3DLUT_OUT_OFFSET_B 0x385e
|
#define mmCM5_CM_3DLUT_OUT_OFFSET_B_BASE_IDX 2
|
#define mmCM5_CM_TEST_DEBUG_INDEX 0x385f
|
#define mmCM5_CM_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmCM5_CM_TEST_DEBUG_DATA 0x3860
|
#define mmCM5_CM_TEST_DEBUG_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp5_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xe268
|
#define mmDC_PERFMON28_PERFCOUNTER_CNTL 0x389a
|
#define mmDC_PERFMON28_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON28_PERFCOUNTER_CNTL2 0x389b
|
#define mmDC_PERFMON28_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON28_PERFCOUNTER_STATE 0x389c
|
#define mmDC_PERFMON28_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON28_PERFMON_CNTL 0x389d
|
#define mmDC_PERFMON28_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON28_PERFMON_CNTL2 0x389e
|
#define mmDC_PERFMON28_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON28_PERFMON_CVALUE_INT_MISC 0x389f
|
#define mmDC_PERFMON28_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON28_PERFMON_CVALUE_LOW 0x38a0
|
#define mmDC_PERFMON28_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON28_PERFMON_HI 0x38a1
|
#define mmDC_PERFMON28_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON28_PERFMON_LOW 0x38a2
|
#define mmDC_PERFMON28_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_hda_azcontroller_azdec
|
// base address: 0x0
|
#define mmCORB_WRITE_POINTER 0x0000
|
#define mmCORB_WRITE_POINTER_BASE_IDX 0
|
#define mmCORB_READ_POINTER 0x0000
|
#define mmCORB_READ_POINTER_BASE_IDX 0
|
#define mmCORB_CONTROL 0x0001
|
#define mmCORB_CONTROL_BASE_IDX 0
|
#define mmCORB_STATUS 0x0001
|
#define mmCORB_STATUS_BASE_IDX 0
|
#define mmCORB_SIZE 0x0001
|
#define mmCORB_SIZE_BASE_IDX 0
|
#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
|
#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
|
#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmRIRB_WRITE_POINTER 0x0004
|
#define mmRIRB_WRITE_POINTER_BASE_IDX 0
|
#define mmRESPONSE_INTERRUPT_COUNT 0x0004
|
#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
|
#define mmRIRB_CONTROL 0x0005
|
#define mmRIRB_CONTROL_BASE_IDX 0
|
#define mmRIRB_STATUS 0x0005
|
#define mmRIRB_STATUS_BASE_IDX 0
|
#define mmRIRB_SIZE 0x0005
|
#define mmRIRB_SIZE_BASE_IDX 0
|
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
|
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
|
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
|
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
|
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
|
#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
|
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
|
#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
|
#define mmIMMEDIATE_COMMAND_STATUS 0x0008
|
#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
|
#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
|
#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
|
#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
|
#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_hda_azendpoint_azdec
|
// base address: 0x0
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
|
|
|
// addressBlock: dce_dc_hda_azinputendpoint_azdec
|
// base address: 0x0
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
|
#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
|
|
|
// addressBlock: dce_dc_hda_azroot_azdec
|
// base address: 0x0
|
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
|
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
|
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
|
#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
|
|
|
// addressBlock: dce_dc_hda_azstream0_azdec
|
// base address: 0x0
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761
|
#define mmAZSTREAM0_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_hda_azstream1_azdec
|
// base address: 0x20
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769
|
#define mmAZSTREAM1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_hda_azstream2_azdec
|
// base address: 0x40
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771
|
#define mmAZSTREAM2_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_hda_azstream3_azdec
|
// base address: 0x60
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779
|
#define mmAZSTREAM3_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_hda_azstream4_azdec
|
// base address: 0x80
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781
|
#define mmAZSTREAM4_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_hda_azstream5_azdec
|
// base address: 0xa0
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789
|
#define mmAZSTREAM5_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_hda_azstream6_azdec
|
// base address: 0xc0
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791
|
#define mmAZSTREAM6_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_hda_azstream7_azdec
|
// base address: 0xe0
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799
|
#define mmAZSTREAM7_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
|
|
|
// addressBlock: vga_vgaseqind
|
// base address: 0x0
|
#define ixSEQ00 0x0000
|
#define ixSEQ01 0x0001
|
#define ixSEQ02 0x0002
|
#define ixSEQ03 0x0003
|
#define ixSEQ04 0x0004
|
|
|
// addressBlock: vga_vgacrtind
|
// base address: 0x0
|
#define ixCRT00 0x0000
|
#define ixCRT01 0x0001
|
#define ixCRT02 0x0002
|
#define ixCRT03 0x0003
|
#define ixCRT04 0x0004
|
#define ixCRT05 0x0005
|
#define ixCRT06 0x0006
|
#define ixCRT07 0x0007
|
#define ixCRT08 0x0008
|
#define ixCRT09 0x0009
|
#define ixCRT0A 0x000a
|
#define ixCRT0B 0x000b
|
#define ixCRT0C 0x000c
|
#define ixCRT0D 0x000d
|
#define ixCRT0E 0x000e
|
#define ixCRT0F 0x000f
|
#define ixCRT10 0x0010
|
#define ixCRT11 0x0011
|
#define ixCRT12 0x0012
|
#define ixCRT13 0x0013
|
#define ixCRT14 0x0014
|
#define ixCRT15 0x0015
|
#define ixCRT16 0x0016
|
#define ixCRT17 0x0017
|
#define ixCRT18 0x0018
|
#define ixCRT1E 0x001e
|
#define ixCRT1F 0x001f
|
#define ixCRT22 0x0022
|
|
|
// addressBlock: vga_vgagrphind
|
// base address: 0x0
|
#define ixGRA00 0x0000
|
#define ixGRA01 0x0001
|
#define ixGRA02 0x0002
|
#define ixGRA03 0x0003
|
#define ixGRA04 0x0004
|
#define ixGRA05 0x0005
|
#define ixGRA06 0x0006
|
#define ixGRA07 0x0007
|
#define ixGRA08 0x0008
|
|
|
// addressBlock: vga_vgaattrind
|
// base address: 0x0
|
#define ixATTR00 0x0000
|
#define ixATTR01 0x0001
|
#define ixATTR02 0x0002
|
#define ixATTR03 0x0003
|
#define ixATTR04 0x0004
|
#define ixATTR05 0x0005
|
#define ixATTR06 0x0006
|
#define ixATTR07 0x0007
|
#define ixATTR08 0x0008
|
#define ixATTR09 0x0009
|
#define ixATTR0A 0x000a
|
#define ixATTR0B 0x000b
|
#define ixATTR0C 0x000c
|
#define ixATTR0D 0x000d
|
#define ixATTR0E 0x000e
|
#define ixATTR0F 0x000f
|
#define ixATTR10 0x0010
|
#define ixATTR11 0x0011
|
#define ixATTR12 0x0012
|
#define ixATTR13 0x0013
|
#define ixATTR14 0x0014
|
|
|
// addressBlock: azendpoint_f2codecind
|
// base address: 0x0
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
|
#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
|
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
|
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
|
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
|
#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
|
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
|
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
|
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
|
|
|
// addressBlock: azendpoint_descriptorind
|
// base address: 0x0
|
#define ixAUDIO_DESCRIPTOR0 0x0001
|
#define ixAUDIO_DESCRIPTOR1 0x0002
|
#define ixAUDIO_DESCRIPTOR2 0x0003
|
#define ixAUDIO_DESCRIPTOR3 0x0004
|
#define ixAUDIO_DESCRIPTOR4 0x0005
|
#define ixAUDIO_DESCRIPTOR5 0x0006
|
#define ixAUDIO_DESCRIPTOR6 0x0007
|
#define ixAUDIO_DESCRIPTOR7 0x0008
|
#define ixAUDIO_DESCRIPTOR8 0x0009
|
#define ixAUDIO_DESCRIPTOR9 0x000a
|
#define ixAUDIO_DESCRIPTOR10 0x000b
|
#define ixAUDIO_DESCRIPTOR11 0x000c
|
#define ixAUDIO_DESCRIPTOR12 0x000d
|
#define ixAUDIO_DESCRIPTOR13 0x000e
|
|
|
// addressBlock: azendpoint_sinkinfoind
|
// base address: 0x0
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
|
#define ixSINK_DESCRIPTION0 0x0005
|
#define ixSINK_DESCRIPTION1 0x0006
|
#define ixSINK_DESCRIPTION2 0x0007
|
#define ixSINK_DESCRIPTION3 0x0008
|
#define ixSINK_DESCRIPTION4 0x0009
|
#define ixSINK_DESCRIPTION5 0x000a
|
#define ixSINK_DESCRIPTION6 0x000b
|
#define ixSINK_DESCRIPTION7 0x000c
|
#define ixSINK_DESCRIPTION8 0x000d
|
#define ixSINK_DESCRIPTION9 0x000e
|
#define ixSINK_DESCRIPTION10 0x000f
|
#define ixSINK_DESCRIPTION11 0x0010
|
#define ixSINK_DESCRIPTION12 0x0011
|
#define ixSINK_DESCRIPTION13 0x0012
|
#define ixSINK_DESCRIPTION14 0x0013
|
#define ixSINK_DESCRIPTION15 0x0014
|
#define ixSINK_DESCRIPTION16 0x0015
|
#define ixSINK_DESCRIPTION17 0x0016
|
|
|
// addressBlock: azf0controller_azinputcrc0resultind
|
// base address: 0x0
|
#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
|
#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
|
#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
|
#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
|
#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
|
#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
|
#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
|
#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
|
|
|
// addressBlock: azf0controller_azinputcrc1resultind
|
// base address: 0x0
|
#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
|
#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
|
#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
|
#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
|
#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
|
#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
|
#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
|
#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
|
|
|
// addressBlock: azf0controller_azcrc0resultind
|
// base address: 0x0
|
#define ixAZALIA_CRC0_CHANNEL0 0x0000
|
#define ixAZALIA_CRC0_CHANNEL1 0x0001
|
#define ixAZALIA_CRC0_CHANNEL2 0x0002
|
#define ixAZALIA_CRC0_CHANNEL3 0x0003
|
#define ixAZALIA_CRC0_CHANNEL4 0x0004
|
#define ixAZALIA_CRC0_CHANNEL5 0x0005
|
#define ixAZALIA_CRC0_CHANNEL6 0x0006
|
#define ixAZALIA_CRC0_CHANNEL7 0x0007
|
|
|
// addressBlock: azf0controller_azcrc1resultind
|
// base address: 0x0
|
#define ixAZALIA_CRC1_CHANNEL0 0x0000
|
#define ixAZALIA_CRC1_CHANNEL1 0x0001
|
#define ixAZALIA_CRC1_CHANNEL2 0x0002
|
#define ixAZALIA_CRC1_CHANNEL3 0x0003
|
#define ixAZALIA_CRC1_CHANNEL4 0x0004
|
#define ixAZALIA_CRC1_CHANNEL5 0x0005
|
#define ixAZALIA_CRC1_CHANNEL6 0x0006
|
#define ixAZALIA_CRC1_CHANNEL7 0x0007
|
|
|
// addressBlock: azinputendpoint_f2codecind
|
// base address: 0x0
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
|
|
|
// addressBlock: azroot_f2codecind
|
// base address: 0x0
|
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
|
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
|
#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
|
#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
|
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
|
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
|
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
|
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
|
#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
|
|
|
// addressBlock: azf0stream0_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream1_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream2_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream3_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream4_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream5_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream6_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream7_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream8_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream9_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream10_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream11_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream12_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream13_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream14_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0stream15_streamind
|
// base address: 0x0
|
#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
|
#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
|
#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
|
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
|
#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
|
|
|
// addressBlock: azf0endpoint0_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
|
#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
|
|
|
// addressBlock: azf0endpoint1_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
|
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
|
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
|
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
|
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
|
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
|
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
|
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
|
#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
|
|
|
// addressBlock: azf0endpoint2_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
|
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
|
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
|
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
|
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
|
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
|
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
|
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
|
#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
|
|
|
// addressBlock: azf0endpoint3_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
|
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
|
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
|
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
|
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
|
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
|
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
|
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
|
#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
|
|
|
// addressBlock: azf0endpoint4_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
|
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
|
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
|
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
|
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
|
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
|
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
|
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
|
#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
|
|
|
// addressBlock: azf0endpoint5_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
|
#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
|
|
|
// addressBlock: azf0endpoint6_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
|
#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
|
|
|
// addressBlock: azf0endpoint7_endpointind
|
// base address: 0x0
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
|
#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
|
#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
|
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
|
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
|
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
|
#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
|
|
|
// addressBlock: azf0inputendpoint0_inputendpointind
|
// base address: 0x0
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
|
#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
|
|
|
// addressBlock: azf0inputendpoint1_inputendpointind
|
// base address: 0x0
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
|
#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
|
|
|
// addressBlock: azf0inputendpoint2_inputendpointind
|
// base address: 0x0
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
|
#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
|
|
|
// addressBlock: azf0inputendpoint3_inputendpointind
|
// base address: 0x0
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
|
#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
|
|
|
// addressBlock: azf0inputendpoint4_inputendpointind
|
// base address: 0x0
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
|
#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
|
|
|
// addressBlock: azf0inputendpoint5_inputendpointind
|
// base address: 0x0
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
|
#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
|
|
|
// addressBlock: azf0inputendpoint6_inputendpointind
|
// base address: 0x0
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
|
#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
|
|
|
// addressBlock: azf0inputendpoint7_inputendpointind
|
// base address: 0x0
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
|
#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
|
|
|
#endif
|
