/*
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* Copyright (C) 2017 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _dcn_1_0_OFFSET_HEADER
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#define _dcn_1_0_OFFSET_HEADER
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// addressBlock: dce_dc_hda_azcontroller_azdec
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// base address: 0x1300000
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// addressBlock: dce_dc_hda_azendpoint_azdec
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// base address: 0x1300000
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// addressBlock: dce_dc_hda_azinputendpoint_azdec
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// base address: 0x1300000
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// addressBlock: dce_dc_hda_azroot_azdec
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// base address: 0x1300000
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// addressBlock: dce_dc_hda_azstream0_azdec
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// base address: 0x1300000
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// addressBlock: dce_dc_hda_azstream1_azdec
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// base address: 0x1300020
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// addressBlock: dce_dc_hda_azstream2_azdec
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// base address: 0x1300040
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// addressBlock: dce_dc_hda_azstream3_azdec
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// base address: 0x1300060
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// addressBlock: dce_dc_hda_azstream4_azdec
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// base address: 0x1300080
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// addressBlock: dce_dc_hda_azstream5_azdec
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// base address: 0x13000a0
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// addressBlock: dce_dc_hda_azstream6_azdec
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// base address: 0x13000c0
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// addressBlock: dce_dc_hda_azstream7_azdec
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// base address: 0x13000e0
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// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
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// base address: 0x48
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#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000
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#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
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#define mmVGA_MEM_READ_PAGE_ADDR 0x0001
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#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
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// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986]
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// base address: 0x3b4
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#define mmCRTC8_IDX 0x002d
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#define mmCRTC8_IDX_BASE_IDX 1
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#define mmCRTC8_DATA 0x002d
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#define mmCRTC8_DATA_BASE_IDX 1
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#define mmGENFC_WT 0x002e
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#define mmGENFC_WT_BASE_IDX 1
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#define mmGENS1 0x002e
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#define mmGENS1_BASE_IDX 1
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#define mmATTRDW 0x0030
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#define mmATTRDW_BASE_IDX 1
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#define mmATTRX 0x0030
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#define mmATTRX_BASE_IDX 1
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#define mmATTRDR 0x0030
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#define mmATTRDR_BASE_IDX 1
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#define mmGENMO_WT 0x0030
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#define mmGENMO_WT_BASE_IDX 1
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#define mmGENS0 0x0030
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#define mmGENS0_BASE_IDX 1
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#define mmGENENB 0x0030
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#define mmGENENB_BASE_IDX 1
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#define mmSEQ8_IDX 0x0031
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#define mmSEQ8_IDX_BASE_IDX 1
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#define mmSEQ8_DATA 0x0031
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#define mmSEQ8_DATA_BASE_IDX 1
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#define mmDAC_MASK 0x0031
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#define mmDAC_MASK_BASE_IDX 1
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#define mmDAC_R_INDEX 0x0031
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#define mmDAC_R_INDEX_BASE_IDX 1
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#define mmDAC_W_INDEX 0x0032
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#define mmDAC_W_INDEX_BASE_IDX 1
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#define mmDAC_DATA 0x0032
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#define mmDAC_DATA_BASE_IDX 1
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#define mmGENFC_RD 0x0032
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#define mmGENFC_RD_BASE_IDX 1
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#define mmGENMO_RD 0x0033
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#define mmGENMO_RD_BASE_IDX 1
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#define mmGRPH8_IDX 0x0033
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#define mmGRPH8_IDX_BASE_IDX 1
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#define mmGRPH8_DATA 0x0033
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#define mmGRPH8_DATA_BASE_IDX 1
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#define mmCRTC8_IDX_1 0x0035
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#define mmCRTC8_IDX_1_BASE_IDX 1
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#define mmCRTC8_DATA_1 0x0035
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#define mmCRTC8_DATA_1_BASE_IDX 1
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#define mmGENFC_WT_1 0x0036
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#define mmGENFC_WT_1_BASE_IDX 1
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#define mmGENS1_1 0x0036
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#define mmGENS1_1_BASE_IDX 1
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// addressBlock: dce_dc_hda_azcontroller_azdec
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// base address: 0x0
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#define mmCORB_WRITE_POINTER 0x0000
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#define mmCORB_WRITE_POINTER_BASE_IDX 0
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#define mmCORB_READ_POINTER 0x0000
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#define mmCORB_READ_POINTER_BASE_IDX 0
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#define mmCORB_CONTROL 0x0001
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#define mmCORB_CONTROL_BASE_IDX 0
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#define mmCORB_STATUS 0x0001
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#define mmCORB_STATUS_BASE_IDX 0
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#define mmCORB_SIZE 0x0001
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#define mmCORB_SIZE_BASE_IDX 0
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#define mmRIRB_LOWER_BASE_ADDRESS 0x0002
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#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmRIRB_UPPER_BASE_ADDRESS 0x0003
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#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmRIRB_WRITE_POINTER 0x0004
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#define mmRIRB_WRITE_POINTER_BASE_IDX 0
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#define mmRESPONSE_INTERRUPT_COUNT 0x0004
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#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0
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#define mmRIRB_CONTROL 0x0005
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#define mmRIRB_CONTROL_BASE_IDX 0
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#define mmRIRB_STATUS 0x0005
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#define mmRIRB_STATUS_BASE_IDX 0
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#define mmRIRB_SIZE 0x0005
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#define mmRIRB_SIZE_BASE_IDX 0
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#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006
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#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0
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#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
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#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
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#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
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#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
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#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007
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#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0
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#define mmIMMEDIATE_COMMAND_STATUS 0x0008
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#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0
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#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a
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#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b
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#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c
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#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_hda_azendpoint_azdec
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// base address: 0x0
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
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// addressBlock: dce_dc_hda_azinputendpoint_azdec
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// base address: 0x0
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006
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#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0
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// addressBlock: dce_dc_hda_azroot_azdec
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// base address: 0x0
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#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006
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#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0
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#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006
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#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0
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// addressBlock: dce_dc_hda_azstream0_azdec
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// base address: 0x0
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761
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#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_hda_azstream1_azdec
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// base address: 0x20
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769
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#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_hda_azstream2_azdec
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// base address: 0x40
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771
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#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_hda_azstream3_azdec
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// base address: 0x60
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779
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#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_hda_azstream4_azdec
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// base address: 0x80
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781
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#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_hda_azstream5_azdec
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// base address: 0xa0
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789
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#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_hda_azstream6_azdec
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// base address: 0xc0
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791
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#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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// addressBlock: dce_dc_hda_azstream7_azdec
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// base address: 0xe0
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#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046
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#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0
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#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047
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#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0
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#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048
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#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0
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#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049
|
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0
|
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a
|
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0
|
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a
|
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0
|
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c
|
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d
|
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0
|
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799
|
#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1
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|
|
// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76]
|
// base address: 0x48
|
//#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000
|
//#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001
|
|
|
// addressBlock: dce_dc_mmhubbub_vga_dispdec
|
// base address: 0x0
|
//#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000
|
//#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001
|
#define mmVGA_RENDER_CONTROL 0x0000
|
#define mmVGA_RENDER_CONTROL_BASE_IDX 1
|
#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001
|
#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1
|
#define mmVGA_MODE_CONTROL 0x0002
|
#define mmVGA_MODE_CONTROL_BASE_IDX 1
|
#define mmVGA_SURFACE_PITCH_SELECT 0x0003
|
#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1
|
#define mmVGA_MEMORY_BASE_ADDRESS 0x0004
|
#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1
|
#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006
|
#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1
|
#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008
|
#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1
|
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009
|
#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1
|
#define mmVGA_HDP_CONTROL 0x000a
|
#define mmVGA_HDP_CONTROL_BASE_IDX 1
|
#define mmVGA_CACHE_CONTROL 0x000b
|
#define mmVGA_CACHE_CONTROL_BASE_IDX 1
|
#define mmD1VGA_CONTROL 0x000c
|
#define mmD1VGA_CONTROL_BASE_IDX 1
|
#define mmD2VGA_CONTROL 0x000e
|
#define mmD2VGA_CONTROL_BASE_IDX 1
|
#define mmVGA_STATUS 0x0010
|
#define mmVGA_STATUS_BASE_IDX 1
|
#define mmVGA_INTERRUPT_CONTROL 0x0011
|
#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1
|
#define mmVGA_STATUS_CLEAR 0x0012
|
#define mmVGA_STATUS_CLEAR_BASE_IDX 1
|
#define mmVGA_INTERRUPT_STATUS 0x0013
|
#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1
|
#define mmVGA_MAIN_CONTROL 0x0014
|
#define mmVGA_MAIN_CONTROL_BASE_IDX 1
|
#define mmVGA_TEST_CONTROL 0x0015
|
#define mmVGA_TEST_CONTROL_BASE_IDX 1
|
#define mmVGA_QOS_CTRL 0x0018
|
#define mmVGA_QOS_CTRL_BASE_IDX 1
|
//#define mmVGA_CRTC8_IDX 0x002d
|
//#define mmVGA_CRTC8_DATA 0x002d
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//#define mmVGA_GENFC_WT 0x002e
|
//#define mmVGA_GENS1 0x002e
|
//#define mmVGA_ATTRDW 0x0030
|
//#define mmVGA_ATTRX 0x0030
|
//#define mmVGA_ATTRDR 0x0030
|
//#define mmVGA_GENMO_WT 0x0030
|
//#define mmVGA_GENS0 0x0030
|
//#define mmVGA_GENENB 0x0030
|
//#define mmVGA_SEQ8_IDX 0x0031
|
//#define mmVGA_SEQ8_DATA 0x0031
|
//#define mmVGA_DAC_MASK 0x0031
|
//#define mmVGA_DAC_R_INDEX 0x0031
|
//#define mmVGA_DAC_W_INDEX 0x0032
|
//#define mmVGA_DAC_DATA 0x0032
|
//#define mmVGA_GENFC_RD 0x0032
|
//#define mmVGA_GENMO_RD 0x0033
|
//#define mmVGA_GRPH8_IDX 0x0033
|
//#define mmVGA_GRPH8_DATA 0x0033
|
//#define mmVGA_CRTC8_IDX_1 0x0035
|
//#define mmVGA_CRTC8_DATA_1 0x0035
|
//#define mmVGA_GENFC_WT_1 0x0036
|
//#define mmVGA_GENS1_1 0x0036
|
#define mmD3VGA_CONTROL 0x0038
|
#define mmD3VGA_CONTROL_BASE_IDX 1
|
#define mmD4VGA_CONTROL 0x0039
|
#define mmD4VGA_CONTROL_BASE_IDX 1
|
#define mmD5VGA_CONTROL 0x003a
|
#define mmD5VGA_CONTROL_BASE_IDX 1
|
#define mmD6VGA_CONTROL 0x003b
|
#define mmD6VGA_CONTROL_BASE_IDX 1
|
#define mmVGA_SOURCE_SELECT 0x003c
|
#define mmVGA_SOURCE_SELECT_BASE_IDX 1
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|
|
// addressBlock: dce_dc_dccg_dccg_dispdec
|
// base address: 0x0
|
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
|
#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
|
#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
|
#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
|
#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmDP_DTO_DBUF_EN 0x0044
|
#define mmDP_DTO_DBUF_EN_BASE_IDX 1
|
#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048
|
#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmREFCLK_CNTL 0x0049
|
#define mmREFCLK_CNTL_BASE_IDX 1
|
#define mmMIPI_CLK_CNTL 0x004a
|
#define mmMIPI_CLK_CNTL_BASE_IDX 1
|
#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b
|
#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c
|
#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmDCCG_PERFMON_CNTL2 0x004e
|
#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1
|
#define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f
|
#define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmDCCG_CBUS_WRCMD_DELAY 0x0050
|
#define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1
|
#define mmDCCG_DS_DTO_INCR 0x0053
|
#define mmDCCG_DS_DTO_INCR_BASE_IDX 1
|
#define mmDCCG_DS_DTO_MODULO 0x0054
|
#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1
|
#define mmDCCG_DS_CNTL 0x0055
|
#define mmDCCG_DS_CNTL_BASE_IDX 1
|
#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056
|
#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1
|
#define mmSYMCLKG_CLOCK_ENABLE 0x0057
|
#define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1
|
#define mmDPREFCLK_CNTL 0x0058
|
#define mmDPREFCLK_CNTL_BASE_IDX 1
|
#define mmAOMCLK0_CNTL 0x0059
|
#define mmAOMCLK0_CNTL_BASE_IDX 1
|
#define mmAOMCLK1_CNTL 0x005a
|
#define mmAOMCLK1_CNTL_BASE_IDX 1
|
#define mmAOMCLK2_CNTL 0x005b
|
#define mmAOMCLK2_CNTL_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO2_PHASE 0x005c
|
#define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO2_MODULO 0x005d
|
#define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1
|
#define mmDCE_VERSION 0x005e
|
#define mmDCE_VERSION_BASE_IDX 1
|
#define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
|
#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmDCCG_GTC_CNTL 0x0060
|
#define mmDCCG_GTC_CNTL_BASE_IDX 1
|
#define mmDCCG_GTC_DTO_INCR 0x0061
|
#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1
|
#define mmDCCG_GTC_DTO_MODULO 0x0062
|
#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1
|
#define mmDCCG_GTC_CURRENT 0x0063
|
#define mmDCCG_GTC_CURRENT_BASE_IDX 1
|
#define mmMIPI_DTO_CNTL 0x0065
|
#define mmMIPI_DTO_CNTL_BASE_IDX 1
|
#define mmMIPI_DTO_PHASE 0x0066
|
#define mmMIPI_DTO_PHASE_BASE_IDX 1
|
#define mmMIPI_DTO_MODULO 0x0067
|
#define mmMIPI_DTO_MODULO_BASE_IDX 1
|
#define mmDAC_CLK_ENABLE 0x0068
|
#define mmDAC_CLK_ENABLE_BASE_IDX 1
|
#define mmDVO_CLK_ENABLE 0x0069
|
#define mmDVO_CLK_ENABLE_BASE_IDX 1
|
#define mmAVSYNC_COUNTER_WRITE 0x006a
|
#define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1
|
#define mmAVSYNC_COUNTER_CONTROL 0x006b
|
#define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1
|
#define mmAVSYNC_COUNTER_READ 0x006f
|
#define mmAVSYNC_COUNTER_READ_BASE_IDX 1
|
#define mmMILLISECOND_TIME_BASE_DIV 0x0070
|
#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1
|
#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071
|
#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1
|
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072
|
#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1
|
#define mmDCCG_PERFMON_CNTL 0x0073
|
#define mmDCCG_PERFMON_CNTL_BASE_IDX 1
|
#define mmDCCG_GATE_DISABLE_CNTL 0x0074
|
#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1
|
#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075
|
#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076
|
#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmDCCG_CAC_STATUS 0x0077
|
#define mmDCCG_CAC_STATUS_BASE_IDX 1
|
#define mmPIXCLK1_RESYNC_CNTL 0x0078
|
#define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1
|
#define mmPIXCLK2_RESYNC_CNTL 0x0079
|
#define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1
|
#define mmPIXCLK0_RESYNC_CNTL 0x007a
|
#define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1
|
#define mmMICROSECOND_TIME_BASE_DIV 0x007b
|
#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1
|
#define mmDCCG_GATE_DISABLE_CNTL2 0x007c
|
#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1
|
#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d
|
#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
|
#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
#define mmDCCG_DISP_CNTL_REG 0x007f
|
#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1
|
#define mmOTG0_PIXEL_RATE_CNTL 0x0080
|
#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO0_PHASE 0x0081
|
#define mmDP_DTO0_PHASE_BASE_IDX 1
|
#define mmDP_DTO0_MODULO 0x0082
|
#define mmDP_DTO0_MODULO_BASE_IDX 1
|
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083
|
#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmOTG1_PIXEL_RATE_CNTL 0x0084
|
#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO1_PHASE 0x0085
|
#define mmDP_DTO1_PHASE_BASE_IDX 1
|
#define mmDP_DTO1_MODULO 0x0086
|
#define mmDP_DTO1_MODULO_BASE_IDX 1
|
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087
|
#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmOTG2_PIXEL_RATE_CNTL 0x0088
|
#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO2_PHASE 0x0089
|
#define mmDP_DTO2_PHASE_BASE_IDX 1
|
#define mmDP_DTO2_MODULO 0x008a
|
#define mmDP_DTO2_MODULO_BASE_IDX 1
|
#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b
|
#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmOTG3_PIXEL_RATE_CNTL 0x008c
|
#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO3_PHASE 0x008d
|
#define mmDP_DTO3_PHASE_BASE_IDX 1
|
#define mmDP_DTO3_MODULO 0x008e
|
#define mmDP_DTO3_MODULO_BASE_IDX 1
|
#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f
|
#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmOTG4_PIXEL_RATE_CNTL 0x0090
|
#define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO4_PHASE 0x0091
|
#define mmDP_DTO4_PHASE_BASE_IDX 1
|
#define mmDP_DTO4_MODULO 0x0092
|
#define mmDP_DTO4_MODULO_BASE_IDX 1
|
#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093
|
#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmOTG5_PIXEL_RATE_CNTL 0x0094
|
#define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDP_DTO5_PHASE 0x0095
|
#define mmDP_DTO5_PHASE_BASE_IDX 1
|
#define mmDP_DTO5_MODULO 0x0096
|
#define mmDP_DTO5_MODULO_BASE_IDX 1
|
#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097
|
#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1
|
#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098
|
#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1
|
#define mmSYMCLKA_CLOCK_ENABLE 0x00a0
|
#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKB_CLOCK_ENABLE 0x00a1
|
#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKC_CLOCK_ENABLE 0x00a2
|
#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKD_CLOCK_ENABLE 0x00a3
|
#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKE_CLOCK_ENABLE 0x00a4
|
#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1
|
#define mmSYMCLKF_CLOCK_ENABLE 0x00a5
|
#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1
|
#define mmDCCG_SOFT_RESET 0x00a6
|
#define mmDCCG_SOFT_RESET_BASE_IDX 1
|
#define mmDVOACLKD_CNTL 0x00a8
|
#define mmDVOACLKD_CNTL_BASE_IDX 1
|
#define mmDVOACLKC_MVP_CNTL 0x00a9
|
#define mmDVOACLKC_MVP_CNTL_BASE_IDX 1
|
#define mmDVOACLKC_CNTL 0x00aa
|
#define mmDVOACLKC_CNTL_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab
|
#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac
|
#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad
|
#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae
|
#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1
|
#define mmDCCG_AUDIO_DTO1_MODULE 0x00af
|
#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1
|
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0
|
#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1
|
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1
|
#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1
|
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2
|
#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1
|
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3
|
#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1
|
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4
|
#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1
|
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5
|
#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1
|
#define mmDCCG_VSYNC_CNT_CTRL 0x00b8
|
#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1
|
#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9
|
#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1
|
#define mmDCCG_TEST_CLK_SEL 0x00be
|
#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_dccg_dccg_dfs_dispdec
|
// base address: 0x0
|
#define mmDENTIST_DISPCLK_CNTL 0x0064
|
#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1
|
|
|
// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec
|
// base address: 0x0
|
#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000
|
#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001
|
#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002
|
#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFMON_CNTL 0x0003
|
#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004
|
#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005
|
#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006
|
#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFMON_HI 0x0007
|
#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON0_PERFMON_LOW 0x0008
|
#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec
|
// base address: 0x30
|
#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c
|
#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d
|
#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e
|
#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFMON_CNTL 0x000f
|
#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010
|
#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011
|
#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012
|
#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFMON_HI 0x0013
|
#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON1_PERFMON_LOW 0x0014
|
#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dccg_dccg_pll_dispdec
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// base address: 0x0
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#define mmPLL_MACRO_CNTL_RESERVED0 0x0018
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#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED1 0x0019
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#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED2 0x001a
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#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED3 0x001b
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#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED4 0x001c
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#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED5 0x001d
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#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED6 0x001e
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#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED7 0x001f
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#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED8 0x0020
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#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED9 0x0021
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#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED10 0x0022
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#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED11 0x0023
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#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED12 0x0024
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#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED13 0x0025
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#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED14 0x0026
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#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED15 0x0027
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#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED16 0x0028
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#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED17 0x0029
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#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED18 0x002a
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#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED19 0x002b
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#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED20 0x002c
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#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED21 0x002d
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#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED22 0x002e
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#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED23 0x002f
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#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED24 0x0030
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#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED25 0x0031
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#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED26 0x0032
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#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED27 0x0033
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#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED28 0x0034
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#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED29 0x0035
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#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED30 0x0036
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#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED31 0x0037
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#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED32 0x0038
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#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED33 0x0039
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#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED34 0x003a
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#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED35 0x003b
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#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED36 0x003c
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#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED37 0x003d
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#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED38 0x003e
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#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED39 0x003f
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#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED40 0x0040
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#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmPLL_MACRO_CNTL_RESERVED41 0x0041
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#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2
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// addressBlock: dce_dc_dmu_rbbmif_dispdec
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// base address: 0x0
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#define mmRBBMIF_TIMEOUT 0x0055
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#define mmRBBMIF_TIMEOUT_BASE_IDX 2
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#define mmRBBMIF_STATUS 0x0056
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#define mmRBBMIF_STATUS_BASE_IDX 2
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#define mmRBBMIF_INT_STATUS 0x0057
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#define mmRBBMIF_INT_STATUS_BASE_IDX 2
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#define mmRBBMIF_TIMEOUT_DIS 0x0058
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#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2
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#define mmRBBMIF_STATUS_FLAG 0x0059
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#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2
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// addressBlock: dce_dc_dmu_dc_pg_dispdec
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// base address: 0x0
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#define mmDOMAIN0_PG_CONFIG 0x008a
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#define mmDOMAIN0_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN0_PG_STATUS 0x008b
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#define mmDOMAIN0_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN1_PG_CONFIG 0x008c
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#define mmDOMAIN1_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN1_PG_STATUS 0x008d
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#define mmDOMAIN1_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN2_PG_CONFIG 0x008e
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#define mmDOMAIN2_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN2_PG_STATUS 0x008f
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#define mmDOMAIN2_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN3_PG_CONFIG 0x0090
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#define mmDOMAIN3_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN3_PG_STATUS 0x0091
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#define mmDOMAIN3_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN4_PG_CONFIG 0x0092
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#define mmDOMAIN4_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN4_PG_STATUS 0x0093
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#define mmDOMAIN4_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN5_PG_CONFIG 0x0094
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#define mmDOMAIN5_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN5_PG_STATUS 0x0095
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#define mmDOMAIN5_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN6_PG_CONFIG 0x0096
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#define mmDOMAIN6_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN6_PG_STATUS 0x0097
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#define mmDOMAIN6_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN7_PG_CONFIG 0x0098
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#define mmDOMAIN7_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN7_PG_STATUS 0x0099
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#define mmDOMAIN7_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN8_PG_CONFIG 0x009a
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#define mmDOMAIN8_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN8_PG_STATUS 0x009b
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#define mmDOMAIN8_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN9_PG_CONFIG 0x009c
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#define mmDOMAIN9_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN9_PG_STATUS 0x009d
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#define mmDOMAIN9_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN10_PG_CONFIG 0x009e
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#define mmDOMAIN10_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN10_PG_STATUS 0x009f
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#define mmDOMAIN10_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN11_PG_CONFIG 0x00a0
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#define mmDOMAIN11_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN11_PG_STATUS 0x00a1
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#define mmDOMAIN11_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN12_PG_CONFIG 0x00a2
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#define mmDOMAIN12_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN12_PG_STATUS 0x00a3
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#define mmDOMAIN12_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN13_PG_CONFIG 0x00a4
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#define mmDOMAIN13_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN13_PG_STATUS 0x00a5
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#define mmDOMAIN13_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN14_PG_CONFIG 0x00a6
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#define mmDOMAIN14_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN14_PG_STATUS 0x00a7
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#define mmDOMAIN14_PG_STATUS_BASE_IDX 2
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#define mmDOMAIN15_PG_CONFIG 0x00a8
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#define mmDOMAIN15_PG_CONFIG_BASE_IDX 2
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#define mmDOMAIN15_PG_STATUS 0x00a9
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#define mmDOMAIN15_PG_STATUS_BASE_IDX 2
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#define mmDCPG_INTERRUPT_STATUS 0x00aa
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#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDCPG_INTERRUPT_CONTROL_1 0x00ab
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#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2
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#define mmDCPG_INTERRUPT_CONTROL_2 0x00ac
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#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2
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#define mmDC_IP_REQUEST_CNTL 0x00ad
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#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2
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#define mmDC_PGCNTL_STATUS_REG 0x00ae
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#define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2
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// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec
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// base address: 0x2f8
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#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be
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#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf
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#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0
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#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_CNTL 0x00c1
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#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2
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#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3
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#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4
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#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_HI 0x00c5
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#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON2_PERFMON_LOW 0x00c6
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#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dmu_dmu_misc_dispdec
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// base address: 0x0
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#define mmCC_DC_PIPE_DIS 0x00ca
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#define mmCC_DC_PIPE_DIS_BASE_IDX 2
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#define mmDMU_CLK_CNTL 0x00cb
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#define mmDMU_CLK_CNTL_BASE_IDX 2
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#define mmDMU_MEM_PWR_CNTL 0x00cc
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#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2
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#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd
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#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2
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#define mmSMU_INTERRUPT_CONTROL 0x00ce
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#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dmu_dmcu_dispdec
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// base address: 0x0
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#define mmDMCU_CTRL 0x00da
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#define mmDMCU_CTRL_BASE_IDX 2
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#define mmDMCU_STATUS 0x00db
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#define mmDMCU_STATUS_BASE_IDX 2
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#define mmDMCU_PC_START_ADDR 0x00dc
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#define mmDMCU_PC_START_ADDR_BASE_IDX 2
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#define mmDMCU_FW_START_ADDR 0x00dd
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#define mmDMCU_FW_START_ADDR_BASE_IDX 2
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#define mmDMCU_FW_END_ADDR 0x00de
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#define mmDMCU_FW_END_ADDR_BASE_IDX 2
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#define mmDMCU_FW_ISR_START_ADDR 0x00df
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#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2
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#define mmDMCU_FW_CS_HI 0x00e0
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#define mmDMCU_FW_CS_HI_BASE_IDX 2
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#define mmDMCU_FW_CS_LO 0x00e1
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#define mmDMCU_FW_CS_LO_BASE_IDX 2
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#define mmDMCU_RAM_ACCESS_CTRL 0x00e2
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#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2
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#define mmDMCU_ERAM_WR_CTRL 0x00e3
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#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2
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#define mmDMCU_ERAM_WR_DATA 0x00e4
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#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2
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#define mmDMCU_ERAM_RD_CTRL 0x00e5
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#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2
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#define mmDMCU_ERAM_RD_DATA 0x00e6
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#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2
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#define mmDMCU_IRAM_WR_CTRL 0x00e7
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#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2
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#define mmDMCU_IRAM_WR_DATA 0x00e8
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#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2
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#define mmDMCU_IRAM_RD_CTRL 0x00e9
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#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2
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#define mmDMCU_IRAM_RD_DATA 0x00ea
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#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2
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#define mmDMCU_EVENT_TRIGGER 0x00eb
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#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2
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#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec
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#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2
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#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed
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#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2
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#define mmDMCU_INTERRUPT_STATUS 0x00ee
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#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDMCU_INTERRUPT_STATUS_1 0x00ef
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#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2
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#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0
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#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2
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#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1
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#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2
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#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2
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#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2
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#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3
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#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2
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#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4
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#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2
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#define mmDC_DMCU_SCRATCH 0x00f5
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#define mmDC_DMCU_SCRATCH_BASE_IDX 2
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#define mmDMCU_INT_CNT 0x00f6
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#define mmDMCU_INT_CNT_BASE_IDX 2
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#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7
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#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2
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#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8
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#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2
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#define mmMASTER_COMM_DATA_REG1 0x00f9
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#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2
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#define mmMASTER_COMM_DATA_REG2 0x00fa
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#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2
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#define mmMASTER_COMM_DATA_REG3 0x00fb
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#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2
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#define mmMASTER_COMM_CMD_REG 0x00fc
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#define mmMASTER_COMM_CMD_REG_BASE_IDX 2
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#define mmMASTER_COMM_CNTL_REG 0x00fd
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#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2
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#define mmSLAVE_COMM_DATA_REG1 0x00fe
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#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2
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#define mmSLAVE_COMM_DATA_REG2 0x00ff
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#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2
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#define mmSLAVE_COMM_DATA_REG3 0x0100
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#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2
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#define mmSLAVE_COMM_CMD_REG 0x0101
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#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2
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#define mmSLAVE_COMM_CNTL_REG 0x0102
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#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105
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#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106
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#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107
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#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108
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#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109
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#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2
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#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113
|
#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2
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#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114
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#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2
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#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115
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#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2
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#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116
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#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2
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#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119
|
#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
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#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a
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#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2
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#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b
|
#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2
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#define mmDMCU_INT_CNT_CONTINUE 0x011c
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#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2
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// addressBlock: dce_dc_dmu_ihc_dispdec
|
// base address: 0x0
|
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126
|
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2
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#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127
|
#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2
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#define mmDC_GPU_TIMER_READ 0x0128
|
#define mmDC_GPU_TIMER_READ_BASE_IDX 2
|
#define mmDC_GPU_TIMER_READ_CNTL 0x0129
|
#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2
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#define mmDISP_INTERRUPT_STATUS 0x012a
|
#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f
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#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140
|
#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141
|
#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142
|
#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143
|
#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2
|
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144
|
#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2
|
|
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// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec
|
// base address: 0x0
|
#define mmCNV0_WB_ENABLE 0x01da
|
#define mmCNV0_WB_ENABLE_BASE_IDX 2
|
#define mmCNV0_WB_EC_CONFIG 0x01db
|
#define mmCNV0_WB_EC_CONFIG_BASE_IDX 2
|
#define mmCNV0_CNV_MODE 0x01dc
|
#define mmCNV0_CNV_MODE_BASE_IDX 2
|
#define mmCNV0_CNV_WINDOW_START 0x01dd
|
#define mmCNV0_CNV_WINDOW_START_BASE_IDX 2
|
#define mmCNV0_CNV_WINDOW_SIZE 0x01de
|
#define mmCNV0_CNV_WINDOW_SIZE_BASE_IDX 2
|
#define mmCNV0_CNV_UPDATE 0x01df
|
#define mmCNV0_CNV_UPDATE_BASE_IDX 2
|
#define mmCNV0_CNV_SOURCE_SIZE 0x01e0
|
#define mmCNV0_CNV_SOURCE_SIZE_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_CONTROL 0x01e1
|
#define mmCNV0_CNV_CSC_CONTROL_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_C11_C12 0x01e2
|
#define mmCNV0_CNV_CSC_C11_C12_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_C13_C14 0x01e3
|
#define mmCNV0_CNV_CSC_C13_C14_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_C21_C22 0x01e4
|
#define mmCNV0_CNV_CSC_C21_C22_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_C23_C24 0x01e5
|
#define mmCNV0_CNV_CSC_C23_C24_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_C31_C32 0x01e6
|
#define mmCNV0_CNV_CSC_C31_C32_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_C33_C34 0x01e7
|
#define mmCNV0_CNV_CSC_C33_C34_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_ROUND_OFFSET_R 0x01e8
|
#define mmCNV0_CNV_CSC_ROUND_OFFSET_R_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_ROUND_OFFSET_G 0x01e9
|
#define mmCNV0_CNV_CSC_ROUND_OFFSET_G_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_ROUND_OFFSET_B 0x01ea
|
#define mmCNV0_CNV_CSC_ROUND_OFFSET_B_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_CLAMP_R 0x01eb
|
#define mmCNV0_CNV_CSC_CLAMP_R_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_CLAMP_G 0x01ec
|
#define mmCNV0_CNV_CSC_CLAMP_G_BASE_IDX 2
|
#define mmCNV0_CNV_CSC_CLAMP_B 0x01ed
|
#define mmCNV0_CNV_CSC_CLAMP_B_BASE_IDX 2
|
#define mmCNV0_CNV_TEST_CNTL 0x01ee
|
#define mmCNV0_CNV_TEST_CNTL_BASE_IDX 2
|
#define mmCNV0_CNV_TEST_CRC_RED 0x01ef
|
#define mmCNV0_CNV_TEST_CRC_RED_BASE_IDX 2
|
#define mmCNV0_CNV_TEST_CRC_GREEN 0x01f0
|
#define mmCNV0_CNV_TEST_CRC_GREEN_BASE_IDX 2
|
#define mmCNV0_CNV_TEST_CRC_BLUE 0x01f1
|
#define mmCNV0_CNV_TEST_CRC_BLUE_BASE_IDX 2
|
#define mmCNV0_CNV_INPUT_SELECT 0x01f5
|
#define mmCNV0_CNV_INPUT_SELECT_BASE_IDX 2
|
#define mmCNV0_WB_SOFT_RESET 0x01f8
|
#define mmCNV0_WB_SOFT_RESET_BASE_IDX 2
|
#define mmCNV0_WB_WARM_UP_MODE_CTL1 0x01f9
|
#define mmCNV0_WB_WARM_UP_MODE_CTL1_BASE_IDX 2
|
#define mmCNV0_WB_WARM_UP_MODE_CTL2 0x01fa
|
#define mmCNV0_WB_WARM_UP_MODE_CTL2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec
|
// base address: 0x0
|
#define mmWBSCL0_WBSCL_COEF_RAM_SELECT 0x020a
|
#define mmWBSCL0_WBSCL_COEF_RAM_SELECT_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA 0x020b
|
#define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_MODE 0x020c
|
#define mmWBSCL0_WBSCL_MODE_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_TAP_CONTROL 0x020d
|
#define mmWBSCL0_WBSCL_TAP_CONTROL_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_DEST_SIZE 0x020e
|
#define mmWBSCL0_WBSCL_DEST_SIZE_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO 0x020f
|
#define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB 0x0210
|
#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR 0x0211
|
#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO 0x0212
|
#define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB 0x0213
|
#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR 0x0214
|
#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_ROUND_OFFSET 0x0215
|
#define mmWBSCL0_WBSCL_ROUND_OFFSET_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_CLAMP 0x0216
|
#define mmWBSCL0_WBSCL_CLAMP_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_OVERFLOW_STATUS 0x0217
|
#define mmWBSCL0_WBSCL_OVERFLOW_STATUS_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS 0x0218
|
#define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY 0x0219
|
#define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_TEST_CNTL 0x021a
|
#define mmWBSCL0_WBSCL_TEST_CNTL_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_TEST_CRC_RED 0x021b
|
#define mmWBSCL0_WBSCL_TEST_CRC_RED_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_TEST_CRC_GREEN 0x021c
|
#define mmWBSCL0_WBSCL_TEST_CRC_GREEN_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_TEST_CRC_BLUE 0x021d
|
#define mmWBSCL0_WBSCL_TEST_CRC_BLUE_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN 0x021e
|
#define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
|
#define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT 0x021f
|
#define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
|
#define mmWBSCL0_WBSCL_RAM_SHUTDOWN 0x0222
|
#define mmWBSCL0_WBSCL_RAM_SHUTDOWN_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x8e8
|
#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x023a
|
#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x023b
|
#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x023c
|
#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_CNTL 0x023d
|
#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_CNTL2 0x023e
|
#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x023f
|
#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0240
|
#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_HI 0x0241
|
#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON3_PERFMON_LOW 0x0242
|
#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_wb1_dispdec_cnv_dispdec
|
// base address: 0x1b0
|
#define mmCNV1_WB_ENABLE 0x0246
|
#define mmCNV1_WB_ENABLE_BASE_IDX 2
|
#define mmCNV1_WB_EC_CONFIG 0x0247
|
#define mmCNV1_WB_EC_CONFIG_BASE_IDX 2
|
#define mmCNV1_CNV_MODE 0x0248
|
#define mmCNV1_CNV_MODE_BASE_IDX 2
|
#define mmCNV1_CNV_WINDOW_START 0x0249
|
#define mmCNV1_CNV_WINDOW_START_BASE_IDX 2
|
#define mmCNV1_CNV_WINDOW_SIZE 0x024a
|
#define mmCNV1_CNV_WINDOW_SIZE_BASE_IDX 2
|
#define mmCNV1_CNV_UPDATE 0x024b
|
#define mmCNV1_CNV_UPDATE_BASE_IDX 2
|
#define mmCNV1_CNV_SOURCE_SIZE 0x024c
|
#define mmCNV1_CNV_SOURCE_SIZE_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_CONTROL 0x024d
|
#define mmCNV1_CNV_CSC_CONTROL_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_C11_C12 0x024e
|
#define mmCNV1_CNV_CSC_C11_C12_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_C13_C14 0x024f
|
#define mmCNV1_CNV_CSC_C13_C14_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_C21_C22 0x0250
|
#define mmCNV1_CNV_CSC_C21_C22_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_C23_C24 0x0251
|
#define mmCNV1_CNV_CSC_C23_C24_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_C31_C32 0x0252
|
#define mmCNV1_CNV_CSC_C31_C32_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_C33_C34 0x0253
|
#define mmCNV1_CNV_CSC_C33_C34_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_ROUND_OFFSET_R 0x0254
|
#define mmCNV1_CNV_CSC_ROUND_OFFSET_R_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_ROUND_OFFSET_G 0x0255
|
#define mmCNV1_CNV_CSC_ROUND_OFFSET_G_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_ROUND_OFFSET_B 0x0256
|
#define mmCNV1_CNV_CSC_ROUND_OFFSET_B_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_CLAMP_R 0x0257
|
#define mmCNV1_CNV_CSC_CLAMP_R_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_CLAMP_G 0x0258
|
#define mmCNV1_CNV_CSC_CLAMP_G_BASE_IDX 2
|
#define mmCNV1_CNV_CSC_CLAMP_B 0x0259
|
#define mmCNV1_CNV_CSC_CLAMP_B_BASE_IDX 2
|
#define mmCNV1_CNV_TEST_CNTL 0x025a
|
#define mmCNV1_CNV_TEST_CNTL_BASE_IDX 2
|
#define mmCNV1_CNV_TEST_CRC_RED 0x025b
|
#define mmCNV1_CNV_TEST_CRC_RED_BASE_IDX 2
|
#define mmCNV1_CNV_TEST_CRC_GREEN 0x025c
|
#define mmCNV1_CNV_TEST_CRC_GREEN_BASE_IDX 2
|
#define mmCNV1_CNV_TEST_CRC_BLUE 0x025d
|
#define mmCNV1_CNV_TEST_CRC_BLUE_BASE_IDX 2
|
#define mmCNV1_CNV_INPUT_SELECT 0x0261
|
#define mmCNV1_CNV_INPUT_SELECT_BASE_IDX 2
|
#define mmCNV1_WB_SOFT_RESET 0x0264
|
#define mmCNV1_WB_SOFT_RESET_BASE_IDX 2
|
#define mmCNV1_WB_WARM_UP_MODE_CTL1 0x0265
|
#define mmCNV1_WB_WARM_UP_MODE_CTL1_BASE_IDX 2
|
#define mmCNV1_WB_WARM_UP_MODE_CTL2 0x0266
|
#define mmCNV1_WB_WARM_UP_MODE_CTL2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec
|
// base address: 0x1b0
|
#define mmWBSCL1_WBSCL_COEF_RAM_SELECT 0x0276
|
#define mmWBSCL1_WBSCL_COEF_RAM_SELECT_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA 0x0277
|
#define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_MODE 0x0278
|
#define mmWBSCL1_WBSCL_MODE_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_TAP_CONTROL 0x0279
|
#define mmWBSCL1_WBSCL_TAP_CONTROL_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_DEST_SIZE 0x027a
|
#define mmWBSCL1_WBSCL_DEST_SIZE_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO 0x027b
|
#define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB 0x027c
|
#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR 0x027d
|
#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO 0x027e
|
#define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB 0x027f
|
#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR 0x0280
|
#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_ROUND_OFFSET 0x0281
|
#define mmWBSCL1_WBSCL_ROUND_OFFSET_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_CLAMP 0x0282
|
#define mmWBSCL1_WBSCL_CLAMP_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_OVERFLOW_STATUS 0x0283
|
#define mmWBSCL1_WBSCL_OVERFLOW_STATUS_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS 0x0284
|
#define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY 0x0285
|
#define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_TEST_CNTL 0x0286
|
#define mmWBSCL1_WBSCL_TEST_CNTL_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_TEST_CRC_RED 0x0287
|
#define mmWBSCL1_WBSCL_TEST_CRC_RED_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_TEST_CRC_GREEN 0x0288
|
#define mmWBSCL1_WBSCL_TEST_CRC_GREEN_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_TEST_CRC_BLUE 0x0289
|
#define mmWBSCL1_WBSCL_TEST_CRC_BLUE_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN 0x028a
|
#define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2
|
#define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT 0x028b
|
#define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2
|
#define mmWBSCL1_WBSCL_RAM_SHUTDOWN 0x028e
|
#define mmWBSCL1_WBSCL_RAM_SHUTDOWN_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xa98
|
#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x02a6
|
#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x02a7
|
#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x02a8
|
#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFMON_CNTL 0x02a9
|
#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFMON_CNTL2 0x02aa
|
#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x02ab
|
#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x02ac
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#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_HI 0x02ad
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#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON4_PERFMON_LOW 0x02ae
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#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec
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// base address: 0x0
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x02b4
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x02b5
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#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x02b6
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#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x02b7
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#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x02b8
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#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x02b9
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#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x02ba
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#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x02bb
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#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x02bc
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#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x02bd
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#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x02be
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#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x02bf
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#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x02c2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x02c4
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5
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#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x02c6
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x02c8
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9
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#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x02ca
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x02cc
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd
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#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x02ce
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x02d0
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1
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#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2
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#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3
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#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x02d4
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#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x02d5
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#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6
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#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x02d7
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#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8
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#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
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#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9
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#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db
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#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
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#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc
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#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
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// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec
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// base address: 0x100
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02f4
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02f5
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#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02f6
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#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02f7
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#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02f8
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#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02f9
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#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02fa
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#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02fb
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#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02fc
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#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02fd
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#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02fe
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#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02ff
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#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x0302
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x0304
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305
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#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x0306
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x0308
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309
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#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x030a
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x030c
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d
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#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x030e
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x0310
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311
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#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312
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#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313
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#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x0314
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#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x0315
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#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x0316
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#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x0317
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#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x0318
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#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2
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#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x0319
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#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x031b
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#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2
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#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x031c
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#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2
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// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec
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// base address: 0x0
|
#define mmWBIF0_MISC_CTRL 0x0333
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#define mmWBIF0_MISC_CTRL_BASE_IDX 2
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#define mmWBIF0_SMU_WM_CONTROL 0x0334
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#define mmWBIF0_SMU_WM_CONTROL_BASE_IDX 2
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#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335
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#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336
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#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmWBIF1_MISC_CTRL 0x0337
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#define mmWBIF1_MISC_CTRL_BASE_IDX 2
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#define mmWBIF1_SMU_WM_CONTROL 0x0338
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#define mmWBIF1_SMU_WM_CONTROL_BASE_IDX 2
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#define mmWBIF1_PHASE0_OUTSTANDING_COUNTER 0x0339
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#define mmWBIF1_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmWBIF1_PHASE1_OUTSTANDING_COUNTER 0x033a
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#define mmWBIF1_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmVGA_SRC_SPLIT_CNTL 0x033b
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#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2
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#define mmMMHUBBUB_MEM_PWR_STATUS 0x033c
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#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2
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#define mmMMHUBBUB_MEM_PWR_CNTL 0x033d
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#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2
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#define mmMMHUBBUB_CLOCK_CNTL 0x033e
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#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2
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#define mmMMHUBBUB_SOFT_RESET 0x033f
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#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2
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// addressBlock: dce_dc_mmhubbub_vgaif_dispdec
|
// base address: 0x0
|
#define mmMCIF_CONTROL 0x034a
|
#define mmMCIF_CONTROL_BASE_IDX 2
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#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b
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#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2
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#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e
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#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f
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#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2
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#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350
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#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2
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// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xd48
|
#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0352
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#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0353
|
#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x0354
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#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON5_PERFMON_CNTL 0x0355
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#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON5_PERFMON_CNTL2 0x0356
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#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0357
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#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0358
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#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON5_PERFMON_HI 0x0359
|
#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON5_PERFMON_LOW 0x035a
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#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream0_dispdec
|
// base address: 0x0
|
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e
|
#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f
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#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream1_dispdec
|
// base address: 0x8
|
#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360
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#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361
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#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream2_dispdec
|
// base address: 0x10
|
#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362
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#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363
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#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0stream3_dispdec
|
// base address: 0x18
|
#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364
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#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365
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#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream4_dispdec
|
// base address: 0x20
|
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366
|
#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2
|
#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367
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#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream5_dispdec
|
// base address: 0x28
|
#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368
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#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369
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#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream6_dispdec
|
// base address: 0x30
|
#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a
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#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b
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#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0stream7_dispdec
|
// base address: 0x38
|
#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c
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#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d
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#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_az_misc_dispdec
|
// base address: 0x0
|
#define mmAZ_CLOCK_CNTL 0x0372
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#define mmAZ_CLOCK_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec
|
// base address: 0xde8
|
#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x037a
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#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x037b
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#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x037c
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#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_CNTL 0x037d
|
#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_CNTL2 0x037e
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#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x037f
|
#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0380
|
#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_HI 0x0381
|
#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON6_PERFMON_LOW 0x0382
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#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint0_dispdec
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// base address: 0x0
|
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386
|
#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387
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#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint1_dispdec
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// base address: 0x18
|
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c
|
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d
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#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint2_dispdec
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// base address: 0x30
|
#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392
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#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393
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#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0endpoint3_dispdec
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// base address: 0x48
|
#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398
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#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399
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#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint4_dispdec
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// base address: 0x60
|
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e
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#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f
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#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint5_dispdec
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// base address: 0x78
|
#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4
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#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5
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#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0endpoint6_dispdec
|
// base address: 0x90
|
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa
|
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab
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#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0endpoint7_dispdec
|
// base address: 0xa8
|
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0
|
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1
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#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0controller_dispdec
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// base address: 0x0
|
#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2
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#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2
|
#define mmAZALIA_AUDIO_DTO 0x03c3
|
#define mmAZALIA_AUDIO_DTO_BASE_IDX 2
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#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4
|
#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2
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#define mmAZALIA_SOCCLK_CONTROL 0x03c5
|
#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2
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#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6
|
#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2
|
#define mmAZALIA_DATA_DMA_CONTROL 0x03c7
|
#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2
|
#define mmAZALIA_BDL_DMA_CONTROL 0x03c8
|
#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2
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#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9
|
#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2
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#define mmAZALIA_CORB_DMA_CONTROL 0x03ca
|
#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2
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#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1
|
#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2
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#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2
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#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2
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#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3
|
#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2
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#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4
|
#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
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#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5
|
#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2
|
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6
|
#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9
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#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da
|
#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db
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#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc
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#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd
|
#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de
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#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df
|
#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0
|
#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2
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#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1
|
#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2
|
#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2
|
#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2
|
#define mmAZALIA_CRC0_CONTROL0 0x03e3
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#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2
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#define mmAZALIA_CRC0_CONTROL1 0x03e4
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#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2
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#define mmAZALIA_CRC0_CONTROL2 0x03e5
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#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2
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#define mmAZALIA_CRC0_CONTROL3 0x03e6
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#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2
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#define mmAZALIA_CRC0_RESULT 0x03e7
|
#define mmAZALIA_CRC0_RESULT_BASE_IDX 2
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#define mmAZALIA_CRC1_CONTROL0 0x03e8
|
#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2
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#define mmAZALIA_CRC1_CONTROL1 0x03e9
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#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2
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#define mmAZALIA_CRC1_CONTROL2 0x03ea
|
#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2
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#define mmAZALIA_CRC1_CONTROL3 0x03eb
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#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2
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#define mmAZALIA_CRC1_RESULT 0x03ec
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#define mmAZALIA_CRC1_RESULT_BASE_IDX 2
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#define mmAZALIA_MEM_PWR_CTRL 0x03ee
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#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2
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#define mmAZALIA_MEM_PWR_STATUS 0x03ef
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#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0root_dispdec
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// base address: 0x0
|
#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406
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#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407
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#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408
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#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409
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#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d
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#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411
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#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2
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#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412
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#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
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#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413
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#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415
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#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416
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#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417
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#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418
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#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419
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#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a
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#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2
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#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b
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#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2
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#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c
|
#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2
|
#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d
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#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2
|
|
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// addressBlock: dce_dc_hda_azf0stream8_dispdec
|
// base address: 0x320
|
#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426
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#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427
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#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0stream9_dispdec
|
// base address: 0x328
|
#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428
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#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429
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#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2
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|
|
// addressBlock: dce_dc_hda_azf0stream10_dispdec
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// base address: 0x330
|
#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a
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#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b
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#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0stream11_dispdec
|
// base address: 0x338
|
#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c
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#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d
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#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2
|
|
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// addressBlock: dce_dc_hda_azf0stream12_dispdec
|
// base address: 0x340
|
#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e
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#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f
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#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0stream13_dispdec
|
// base address: 0x348
|
#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430
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#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431
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#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0stream14_dispdec
|
// base address: 0x350
|
#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432
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#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433
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#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0stream15_dispdec
|
// base address: 0x358
|
#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434
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#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2
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#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435
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#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec
|
// base address: 0x0
|
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a
|
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b
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#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec
|
// base address: 0x10
|
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e
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#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f
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#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec
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// base address: 0x20
|
#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442
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#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
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#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443
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#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec
|
// base address: 0x30
|
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446
|
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447
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#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec
|
// base address: 0x40
|
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a
|
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b
|
#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec
|
// base address: 0x50
|
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e
|
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f
|
#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
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|
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// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec
|
// base address: 0x60
|
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452
|
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453
|
#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
|
|
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// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec
|
// base address: 0x70
|
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456
|
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2
|
#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457
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#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2
|
|
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// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec
|
// base address: 0x0
|
#define mmDCHUBBUB_SDPIF_CFG0 0x048f
|
#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2
|
#define mmDCHUBBUB_SDPIF_CFG1 0x0490
|
#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2
|
#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491
|
#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2
|
#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492
|
#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2
|
#define mmDCHUBBUB_SDPIF_FB_BASE 0x0493
|
#define mmDCHUBBUB_SDPIF_FB_BASE_BASE_IDX 2
|
#define mmDCHUBBUB_SDPIF_FB_TOP 0x0494
|
#define mmDCHUBBUB_SDPIF_FB_TOP_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_FB_OFFSET 0x0495
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#define mmDCHUBBUB_SDPIF_FB_OFFSET_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_AGP_BOT 0x0496
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#define mmDCHUBBUB_SDPIF_AGP_BOT_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_AGP_TOP 0x0497
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#define mmDCHUBBUB_SDPIF_AGP_TOP_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_AGP_BASE 0x0498
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#define mmDCHUBBUB_SDPIF_AGP_BASE_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_APER_BASE 0x0499
|
#define mmDCHUBBUB_SDPIF_APER_BASE_BASE_IDX 2
|
#define mmDCHUBBUB_SDPIF_APER_TOP 0x049a
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#define mmDCHUBBUB_SDPIF_APER_TOP_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_APER_DEF_0 0x049b
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#define mmDCHUBBUB_SDPIF_APER_DEF_0_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_APER_DEF_1 0x049c
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#define mmDCHUBBUB_SDPIF_APER_DEF_1_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d
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#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1 0x049e
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#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W 0x049f
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#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0 0x04a0
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#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0 0x04a1
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#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0 0x04a2
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0 0x04a3
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0 0x04a4
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0 0x04a5
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1 0x04a6
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#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1 0x04a7
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#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1 0x04a8
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1 0x04a9
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1 0x04aa
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1 0x04ab
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2 0x04ac
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#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2 0x04ad
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#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2 0x04ae
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2 0x04af
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2 0x04b0
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2 0x04b1
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3 0x04b2
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#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3 0x04b3
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#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3 0x04b4
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3 0x04b5
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#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3 0x04b6
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3 0x04b7
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#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x04b8
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#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04b9
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#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04ba
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#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec
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// base address: 0x0
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf
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#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0
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#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1
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#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3
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#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4
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#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5
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#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6
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#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7
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#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8
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#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9
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#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da
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#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db
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#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc
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#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd
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#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de
|
#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df
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#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04e0
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#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04e1
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#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDCHUBBUB_CRC_CTRL 0x04e2
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#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2
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#define mmDCHUBBUB_CRC0_VAL_R_G 0x04e3
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#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2
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#define mmDCHUBBUB_CRC0_VAL_B_A 0x04e4
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#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2
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#define mmDCHUBBUB_CRC1_VAL_R_G 0x04e5
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#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2
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#define mmDCHUBBUB_CRC1_VAL_B_A 0x04e6
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#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2
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// addressBlock: dce_dc_dchubbub_hubbub_dispdec
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// base address: 0x0
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#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505
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#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2
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#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506
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#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2
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#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507
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#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2
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#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508
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#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2
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#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0x050a
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#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2
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#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0x050f
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#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2
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#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0x0514
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#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518
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#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2
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#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0x0519
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#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a
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#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b
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#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c
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#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2
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#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d
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#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2
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#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e
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#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2
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#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f
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#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2
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#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520
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#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2
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#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521
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#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2
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#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522
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#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2
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#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523
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#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2
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#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524
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#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2
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#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525
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#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2
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#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526
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#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2
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#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527
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#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2
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#define mmVTG0_CONTROL 0x0528
|
#define mmVTG0_CONTROL_BASE_IDX 2
|
#define mmVTG1_CONTROL 0x0529
|
#define mmVTG1_CONTROL_BASE_IDX 2
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#define mmVTG2_CONTROL 0x052a
|
#define mmVTG2_CONTROL_BASE_IDX 2
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#define mmVTG3_CONTROL 0x052b
|
#define mmVTG3_CONTROL_BASE_IDX 2
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#define mmVTG4_CONTROL 0x052c
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#define mmVTG4_CONTROL_BASE_IDX 2
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#define mmVTG5_CONTROL 0x052d
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#define mmVTG5_CONTROL_BASE_IDX 2
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#define mmDCHUBBUB_SOFT_RESET 0x052e
|
#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2
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#define mmDCHUBBUB_CLOCK_CNTL 0x052f
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#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2
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#define mmDCFCLK_CNTL 0x0530
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#define mmDCFCLK_CNTL_BASE_IDX 2
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#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531
|
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2
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#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532
|
#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2
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#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533
|
#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2
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#define mmDCHUBBUB_SPARE 0x0534
|
#define mmDCHUBBUB_SPARE_BASE_IDX 2
|
#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053a
|
#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2
|
#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053b
|
#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x1534
|
#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x054d
|
#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x054e
|
#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x054f
|
#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFMON_CNTL 0x0550
|
#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFMON_CNTL2 0x0551
|
#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0552
|
#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0553
|
#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFMON_HI 0x0554
|
#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON7_PERFMON_LOW 0x0555
|
#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec
|
// base address: 0x0
|
#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x0559
|
#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2
|
#define mmHUBP0_DCSURF_ADDR_CONFIG 0x055a
|
#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2
|
#define mmHUBP0_DCSURF_TILING_CONFIG 0x055b
|
#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x055c
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x055e
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x055f
|
#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x0560
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x0561
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x0562
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0563
|
#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
|
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x0564
|
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
|
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x0565
|
#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
|
#define mmHUBP0_DCHUBP_CNTL 0x0566
|
#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2
|
#define mmHUBP0_HUBP_CLK_CNTL 0x0567
|
#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2
|
#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x0568
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#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2
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#define mmHUBP0_HUBPREQ_DEBUG_DB 0x0569
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#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define mmHUBP0_HUBPREQ_DEBUG 0x056a
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#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2
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#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x056e
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#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
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#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x056f
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#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec
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// base address: 0x0
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#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x057b
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#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x057c
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#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x057d
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#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x057e
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#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x057f
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#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0580
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#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0581
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#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0582
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#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0583
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#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0584
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#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0585
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#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0586
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#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0587
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#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0588
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#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0589
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#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x058a
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#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x058b
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#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x058c
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#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x058d
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#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x058e
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#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x058f
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#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL 0x0590
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#define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME 0x0591
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#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0592
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#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0593
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#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0594
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#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0595
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#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0596
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#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0597
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#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0598
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#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0599
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#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x059a
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#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x059b
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#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2
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#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x059c
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#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2
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#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x059d
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#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
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#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x059e
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#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x059f
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#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x05a0
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#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x05a1
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#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x05a2
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#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x05a3
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#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x05a4
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#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x05a5
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#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x05a6
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#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x05a7
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#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x05a8
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#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x05a9
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#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x05aa
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x05ab
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x05ac
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x05ad
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x05ae
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x05af
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x05b0
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x05b1
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS 0x05b2
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x05b3
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL 0x05b4
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#define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2
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#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x05b5
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#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
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#define mmHUBPREQ0_BLANK_OFFSET_0 0x05b6
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#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2
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#define mmHUBPREQ0_BLANK_OFFSET_1 0x05b7
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#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2
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#define mmHUBPREQ0_DST_DIMENSIONS 0x05b8
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#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2
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#define mmHUBPREQ0_DST_AFTER_SCALER 0x05b9
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#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2
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#define mmHUBPREQ0_PREFETCH_SETTINS 0x05ba
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#define mmHUBPREQ0_PREFETCH_SETTINS_BASE_IDX 2
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#define mmHUBPREQ0_PREFETCH_SETTINS_C 0x05bb
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#define mmHUBPREQ0_PREFETCH_SETTINS_C_BASE_IDX 2
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#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x05bc
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#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x05bd
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#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x05be
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#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x05bf
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#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x05c0
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#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ0_NOM_PARAMETERS_0 0x05c1
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#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ0_NOM_PARAMETERS_1 0x05c2
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#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ0_NOM_PARAMETERS_2 0x05c3
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#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ0_NOM_PARAMETERS_3 0x05c4
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#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ0_NOM_PARAMETERS_4 0x05c5
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#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ0_NOM_PARAMETERS_5 0x05c6
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#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ0_NOM_PARAMETERS_6 0x05c7
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#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ0_NOM_PARAMETERS_7 0x05c8
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#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2
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#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x05c9
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#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2
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#define mmHUBPREQ0_PER_LINE_DELIVERY 0x05ca
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#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2
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#define mmHUBPREQ0_CURSOR_SETTINS 0x05cb
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#define mmHUBPREQ0_CURSOR_SETTINS_BASE_IDX 2
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#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x05cc
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#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
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#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x05cd
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#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x05ce
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#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec
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// base address: 0x0
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#define mmHUBPRET0_HUBPRET_CONTROL 0x05e0
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#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2
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#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x05e1
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#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x05e2
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#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x05e3
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#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
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#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x05e4
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#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
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#define mmHUBPRET0_HUBPRET_READ_LINE0 0x05e5
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#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2
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#define mmHUBPRET0_HUBPRET_READ_LINE1 0x05e6
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#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2
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#define mmHUBPRET0_HUBPRET_INTERRUPT 0x05e7
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#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2
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#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x05e8
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#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
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#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x05e9
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#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec
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// base address: 0x0
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#define mmCURSOR0_CURSOR_CONTROL 0x05ec
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#define mmCURSOR0_CURSOR_CONTROL_BASE_IDX 2
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#define mmCURSOR0_CURSOR_SURFACE_ADDRESS 0x05ed
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#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH 0x05ee
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#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR0_CURSOR_SIZE 0x05ef
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#define mmCURSOR0_CURSOR_SIZE_BASE_IDX 2
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#define mmCURSOR0_CURSOR_POSITION 0x05f0
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#define mmCURSOR0_CURSOR_POSITION_BASE_IDX 2
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#define mmCURSOR0_CURSOR_HOT_SPOT 0x05f1
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#define mmCURSOR0_CURSOR_HOT_SPOT_BASE_IDX 2
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#define mmCURSOR0_CURSOR_STEREO_CONTROL 0x05f2
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#define mmCURSOR0_CURSOR_STEREO_CONTROL_BASE_IDX 2
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#define mmCURSOR0_CURSOR_DST_OFFSET 0x05f3
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#define mmCURSOR0_CURSOR_DST_OFFSET_BASE_IDX 2
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#define mmCURSOR0_CURSOR_MEM_PWR_CTRL 0x05f4
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#define mmCURSOR0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCURSOR0_CURSOR_MEM_PWR_STATUS 0x05f5
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#define mmCURSOR0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x1844
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#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0611
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#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x0612
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#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x0613
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#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_CNTL 0x0614
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#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_CNTL2 0x0615
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#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x0616
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#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x0617
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#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_HI 0x0618
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#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON8_PERFMON_LOW 0x0619
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#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec
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// base address: 0x310
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#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x061d
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#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2
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#define mmHUBP1_DCSURF_ADDR_CONFIG 0x061e
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#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2
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#define mmHUBP1_DCSURF_TILING_CONFIG 0x061f
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#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x0620
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x0621
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x0622
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0623
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#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x0624
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x0625
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x0626
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0627
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#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x0628
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#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
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#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x0629
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#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
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#define mmHUBP1_DCHUBP_CNTL 0x062a
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#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2
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#define mmHUBP1_HUBP_CLK_CNTL 0x062b
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#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2
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#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x062c
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#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2
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#define mmHUBP1_HUBPREQ_DEBUG_DB 0x062d
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#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define mmHUBP1_HUBPREQ_DEBUG 0x062e
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#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2
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#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0632
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#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
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#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0633
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#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec
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// base address: 0x310
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#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x063f
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#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x0640
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#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0641
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0642
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0643
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0644
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#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0645
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0646
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0647
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0648
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#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0649
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x064a
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x064b
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x064c
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#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x064d
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x064e
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x064f
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0650
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#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x0651
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#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x0652
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#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x0653
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#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL 0x0654
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#define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME 0x0655
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#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x0656
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#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x0657
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x0658
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x0659
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x065a
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#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x065b
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x065c
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x065d
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x065e
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#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x065f
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#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2
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#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0660
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#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2
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#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0661
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#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
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#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0662
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#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0663
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#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0664
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#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x0665
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#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x0666
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#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0667
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#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x0668
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x0669
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x066a
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x066b
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x066c
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x066d
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#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x066e
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x066f
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0670
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0671
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0672
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0673
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0674
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0675
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS 0x0676
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x0677
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL 0x0678
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#define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2
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#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0679
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#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
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#define mmHUBPREQ1_BLANK_OFFSET_0 0x067a
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#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2
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#define mmHUBPREQ1_BLANK_OFFSET_1 0x067b
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#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2
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#define mmHUBPREQ1_DST_DIMENSIONS 0x067c
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#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2
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#define mmHUBPREQ1_DST_AFTER_SCALER 0x067d
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#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2
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#define mmHUBPREQ1_PREFETCH_SETTINS 0x067e
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#define mmHUBPREQ1_PREFETCH_SETTINS_BASE_IDX 2
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#define mmHUBPREQ1_PREFETCH_SETTINS_C 0x067f
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#define mmHUBPREQ1_PREFETCH_SETTINS_C_BASE_IDX 2
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#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0680
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#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0681
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#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0682
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#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0683
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#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x0684
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#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_0 0x0685
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#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_1 0x0686
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#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0687
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#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0688
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#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0689
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#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_5 0x068a
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#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_6 0x068b
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#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ1_NOM_PARAMETERS_7 0x068c
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#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2
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#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x068d
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#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2
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#define mmHUBPREQ1_PER_LINE_DELIVERY 0x068e
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#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2
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#define mmHUBPREQ1_CURSOR_SETTINS 0x068f
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#define mmHUBPREQ1_CURSOR_SETTINS_BASE_IDX 2
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#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0690
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#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
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#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x0691
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#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x0692
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#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec
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// base address: 0x310
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#define mmHUBPRET1_HUBPRET_CONTROL 0x06a4
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#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x06a5
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#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x06a6
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#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x06a7
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#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x06a8
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#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_READ_LINE0 0x06a9
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#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_READ_LINE1 0x06aa
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#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_INTERRUPT 0x06ab
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#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x06ac
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#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
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#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x06ad
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#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec
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// base address: 0x310
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#define mmCURSOR1_CURSOR_CONTROL 0x06b0
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#define mmCURSOR1_CURSOR_CONTROL_BASE_IDX 2
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#define mmCURSOR1_CURSOR_SURFACE_ADDRESS 0x06b1
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#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH 0x06b2
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#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR1_CURSOR_SIZE 0x06b3
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#define mmCURSOR1_CURSOR_SIZE_BASE_IDX 2
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#define mmCURSOR1_CURSOR_POSITION 0x06b4
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#define mmCURSOR1_CURSOR_POSITION_BASE_IDX 2
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#define mmCURSOR1_CURSOR_HOT_SPOT 0x06b5
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#define mmCURSOR1_CURSOR_HOT_SPOT_BASE_IDX 2
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#define mmCURSOR1_CURSOR_STEREO_CONTROL 0x06b6
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#define mmCURSOR1_CURSOR_STEREO_CONTROL_BASE_IDX 2
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#define mmCURSOR1_CURSOR_DST_OFFSET 0x06b7
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#define mmCURSOR1_CURSOR_DST_OFFSET_BASE_IDX 2
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#define mmCURSOR1_CURSOR_MEM_PWR_CTRL 0x06b8
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#define mmCURSOR1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCURSOR1_CURSOR_MEM_PWR_STATUS 0x06b9
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#define mmCURSOR1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x1b54
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#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x06d5
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#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x06d6
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#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x06d7
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#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_CNTL 0x06d8
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#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_CNTL2 0x06d9
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#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x06da
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#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x06db
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#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_HI 0x06dc
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#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON9_PERFMON_LOW 0x06dd
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#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec
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// base address: 0x620
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#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x06e1
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#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2
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#define mmHUBP2_DCSURF_ADDR_CONFIG 0x06e2
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#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2
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#define mmHUBP2_DCSURF_TILING_CONFIG 0x06e3
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#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x06e4
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x06e5
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x06e6
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06e7
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#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x06e8
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x06e9
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x06ea
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06eb
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#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x06ec
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#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
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#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x06ed
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#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
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#define mmHUBP2_DCHUBP_CNTL 0x06ee
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#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2
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#define mmHUBP2_HUBP_CLK_CNTL 0x06ef
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#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2
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#define mmHUBP2_DCHUBP_VMPG_CONFIG 0x06f0
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#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2
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#define mmHUBP2_HUBPREQ_DEBUG_DB 0x06f1
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#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define mmHUBP2_HUBPREQ_DEBUG 0x06f2
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#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2
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#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06f6
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#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
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#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06f7
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#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec
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// base address: 0x620
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#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x0703
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#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x0704
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#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0705
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0706
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0707
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0708
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#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0709
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x070a
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x070b
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x070c
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#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x070d
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x070e
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x070f
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0710
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#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0711
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0712
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0713
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0714
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#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x0715
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#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x0716
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#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x0717
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#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL 0x0718
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#define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME 0x0719
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#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x071a
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#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x071b
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x071c
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x071d
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x071e
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#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x071f
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0720
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0721
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0722
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#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x0723
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#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2
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#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x0724
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#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2
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#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x0725
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#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
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#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x0726
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#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x0727
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#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x0728
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#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x0729
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#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x072a
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#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x072b
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#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x072c
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x072d
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x072e
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x072f
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0730
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0731
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#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x0732
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x0733
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0734
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0735
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0736
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0737
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0738
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0739
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS 0x073a
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x073b
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL 0x073c
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#define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2
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#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x073d
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#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
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#define mmHUBPREQ2_BLANK_OFFSET_0 0x073e
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#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2
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#define mmHUBPREQ2_BLANK_OFFSET_1 0x073f
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#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2
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#define mmHUBPREQ2_DST_DIMENSIONS 0x0740
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#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2
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#define mmHUBPREQ2_DST_AFTER_SCALER 0x0741
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#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2
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#define mmHUBPREQ2_PREFETCH_SETTINS 0x0742
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#define mmHUBPREQ2_PREFETCH_SETTINS_BASE_IDX 2
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#define mmHUBPREQ2_PREFETCH_SETTINS_C 0x0743
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#define mmHUBPREQ2_PREFETCH_SETTINS_C_BASE_IDX 2
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#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0744
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#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0745
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#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0746
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#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0747
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#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0748
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#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_0 0x0749
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#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_1 0x074a
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#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_2 0x074b
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#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_3 0x074c
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#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_4 0x074d
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#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_5 0x074e
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#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_6 0x074f
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#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0750
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#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2
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#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0751
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#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2
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#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0752
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#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2
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#define mmHUBPREQ2_CURSOR_SETTINS 0x0753
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#define mmHUBPREQ2_CURSOR_SETTINS_BASE_IDX 2
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#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0754
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#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
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#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0755
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#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0756
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#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec
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// base address: 0x620
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#define mmHUBPRET2_HUBPRET_CONTROL 0x0768
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#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0769
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#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x076a
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#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x076b
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#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x076c
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#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_READ_LINE0 0x076d
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#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_READ_LINE1 0x076e
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#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_INTERRUPT 0x076f
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#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x0770
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#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
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#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x0771
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#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec
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// base address: 0x620
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#define mmCURSOR2_CURSOR_CONTROL 0x0774
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#define mmCURSOR2_CURSOR_CONTROL_BASE_IDX 2
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#define mmCURSOR2_CURSOR_SURFACE_ADDRESS 0x0775
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#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH 0x0776
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#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR2_CURSOR_SIZE 0x0777
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#define mmCURSOR2_CURSOR_SIZE_BASE_IDX 2
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#define mmCURSOR2_CURSOR_POSITION 0x0778
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#define mmCURSOR2_CURSOR_POSITION_BASE_IDX 2
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#define mmCURSOR2_CURSOR_HOT_SPOT 0x0779
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#define mmCURSOR2_CURSOR_HOT_SPOT_BASE_IDX 2
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#define mmCURSOR2_CURSOR_STEREO_CONTROL 0x077a
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#define mmCURSOR2_CURSOR_STEREO_CONTROL_BASE_IDX 2
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#define mmCURSOR2_CURSOR_DST_OFFSET 0x077b
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#define mmCURSOR2_CURSOR_DST_OFFSET_BASE_IDX 2
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#define mmCURSOR2_CURSOR_MEM_PWR_CTRL 0x077c
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#define mmCURSOR2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCURSOR2_CURSOR_MEM_PWR_STATUS 0x077d
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#define mmCURSOR2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x1e64
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#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0799
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#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x079a
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#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x079b
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#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_CNTL 0x079c
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#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_CNTL2 0x079d
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#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x079e
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#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x079f
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#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_HI 0x07a0
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#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON10_PERFMON_LOW 0x07a1
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#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec
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// base address: 0x930
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#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x07a5
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#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2
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#define mmHUBP3_DCSURF_ADDR_CONFIG 0x07a6
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#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2
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#define mmHUBP3_DCSURF_TILING_CONFIG 0x07a7
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#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x07a8
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a9
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x07aa
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07ab
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#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x07ac
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x07ad
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x07ae
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07af
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#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2
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#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x07b0
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#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2
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#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x07b1
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#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2
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#define mmHUBP3_DCHUBP_CNTL 0x07b2
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#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2
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#define mmHUBP3_HUBP_CLK_CNTL 0x07b3
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#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2
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#define mmHUBP3_DCHUBP_VMPG_CONFIG 0x07b4
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#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2
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#define mmHUBP3_HUBPREQ_DEBUG_DB 0x07b5
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#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2
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#define mmHUBP3_HUBPREQ_DEBUG 0x07b6
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#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2
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#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07ba
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#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2
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#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07bb
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#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec
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// base address: 0x930
|
#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x07c7
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#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x07c8
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#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c9
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07ca
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07cb
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07cc
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#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07cd
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07ce
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07cf
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07d0
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#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07d1
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07d2
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07d3
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07d4
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#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07d5
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07d6
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d7
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d8
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#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x07d9
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#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x07da
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#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x07db
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#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL 0x07dc
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#define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME 0x07dd
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#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x07de
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#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x07df
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x07e0
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x07e1
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x07e2
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#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x07e3
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07e4
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07e5
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e6
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#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2
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#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x07e7
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#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2
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#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x07e8
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#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2
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#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x07e9
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#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2
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#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x07ea
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#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x07eb
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#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x07ec
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#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x07ed
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#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x07ee
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#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2
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#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x07ef
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#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x07f0
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x07f1
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x07f2
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x07f3
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x07f4
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x07f5
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#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x07f6
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x07f7
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x07f8
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x07f9
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x07fa
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x07fb
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x07fc
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x07fd
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS 0x07fe
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x07ff
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL 0x0800
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#define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2
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#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x0801
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#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2
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#define mmHUBPREQ3_BLANK_OFFSET_0 0x0802
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#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2
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#define mmHUBPREQ3_BLANK_OFFSET_1 0x0803
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#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2
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#define mmHUBPREQ3_DST_DIMENSIONS 0x0804
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#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2
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#define mmHUBPREQ3_DST_AFTER_SCALER 0x0805
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#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2
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#define mmHUBPREQ3_PREFETCH_SETTINS 0x0806
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#define mmHUBPREQ3_PREFETCH_SETTINS_BASE_IDX 2
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#define mmHUBPREQ3_PREFETCH_SETTINS_C 0x0807
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#define mmHUBPREQ3_PREFETCH_SETTINS_C_BASE_IDX 2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x0808
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#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x0809
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#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x080a
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#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x080b
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#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x080c
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#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_0 0x080d
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#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_1 0x080e
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#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_2 0x080f
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#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_3 0x0810
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#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_4 0x0811
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#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_5 0x0812
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#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_6 0x0813
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#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2
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#define mmHUBPREQ3_NOM_PARAMETERS_7 0x0814
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#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2
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#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x0815
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#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2
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#define mmHUBPREQ3_PER_LINE_DELIVERY 0x0816
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#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2
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#define mmHUBPREQ3_CURSOR_SETTINS 0x0817
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#define mmHUBPREQ3_CURSOR_SETTINS_BASE_IDX 2
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#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x0818
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#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2
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#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x0819
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#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x081a
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#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec
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// base address: 0x930
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#define mmHUBPRET3_HUBPRET_CONTROL 0x082c
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#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x082d
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#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x082e
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#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x082f
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#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0830
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#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0831
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#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0832
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#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0833
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#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0834
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#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2
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#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0835
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#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec
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// base address: 0x930
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#define mmCURSOR3_CURSOR_CONTROL 0x0838
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#define mmCURSOR3_CURSOR_CONTROL_BASE_IDX 2
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#define mmCURSOR3_CURSOR_SURFACE_ADDRESS 0x0839
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#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2
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#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH 0x083a
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#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2
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#define mmCURSOR3_CURSOR_SIZE 0x083b
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#define mmCURSOR3_CURSOR_SIZE_BASE_IDX 2
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#define mmCURSOR3_CURSOR_POSITION 0x083c
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#define mmCURSOR3_CURSOR_POSITION_BASE_IDX 2
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#define mmCURSOR3_CURSOR_HOT_SPOT 0x083d
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#define mmCURSOR3_CURSOR_HOT_SPOT_BASE_IDX 2
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#define mmCURSOR3_CURSOR_STEREO_CONTROL 0x083e
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#define mmCURSOR3_CURSOR_STEREO_CONTROL_BASE_IDX 2
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#define mmCURSOR3_CURSOR_DST_OFFSET 0x083f
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#define mmCURSOR3_CURSOR_DST_OFFSET_BASE_IDX 2
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#define mmCURSOR3_CURSOR_MEM_PWR_CTRL 0x0840
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#define mmCURSOR3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCURSOR3_CURSOR_MEM_PWR_STATUS 0x0841
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#define mmCURSOR3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x2174
|
#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x085d
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#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x085e
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#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x085f
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#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_CNTL 0x0860
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#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_CNTL2 0x0861
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#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0862
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#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0863
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#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_HI 0x0864
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#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON11_PERFMON_LOW 0x0865
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#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
|
// base address: 0x0
|
#define mmDPP_TOP0_DPP_CONTROL 0x0c3d
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#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2
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#define mmDPP_TOP0_DPP_SOFT_RESET 0x0c3e
|
#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2
|
#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0c3f
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#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2
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#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0c40
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#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2
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#define mmDPP_TOP0_DPP_CRC_CTRL 0x0c41
|
#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2
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#define mmDPP_TOP0_HOST_READ_CONTROL 0x0c42
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#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec
|
// base address: 0x0
|
#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0c47
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#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
|
#define mmCNVC_CFG0_FORMAT_CONTROL 0x0c48
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#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS 0x0c49
|
#define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS_BASE_IDX 2
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#define mmCNVC_CFG0_DENORM_CONTROL 0x0c4a
|
#define mmCNVC_CFG0_DENORM_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0c4c
|
#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2
|
#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0c4d
|
#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2
|
#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0c4e
|
#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2
|
#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0c4f
|
#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2
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#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0c50
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#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2
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|
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// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec
|
// base address: 0x0
|
#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0c58
|
#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2
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#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0c59
|
#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2
|
#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0c5a
|
#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2
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#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0c5b
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#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
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|
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// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec
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// base address: 0x0
|
#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0c62
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#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
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#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0c63
|
#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmDSCL0_SCL_MODE 0x0c64
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#define mmDSCL0_SCL_MODE_BASE_IDX 2
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#define mmDSCL0_SCL_TAP_CONTROL 0x0c65
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#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmDSCL0_DSCL_CONTROL 0x0c66
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#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2
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#define mmDSCL0_DSCL_2TAP_CONTROL 0x0c67
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#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2
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#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0c68
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#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0c69
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#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0c6a
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#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0c6b
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#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0c6c
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#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0c6d
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#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0c6e
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#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0c6f
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#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0c70
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#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0c71
|
#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0c72
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#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
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#define mmDSCL0_SCL_BLACK_OFFSET 0x0c73
|
#define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2
|
#define mmDSCL0_DSCL_UPDATE 0x0c74
|
#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2
|
#define mmDSCL0_DSCL_AUTOCAL 0x0c75
|
#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2
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#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0c76
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#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0c77
|
#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmDSCL0_OTG_H_BLANK 0x0c78
|
#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2
|
#define mmDSCL0_OTG_V_BLANK 0x0c79
|
#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2
|
#define mmDSCL0_RECOUT_START 0x0c7a
|
#define mmDSCL0_RECOUT_START_BASE_IDX 2
|
#define mmDSCL0_RECOUT_SIZE 0x0c7b
|
#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2
|
#define mmDSCL0_MPC_SIZE 0x0c7c
|
#define mmDSCL0_MPC_SIZE_BASE_IDX 2
|
#define mmDSCL0_LB_DATA_FORMAT 0x0c7d
|
#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2
|
#define mmDSCL0_LB_MEMORY_CTRL 0x0c7e
|
#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2
|
#define mmDSCL0_LB_V_COUNTER 0x0c7f
|
#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2
|
#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0c80
|
#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0c81
|
#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDSCL0_OBUF_CONTROL 0x0c82
|
#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2
|
#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0c83
|
#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec
|
// base address: 0x0
|
#define mmCM0_CM_CONTROL 0x0c92
|
#define mmCM0_CM_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_COMA_C11_C12 0x0c93
|
#define mmCM0_CM_COMA_C11_C12_BASE_IDX 2
|
#define mmCM0_CM_COMA_C13_C14 0x0c94
|
#define mmCM0_CM_COMA_C13_C14_BASE_IDX 2
|
#define mmCM0_CM_COMA_C21_C22 0x0c95
|
#define mmCM0_CM_COMA_C21_C22_BASE_IDX 2
|
#define mmCM0_CM_COMA_C23_C24 0x0c96
|
#define mmCM0_CM_COMA_C23_C24_BASE_IDX 2
|
#define mmCM0_CM_COMA_C31_C32 0x0c97
|
#define mmCM0_CM_COMA_C31_C32_BASE_IDX 2
|
#define mmCM0_CM_COMA_C33_C34 0x0c98
|
#define mmCM0_CM_COMA_C33_C34_BASE_IDX 2
|
#define mmCM0_CM_COMB_C11_C12 0x0c99
|
#define mmCM0_CM_COMB_C11_C12_BASE_IDX 2
|
#define mmCM0_CM_COMB_C13_C14 0x0c9a
|
#define mmCM0_CM_COMB_C13_C14_BASE_IDX 2
|
#define mmCM0_CM_COMB_C21_C22 0x0c9b
|
#define mmCM0_CM_COMB_C21_C22_BASE_IDX 2
|
#define mmCM0_CM_COMB_C23_C24 0x0c9c
|
#define mmCM0_CM_COMB_C23_C24_BASE_IDX 2
|
#define mmCM0_CM_COMB_C31_C32 0x0c9d
|
#define mmCM0_CM_COMB_C31_C32_BASE_IDX 2
|
#define mmCM0_CM_COMB_C33_C34 0x0c9e
|
#define mmCM0_CM_COMB_C33_C34_BASE_IDX 2
|
#define mmCM0_CM_IGAM_CONTROL 0x0c9f
|
#define mmCM0_CM_IGAM_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_IGAM_LUT_RW_CONTROL 0x0ca0
|
#define mmCM0_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_IGAM_LUT_RW_INDEX 0x0ca1
|
#define mmCM0_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2
|
#define mmCM0_CM_IGAM_LUT_SEQ_COLOR 0x0ca2
|
#define mmCM0_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2
|
#define mmCM0_CM_IGAM_LUT_30_COLOR 0x0ca3
|
#define mmCM0_CM_IGAM_LUT_30_COLOR_BASE_IDX 2
|
#define mmCM0_CM_IGAM_LUT_PWL_DATA 0x0ca4
|
#define mmCM0_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2
|
#define mmCM0_CM_IGAM_LUT_AUTOFILL 0x0ca5
|
#define mmCM0_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2
|
#define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0ca6
|
#define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2
|
#define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0ca7
|
#define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2
|
#define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED 0x0ca8
|
#define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2
|
#define mmCM0_CM_ICSC_CONTROL 0x0ca9
|
#define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_ICSC_C11_C12 0x0caa
|
#define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2
|
#define mmCM0_CM_ICSC_C13_C14 0x0cab
|
#define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2
|
#define mmCM0_CM_ICSC_C21_C22 0x0cac
|
#define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2
|
#define mmCM0_CM_ICSC_C23_C24 0x0cad
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#define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2
|
#define mmCM0_CM_ICSC_C31_C32 0x0cae
|
#define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2
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#define mmCM0_CM_ICSC_C33_C34 0x0caf
|
#define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0cb0
|
#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0cb1
|
#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0cb2
|
#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0cb3
|
#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0cb4
|
#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0cb5
|
#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
|
#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0cb6
|
#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
|
#define mmCM0_CM_OCSC_CONTROL 0x0cb7
|
#define mmCM0_CM_OCSC_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_OCSC_C11_C12 0x0cb8
|
#define mmCM0_CM_OCSC_C11_C12_BASE_IDX 2
|
#define mmCM0_CM_OCSC_C13_C14 0x0cb9
|
#define mmCM0_CM_OCSC_C13_C14_BASE_IDX 2
|
#define mmCM0_CM_OCSC_C21_C22 0x0cba
|
#define mmCM0_CM_OCSC_C21_C22_BASE_IDX 2
|
#define mmCM0_CM_OCSC_C23_C24 0x0cbb
|
#define mmCM0_CM_OCSC_C23_C24_BASE_IDX 2
|
#define mmCM0_CM_OCSC_C31_C32 0x0cbc
|
#define mmCM0_CM_OCSC_C31_C32_BASE_IDX 2
|
#define mmCM0_CM_OCSC_C33_C34 0x0cbd
|
#define mmCM0_CM_OCSC_C33_C34_BASE_IDX 2
|
#define mmCM0_CM_BNS_VALUES_R 0x0cbe
|
#define mmCM0_CM_BNS_VALUES_R_BASE_IDX 2
|
#define mmCM0_CM_BNS_VALUES_G 0x0cbf
|
#define mmCM0_CM_BNS_VALUES_G_BASE_IDX 2
|
#define mmCM0_CM_BNS_VALUES_B 0x0cc0
|
#define mmCM0_CM_BNS_VALUES_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_CONTROL 0x0cc1
|
#define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_DGAM_LUT_INDEX 0x0cc2
|
#define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM0_CM_DGAM_LUT_DATA 0x0cc3
|
#define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0cc4
|
#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0cc5
|
#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0cc6
|
#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0cc7
|
#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0cc8
|
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0cc9
|
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0cca
|
#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0ccb
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0ccc
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0ccd
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0cce
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0ccf
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0cd0
|
#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0cd1
|
#define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0cd2
|
#define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0cd3
|
#define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0cd4
|
#define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0cd5
|
#define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0cd6
|
#define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0cd7
|
#define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0cd8
|
#define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0cd9
|
#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0cda
|
#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0cdb
|
#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0cdc
|
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0cdd
|
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0cde
|
#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0cdf
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0ce0
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0ce1
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0ce2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0ce3
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0ce4
|
#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0ce5
|
#define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0ce6
|
#define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0ce7
|
#define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0ce8
|
#define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0ce9
|
#define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0cea
|
#define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0ceb
|
#define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
|
#define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0cec
|
#define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
|
#define mmCM0_CM_RGAM_CONTROL 0x0ced
|
#define mmCM0_CM_RGAM_CONTROL_BASE_IDX 2
|
#define mmCM0_CM_RGAM_LUT_INDEX 0x0cee
|
#define mmCM0_CM_RGAM_LUT_INDEX_BASE_IDX 2
|
#define mmCM0_CM_RGAM_LUT_DATA 0x0cef
|
#define mmCM0_CM_RGAM_LUT_DATA_BASE_IDX 2
|
#define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK 0x0cf0
|
#define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
|
#define mmCM0_CM_RGAM_RAMA_START_CNTL_B 0x0cf1
|
#define mmCM0_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2
|
#define mmCM0_CM_RGAM_RAMA_START_CNTL_G 0x0cf2
|
#define mmCM0_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2
|
#define mmCM0_CM_RGAM_RAMA_START_CNTL_R 0x0cf3
|
#define mmCM0_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0cf4
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#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0cf5
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#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0cf6
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#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_END_CNTL1_B 0x0cf7
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#define mmCM0_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_END_CNTL2_B 0x0cf8
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#define mmCM0_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_END_CNTL1_G 0x0cf9
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#define mmCM0_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_END_CNTL2_G 0x0cfa
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#define mmCM0_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_END_CNTL1_R 0x0cfb
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#define mmCM0_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_END_CNTL2_R 0x0cfc
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#define mmCM0_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_0_1 0x0cfd
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#define mmCM0_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_2_3 0x0cfe
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#define mmCM0_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_4_5 0x0cff
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#define mmCM0_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_6_7 0x0d00
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#define mmCM0_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_8_9 0x0d01
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#define mmCM0_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_10_11 0x0d02
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#define mmCM0_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_12_13 0x0d03
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#define mmCM0_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_14_15 0x0d04
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#define mmCM0_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_16_17 0x0d05
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#define mmCM0_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_18_19 0x0d06
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#define mmCM0_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_20_21 0x0d07
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#define mmCM0_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_22_23 0x0d08
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#define mmCM0_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_24_25 0x0d09
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#define mmCM0_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_26_27 0x0d0a
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#define mmCM0_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_28_29 0x0d0b
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#define mmCM0_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_30_31 0x0d0c
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#define mmCM0_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMA_REGION_32_33 0x0d0d
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#define mmCM0_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_START_CNTL_B 0x0d0e
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#define mmCM0_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_START_CNTL_G 0x0d0f
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#define mmCM0_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_START_CNTL_R 0x0d10
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#define mmCM0_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0d11
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#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0d12
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#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0d13
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#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_END_CNTL1_B 0x0d14
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#define mmCM0_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_END_CNTL2_B 0x0d15
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#define mmCM0_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_END_CNTL1_G 0x0d16
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#define mmCM0_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_END_CNTL2_G 0x0d17
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#define mmCM0_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_END_CNTL1_R 0x0d18
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#define mmCM0_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_END_CNTL2_R 0x0d19
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#define mmCM0_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_0_1 0x0d1a
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#define mmCM0_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_2_3 0x0d1b
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#define mmCM0_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_4_5 0x0d1c
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#define mmCM0_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_6_7 0x0d1d
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#define mmCM0_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_8_9 0x0d1e
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#define mmCM0_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_10_11 0x0d1f
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#define mmCM0_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_12_13 0x0d20
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#define mmCM0_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_14_15 0x0d21
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#define mmCM0_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_16_17 0x0d22
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#define mmCM0_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_18_19 0x0d23
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#define mmCM0_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_20_21 0x0d24
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#define mmCM0_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_22_23 0x0d25
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#define mmCM0_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_24_25 0x0d26
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#define mmCM0_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_26_27 0x0d27
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#define mmCM0_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_28_29 0x0d28
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#define mmCM0_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_30_31 0x0d29
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#define mmCM0_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM0_CM_RGAM_RAMB_REGION_32_33 0x0d2a
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#define mmCM0_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM0_CM_HDR_MULT_COEF 0x0d2b
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#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2
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#define mmCM0_CM_RANGE_CLAMP_CONTROL_R 0x0d2c
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#define mmCM0_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2
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#define mmCM0_CM_RANGE_CLAMP_CONTROL_G 0x0d2d
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#define mmCM0_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2
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#define mmCM0_CM_RANGE_CLAMP_CONTROL_B 0x0d2e
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#define mmCM0_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2
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#define mmCM0_CM_DENORM_CONTROL 0x0d2f
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#define mmCM0_CM_DENORM_CONTROL_BASE_IDX 2
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#define mmCM0_CM_CMOUT_CONTROL 0x0d30
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#define mmCM0_CM_CMOUT_CONTROL_BASE_IDX 2
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#define mmCM0_CM_CMOUT_RANDOM_SEEDS 0x0d31
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#define mmCM0_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2
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#define mmCM0_CM_MEM_PWR_CTRL 0x0d32
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#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCM0_CM_MEM_PWR_STATUS 0x0d33
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#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCM0_CM_TEST_DEBUG_INDEX 0x0d35
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#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2
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#define mmCM0_CM_TEST_DEBUG_DATA 0x0d36
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#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2
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// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x3530
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#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0d4c
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#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0d4d
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#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0d4e
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#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON12_PERFMON_CNTL 0x0d4f
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#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON12_PERFMON_CNTL2 0x0d50
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#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0d51
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#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0d52
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#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON12_PERFMON_HI 0x0d53
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#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON12_PERFMON_LOW 0x0d54
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#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
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// base address: 0x46c
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#define mmDPP_TOP1_DPP_CONTROL 0x0d58
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#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2
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#define mmDPP_TOP1_DPP_SOFT_RESET 0x0d59
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#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2
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#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0d5a
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#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2
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#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0d5b
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#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2
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#define mmDPP_TOP1_DPP_CRC_CTRL 0x0d5c
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#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2
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#define mmDPP_TOP1_HOST_READ_CONTROL 0x0d5d
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#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec
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// base address: 0x46c
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#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0d62
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#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
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#define mmCNVC_CFG1_FORMAT_CONTROL 0x0d63
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#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS 0x0d64
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#define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS_BASE_IDX 2
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#define mmCNVC_CFG1_DENORM_CONTROL 0x0d65
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#define mmCNVC_CFG1_DENORM_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0d67
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#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0d68
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#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2
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#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0d69
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#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2
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#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0d6a
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#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2
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#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0d6b
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#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2
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// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec
|
// base address: 0x46c
|
#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0d73
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#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2
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#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0d74
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#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2
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#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0d75
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#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2
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#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0d76
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#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
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// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec
|
// base address: 0x46c
|
#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0d7d
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#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
|
#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0d7e
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#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmDSCL1_SCL_MODE 0x0d7f
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#define mmDSCL1_SCL_MODE_BASE_IDX 2
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#define mmDSCL1_SCL_TAP_CONTROL 0x0d80
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#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmDSCL1_DSCL_CONTROL 0x0d81
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#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2
|
#define mmDSCL1_DSCL_2TAP_CONTROL 0x0d82
|
#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2
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#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0d83
|
#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0d84
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#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0d85
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#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d86
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#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0d87
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#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0d88
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#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0d89
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#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0d8a
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#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d8b
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#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0d8c
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#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0d8d
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#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
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#define mmDSCL1_SCL_BLACK_OFFSET 0x0d8e
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#define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2
|
#define mmDSCL1_DSCL_UPDATE 0x0d8f
|
#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2
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#define mmDSCL1_DSCL_AUTOCAL 0x0d90
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#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2
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#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d91
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#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d92
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#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmDSCL1_OTG_H_BLANK 0x0d93
|
#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2
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#define mmDSCL1_OTG_V_BLANK 0x0d94
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#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2
|
#define mmDSCL1_RECOUT_START 0x0d95
|
#define mmDSCL1_RECOUT_START_BASE_IDX 2
|
#define mmDSCL1_RECOUT_SIZE 0x0d96
|
#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2
|
#define mmDSCL1_MPC_SIZE 0x0d97
|
#define mmDSCL1_MPC_SIZE_BASE_IDX 2
|
#define mmDSCL1_LB_DATA_FORMAT 0x0d98
|
#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2
|
#define mmDSCL1_LB_MEMORY_CTRL 0x0d99
|
#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2
|
#define mmDSCL1_LB_V_COUNTER 0x0d9a
|
#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2
|
#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0d9b
|
#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0d9c
|
#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDSCL1_OBUF_CONTROL 0x0d9d
|
#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2
|
#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0d9e
|
#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2
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// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec
|
// base address: 0x46c
|
#define mmCM1_CM_CONTROL 0x0dad
|
#define mmCM1_CM_CONTROL_BASE_IDX 2
|
#define mmCM1_CM_COMA_C11_C12 0x0dae
|
#define mmCM1_CM_COMA_C11_C12_BASE_IDX 2
|
#define mmCM1_CM_COMA_C13_C14 0x0daf
|
#define mmCM1_CM_COMA_C13_C14_BASE_IDX 2
|
#define mmCM1_CM_COMA_C21_C22 0x0db0
|
#define mmCM1_CM_COMA_C21_C22_BASE_IDX 2
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#define mmCM1_CM_COMA_C23_C24 0x0db1
|
#define mmCM1_CM_COMA_C23_C24_BASE_IDX 2
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#define mmCM1_CM_COMA_C31_C32 0x0db2
|
#define mmCM1_CM_COMA_C31_C32_BASE_IDX 2
|
#define mmCM1_CM_COMA_C33_C34 0x0db3
|
#define mmCM1_CM_COMA_C33_C34_BASE_IDX 2
|
#define mmCM1_CM_COMB_C11_C12 0x0db4
|
#define mmCM1_CM_COMB_C11_C12_BASE_IDX 2
|
#define mmCM1_CM_COMB_C13_C14 0x0db5
|
#define mmCM1_CM_COMB_C13_C14_BASE_IDX 2
|
#define mmCM1_CM_COMB_C21_C22 0x0db6
|
#define mmCM1_CM_COMB_C21_C22_BASE_IDX 2
|
#define mmCM1_CM_COMB_C23_C24 0x0db7
|
#define mmCM1_CM_COMB_C23_C24_BASE_IDX 2
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#define mmCM1_CM_COMB_C31_C32 0x0db8
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#define mmCM1_CM_COMB_C31_C32_BASE_IDX 2
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#define mmCM1_CM_COMB_C33_C34 0x0db9
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#define mmCM1_CM_COMB_C33_C34_BASE_IDX 2
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#define mmCM1_CM_IGAM_CONTROL 0x0dba
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#define mmCM1_CM_IGAM_CONTROL_BASE_IDX 2
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#define mmCM1_CM_IGAM_LUT_RW_CONTROL 0x0dbb
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#define mmCM1_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2
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#define mmCM1_CM_IGAM_LUT_RW_INDEX 0x0dbc
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#define mmCM1_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2
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#define mmCM1_CM_IGAM_LUT_SEQ_COLOR 0x0dbd
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#define mmCM1_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2
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#define mmCM1_CM_IGAM_LUT_30_COLOR 0x0dbe
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#define mmCM1_CM_IGAM_LUT_30_COLOR_BASE_IDX 2
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#define mmCM1_CM_IGAM_LUT_PWL_DATA 0x0dbf
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#define mmCM1_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2
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#define mmCM1_CM_IGAM_LUT_AUTOFILL 0x0dc0
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#define mmCM1_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2
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#define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0dc1
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#define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2
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#define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0dc2
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#define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2
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#define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED 0x0dc3
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#define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2
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#define mmCM1_CM_ICSC_CONTROL 0x0dc4
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#define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2
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#define mmCM1_CM_ICSC_C11_C12 0x0dc5
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#define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2
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#define mmCM1_CM_ICSC_C13_C14 0x0dc6
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#define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2
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#define mmCM1_CM_ICSC_C21_C22 0x0dc7
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#define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2
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#define mmCM1_CM_ICSC_C23_C24 0x0dc8
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#define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2
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#define mmCM1_CM_ICSC_C31_C32 0x0dc9
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#define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2
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#define mmCM1_CM_ICSC_C33_C34 0x0dca
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#define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2
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#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0dcb
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#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0dcc
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#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0dcd
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#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0dce
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#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0dcf
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#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0dd0
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#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0dd1
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#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
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#define mmCM1_CM_OCSC_CONTROL 0x0dd2
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#define mmCM1_CM_OCSC_CONTROL_BASE_IDX 2
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#define mmCM1_CM_OCSC_C11_C12 0x0dd3
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#define mmCM1_CM_OCSC_C11_C12_BASE_IDX 2
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#define mmCM1_CM_OCSC_C13_C14 0x0dd4
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#define mmCM1_CM_OCSC_C13_C14_BASE_IDX 2
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#define mmCM1_CM_OCSC_C21_C22 0x0dd5
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#define mmCM1_CM_OCSC_C21_C22_BASE_IDX 2
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#define mmCM1_CM_OCSC_C23_C24 0x0dd6
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#define mmCM1_CM_OCSC_C23_C24_BASE_IDX 2
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#define mmCM1_CM_OCSC_C31_C32 0x0dd7
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#define mmCM1_CM_OCSC_C31_C32_BASE_IDX 2
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#define mmCM1_CM_OCSC_C33_C34 0x0dd8
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#define mmCM1_CM_OCSC_C33_C34_BASE_IDX 2
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#define mmCM1_CM_BNS_VALUES_R 0x0dd9
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#define mmCM1_CM_BNS_VALUES_R_BASE_IDX 2
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#define mmCM1_CM_BNS_VALUES_G 0x0dda
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#define mmCM1_CM_BNS_VALUES_G_BASE_IDX 2
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#define mmCM1_CM_BNS_VALUES_B 0x0ddb
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#define mmCM1_CM_BNS_VALUES_B_BASE_IDX 2
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#define mmCM1_CM_DGAM_CONTROL 0x0ddc
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#define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2
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#define mmCM1_CM_DGAM_LUT_INDEX 0x0ddd
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#define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2
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#define mmCM1_CM_DGAM_LUT_DATA 0x0dde
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#define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2
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#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ddf
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#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0de0
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#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0de1
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#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0de2
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#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0de3
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#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0de4
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#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0de5
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#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0de6
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#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0de7
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#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0de8
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#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0de9
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#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0dea
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#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0deb
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#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0dec
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#define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0ded
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#define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0dee
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#define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0def
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#define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0df0
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#define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0df1
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#define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0df2
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#define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0df3
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#define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0df4
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#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0df5
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#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0df6
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#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0df7
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#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0df8
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#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0df9
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#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0dfa
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#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0dfb
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#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0dfc
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#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0dfd
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#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0dfe
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#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0dff
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#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0e00
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#define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0e01
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#define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0e02
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#define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0e03
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#define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0e04
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#define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0e05
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#define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0e06
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#define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0e07
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#define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM1_CM_RGAM_CONTROL 0x0e08
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#define mmCM1_CM_RGAM_CONTROL_BASE_IDX 2
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#define mmCM1_CM_RGAM_LUT_INDEX 0x0e09
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#define mmCM1_CM_RGAM_LUT_INDEX_BASE_IDX 2
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#define mmCM1_CM_RGAM_LUT_DATA 0x0e0a
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#define mmCM1_CM_RGAM_LUT_DATA_BASE_IDX 2
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#define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK 0x0e0b
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#define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_START_CNTL_B 0x0e0c
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#define mmCM1_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_START_CNTL_G 0x0e0d
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#define mmCM1_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_START_CNTL_R 0x0e0e
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#define mmCM1_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0e0f
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#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0e10
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#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0e11
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#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_END_CNTL1_B 0x0e12
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#define mmCM1_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_END_CNTL2_B 0x0e13
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#define mmCM1_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_END_CNTL1_G 0x0e14
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#define mmCM1_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_END_CNTL2_G 0x0e15
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#define mmCM1_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_END_CNTL1_R 0x0e16
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#define mmCM1_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_END_CNTL2_R 0x0e17
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#define mmCM1_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_0_1 0x0e18
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#define mmCM1_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_2_3 0x0e19
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#define mmCM1_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_4_5 0x0e1a
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#define mmCM1_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_6_7 0x0e1b
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#define mmCM1_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_8_9 0x0e1c
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#define mmCM1_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_10_11 0x0e1d
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#define mmCM1_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_12_13 0x0e1e
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#define mmCM1_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_14_15 0x0e1f
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#define mmCM1_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_16_17 0x0e20
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#define mmCM1_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_18_19 0x0e21
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#define mmCM1_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_20_21 0x0e22
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#define mmCM1_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_22_23 0x0e23
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#define mmCM1_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_24_25 0x0e24
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#define mmCM1_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_26_27 0x0e25
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#define mmCM1_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_28_29 0x0e26
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#define mmCM1_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_30_31 0x0e27
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#define mmCM1_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMA_REGION_32_33 0x0e28
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#define mmCM1_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_START_CNTL_B 0x0e29
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#define mmCM1_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_START_CNTL_G 0x0e2a
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#define mmCM1_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_START_CNTL_R 0x0e2b
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#define mmCM1_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0e2c
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#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0e2d
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#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0e2e
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#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_END_CNTL1_B 0x0e2f
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#define mmCM1_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_END_CNTL2_B 0x0e30
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#define mmCM1_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_END_CNTL1_G 0x0e31
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#define mmCM1_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_END_CNTL2_G 0x0e32
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#define mmCM1_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_END_CNTL1_R 0x0e33
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#define mmCM1_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_END_CNTL2_R 0x0e34
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#define mmCM1_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_0_1 0x0e35
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#define mmCM1_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_2_3 0x0e36
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#define mmCM1_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_4_5 0x0e37
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#define mmCM1_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_6_7 0x0e38
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#define mmCM1_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_8_9 0x0e39
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#define mmCM1_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_10_11 0x0e3a
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#define mmCM1_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_12_13 0x0e3b
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#define mmCM1_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_14_15 0x0e3c
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#define mmCM1_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_16_17 0x0e3d
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#define mmCM1_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_18_19 0x0e3e
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#define mmCM1_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_20_21 0x0e3f
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#define mmCM1_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_22_23 0x0e40
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#define mmCM1_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_24_25 0x0e41
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#define mmCM1_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_26_27 0x0e42
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#define mmCM1_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_28_29 0x0e43
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#define mmCM1_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_30_31 0x0e44
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#define mmCM1_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM1_CM_RGAM_RAMB_REGION_32_33 0x0e45
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#define mmCM1_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM1_CM_HDR_MULT_COEF 0x0e46
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#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2
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#define mmCM1_CM_RANGE_CLAMP_CONTROL_R 0x0e47
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#define mmCM1_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2
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#define mmCM1_CM_RANGE_CLAMP_CONTROL_G 0x0e48
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#define mmCM1_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2
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#define mmCM1_CM_RANGE_CLAMP_CONTROL_B 0x0e49
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#define mmCM1_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2
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#define mmCM1_CM_DENORM_CONTROL 0x0e4a
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#define mmCM1_CM_DENORM_CONTROL_BASE_IDX 2
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#define mmCM1_CM_CMOUT_CONTROL 0x0e4b
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#define mmCM1_CM_CMOUT_CONTROL_BASE_IDX 2
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#define mmCM1_CM_CMOUT_RANDOM_SEEDS 0x0e4c
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#define mmCM1_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2
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#define mmCM1_CM_MEM_PWR_CTRL 0x0e4d
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#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCM1_CM_MEM_PWR_STATUS 0x0e4e
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#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCM1_CM_TEST_DEBUG_INDEX 0x0e50
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#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2
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#define mmCM1_CM_TEST_DEBUG_DATA 0x0e51
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#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2
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// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x399c
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#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x0e67
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#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x0e68
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#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x0e69
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#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_CNTL 0x0e6a
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#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_CNTL2 0x0e6b
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#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0e6c
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#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0e6d
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#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_HI 0x0e6e
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#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON13_PERFMON_LOW 0x0e6f
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#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
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// base address: 0x8d8
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#define mmDPP_TOP2_DPP_CONTROL 0x0e73
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#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2
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#define mmDPP_TOP2_DPP_SOFT_RESET 0x0e74
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#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2
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#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0e75
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#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2
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#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0e76
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#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2
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#define mmDPP_TOP2_DPP_CRC_CTRL 0x0e77
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#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2
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#define mmDPP_TOP2_HOST_READ_CONTROL 0x0e78
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#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec
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// base address: 0x8d8
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#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0e7d
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#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
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#define mmCNVC_CFG2_FORMAT_CONTROL 0x0e7e
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#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS 0x0e7f
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#define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS_BASE_IDX 2
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#define mmCNVC_CFG2_DENORM_CONTROL 0x0e80
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#define mmCNVC_CFG2_DENORM_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0e82
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#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0e83
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#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2
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#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0e84
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#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2
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#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0e85
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#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2
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#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0e86
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#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2
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// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec
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// base address: 0x8d8
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#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0e8e
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#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2
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#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0e8f
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#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2
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#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0e90
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#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2
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#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0e91
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#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
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// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec
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// base address: 0x8d8
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#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0e98
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#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
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#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0e99
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#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
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#define mmDSCL2_SCL_MODE 0x0e9a
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#define mmDSCL2_SCL_MODE_BASE_IDX 2
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#define mmDSCL2_SCL_TAP_CONTROL 0x0e9b
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#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2
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#define mmDSCL2_DSCL_CONTROL 0x0e9c
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#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2
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#define mmDSCL2_DSCL_2TAP_CONTROL 0x0e9d
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#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2
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#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0e9e
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#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
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#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0e9f
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#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0ea0
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#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0ea1
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#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0ea2
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#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0ea3
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#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0ea4
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#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0ea5
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#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0ea6
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#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0ea7
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#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0ea8
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#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
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#define mmDSCL2_SCL_BLACK_OFFSET 0x0ea9
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#define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2
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#define mmDSCL2_DSCL_UPDATE 0x0eaa
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#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2
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#define mmDSCL2_DSCL_AUTOCAL 0x0eab
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#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2
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#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0eac
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#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0ead
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#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmDSCL2_OTG_H_BLANK 0x0eae
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#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2
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#define mmDSCL2_OTG_V_BLANK 0x0eaf
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#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2
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#define mmDSCL2_RECOUT_START 0x0eb0
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#define mmDSCL2_RECOUT_START_BASE_IDX 2
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#define mmDSCL2_RECOUT_SIZE 0x0eb1
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#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2
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#define mmDSCL2_MPC_SIZE 0x0eb2
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#define mmDSCL2_MPC_SIZE_BASE_IDX 2
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#define mmDSCL2_LB_DATA_FORMAT 0x0eb3
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#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2
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#define mmDSCL2_LB_MEMORY_CTRL 0x0eb4
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#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2
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#define mmDSCL2_LB_V_COUNTER 0x0eb5
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#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2
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#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0eb6
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#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0eb7
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#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDSCL2_OBUF_CONTROL 0x0eb8
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#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2
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#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0eb9
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#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2
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// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec
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// base address: 0x8d8
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#define mmCM2_CM_CONTROL 0x0ec8
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#define mmCM2_CM_CONTROL_BASE_IDX 2
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#define mmCM2_CM_COMA_C11_C12 0x0ec9
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#define mmCM2_CM_COMA_C11_C12_BASE_IDX 2
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#define mmCM2_CM_COMA_C13_C14 0x0eca
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#define mmCM2_CM_COMA_C13_C14_BASE_IDX 2
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#define mmCM2_CM_COMA_C21_C22 0x0ecb
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#define mmCM2_CM_COMA_C21_C22_BASE_IDX 2
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#define mmCM2_CM_COMA_C23_C24 0x0ecc
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#define mmCM2_CM_COMA_C23_C24_BASE_IDX 2
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#define mmCM2_CM_COMA_C31_C32 0x0ecd
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#define mmCM2_CM_COMA_C31_C32_BASE_IDX 2
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#define mmCM2_CM_COMA_C33_C34 0x0ece
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#define mmCM2_CM_COMA_C33_C34_BASE_IDX 2
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#define mmCM2_CM_COMB_C11_C12 0x0ecf
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#define mmCM2_CM_COMB_C11_C12_BASE_IDX 2
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#define mmCM2_CM_COMB_C13_C14 0x0ed0
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#define mmCM2_CM_COMB_C13_C14_BASE_IDX 2
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#define mmCM2_CM_COMB_C21_C22 0x0ed1
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#define mmCM2_CM_COMB_C21_C22_BASE_IDX 2
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#define mmCM2_CM_COMB_C23_C24 0x0ed2
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#define mmCM2_CM_COMB_C23_C24_BASE_IDX 2
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#define mmCM2_CM_COMB_C31_C32 0x0ed3
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#define mmCM2_CM_COMB_C31_C32_BASE_IDX 2
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#define mmCM2_CM_COMB_C33_C34 0x0ed4
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#define mmCM2_CM_COMB_C33_C34_BASE_IDX 2
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#define mmCM2_CM_IGAM_CONTROL 0x0ed5
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#define mmCM2_CM_IGAM_CONTROL_BASE_IDX 2
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#define mmCM2_CM_IGAM_LUT_RW_CONTROL 0x0ed6
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#define mmCM2_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2
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#define mmCM2_CM_IGAM_LUT_RW_INDEX 0x0ed7
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#define mmCM2_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2
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#define mmCM2_CM_IGAM_LUT_SEQ_COLOR 0x0ed8
|
#define mmCM2_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2
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#define mmCM2_CM_IGAM_LUT_30_COLOR 0x0ed9
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#define mmCM2_CM_IGAM_LUT_30_COLOR_BASE_IDX 2
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#define mmCM2_CM_IGAM_LUT_PWL_DATA 0x0eda
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#define mmCM2_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2
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#define mmCM2_CM_IGAM_LUT_AUTOFILL 0x0edb
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#define mmCM2_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2
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#define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0edc
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#define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2
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#define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0edd
|
#define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2
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#define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED 0x0ede
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#define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2
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#define mmCM2_CM_ICSC_CONTROL 0x0edf
|
#define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2
|
#define mmCM2_CM_ICSC_C11_C12 0x0ee0
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#define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2
|
#define mmCM2_CM_ICSC_C13_C14 0x0ee1
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#define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2
|
#define mmCM2_CM_ICSC_C21_C22 0x0ee2
|
#define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2
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#define mmCM2_CM_ICSC_C23_C24 0x0ee3
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#define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2
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#define mmCM2_CM_ICSC_C31_C32 0x0ee4
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#define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2
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#define mmCM2_CM_ICSC_C33_C34 0x0ee5
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#define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2
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#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ee6
|
#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0ee7
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#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x0ee8
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#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x0ee9
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#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x0eea
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#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x0eeb
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#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x0eec
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#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
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#define mmCM2_CM_OCSC_CONTROL 0x0eed
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#define mmCM2_CM_OCSC_CONTROL_BASE_IDX 2
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#define mmCM2_CM_OCSC_C11_C12 0x0eee
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#define mmCM2_CM_OCSC_C11_C12_BASE_IDX 2
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#define mmCM2_CM_OCSC_C13_C14 0x0eef
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#define mmCM2_CM_OCSC_C13_C14_BASE_IDX 2
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#define mmCM2_CM_OCSC_C21_C22 0x0ef0
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#define mmCM2_CM_OCSC_C21_C22_BASE_IDX 2
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#define mmCM2_CM_OCSC_C23_C24 0x0ef1
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#define mmCM2_CM_OCSC_C23_C24_BASE_IDX 2
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#define mmCM2_CM_OCSC_C31_C32 0x0ef2
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#define mmCM2_CM_OCSC_C31_C32_BASE_IDX 2
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#define mmCM2_CM_OCSC_C33_C34 0x0ef3
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#define mmCM2_CM_OCSC_C33_C34_BASE_IDX 2
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#define mmCM2_CM_BNS_VALUES_R 0x0ef4
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#define mmCM2_CM_BNS_VALUES_R_BASE_IDX 2
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#define mmCM2_CM_BNS_VALUES_G 0x0ef5
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#define mmCM2_CM_BNS_VALUES_G_BASE_IDX 2
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#define mmCM2_CM_BNS_VALUES_B 0x0ef6
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#define mmCM2_CM_BNS_VALUES_B_BASE_IDX 2
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#define mmCM2_CM_DGAM_CONTROL 0x0ef7
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#define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2
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#define mmCM2_CM_DGAM_LUT_INDEX 0x0ef8
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#define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2
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#define mmCM2_CM_DGAM_LUT_DATA 0x0ef9
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#define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2
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#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x0efa
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#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x0efb
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#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x0efc
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#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x0efd
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#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0efe
|
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eff
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#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0f00
|
#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x0f01
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#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x0f02
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x0f03
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x0f04
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x0f05
|
#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x0f06
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#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x0f07
|
#define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x0f08
|
#define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
|
#define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x0f09
|
#define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x0f0a
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#define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x0f0b
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#define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x0f0c
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#define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x0f0d
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#define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x0f0e
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#define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x0f0f
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#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x0f10
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#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x0f11
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#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0f12
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#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0f13
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#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0f14
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#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x0f15
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#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x0f16
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#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x0f17
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#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x0f18
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#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x0f19
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#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x0f1a
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#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x0f1b
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#define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x0f1c
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#define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x0f1d
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#define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x0f1e
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#define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x0f1f
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#define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x0f20
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#define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x0f21
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#define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x0f22
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#define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM2_CM_RGAM_CONTROL 0x0f23
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#define mmCM2_CM_RGAM_CONTROL_BASE_IDX 2
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#define mmCM2_CM_RGAM_LUT_INDEX 0x0f24
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#define mmCM2_CM_RGAM_LUT_INDEX_BASE_IDX 2
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#define mmCM2_CM_RGAM_LUT_DATA 0x0f25
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#define mmCM2_CM_RGAM_LUT_DATA_BASE_IDX 2
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#define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK 0x0f26
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#define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_START_CNTL_B 0x0f27
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#define mmCM2_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_START_CNTL_G 0x0f28
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#define mmCM2_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_START_CNTL_R 0x0f29
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#define mmCM2_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0f2a
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#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0f2b
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#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0f2c
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#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_END_CNTL1_B 0x0f2d
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#define mmCM2_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_END_CNTL2_B 0x0f2e
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#define mmCM2_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_END_CNTL1_G 0x0f2f
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#define mmCM2_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_END_CNTL2_G 0x0f30
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#define mmCM2_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_END_CNTL1_R 0x0f31
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#define mmCM2_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_END_CNTL2_R 0x0f32
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#define mmCM2_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_0_1 0x0f33
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#define mmCM2_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_2_3 0x0f34
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#define mmCM2_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_4_5 0x0f35
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#define mmCM2_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_6_7 0x0f36
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#define mmCM2_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_8_9 0x0f37
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#define mmCM2_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_10_11 0x0f38
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#define mmCM2_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_12_13 0x0f39
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#define mmCM2_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_14_15 0x0f3a
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#define mmCM2_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_16_17 0x0f3b
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#define mmCM2_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_18_19 0x0f3c
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#define mmCM2_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_20_21 0x0f3d
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#define mmCM2_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_22_23 0x0f3e
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#define mmCM2_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_24_25 0x0f3f
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#define mmCM2_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_26_27 0x0f40
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#define mmCM2_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_28_29 0x0f41
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#define mmCM2_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_30_31 0x0f42
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#define mmCM2_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMA_REGION_32_33 0x0f43
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#define mmCM2_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_START_CNTL_B 0x0f44
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#define mmCM2_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_START_CNTL_G 0x0f45
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#define mmCM2_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_START_CNTL_R 0x0f46
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#define mmCM2_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0f47
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#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0f48
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#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0f49
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#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_END_CNTL1_B 0x0f4a
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#define mmCM2_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_END_CNTL2_B 0x0f4b
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#define mmCM2_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_END_CNTL1_G 0x0f4c
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#define mmCM2_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_END_CNTL2_G 0x0f4d
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#define mmCM2_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_END_CNTL1_R 0x0f4e
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#define mmCM2_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_END_CNTL2_R 0x0f4f
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#define mmCM2_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_0_1 0x0f50
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#define mmCM2_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_2_3 0x0f51
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#define mmCM2_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_4_5 0x0f52
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#define mmCM2_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_6_7 0x0f53
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#define mmCM2_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_8_9 0x0f54
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#define mmCM2_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_10_11 0x0f55
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#define mmCM2_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_12_13 0x0f56
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#define mmCM2_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_14_15 0x0f57
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#define mmCM2_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_16_17 0x0f58
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#define mmCM2_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_18_19 0x0f59
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#define mmCM2_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_20_21 0x0f5a
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#define mmCM2_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_22_23 0x0f5b
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#define mmCM2_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_24_25 0x0f5c
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#define mmCM2_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_26_27 0x0f5d
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#define mmCM2_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_28_29 0x0f5e
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#define mmCM2_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_30_31 0x0f5f
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#define mmCM2_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM2_CM_RGAM_RAMB_REGION_32_33 0x0f60
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#define mmCM2_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM2_CM_HDR_MULT_COEF 0x0f61
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#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2
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#define mmCM2_CM_RANGE_CLAMP_CONTROL_R 0x0f62
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#define mmCM2_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2
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#define mmCM2_CM_RANGE_CLAMP_CONTROL_G 0x0f63
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#define mmCM2_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2
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#define mmCM2_CM_RANGE_CLAMP_CONTROL_B 0x0f64
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#define mmCM2_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2
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#define mmCM2_CM_DENORM_CONTROL 0x0f65
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#define mmCM2_CM_DENORM_CONTROL_BASE_IDX 2
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#define mmCM2_CM_CMOUT_CONTROL 0x0f66
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#define mmCM2_CM_CMOUT_CONTROL_BASE_IDX 2
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#define mmCM2_CM_CMOUT_RANDOM_SEEDS 0x0f67
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#define mmCM2_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2
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#define mmCM2_CM_MEM_PWR_CTRL 0x0f68
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#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCM2_CM_MEM_PWR_STATUS 0x0f69
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#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2
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#define mmCM2_CM_TEST_DEBUG_INDEX 0x0f6b
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#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2
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#define mmCM2_CM_TEST_DEBUG_DATA 0x0f6c
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#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2
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// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
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// base address: 0x3e08
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#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x0f82
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#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x0f83
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#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x0f84
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#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON14_PERFMON_CNTL 0x0f85
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#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON14_PERFMON_CNTL2 0x0f86
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#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x0f87
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#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x0f88
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#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON14_PERFMON_HI 0x0f89
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#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON14_PERFMON_LOW 0x0f8a
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#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
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// base address: 0xd44
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#define mmDPP_TOP3_DPP_CONTROL 0x0f8e
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#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2
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#define mmDPP_TOP3_DPP_SOFT_RESET 0x0f8f
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#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2
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#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x0f90
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#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2
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#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x0f91
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#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2
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#define mmDPP_TOP3_DPP_CRC_CTRL 0x0f92
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#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2
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#define mmDPP_TOP3_HOST_READ_CONTROL 0x0f93
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#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec
|
// base address: 0xd44
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#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x0f98
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#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2
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#define mmCNVC_CFG3_FORMAT_CONTROL 0x0f99
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#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS 0x0f9a
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#define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS_BASE_IDX 2
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#define mmCNVC_CFG3_DENORM_CONTROL 0x0f9b
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#define mmCNVC_CFG3_DENORM_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x0f9d
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#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2
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#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x0f9e
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#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2
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#define mmCNVC_CFG3_COLOR_KEYER_RED 0x0f9f
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#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2
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#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x0fa0
|
#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2
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#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x0fa1
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#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2
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// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec
|
// base address: 0xd44
|
#define mmCNVC_CUR3_CURSOR0_CONTROL 0x0fa9
|
#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2
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#define mmCNVC_CUR3_CURSOR0_COLOR0 0x0faa
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#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2
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#define mmCNVC_CUR3_CURSOR0_COLOR1 0x0fab
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#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2
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#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x0fac
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#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2
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// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec
|
// base address: 0xd44
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#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x0fb3
|
#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2
|
#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x0fb4
|
#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2
|
#define mmDSCL3_SCL_MODE 0x0fb5
|
#define mmDSCL3_SCL_MODE_BASE_IDX 2
|
#define mmDSCL3_SCL_TAP_CONTROL 0x0fb6
|
#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL3_DSCL_CONTROL 0x0fb7
|
#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2
|
#define mmDSCL3_DSCL_2TAP_CONTROL 0x0fb8
|
#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2
|
#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0fb9
|
#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2
|
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0fba
|
#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2
|
#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x0fbb
|
#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2
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#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fbc
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#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x0fbd
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#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0fbe
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#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2
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#define mmDSCL3_SCL_VERT_FILTER_INIT 0x0fbf
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#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2
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#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x0fc0
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#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2
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#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fc1
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#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2
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#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x0fc2
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#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2
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#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x0fc3
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#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2
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#define mmDSCL3_SCL_BLACK_OFFSET 0x0fc4
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#define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2
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#define mmDSCL3_DSCL_UPDATE 0x0fc5
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#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2
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#define mmDSCL3_DSCL_AUTOCAL 0x0fc6
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#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2
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#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fc7
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#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2
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#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fc8
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#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2
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#define mmDSCL3_OTG_H_BLANK 0x0fc9
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#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2
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#define mmDSCL3_OTG_V_BLANK 0x0fca
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#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2
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#define mmDSCL3_RECOUT_START 0x0fcb
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#define mmDSCL3_RECOUT_START_BASE_IDX 2
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#define mmDSCL3_RECOUT_SIZE 0x0fcc
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#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2
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#define mmDSCL3_MPC_SIZE 0x0fcd
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#define mmDSCL3_MPC_SIZE_BASE_IDX 2
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#define mmDSCL3_LB_DATA_FORMAT 0x0fce
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#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2
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#define mmDSCL3_LB_MEMORY_CTRL 0x0fcf
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#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2
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#define mmDSCL3_LB_V_COUNTER 0x0fd0
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#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2
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#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x0fd1
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#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2
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#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x0fd2
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#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2
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#define mmDSCL3_OBUF_CONTROL 0x0fd3
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#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2
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#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x0fd4
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#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2
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// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec
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// base address: 0xd44
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#define mmCM3_CM_CONTROL 0x0fe3
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#define mmCM3_CM_CONTROL_BASE_IDX 2
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#define mmCM3_CM_COMA_C11_C12 0x0fe4
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#define mmCM3_CM_COMA_C11_C12_BASE_IDX 2
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#define mmCM3_CM_COMA_C13_C14 0x0fe5
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#define mmCM3_CM_COMA_C13_C14_BASE_IDX 2
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#define mmCM3_CM_COMA_C21_C22 0x0fe6
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#define mmCM3_CM_COMA_C21_C22_BASE_IDX 2
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#define mmCM3_CM_COMA_C23_C24 0x0fe7
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#define mmCM3_CM_COMA_C23_C24_BASE_IDX 2
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#define mmCM3_CM_COMA_C31_C32 0x0fe8
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#define mmCM3_CM_COMA_C31_C32_BASE_IDX 2
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#define mmCM3_CM_COMA_C33_C34 0x0fe9
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#define mmCM3_CM_COMA_C33_C34_BASE_IDX 2
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#define mmCM3_CM_COMB_C11_C12 0x0fea
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#define mmCM3_CM_COMB_C11_C12_BASE_IDX 2
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#define mmCM3_CM_COMB_C13_C14 0x0feb
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#define mmCM3_CM_COMB_C13_C14_BASE_IDX 2
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#define mmCM3_CM_COMB_C21_C22 0x0fec
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#define mmCM3_CM_COMB_C21_C22_BASE_IDX 2
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#define mmCM3_CM_COMB_C23_C24 0x0fed
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#define mmCM3_CM_COMB_C23_C24_BASE_IDX 2
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#define mmCM3_CM_COMB_C31_C32 0x0fee
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#define mmCM3_CM_COMB_C31_C32_BASE_IDX 2
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#define mmCM3_CM_COMB_C33_C34 0x0fef
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#define mmCM3_CM_COMB_C33_C34_BASE_IDX 2
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#define mmCM3_CM_IGAM_CONTROL 0x0ff0
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#define mmCM3_CM_IGAM_CONTROL_BASE_IDX 2
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#define mmCM3_CM_IGAM_LUT_RW_CONTROL 0x0ff1
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#define mmCM3_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2
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#define mmCM3_CM_IGAM_LUT_RW_INDEX 0x0ff2
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#define mmCM3_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2
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#define mmCM3_CM_IGAM_LUT_SEQ_COLOR 0x0ff3
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#define mmCM3_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2
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#define mmCM3_CM_IGAM_LUT_30_COLOR 0x0ff4
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#define mmCM3_CM_IGAM_LUT_30_COLOR_BASE_IDX 2
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#define mmCM3_CM_IGAM_LUT_PWL_DATA 0x0ff5
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#define mmCM3_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2
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#define mmCM3_CM_IGAM_LUT_AUTOFILL 0x0ff6
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#define mmCM3_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2
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#define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0ff7
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#define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2
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#define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0ff8
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#define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2
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#define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED 0x0ff9
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#define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2
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#define mmCM3_CM_ICSC_CONTROL 0x0ffa
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#define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2
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#define mmCM3_CM_ICSC_C11_C12 0x0ffb
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#define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2
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#define mmCM3_CM_ICSC_C13_C14 0x0ffc
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#define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2
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#define mmCM3_CM_ICSC_C21_C22 0x0ffd
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#define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2
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#define mmCM3_CM_ICSC_C23_C24 0x0ffe
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#define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2
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#define mmCM3_CM_ICSC_C31_C32 0x0fff
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#define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2
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#define mmCM3_CM_ICSC_C33_C34 0x1000
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#define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1001
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#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x1002
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#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x1003
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#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x1004
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#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x1005
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#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x1006
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#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2
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#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x1007
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#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2
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#define mmCM3_CM_OCSC_CONTROL 0x1008
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#define mmCM3_CM_OCSC_CONTROL_BASE_IDX 2
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#define mmCM3_CM_OCSC_C11_C12 0x1009
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#define mmCM3_CM_OCSC_C11_C12_BASE_IDX 2
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#define mmCM3_CM_OCSC_C13_C14 0x100a
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#define mmCM3_CM_OCSC_C13_C14_BASE_IDX 2
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#define mmCM3_CM_OCSC_C21_C22 0x100b
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#define mmCM3_CM_OCSC_C21_C22_BASE_IDX 2
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#define mmCM3_CM_OCSC_C23_C24 0x100c
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#define mmCM3_CM_OCSC_C23_C24_BASE_IDX 2
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#define mmCM3_CM_OCSC_C31_C32 0x100d
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#define mmCM3_CM_OCSC_C31_C32_BASE_IDX 2
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#define mmCM3_CM_OCSC_C33_C34 0x100e
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#define mmCM3_CM_OCSC_C33_C34_BASE_IDX 2
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#define mmCM3_CM_BNS_VALUES_R 0x100f
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#define mmCM3_CM_BNS_VALUES_R_BASE_IDX 2
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#define mmCM3_CM_BNS_VALUES_G 0x1010
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#define mmCM3_CM_BNS_VALUES_G_BASE_IDX 2
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#define mmCM3_CM_BNS_VALUES_B 0x1011
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#define mmCM3_CM_BNS_VALUES_B_BASE_IDX 2
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#define mmCM3_CM_DGAM_CONTROL 0x1012
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#define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2
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#define mmCM3_CM_DGAM_LUT_INDEX 0x1013
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#define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2
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#define mmCM3_CM_DGAM_LUT_DATA 0x1014
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#define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2
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#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x1015
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#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x1016
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#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x1017
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#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x1018
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#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1019
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#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x101a
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#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x101b
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#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x101c
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#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x101d
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#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x101e
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#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x101f
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#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1020
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#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1021
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#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1022
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#define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1023
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#define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x1024
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#define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x1025
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#define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x1026
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#define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x1027
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#define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x1028
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#define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x1029
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#define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x102a
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#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x102b
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#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x102c
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#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x102d
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#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x102e
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#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102f
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#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1030
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#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1031
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#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1032
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#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1033
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#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x1034
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#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x1035
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#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x1036
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#define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x1037
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#define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x1038
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#define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x1039
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#define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x103a
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#define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x103b
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#define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x103c
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#define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x103d
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#define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM3_CM_RGAM_CONTROL 0x103e
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#define mmCM3_CM_RGAM_CONTROL_BASE_IDX 2
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#define mmCM3_CM_RGAM_LUT_INDEX 0x103f
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#define mmCM3_CM_RGAM_LUT_INDEX_BASE_IDX 2
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#define mmCM3_CM_RGAM_LUT_DATA 0x1040
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#define mmCM3_CM_RGAM_LUT_DATA_BASE_IDX 2
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#define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK 0x1041
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#define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_START_CNTL_B 0x1042
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#define mmCM3_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_START_CNTL_G 0x1043
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#define mmCM3_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_START_CNTL_R 0x1044
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#define mmCM3_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B 0x1045
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#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G 0x1046
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#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R 0x1047
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#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_END_CNTL1_B 0x1048
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#define mmCM3_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_END_CNTL2_B 0x1049
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#define mmCM3_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_END_CNTL1_G 0x104a
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#define mmCM3_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_END_CNTL2_G 0x104b
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#define mmCM3_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_END_CNTL1_R 0x104c
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#define mmCM3_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_END_CNTL2_R 0x104d
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#define mmCM3_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_0_1 0x104e
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#define mmCM3_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_2_3 0x104f
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#define mmCM3_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_4_5 0x1050
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#define mmCM3_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_6_7 0x1051
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#define mmCM3_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_8_9 0x1052
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#define mmCM3_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_10_11 0x1053
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#define mmCM3_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_12_13 0x1054
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#define mmCM3_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_14_15 0x1055
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#define mmCM3_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_16_17 0x1056
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#define mmCM3_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_18_19 0x1057
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#define mmCM3_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_20_21 0x1058
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#define mmCM3_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_22_23 0x1059
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#define mmCM3_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_24_25 0x105a
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#define mmCM3_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_26_27 0x105b
|
#define mmCM3_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_28_29 0x105c
|
#define mmCM3_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_30_31 0x105d
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#define mmCM3_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMA_REGION_32_33 0x105e
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#define mmCM3_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_START_CNTL_B 0x105f
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#define mmCM3_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_START_CNTL_G 0x1060
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#define mmCM3_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_START_CNTL_R 0x1061
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#define mmCM3_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B 0x1062
|
#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G 0x1063
|
#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R 0x1064
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#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_END_CNTL1_B 0x1065
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#define mmCM3_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_END_CNTL2_B 0x1066
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#define mmCM3_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_END_CNTL1_G 0x1067
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#define mmCM3_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_END_CNTL2_G 0x1068
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#define mmCM3_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_END_CNTL1_R 0x1069
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#define mmCM3_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_END_CNTL2_R 0x106a
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#define mmCM3_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_0_1 0x106b
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#define mmCM3_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_2_3 0x106c
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#define mmCM3_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_4_5 0x106d
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#define mmCM3_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_6_7 0x106e
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#define mmCM3_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_8_9 0x106f
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#define mmCM3_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_10_11 0x1070
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#define mmCM3_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_12_13 0x1071
|
#define mmCM3_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_14_15 0x1072
|
#define mmCM3_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_16_17 0x1073
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#define mmCM3_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_18_19 0x1074
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#define mmCM3_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_20_21 0x1075
|
#define mmCM3_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_22_23 0x1076
|
#define mmCM3_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_24_25 0x1077
|
#define mmCM3_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_26_27 0x1078
|
#define mmCM3_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_28_29 0x1079
|
#define mmCM3_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_30_31 0x107a
|
#define mmCM3_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2
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#define mmCM3_CM_RGAM_RAMB_REGION_32_33 0x107b
|
#define mmCM3_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2
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#define mmCM3_CM_HDR_MULT_COEF 0x107c
|
#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2
|
#define mmCM3_CM_RANGE_CLAMP_CONTROL_R 0x107d
|
#define mmCM3_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2
|
#define mmCM3_CM_RANGE_CLAMP_CONTROL_G 0x107e
|
#define mmCM3_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2
|
#define mmCM3_CM_RANGE_CLAMP_CONTROL_B 0x107f
|
#define mmCM3_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2
|
#define mmCM3_CM_DENORM_CONTROL 0x1080
|
#define mmCM3_CM_DENORM_CONTROL_BASE_IDX 2
|
#define mmCM3_CM_CMOUT_CONTROL 0x1081
|
#define mmCM3_CM_CMOUT_CONTROL_BASE_IDX 2
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#define mmCM3_CM_CMOUT_RANDOM_SEEDS 0x1082
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#define mmCM3_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2
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#define mmCM3_CM_MEM_PWR_CTRL 0x1083
|
#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2
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#define mmCM3_CM_MEM_PWR_STATUS 0x1084
|
#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmCM3_CM_TEST_DEBUG_INDEX 0x1086
|
#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2
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#define mmCM3_CM_TEST_DEBUG_DATA 0x1087
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#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2
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|
// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x4274
|
#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x109d
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#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x109e
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#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x109f
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#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFMON_CNTL 0x10a0
|
#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFMON_CNTL2 0x10a1
|
#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x10a2
|
#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x10a3
|
#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFMON_HI 0x10a4
|
#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON15_PERFMON_LOW 0x10a5
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#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc0_dispdec
|
// base address: 0x0
|
#define mmMPCC0_MPCC_TOP_SEL 0x1630
|
#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 2
|
#define mmMPCC0_MPCC_BOT_SEL 0x1631
|
#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 2
|
#define mmMPCC0_MPCC_OPP_ID 0x1632
|
#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 2
|
#define mmMPCC0_MPCC_CONTROL 0x1633
|
#define mmMPCC0_MPCC_CONTROL_BASE_IDX 2
|
#define mmMPCC0_MPCC_SM_CONTROL 0x1634
|
#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 2
|
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x1635
|
#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
|
#define mmMPCC0_MPCC_TOP_OFFSET 0x1636
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#define mmMPCC0_MPCC_TOP_OFFSET_BASE_IDX 2
|
#define mmMPCC0_MPCC_BOT_OFFSET 0x1637
|
#define mmMPCC0_MPCC_BOT_OFFSET_BASE_IDX 2
|
#define mmMPCC0_MPCC_OFFSET 0x1638
|
#define mmMPCC0_MPCC_OFFSET_BASE_IDX 2
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#define mmMPCC0_MPCC_BG_R_CR 0x1639
|
#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 2
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#define mmMPCC0_MPCC_BG_G_Y 0x163a
|
#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 2
|
#define mmMPCC0_MPCC_BG_B_CB 0x163b
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#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 2
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#define mmMPCC0_MPCC_STALL_STATUS 0x163c
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#define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 2
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#define mmMPCC0_MPCC_STATUS 0x163d
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#define mmMPCC0_MPCC_STATUS_BASE_IDX 2
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|
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// addressBlock: dce_dc_mpc_mpcc1_dispdec
|
// base address: 0x6c
|
#define mmMPCC1_MPCC_TOP_SEL 0x164b
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#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 2
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#define mmMPCC1_MPCC_BOT_SEL 0x164c
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#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 2
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#define mmMPCC1_MPCC_OPP_ID 0x164d
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#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 2
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#define mmMPCC1_MPCC_CONTROL 0x164e
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#define mmMPCC1_MPCC_CONTROL_BASE_IDX 2
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#define mmMPCC1_MPCC_SM_CONTROL 0x164f
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#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 2
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#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x1650
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#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
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#define mmMPCC1_MPCC_TOP_OFFSET 0x1651
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#define mmMPCC1_MPCC_TOP_OFFSET_BASE_IDX 2
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#define mmMPCC1_MPCC_BOT_OFFSET 0x1652
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#define mmMPCC1_MPCC_BOT_OFFSET_BASE_IDX 2
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#define mmMPCC1_MPCC_OFFSET 0x1653
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#define mmMPCC1_MPCC_OFFSET_BASE_IDX 2
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#define mmMPCC1_MPCC_BG_R_CR 0x1654
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#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 2
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#define mmMPCC1_MPCC_BG_G_Y 0x1655
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#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 2
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#define mmMPCC1_MPCC_BG_B_CB 0x1656
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#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 2
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#define mmMPCC1_MPCC_STALL_STATUS 0x1657
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#define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX 2
|
#define mmMPCC1_MPCC_STATUS 0x1658
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#define mmMPCC1_MPCC_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc2_dispdec
|
// base address: 0xd8
|
#define mmMPCC2_MPCC_TOP_SEL 0x1666
|
#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 2
|
#define mmMPCC2_MPCC_BOT_SEL 0x1667
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#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 2
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#define mmMPCC2_MPCC_OPP_ID 0x1668
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#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 2
|
#define mmMPCC2_MPCC_CONTROL 0x1669
|
#define mmMPCC2_MPCC_CONTROL_BASE_IDX 2
|
#define mmMPCC2_MPCC_SM_CONTROL 0x166a
|
#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 2
|
#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x166b
|
#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
|
#define mmMPCC2_MPCC_TOP_OFFSET 0x166c
|
#define mmMPCC2_MPCC_TOP_OFFSET_BASE_IDX 2
|
#define mmMPCC2_MPCC_BOT_OFFSET 0x166d
|
#define mmMPCC2_MPCC_BOT_OFFSET_BASE_IDX 2
|
#define mmMPCC2_MPCC_OFFSET 0x166e
|
#define mmMPCC2_MPCC_OFFSET_BASE_IDX 2
|
#define mmMPCC2_MPCC_BG_R_CR 0x166f
|
#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 2
|
#define mmMPCC2_MPCC_BG_G_Y 0x1670
|
#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 2
|
#define mmMPCC2_MPCC_BG_B_CB 0x1671
|
#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 2
|
#define mmMPCC2_MPCC_STALL_STATUS 0x1672
|
#define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX 2
|
#define mmMPCC2_MPCC_STATUS 0x1673
|
#define mmMPCC2_MPCC_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpcc3_dispdec
|
// base address: 0x144
|
#define mmMPCC3_MPCC_TOP_SEL 0x1681
|
#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 2
|
#define mmMPCC3_MPCC_BOT_SEL 0x1682
|
#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 2
|
#define mmMPCC3_MPCC_OPP_ID 0x1683
|
#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 2
|
#define mmMPCC3_MPCC_CONTROL 0x1684
|
#define mmMPCC3_MPCC_CONTROL_BASE_IDX 2
|
#define mmMPCC3_MPCC_SM_CONTROL 0x1685
|
#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 2
|
#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x1686
|
#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2
|
#define mmMPCC3_MPCC_TOP_OFFSET 0x1687
|
#define mmMPCC3_MPCC_TOP_OFFSET_BASE_IDX 2
|
#define mmMPCC3_MPCC_BOT_OFFSET 0x1688
|
#define mmMPCC3_MPCC_BOT_OFFSET_BASE_IDX 2
|
#define mmMPCC3_MPCC_OFFSET 0x1689
|
#define mmMPCC3_MPCC_OFFSET_BASE_IDX 2
|
#define mmMPCC3_MPCC_BG_R_CR 0x168a
|
#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 2
|
#define mmMPCC3_MPCC_BG_G_Y 0x168b
|
#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 2
|
#define mmMPCC3_MPCC_BG_B_CB 0x168c
|
#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 2
|
#define mmMPCC3_MPCC_STALL_STATUS 0x168d
|
#define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX 2
|
#define mmMPCC3_MPCC_STATUS 0x168e
|
#define mmMPCC3_MPCC_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpc_cfg_dispdec
|
// base address: 0x0
|
#define mmMPC_CLOCK_CONTROL 0x1723
|
#define mmMPC_CLOCK_CONTROL_BASE_IDX 2
|
#define mmMPC_SOFT_RESET 0x1724
|
#define mmMPC_SOFT_RESET_BASE_IDX 2
|
#define mmMPC_CRC_CTRL 0x1725
|
#define mmMPC_CRC_CTRL_BASE_IDX 2
|
#define mmMPC_CRC_SEL_CONTROL 0x1726
|
#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 2
|
#define mmMPC_CRC_RESULT_AR 0x1727
|
#define mmMPC_CRC_RESULT_AR_BASE_IDX 2
|
#define mmMPC_CRC_RESULT_GB 0x1728
|
#define mmMPC_CRC_RESULT_GB_BASE_IDX 2
|
#define mmMPC_CRC_RESULT_C 0x1729
|
#define mmMPC_CRC_RESULT_C_BASE_IDX 2
|
#define mmMPC_PERFMON_EVENT_CTRL 0x172c
|
#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 2
|
#define mmMPC_BYPASS_BG_AR 0x172d
|
#define mmMPC_BYPASS_BG_AR_BASE_IDX 2
|
#define mmMPC_BYPASS_BG_GB 0x172e
|
#define mmMPC_BYPASS_BG_GB_BASE_IDX 2
|
#define mmMPC_OUT0_MUX 0x172f
|
#define mmMPC_OUT0_MUX_BASE_IDX 2
|
#define mmMPC_OUT1_MUX 0x1730
|
#define mmMPC_OUT1_MUX_BASE_IDX 2
|
#define mmMPC_OUT2_MUX 0x1731
|
#define mmMPC_OUT2_MUX_BASE_IDX 2
|
#define mmMPC_OUT3_MUX 0x1732
|
#define mmMPC_OUT3_MUX_BASE_IDX 2
|
#define mmMPC_STALL_GRACE_WINDOW 0x1756
|
#define mmMPC_STALL_GRACE_WINDOW_BASE_IDX 2
|
#define mmADR_CFG_VUPDATE_LOCK_SET0 0x175b
|
#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 2
|
#define mmADR_VUPDATE_LOCK_SET0 0x175c
|
#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 2
|
#define mmCUR0_VUPDATE_LOCK_SET0 0x175d
|
#define mmCUR0_VUPDATE_LOCK_SET0_BASE_IDX 2
|
#define mmCUR1_VUPDATE_LOCK_SET0 0x175e
|
#define mmCUR1_VUPDATE_LOCK_SET0_BASE_IDX 2
|
#define mmADR_CFG_VUPDATE_LOCK_SET1 0x175f
|
#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 2
|
#define mmADR_VUPDATE_LOCK_SET1 0x1760
|
#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 2
|
#define mmCUR0_VUPDATE_LOCK_SET1 0x1761
|
#define mmCUR0_VUPDATE_LOCK_SET1_BASE_IDX 2
|
#define mmCUR1_VUPDATE_LOCK_SET1 0x1762
|
#define mmCUR1_VUPDATE_LOCK_SET1_BASE_IDX 2
|
#define mmADR_CFG_VUPDATE_LOCK_SET2 0x1763
|
#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 2
|
#define mmADR_VUPDATE_LOCK_SET2 0x1764
|
#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 2
|
#define mmCUR0_VUPDATE_LOCK_SET2 0x1765
|
#define mmCUR0_VUPDATE_LOCK_SET2_BASE_IDX 2
|
#define mmCUR1_VUPDATE_LOCK_SET2 0x1766
|
#define mmCUR1_VUPDATE_LOCK_SET2_BASE_IDX 2
|
#define mmADR_CFG_VUPDATE_LOCK_SET3 0x1767
|
#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 2
|
#define mmADR_VUPDATE_LOCK_SET3 0x1768
|
#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 2
|
#define mmCUR0_VUPDATE_LOCK_SET3 0x1769
|
#define mmCUR0_VUPDATE_LOCK_SET3_BASE_IDX 2
|
#define mmCUR1_VUPDATE_LOCK_SET3 0x176a
|
#define mmCUR1_VUPDATE_LOCK_SET3_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x5e90
|
#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x17a4
|
#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x17a5
|
#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x17a6
|
#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_CNTL 0x17a7
|
#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_CNTL2 0x17a8
|
#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x17a9
|
#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x17aa
|
#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_HI 0x17ab
|
#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON16_PERFMON_LOW 0x17ac
|
#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_abm0_dispdec
|
// base address: 0x0
|
#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x17b0
|
#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
|
#define mmABM0_BL1_PWM_USER_LEVEL 0x17b1
|
#define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX 2
|
#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL 0x17b2
|
#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
|
#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x17b3
|
#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
|
#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x17b4
|
#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
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#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x17b5
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#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
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#define mmABM0_BL1_PWM_ABM_CNTL 0x17b6
|
#define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX 2
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#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17b7
|
#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
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#define mmABM0_BL1_PWM_GRP2_REG_LOCK 0x17b8
|
#define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
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#define mmABM0_DC_ABM1_CNTL 0x17b9
|
#define mmABM0_DC_ABM1_CNTL_BASE_IDX 2
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#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL 0x17ba
|
#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x17bb
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x17bc
|
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x17bd
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x17be
|
#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x17bf
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#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
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#define mmABM0_DC_ABM1_ACE_THRES_12 0x17c0
|
#define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 2
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#define mmABM0_DC_ABM1_ACE_THRES_34 0x17c1
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#define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 2
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#define mmABM0_DC_ABM1_ACE_CNTL_MISC 0x17c2
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#define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
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#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x17c4
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#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_MISC_CTRL 0x17c5
|
#define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 2
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#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA 0x17c6
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#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
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#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x17c7
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#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
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#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x17c8
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#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
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#define mmABM0_DC_ABM1_LS_PIXEL_COUNT 0x17c9
|
#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
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#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x17ca
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#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
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#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x17cb
|
#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
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#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x17cc
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#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_SAMPLE_RATE 0x17cd
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#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
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#define mmABM0_DC_ABM1_LS_SAMPLE_RATE 0x17ce
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#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x17cf
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#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x17d0
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#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x17d1
|
#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x17d2
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#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x17d3
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#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_1 0x17d4
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#define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_2 0x17d5
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#define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_3 0x17d6
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#define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_4 0x17d7
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#define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_5 0x17d8
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#define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_6 0x17d9
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#define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_7 0x17da
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#define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_8 0x17db
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#define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_9 0x17dc
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#define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_10 0x17dd
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#define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_11 0x17de
|
#define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_12 0x17df
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#define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_13 0x17e0
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#define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_14 0x17e1
|
#define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_15 0x17e2
|
#define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_16 0x17e3
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#define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_17 0x17e4
|
#define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_18 0x17e5
|
#define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_19 0x17e6
|
#define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_20 0x17e7
|
#define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_21 0x17e8
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#define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_22 0x17e9
|
#define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_23 0x17ea
|
#define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 2
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#define mmABM0_DC_ABM1_HG_RESULT_24 0x17eb
|
#define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 2
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#define mmABM0_DC_ABM1_BL_MASTER_LOCK 0x17ec
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#define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
|
|
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// addressBlock: dce_dc_opp_abm1_dispdec
|
// base address: 0x118
|
#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x17f6
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#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2
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#define mmABM1_BL1_PWM_USER_LEVEL 0x17f7
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#define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX 2
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#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL 0x17f8
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#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2
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#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x17f9
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#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2
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#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x17fa
|
#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2
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#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x17fb
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#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2
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#define mmABM1_BL1_PWM_ABM_CNTL 0x17fc
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#define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX 2
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#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17fd
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#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2
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#define mmABM1_BL1_PWM_GRP2_REG_LOCK 0x17fe
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#define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 2
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#define mmABM1_DC_ABM1_CNTL 0x17ff
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#define mmABM1_DC_ABM1_CNTL_BASE_IDX 2
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#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL 0x1800
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#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x1801
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x1802
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x1803
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x1804
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x1805
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#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2
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#define mmABM1_DC_ABM1_ACE_THRES_12 0x1806
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#define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 2
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#define mmABM1_DC_ABM1_ACE_THRES_34 0x1807
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#define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 2
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#define mmABM1_DC_ABM1_ACE_CNTL_MISC 0x1808
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#define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 2
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#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x180a
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#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2
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#define mmABM1_DC_ABM1_HG_MISC_CTRL 0x180b
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#define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 2
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#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA 0x180c
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#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2
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#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x180d
|
#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2
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#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x180e
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#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2
|
#define mmABM1_DC_ABM1_LS_PIXEL_COUNT 0x180f
|
#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2
|
#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1810
|
#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2
|
#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1811
|
#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2
|
#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1812
|
#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_SAMPLE_RATE 0x1813
|
#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2
|
#define mmABM1_DC_ABM1_LS_SAMPLE_RATE 0x1814
|
#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1815
|
#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1816
|
#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2
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#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1817
|
#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2
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#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1818
|
#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x1819
|
#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2
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#define mmABM1_DC_ABM1_HG_RESULT_1 0x181a
|
#define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 2
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#define mmABM1_DC_ABM1_HG_RESULT_2 0x181b
|
#define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_3 0x181c
|
#define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 2
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#define mmABM1_DC_ABM1_HG_RESULT_4 0x181d
|
#define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_5 0x181e
|
#define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_6 0x181f
|
#define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_7 0x1820
|
#define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_8 0x1821
|
#define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_9 0x1822
|
#define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 2
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#define mmABM1_DC_ABM1_HG_RESULT_10 0x1823
|
#define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 2
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#define mmABM1_DC_ABM1_HG_RESULT_11 0x1824
|
#define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_12 0x1825
|
#define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_13 0x1826
|
#define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_14 0x1827
|
#define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_15 0x1828
|
#define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_16 0x1829
|
#define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_17 0x182a
|
#define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_18 0x182b
|
#define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_19 0x182c
|
#define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_20 0x182d
|
#define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_21 0x182e
|
#define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_22 0x182f
|
#define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_23 0x1830
|
#define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 2
|
#define mmABM1_DC_ABM1_HG_RESULT_24 0x1831
|
#define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 2
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#define mmABM1_DC_ABM1_BL_MASTER_LOCK 0x1832
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#define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 2
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|
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// addressBlock: dce_dc_opp_fmt0_dispdec
|
// base address: 0x0
|
#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c
|
#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d
|
#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e
|
#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f
|
#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT0_FMT_CONTROL 0x1840
|
#define mmFMT0_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841
|
#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842
|
#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843
|
#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844
|
#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT0_FMT_CLAMP_CNTL 0x1848
|
#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1849
|
#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x184a
|
#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
|
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// addressBlock: dce_dc_opp_oppbuf0_dispdec
|
// base address: 0x0
|
#define mmOPPBUF0_OPPBUF_CONTROL 0x1884
|
#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885
|
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886
|
#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe0_dispdec
|
// base address: 0x0
|
#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c
|
#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec
|
// base address: 0x0
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
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#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892
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#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
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#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894
|
#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
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#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895
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#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
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// addressBlock: dce_dc_opp_fmt1_dispdec
|
// base address: 0x168
|
#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896
|
#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897
|
#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
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#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898
|
#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
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#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899
|
#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT1_FMT_CONTROL 0x189a
|
#define mmFMT1_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b
|
#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
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#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c
|
#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d
|
#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
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#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e
|
#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT1_FMT_CLAMP_CNTL 0x18a2
|
#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2
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#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a3
|
#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a4
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#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_opp_oppbuf1_dispdec
|
// base address: 0x168
|
#define mmOPPBUF1_OPPBUF_CONTROL 0x18de
|
#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df
|
#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
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#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0
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#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
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// addressBlock: dce_dc_opp_opp_pipe1_dispdec
|
// base address: 0x168
|
#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6
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#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec
|
// base address: 0x168
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
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#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef
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#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
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// addressBlock: dce_dc_opp_fmt2_dispdec
|
// base address: 0x2d0
|
#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0
|
#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1
|
#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2
|
#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
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#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3
|
#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT2_FMT_CONTROL 0x18f4
|
#define mmFMT2_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5
|
#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6
|
#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7
|
#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8
|
#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT2_FMT_CLAMP_CNTL 0x18fc
|
#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fd
|
#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fe
|
#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_opp_oppbuf2_dispdec
|
// base address: 0x2d0
|
#define mmOPPBUF2_OPPBUF_CONTROL 0x1938
|
#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939
|
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a
|
#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
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// addressBlock: dce_dc_opp_opp_pipe2_dispdec
|
// base address: 0x2d0
|
#define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940
|
#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2
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|
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// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec
|
// base address: 0x2d0
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949
|
#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
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|
|
// addressBlock: dce_dc_opp_fmt3_dispdec
|
// base address: 0x438
|
#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a
|
#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b
|
#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c
|
#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d
|
#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT3_FMT_CONTROL 0x194e
|
#define mmFMT3_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f
|
#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950
|
#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951
|
#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952
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#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT3_FMT_CLAMP_CNTL 0x1956
|
#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1957
|
#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1958
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#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
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// addressBlock: dce_dc_opp_oppbuf3_dispdec
|
// base address: 0x438
|
#define mmOPPBUF3_OPPBUF_CONTROL 0x1992
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#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993
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#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
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#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994
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#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
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// addressBlock: dce_dc_opp_opp_pipe3_dispdec
|
// base address: 0x438
|
#define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a
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#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2
|
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// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec
|
// base address: 0x438
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f
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#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2
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#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2
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#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3
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#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
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|
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// addressBlock: dce_dc_opp_fmt4_dispdec
|
// base address: 0x5a0
|
#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4
|
#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5
|
#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6
|
#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7
|
#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT4_FMT_CONTROL 0x19a8
|
#define mmFMT4_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9
|
#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa
|
#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab
|
#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac
|
#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT4_FMT_CLAMP_CNTL 0x19b0
|
#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19b1
|
#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19b2
|
#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_oppbuf4_dispdec
|
// base address: 0x5a0
|
#define mmOPPBUF4_OPPBUF_CONTROL 0x19ec
|
#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed
|
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee
|
#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe4_dispdec
|
// base address: 0x5a0
|
#define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4
|
#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec
|
// base address: 0x5a0
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd
|
#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_fmt5_dispdec
|
// base address: 0x708
|
#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe
|
#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
|
#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff
|
#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2
|
#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00
|
#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2
|
#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01
|
#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2
|
#define mmFMT5_FMT_CONTROL 0x1a02
|
#define mmFMT5_FMT_CONTROL_BASE_IDX 2
|
#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03
|
#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2
|
#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04
|
#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2
|
#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05
|
#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2
|
#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06
|
#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2
|
#define mmFMT5_FMT_CLAMP_CNTL 0x1a0a
|
#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2
|
#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a0b
|
#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2
|
#define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a0c
|
#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_oppbuf5_dispdec
|
// base address: 0x708
|
#define mmOPPBUF5_OPPBUF_CONTROL 0x1a46
|
#define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2
|
#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47
|
#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2
|
#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48
|
#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe5_dispdec
|
// base address: 0x708
|
#define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e
|
#define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec
|
// base address: 0x708
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57
|
#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_top_dispdec
|
// base address: 0x0
|
#define mmOPP_TOP_CLK_CONTROL 0x1a5e
|
#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec
|
// base address: 0x6af8
|
#define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x1abe
|
#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x1abf
|
#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFCOUNTER_STATE 0x1ac0
|
#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_CNTL 0x1ac1
|
#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_CNTL2 0x1ac2
|
#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1ac3
|
#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x1ac4
|
#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_HI 0x1ac5
|
#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2
|
#define mmDC_PERFMON17_PERFMON_LOW 0x1ac6
|
#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_odm0_dispdec
|
// base address: 0x0
|
#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca
|
#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
|
#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb
|
#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
|
#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acd
|
#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
|
#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1acf
|
#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_optc_odm1_dispdec
|
// base address: 0x40
|
#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada
|
#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
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#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb
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#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
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#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1add
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#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
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#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1adf
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#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_odm2_dispdec
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// base address: 0x80
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#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea
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#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
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#define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb
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#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
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#define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aed
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#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
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#define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1aef
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#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_odm3_dispdec
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// base address: 0xc0
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#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa
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#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
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#define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb
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#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
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#define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1afd
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#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
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#define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1aff
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#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_odm4_dispdec
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// base address: 0x100
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#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a
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#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
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#define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b
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#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
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#define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0d
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#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
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#define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b0f
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#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_odm5_dispdec
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// base address: 0x140
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#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a
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#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2
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#define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b
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#define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2
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#define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1d
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#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2
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#define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b1f
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#define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_otg0_dispdec
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// base address: 0x0
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#define mmOTG0_OTG_H_TOTAL 0x1b2a
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#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2
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#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b
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#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2
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#define mmOTG0_OTG_H_SYNC_A 0x1b2c
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#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2
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#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d
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#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e
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#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_V_TOTAL 0x1b2f
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#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2
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#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30
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#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2
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#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31
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#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2
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#define mmOTG0_OTG_V_TOTAL_MID 0x1b32
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#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2
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#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33
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#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34
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#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35
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#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_V_BLANK_START_END 0x1b36
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#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2
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#define mmOTG0_OTG_V_SYNC_A 0x1b37
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#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2
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#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38
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#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_TRIGA_CNTL 0x1b39
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#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a
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#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b
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#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c
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#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d
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#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e
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#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f
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#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmOTG0_OTG_AVSYNC_COUNTER 0x1b40
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#define mmOTG0_OTG_AVSYNC_COUNTER_BASE_IDX 2
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#define mmOTG0_OTG_CONTROL 0x1b41
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#define mmOTG0_OTG_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_BLANK_CONTROL 0x1b42
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#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_PIPE_ABORT_CONTROL 0x1b43
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#define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44
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#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45
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#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_FIELD_INDICATION_CONTROL 0x1b46
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#define mmOTG0_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47
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#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48
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#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmOTG0_OTG_STATUS 0x1b49
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#define mmOTG0_OTG_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_STATUS_POSITION 0x1b4a
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#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b
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#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c
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#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d
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#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2
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#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e
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#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2
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#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f
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#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_COUNT_RESET 0x1b50
|
#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2
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#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51
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#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52
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#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_STEREO_STATUS 0x1b53
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#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_STEREO_CONTROL 0x1b54
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#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55
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#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56
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#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57
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#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58
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#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59
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#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a
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#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b
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#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_TEST_PATTERN_CONTROL 0x1b5c
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#define mmOTG0_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_TEST_PATTERN_PARAMETERS 0x1b5d
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#define mmOTG0_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
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#define mmOTG0_OTG_TEST_PATTERN_COLOR 0x1b5e
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#define mmOTG0_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
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#define mmOTG0_OTG_MASTER_EN 0x1b5f
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#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2
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#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b61
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#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b62
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#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmOTG0_OTG_BLACK_COLOR 0x1b63
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#define mmOTG0_OTG_BLACK_COLOR_BASE_IDX 2
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#define mmOTG0_OTG_BLACK_COLOR_EXT 0x1b64
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#define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b65
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#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b66
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#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b67
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#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b68
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#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b69
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#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b6a
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#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC_CNTL 0x1b6b
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#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2
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#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6c
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#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6d
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#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6e
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#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6f
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#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC0_DATA_RG 0x1b70
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#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2
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#define mmOTG0_OTG_CRC0_DATA_B 0x1b71
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#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2
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#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b72
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#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b73
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#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b74
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#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b75
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#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_CRC1_DATA_RG 0x1b76
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#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2
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#define mmOTG0_OTG_CRC1_DATA_B 0x1b77
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#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2
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#define mmOTG0_OTG_CRC2_DATA_RG 0x1b78
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#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2
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#define mmOTG0_OTG_CRC2_DATA_B 0x1b79
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#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2
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#define mmOTG0_OTG_CRC3_DATA_RG 0x1b7a
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#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2
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#define mmOTG0_OTG_CRC3_DATA_B 0x1b7b
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#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2
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#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7c
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#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7d
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#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b84
|
#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b85
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#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b86
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#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b87
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#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmOTG0_OTG_CLOCK_CONTROL 0x1b88
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#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b89
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#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2
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#define mmOTG0_OTG_VUPDATE_PARAM 0x1b8a
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#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2
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#define mmOTG0_OTG_VREADY_PARAM 0x1b8b
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#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2
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#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8c
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#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8d
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#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG0_OTG_GSL_CONTROL 0x1b8e
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#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8f
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#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2
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#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b90
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#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2
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#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b91
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#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
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#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b92
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#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2
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#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b93
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#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2
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#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b94
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#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2
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#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b95
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#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2
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#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b96
|
#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b97
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#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS 0x1b98
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#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
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#define mmOTG0_OTG_DRR_CONTROL 0x1b99
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#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_REQUEST_CONTROL 0x1b9a
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#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2
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#define mmOTG0_OTG_SPARE_REGISTER 0x1b9b
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#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2
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|
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// addressBlock: dce_dc_optc_otg1_dispdec
|
// base address: 0x200
|
#define mmOTG1_OTG_H_TOTAL 0x1baa
|
#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2
|
#define mmOTG1_OTG_H_BLANK_START_END 0x1bab
|
#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2
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#define mmOTG1_OTG_H_SYNC_A 0x1bac
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#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2
|
#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad
|
#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae
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#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2
|
#define mmOTG1_OTG_V_TOTAL 0x1baf
|
#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2
|
#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0
|
#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2
|
#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1
|
#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2
|
#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2
|
#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2
|
#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3
|
#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2
|
#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4
|
#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
|
#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5
|
#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
|
#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6
|
#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2
|
#define mmOTG1_OTG_V_SYNC_A 0x1bb7
|
#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2
|
#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8
|
#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2
|
#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9
|
#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2
|
#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba
|
#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb
|
#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2
|
#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc
|
#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
|
#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd
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#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe
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#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf
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#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmOTG1_OTG_AVSYNC_COUNTER 0x1bc0
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#define mmOTG1_OTG_AVSYNC_COUNTER_BASE_IDX 2
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#define mmOTG1_OTG_CONTROL 0x1bc1
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#define mmOTG1_OTG_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2
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#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_PIPE_ABORT_CONTROL 0x1bc3
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#define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4
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#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5
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#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_FIELD_INDICATION_CONTROL 0x1bc6
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#define mmOTG1_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7
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#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8
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#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmOTG1_OTG_STATUS 0x1bc9
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#define mmOTG1_OTG_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_STATUS_POSITION 0x1bca
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#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb
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#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc
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#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd
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#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2
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#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce
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#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2
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#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf
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#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_COUNT_RESET 0x1bd0
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#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2
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#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1
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#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2
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#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_STEREO_STATUS 0x1bd3
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#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4
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#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5
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#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6
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#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7
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#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8
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#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9
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#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_UPDATE_LOCK 0x1bda
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#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb
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#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_TEST_PATTERN_CONTROL 0x1bdc
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#define mmOTG1_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_TEST_PATTERN_PARAMETERS 0x1bdd
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#define mmOTG1_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
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#define mmOTG1_OTG_TEST_PATTERN_COLOR 0x1bde
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#define mmOTG1_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
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#define mmOTG1_OTG_MASTER_EN 0x1bdf
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#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2
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#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1be1
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#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1be2
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#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmOTG1_OTG_BLACK_COLOR 0x1be3
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#define mmOTG1_OTG_BLACK_COLOR_BASE_IDX 2
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#define mmOTG1_OTG_BLACK_COLOR_EXT 0x1be4
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#define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be5
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#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be6
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#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be7
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#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be8
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#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be9
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#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1bea
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#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC_CNTL 0x1beb
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#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2
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#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bec
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#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1bed
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#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bee
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#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bef
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#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC0_DATA_RG 0x1bf0
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#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2
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#define mmOTG1_OTG_CRC0_DATA_B 0x1bf1
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#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2
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#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf2
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#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf3
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#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf4
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#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf5
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#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf6
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#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2
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#define mmOTG1_OTG_CRC1_DATA_B 0x1bf7
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#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2
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#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf8
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#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2
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#define mmOTG1_OTG_CRC2_DATA_B 0x1bf9
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#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2
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#define mmOTG1_OTG_CRC3_DATA_RG 0x1bfa
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#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2
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#define mmOTG1_OTG_CRC3_DATA_B 0x1bfb
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#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2
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#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfc
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#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfd
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#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c04
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#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c05
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#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c06
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#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c07
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#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmOTG1_OTG_CLOCK_CONTROL 0x1c08
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#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c09
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#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2
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#define mmOTG1_OTG_VUPDATE_PARAM 0x1c0a
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#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2
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#define mmOTG1_OTG_VREADY_PARAM 0x1c0b
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#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2
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#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0c
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#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0d
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#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG1_OTG_GSL_CONTROL 0x1c0e
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#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0f
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#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2
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#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c10
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#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2
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#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c11
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#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
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#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c12
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#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2
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#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c13
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#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2
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#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c14
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#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2
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#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c15
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#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2
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#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c16
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#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c17
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#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS 0x1c18
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#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
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#define mmOTG1_OTG_DRR_CONTROL 0x1c19
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#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_REQUEST_CONTROL 0x1c1a
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#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2
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#define mmOTG1_OTG_SPARE_REGISTER 0x1c1b
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#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_otg2_dispdec
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// base address: 0x400
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#define mmOTG2_OTG_H_TOTAL 0x1c2a
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#define mmOTG2_OTG_H_TOTAL_BASE_IDX 2
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#define mmOTG2_OTG_H_BLANK_START_END 0x1c2b
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#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2
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#define mmOTG2_OTG_H_SYNC_A 0x1c2c
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#define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2
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#define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d
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#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e
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#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_V_TOTAL 0x1c2f
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#define mmOTG2_OTG_V_TOTAL_BASE_IDX 2
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#define mmOTG2_OTG_V_TOTAL_MIN 0x1c30
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#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2
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#define mmOTG2_OTG_V_TOTAL_MAX 0x1c31
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#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2
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#define mmOTG2_OTG_V_TOTAL_MID 0x1c32
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#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2
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#define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33
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#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34
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#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35
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#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_V_BLANK_START_END 0x1c36
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#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2
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#define mmOTG2_OTG_V_SYNC_A 0x1c37
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#define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2
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#define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38
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#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_TRIGA_CNTL 0x1c39
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#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a
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#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG2_OTG_TRIGB_CNTL 0x1c3b
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#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c
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#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d
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#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_FLOW_CONTROL 0x1c3e
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#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f
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#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmOTG2_OTG_AVSYNC_COUNTER 0x1c40
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#define mmOTG2_OTG_AVSYNC_COUNTER_BASE_IDX 2
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#define mmOTG2_OTG_CONTROL 0x1c41
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#define mmOTG2_OTG_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_BLANK_CONTROL 0x1c42
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#define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_PIPE_ABORT_CONTROL 0x1c43
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#define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44
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#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_INTERLACE_STATUS 0x1c45
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#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_FIELD_INDICATION_CONTROL 0x1c46
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#define mmOTG2_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47
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#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48
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#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmOTG2_OTG_STATUS 0x1c49
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#define mmOTG2_OTG_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_STATUS_POSITION 0x1c4a
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#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b
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#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c
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#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d
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#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2
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#define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e
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#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2
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#define mmOTG2_OTG_COUNT_CONTROL 0x1c4f
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#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_COUNT_RESET 0x1c50
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#define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2
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#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51
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#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52
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#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_STEREO_STATUS 0x1c53
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#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_STEREO_CONTROL 0x1c54
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#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55
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#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56
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#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57
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#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58
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#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59
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#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_UPDATE_LOCK 0x1c5a
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#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b
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#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_TEST_PATTERN_CONTROL 0x1c5c
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#define mmOTG2_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_TEST_PATTERN_PARAMETERS 0x1c5d
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#define mmOTG2_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
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#define mmOTG2_OTG_TEST_PATTERN_COLOR 0x1c5e
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#define mmOTG2_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
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#define mmOTG2_OTG_MASTER_EN 0x1c5f
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#define mmOTG2_OTG_MASTER_EN_BASE_IDX 2
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#define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c61
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#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c62
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#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmOTG2_OTG_BLACK_COLOR 0x1c63
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#define mmOTG2_OTG_BLACK_COLOR_BASE_IDX 2
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#define mmOTG2_OTG_BLACK_COLOR_EXT 0x1c64
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#define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c65
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#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c66
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#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c67
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#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c68
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#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c69
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#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c6a
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#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC_CNTL 0x1c6b
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#define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2
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#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6c
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#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6d
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#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6e
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#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6f
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#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC0_DATA_RG 0x1c70
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#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2
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#define mmOTG2_OTG_CRC0_DATA_B 0x1c71
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#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2
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#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c72
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#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c73
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#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c74
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#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c75
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#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_CRC1_DATA_RG 0x1c76
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#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2
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#define mmOTG2_OTG_CRC1_DATA_B 0x1c77
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#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2
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#define mmOTG2_OTG_CRC2_DATA_RG 0x1c78
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#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2
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#define mmOTG2_OTG_CRC2_DATA_B 0x1c79
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#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2
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#define mmOTG2_OTG_CRC3_DATA_RG 0x1c7a
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#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2
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#define mmOTG2_OTG_CRC3_DATA_B 0x1c7b
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#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2
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#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7c
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#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7d
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#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c84
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#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c85
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#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c86
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#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c87
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#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmOTG2_OTG_CLOCK_CONTROL 0x1c88
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#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_VSTARTUP_PARAM 0x1c89
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#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2
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#define mmOTG2_OTG_VUPDATE_PARAM 0x1c8a
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#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2
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#define mmOTG2_OTG_VREADY_PARAM 0x1c8b
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#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2
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#define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8c
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#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8d
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#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG2_OTG_GSL_CONTROL 0x1c8e
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#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_GSL_WINDOW_X 0x1c8f
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#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2
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#define mmOTG2_OTG_GSL_WINDOW_Y 0x1c90
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#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2
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#define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c91
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#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
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#define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c92
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#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2
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#define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c93
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#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2
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#define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c94
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#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2
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#define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c95
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#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2
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#define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c96
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#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c97
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#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS 0x1c98
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#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
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#define mmOTG2_OTG_DRR_CONTROL 0x1c99
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#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_REQUEST_CONTROL 0x1c9a
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#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2
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#define mmOTG2_OTG_SPARE_REGISTER 0x1c9b
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#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_otg3_dispdec
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// base address: 0x600
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#define mmOTG3_OTG_H_TOTAL 0x1caa
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#define mmOTG3_OTG_H_TOTAL_BASE_IDX 2
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#define mmOTG3_OTG_H_BLANK_START_END 0x1cab
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#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2
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#define mmOTG3_OTG_H_SYNC_A 0x1cac
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#define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2
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#define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad
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#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_H_TIMING_CNTL 0x1cae
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#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_V_TOTAL 0x1caf
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#define mmOTG3_OTG_V_TOTAL_BASE_IDX 2
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#define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0
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#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2
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#define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1
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#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2
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#define mmOTG3_OTG_V_TOTAL_MID 0x1cb2
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#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2
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#define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3
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#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4
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#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5
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#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_V_BLANK_START_END 0x1cb6
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#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2
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#define mmOTG3_OTG_V_SYNC_A 0x1cb7
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#define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2
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#define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8
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#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_TRIGA_CNTL 0x1cb9
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#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba
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#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG3_OTG_TRIGB_CNTL 0x1cbb
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#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc
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#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd
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#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_FLOW_CONTROL 0x1cbe
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#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf
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#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmOTG3_OTG_AVSYNC_COUNTER 0x1cc0
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#define mmOTG3_OTG_AVSYNC_COUNTER_BASE_IDX 2
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#define mmOTG3_OTG_CONTROL 0x1cc1
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#define mmOTG3_OTG_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_BLANK_CONTROL 0x1cc2
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#define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_PIPE_ABORT_CONTROL 0x1cc3
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#define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4
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#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5
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#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_FIELD_INDICATION_CONTROL 0x1cc6
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#define mmOTG3_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7
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#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8
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#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmOTG3_OTG_STATUS 0x1cc9
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#define mmOTG3_OTG_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_STATUS_POSITION 0x1cca
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#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb
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#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc
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#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd
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#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2
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#define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce
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#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2
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#define mmOTG3_OTG_COUNT_CONTROL 0x1ccf
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#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_COUNT_RESET 0x1cd0
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#define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2
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#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1
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#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2
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#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_STEREO_STATUS 0x1cd3
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#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_STEREO_CONTROL 0x1cd4
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#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5
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#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6
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#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7
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#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8
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#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9
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#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_UPDATE_LOCK 0x1cda
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#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb
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#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_TEST_PATTERN_CONTROL 0x1cdc
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#define mmOTG3_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_TEST_PATTERN_PARAMETERS 0x1cdd
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#define mmOTG3_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
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#define mmOTG3_OTG_TEST_PATTERN_COLOR 0x1cde
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#define mmOTG3_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
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#define mmOTG3_OTG_MASTER_EN 0x1cdf
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#define mmOTG3_OTG_MASTER_EN_BASE_IDX 2
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#define mmOTG3_OTG_BLANK_DATA_COLOR 0x1ce1
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#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1ce2
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#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmOTG3_OTG_BLACK_COLOR 0x1ce3
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#define mmOTG3_OTG_BLACK_COLOR_BASE_IDX 2
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#define mmOTG3_OTG_BLACK_COLOR_EXT 0x1ce4
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#define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce5
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#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce6
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#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce7
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#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce8
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#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce9
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#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1cea
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#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC_CNTL 0x1ceb
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#define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2
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#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cec
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#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ced
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#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cee
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#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1cef
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#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC0_DATA_RG 0x1cf0
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#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2
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#define mmOTG3_OTG_CRC0_DATA_B 0x1cf1
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#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2
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#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf2
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#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf3
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#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf4
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#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf5
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#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_CRC1_DATA_RG 0x1cf6
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#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2
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#define mmOTG3_OTG_CRC1_DATA_B 0x1cf7
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#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2
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#define mmOTG3_OTG_CRC2_DATA_RG 0x1cf8
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#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2
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#define mmOTG3_OTG_CRC2_DATA_B 0x1cf9
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#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2
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#define mmOTG3_OTG_CRC3_DATA_RG 0x1cfa
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#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2
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#define mmOTG3_OTG_CRC3_DATA_B 0x1cfb
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#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2
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#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfc
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#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfd
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#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d04
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#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d05
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#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d06
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#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d07
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#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmOTG3_OTG_CLOCK_CONTROL 0x1d08
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#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_VSTARTUP_PARAM 0x1d09
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#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2
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#define mmOTG3_OTG_VUPDATE_PARAM 0x1d0a
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#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2
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#define mmOTG3_OTG_VREADY_PARAM 0x1d0b
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#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2
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#define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0c
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#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0d
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#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG3_OTG_GSL_CONTROL 0x1d0e
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#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_GSL_WINDOW_X 0x1d0f
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#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2
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#define mmOTG3_OTG_GSL_WINDOW_Y 0x1d10
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#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2
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#define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d11
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#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
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#define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d12
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#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2
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#define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d13
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#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2
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#define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d14
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#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2
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#define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d15
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#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2
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#define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d16
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#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d17
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#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS 0x1d18
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#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
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#define mmOTG3_OTG_DRR_CONTROL 0x1d19
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#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_REQUEST_CONTROL 0x1d1a
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#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2
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#define mmOTG3_OTG_SPARE_REGISTER 0x1d1b
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#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_otg4_dispdec
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// base address: 0x800
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#define mmOTG4_OTG_H_TOTAL 0x1d2a
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#define mmOTG4_OTG_H_TOTAL_BASE_IDX 2
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#define mmOTG4_OTG_H_BLANK_START_END 0x1d2b
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#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2
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#define mmOTG4_OTG_H_SYNC_A 0x1d2c
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#define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2
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#define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d
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#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e
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#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_V_TOTAL 0x1d2f
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#define mmOTG4_OTG_V_TOTAL_BASE_IDX 2
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#define mmOTG4_OTG_V_TOTAL_MIN 0x1d30
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#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2
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#define mmOTG4_OTG_V_TOTAL_MAX 0x1d31
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#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2
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#define mmOTG4_OTG_V_TOTAL_MID 0x1d32
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#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2
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#define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33
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#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34
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#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35
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#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_V_BLANK_START_END 0x1d36
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#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2
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#define mmOTG4_OTG_V_SYNC_A 0x1d37
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#define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2
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#define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38
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#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_TRIGA_CNTL 0x1d39
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#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a
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#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG4_OTG_TRIGB_CNTL 0x1d3b
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#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c
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#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d
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#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_FLOW_CONTROL 0x1d3e
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#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f
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#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmOTG4_OTG_AVSYNC_COUNTER 0x1d40
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#define mmOTG4_OTG_AVSYNC_COUNTER_BASE_IDX 2
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#define mmOTG4_OTG_CONTROL 0x1d41
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#define mmOTG4_OTG_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_BLANK_CONTROL 0x1d42
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#define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_PIPE_ABORT_CONTROL 0x1d43
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#define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44
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#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_INTERLACE_STATUS 0x1d45
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#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_FIELD_INDICATION_CONTROL 0x1d46
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#define mmOTG4_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47
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#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48
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#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmOTG4_OTG_STATUS 0x1d49
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#define mmOTG4_OTG_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_STATUS_POSITION 0x1d4a
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#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b
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#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c
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#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d
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#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2
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#define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e
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#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2
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#define mmOTG4_OTG_COUNT_CONTROL 0x1d4f
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#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_COUNT_RESET 0x1d50
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#define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2
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#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51
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#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52
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#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_STEREO_STATUS 0x1d53
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#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_STEREO_CONTROL 0x1d54
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#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55
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#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56
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#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57
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#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58
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#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59
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#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_UPDATE_LOCK 0x1d5a
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#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b
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#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_TEST_PATTERN_CONTROL 0x1d5c
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#define mmOTG4_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_TEST_PATTERN_PARAMETERS 0x1d5d
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#define mmOTG4_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
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#define mmOTG4_OTG_TEST_PATTERN_COLOR 0x1d5e
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#define mmOTG4_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
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#define mmOTG4_OTG_MASTER_EN 0x1d5f
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#define mmOTG4_OTG_MASTER_EN_BASE_IDX 2
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#define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d61
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#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d62
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#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmOTG4_OTG_BLACK_COLOR 0x1d63
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#define mmOTG4_OTG_BLACK_COLOR_BASE_IDX 2
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#define mmOTG4_OTG_BLACK_COLOR_EXT 0x1d64
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#define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d65
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#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d66
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#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d67
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#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d68
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#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d69
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#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d6a
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#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC_CNTL 0x1d6b
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#define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2
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#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6c
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#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6d
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#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6e
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#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6f
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#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC0_DATA_RG 0x1d70
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#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2
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#define mmOTG4_OTG_CRC0_DATA_B 0x1d71
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#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2
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#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d72
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#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d73
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#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d74
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#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d75
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#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_CRC1_DATA_RG 0x1d76
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#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2
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#define mmOTG4_OTG_CRC1_DATA_B 0x1d77
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#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2
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#define mmOTG4_OTG_CRC2_DATA_RG 0x1d78
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#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2
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#define mmOTG4_OTG_CRC2_DATA_B 0x1d79
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#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2
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#define mmOTG4_OTG_CRC3_DATA_RG 0x1d7a
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#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2
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#define mmOTG4_OTG_CRC3_DATA_B 0x1d7b
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#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2
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#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7c
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#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7d
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#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d84
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#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d85
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#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d86
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#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d87
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#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmOTG4_OTG_CLOCK_CONTROL 0x1d88
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#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_VSTARTUP_PARAM 0x1d89
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#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2
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#define mmOTG4_OTG_VUPDATE_PARAM 0x1d8a
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#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2
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#define mmOTG4_OTG_VREADY_PARAM 0x1d8b
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#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2
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#define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8c
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#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8d
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#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG4_OTG_GSL_CONTROL 0x1d8e
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#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_GSL_WINDOW_X 0x1d8f
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#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2
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#define mmOTG4_OTG_GSL_WINDOW_Y 0x1d90
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#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2
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#define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d91
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#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
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#define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d92
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#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2
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#define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d93
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#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2
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#define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d94
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#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2
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#define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d95
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#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2
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#define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d96
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#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d97
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#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS 0x1d98
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#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
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#define mmOTG4_OTG_DRR_CONTROL 0x1d99
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#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_REQUEST_CONTROL 0x1d9a
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#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2
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#define mmOTG4_OTG_SPARE_REGISTER 0x1d9b
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#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2
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// addressBlock: dce_dc_optc_otg5_dispdec
|
// base address: 0xa00
|
#define mmOTG5_OTG_H_TOTAL 0x1daa
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#define mmOTG5_OTG_H_TOTAL_BASE_IDX 2
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#define mmOTG5_OTG_H_BLANK_START_END 0x1dab
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#define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2
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#define mmOTG5_OTG_H_SYNC_A 0x1dac
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#define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2
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#define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad
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#define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_H_TIMING_CNTL 0x1dae
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#define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_V_TOTAL 0x1daf
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#define mmOTG5_OTG_V_TOTAL_BASE_IDX 2
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#define mmOTG5_OTG_V_TOTAL_MIN 0x1db0
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#define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2
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#define mmOTG5_OTG_V_TOTAL_MAX 0x1db1
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#define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2
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#define mmOTG5_OTG_V_TOTAL_MID 0x1db2
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#define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2
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#define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3
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#define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4
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#define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5
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#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_V_BLANK_START_END 0x1db6
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#define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2
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#define mmOTG5_OTG_V_SYNC_A 0x1db7
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#define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2
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#define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8
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#define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_TRIGA_CNTL 0x1db9
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#define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba
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#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG5_OTG_TRIGB_CNTL 0x1dbb
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#define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc
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#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2
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#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd
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#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_FLOW_CONTROL 0x1dbe
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#define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf
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#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2
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#define mmOTG5_OTG_AVSYNC_COUNTER 0x1dc0
|
#define mmOTG5_OTG_AVSYNC_COUNTER_BASE_IDX 2
|
#define mmOTG5_OTG_CONTROL 0x1dc1
|
#define mmOTG5_OTG_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_BLANK_CONTROL 0x1dc2
|
#define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_PIPE_ABORT_CONTROL 0x1dc3
|
#define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4
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#define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5
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#define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_FIELD_INDICATION_CONTROL 0x1dc6
|
#define mmOTG5_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7
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#define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2
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#define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8
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#define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2
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#define mmOTG5_OTG_STATUS 0x1dc9
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#define mmOTG5_OTG_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_STATUS_POSITION 0x1dca
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#define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb
|
#define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc
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#define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2
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#define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd
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#define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2
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#define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce
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#define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2
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#define mmOTG5_OTG_COUNT_CONTROL 0x1dcf
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#define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_COUNT_RESET 0x1dd0
|
#define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2
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#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1
|
#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2
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#define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2
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#define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_STEREO_STATUS 0x1dd3
|
#define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2
|
#define mmOTG5_OTG_STEREO_CONTROL 0x1dd4
|
#define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5
|
#define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6
|
#define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7
|
#define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8
|
#define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2
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#define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9
|
#define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_UPDATE_LOCK 0x1dda
|
#define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb
|
#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_TEST_PATTERN_CONTROL 0x1ddc
|
#define mmOTG5_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2
|
#define mmOTG5_OTG_TEST_PATTERN_PARAMETERS 0x1ddd
|
#define mmOTG5_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2
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#define mmOTG5_OTG_TEST_PATTERN_COLOR 0x1dde
|
#define mmOTG5_OTG_TEST_PATTERN_COLOR_BASE_IDX 2
|
#define mmOTG5_OTG_MASTER_EN 0x1ddf
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#define mmOTG5_OTG_MASTER_EN_BASE_IDX 2
|
#define mmOTG5_OTG_BLANK_DATA_COLOR 0x1de1
|
#define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2
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#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1de2
|
#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2
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#define mmOTG5_OTG_BLACK_COLOR 0x1de3
|
#define mmOTG5_OTG_BLACK_COLOR_BASE_IDX 2
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#define mmOTG5_OTG_BLACK_COLOR_EXT 0x1de4
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#define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX 2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de5
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#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de6
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#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de7
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#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de8
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#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de9
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#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2
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#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1dea
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#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC_CNTL 0x1deb
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#define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2
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#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dec
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#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ded
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#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dee
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#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1def
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#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC0_DATA_RG 0x1df0
|
#define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2
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#define mmOTG5_OTG_CRC0_DATA_B 0x1df1
|
#define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2
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#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df2
|
#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df3
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#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df4
|
#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df5
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#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_CRC1_DATA_RG 0x1df6
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#define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2
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#define mmOTG5_OTG_CRC1_DATA_B 0x1df7
|
#define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2
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#define mmOTG5_OTG_CRC2_DATA_RG 0x1df8
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#define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2
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#define mmOTG5_OTG_CRC2_DATA_B 0x1df9
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#define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2
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#define mmOTG5_OTG_CRC3_DATA_RG 0x1dfa
|
#define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2
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#define mmOTG5_OTG_CRC3_DATA_B 0x1dfb
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#define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2
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#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfc
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#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2
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#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfd
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#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2
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#define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e04
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#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e05
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#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e06
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#define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2
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#define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e07
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#define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2
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#define mmOTG5_OTG_CLOCK_CONTROL 0x1e08
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#define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_VSTARTUP_PARAM 0x1e09
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#define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2
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#define mmOTG5_OTG_VUPDATE_PARAM 0x1e0a
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#define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2
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#define mmOTG5_OTG_VREADY_PARAM 0x1e0b
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#define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2
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#define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0c
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#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0d
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#define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2
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#define mmOTG5_OTG_GSL_CONTROL 0x1e0e
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#define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_GSL_WINDOW_X 0x1e0f
|
#define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2
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#define mmOTG5_OTG_GSL_WINDOW_Y 0x1e10
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#define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2
|
#define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e11
|
#define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2
|
#define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e12
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#define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2
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#define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e13
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#define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2
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#define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e14
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#define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2
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#define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e15
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#define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2
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#define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e16
|
#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e17
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#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS 0x1e18
|
#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2
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#define mmOTG5_OTG_DRR_CONTROL 0x1e19
|
#define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_REQUEST_CONTROL 0x1e1a
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#define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2
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#define mmOTG5_OTG_SPARE_REGISTER 0x1e1b
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#define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2
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|
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// addressBlock: dce_dc_optc_optc_misc_dispdec
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// base address: 0x0
|
#define mmDWB_SOURCE_SELECT 0x1e2a
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#define mmDWB_SOURCE_SELECT_BASE_IDX 2
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#define mmGSL_SOURCE_SELECT 0x1e2b
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#define mmGSL_SOURCE_SELECT_BASE_IDX 2
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#define mmOPTC_CLOCK_CONTROL 0x1e2c
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#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2
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#define mmOPTC_MISC_SPARE_REGISTER 0x1e2d
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#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2
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|
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// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec
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// base address: 0x79a8
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#define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1e6a
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#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1e6b
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#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1e6c
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#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON18_PERFMON_CNTL 0x1e6d
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#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON18_PERFMON_CNTL2 0x1e6e
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#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1e6f
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#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1e70
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#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON18_PERFMON_HI 0x1e71
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#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON18_PERFMON_LOW 0x1e72
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#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2
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|
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// addressBlock: dce_dc_dio_dac_dispdec
|
// base address: 0x0
|
#define mmDAC_ENABLE 0x1e76
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#define mmDAC_ENABLE_BASE_IDX 2
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#define mmDAC_SOURCE_SELECT 0x1e77
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#define mmDAC_SOURCE_SELECT_BASE_IDX 2
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#define mmDAC_CRC_EN 0x1e78
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#define mmDAC_CRC_EN_BASE_IDX 2
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#define mmDAC_CRC_CONTROL 0x1e79
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#define mmDAC_CRC_CONTROL_BASE_IDX 2
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#define mmDAC_CRC_SIG_RGB_MASK 0x1e7a
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#define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2
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#define mmDAC_CRC_SIG_CONTROL_MASK 0x1e7b
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#define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2
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#define mmDAC_CRC_SIG_RGB 0x1e7c
|
#define mmDAC_CRC_SIG_RGB_BASE_IDX 2
|
#define mmDAC_CRC_SIG_CONTROL 0x1e7d
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#define mmDAC_CRC_SIG_CONTROL_BASE_IDX 2
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#define mmDAC_SYNC_TRISTATE_CONTROL 0x1e7e
|
#define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2
|
#define mmDAC_STEREOSYNC_SELECT 0x1e7f
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#define mmDAC_STEREOSYNC_SELECT_BASE_IDX 2
|
#define mmDAC_AUTODETECT_CONTROL 0x1e80
|
#define mmDAC_AUTODETECT_CONTROL_BASE_IDX 2
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#define mmDAC_AUTODETECT_CONTROL2 0x1e81
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#define mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2
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#define mmDAC_AUTODETECT_CONTROL3 0x1e82
|
#define mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2
|
#define mmDAC_AUTODETECT_STATUS 0x1e83
|
#define mmDAC_AUTODETECT_STATUS_BASE_IDX 2
|
#define mmDAC_AUTODETECT_INT_CONTROL 0x1e84
|
#define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2
|
#define mmDAC_FORCE_OUTPUT_CNTL 0x1e85
|
#define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2
|
#define mmDAC_FORCE_DATA 0x1e86
|
#define mmDAC_FORCE_DATA_BASE_IDX 2
|
#define mmDAC_POWERDOWN 0x1e87
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#define mmDAC_POWERDOWN_BASE_IDX 2
|
#define mmDAC_CONTROL 0x1e88
|
#define mmDAC_CONTROL_BASE_IDX 2
|
#define mmDAC_COMPARATOR_ENABLE 0x1e89
|
#define mmDAC_COMPARATOR_ENABLE_BASE_IDX 2
|
#define mmDAC_COMPARATOR_OUTPUT 0x1e8a
|
#define mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2
|
#define mmDAC_PWR_CNTL 0x1e8b
|
#define mmDAC_PWR_CNTL_BASE_IDX 2
|
#define mmDAC_DFT_CONFIG 0x1e8c
|
#define mmDAC_DFT_CONFIG_BASE_IDX 2
|
#define mmDAC_FIFO_STATUS 0x1e8d
|
#define mmDAC_FIFO_STATUS_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dout_i2c_dispdec
|
// base address: 0x0
|
#define mmDC_I2C_CONTROL 0x1e98
|
#define mmDC_I2C_CONTROL_BASE_IDX 2
|
#define mmDC_I2C_ARBITRATION 0x1e99
|
#define mmDC_I2C_ARBITRATION_BASE_IDX 2
|
#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a
|
#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmDC_I2C_SW_STATUS 0x1e9b
|
#define mmDC_I2C_SW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c
|
#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d
|
#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC3_HW_STATUS 0x1e9e
|
#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC4_HW_STATUS 0x1e9f
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#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC5_HW_STATUS 0x1ea0
|
#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC6_HW_STATUS 0x1ea1
|
#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDC1_SPEED 0x1ea2
|
#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2
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#define mmDC_I2C_DDC1_SETUP 0x1ea3
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#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC2_SPEED 0x1ea4
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#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2
|
#define mmDC_I2C_DDC2_SETUP 0x1ea5
|
#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2
|
#define mmDC_I2C_DDC3_SPEED 0x1ea6
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#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2
|
#define mmDC_I2C_DDC3_SETUP 0x1ea7
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#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC4_SPEED 0x1ea8
|
#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2
|
#define mmDC_I2C_DDC4_SETUP 0x1ea9
|
#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC5_SPEED 0x1eaa
|
#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2
|
#define mmDC_I2C_DDC5_SETUP 0x1eab
|
#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2
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#define mmDC_I2C_DDC6_SPEED 0x1eac
|
#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2
|
#define mmDC_I2C_DDC6_SETUP 0x1ead
|
#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2
|
#define mmDC_I2C_TRANSACTION0 0x1eae
|
#define mmDC_I2C_TRANSACTION0_BASE_IDX 2
|
#define mmDC_I2C_TRANSACTION1 0x1eaf
|
#define mmDC_I2C_TRANSACTION1_BASE_IDX 2
|
#define mmDC_I2C_TRANSACTION2 0x1eb0
|
#define mmDC_I2C_TRANSACTION2_BASE_IDX 2
|
#define mmDC_I2C_TRANSACTION3 0x1eb1
|
#define mmDC_I2C_TRANSACTION3_BASE_IDX 2
|
#define mmDC_I2C_DATA 0x1eb2
|
#define mmDC_I2C_DATA_BASE_IDX 2
|
#define mmDC_I2C_DDCVGA_HW_STATUS 0x1eb3
|
#define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2
|
#define mmDC_I2C_DDCVGA_SPEED 0x1eb4
|
#define mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2
|
#define mmDC_I2C_DDCVGA_SETUP 0x1eb5
|
#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2
|
#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6
|
#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2
|
#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7
|
#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_generic_i2c_dispdec
|
// base address: 0x0
|
#define mmGENERIC_I2C_CONTROL 0x1eb8
|
#define mmGENERIC_I2C_CONTROL_BASE_IDX 2
|
#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1eb9
|
#define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2
|
#define mmGENERIC_I2C_STATUS 0x1eba
|
#define mmGENERIC_I2C_STATUS_BASE_IDX 2
|
#define mmGENERIC_I2C_SPEED 0x1ebb
|
#define mmGENERIC_I2C_SPEED_BASE_IDX 2
|
#define mmGENERIC_I2C_SETUP 0x1ebc
|
#define mmGENERIC_I2C_SETUP_BASE_IDX 2
|
#define mmGENERIC_I2C_TRANSACTION 0x1ebd
|
#define mmGENERIC_I2C_TRANSACTION_BASE_IDX 2
|
#define mmGENERIC_I2C_DATA 0x1ebe
|
#define mmGENERIC_I2C_DATA_BASE_IDX 2
|
#define mmGENERIC_I2C_PIN_SELECTION 0x1ebf
|
#define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dio_misc_dispdec
|
// base address: 0x0
|
#define mmDIO_SCRATCH0 0x1eca
|
#define mmDIO_SCRATCH0_BASE_IDX 2
|
#define mmDIO_SCRATCH1 0x1ecb
|
#define mmDIO_SCRATCH1_BASE_IDX 2
|
#define mmDIO_SCRATCH2 0x1ecc
|
#define mmDIO_SCRATCH2_BASE_IDX 2
|
#define mmDIO_SCRATCH3 0x1ecd
|
#define mmDIO_SCRATCH3_BASE_IDX 2
|
#define mmDIO_SCRATCH4 0x1ece
|
#define mmDIO_SCRATCH4_BASE_IDX 2
|
#define mmDIO_SCRATCH5 0x1ecf
|
#define mmDIO_SCRATCH5_BASE_IDX 2
|
#define mmDIO_SCRATCH6 0x1ed0
|
#define mmDIO_SCRATCH6_BASE_IDX 2
|
#define mmDIO_SCRATCH7 0x1ed1
|
#define mmDIO_SCRATCH7_BASE_IDX 2
|
#define mmDCE_VCE_CONTROL 0x1ed2
|
#define mmDCE_VCE_CONTROL_BASE_IDX 2
|
#define mmDIO_MEM_PWR_STATUS 0x1edd
|
#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2
|
#define mmDIO_MEM_PWR_CTRL 0x1ede
|
#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2
|
#define mmDIO_MEM_PWR_CTRL2 0x1edf
|
#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2
|
#define mmDIO_CLK_CNTL 0x1ee0
|
#define mmDIO_CLK_CNTL_BASE_IDX 2
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#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4
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#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2
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#define mmDIO_STEREOSYNC_SEL 0x1eea
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#define mmDIO_STEREOSYNC_SEL_BASE_IDX 2
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#define mmDIO_SOFT_RESET 0x1eed
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#define mmDIO_SOFT_RESET_BASE_IDX 2
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#define mmDIG_SOFT_RESET 0x1eee
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#define mmDIG_SOFT_RESET_BASE_IDX 2
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#define mmDIO_MEM_PWR_STATUS1 0x1ef0
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#define mmDIO_MEM_PWR_STATUS1_BASE_IDX 2
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#define mmDIO_CLK_CNTL2 0x1ef2
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#define mmDIO_CLK_CNTL2_BASE_IDX 2
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#define mmDIO_CLK_CNTL3 0x1ef3
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#define mmDIO_CLK_CNTL3_BASE_IDX 2
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#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff
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#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2
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#define mmDIO_PSP_INTERRUPT_STATUS 0x1f00
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#define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIO_PSP_INTERRUPT_CLEAR 0x1f01
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#define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2
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#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02
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#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2
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#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03
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#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2
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// addressBlock: dce_dc_dio_hpd0_dispdec
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// base address: 0x0
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#define mmHPD0_DC_HPD_INT_STATUS 0x1f14
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#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15
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#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD0_DC_HPD_CONTROL 0x1f16
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#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17
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#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18
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#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_hpd1_dispdec
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// base address: 0x20
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#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c
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#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d
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#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD1_DC_HPD_CONTROL 0x1f1e
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#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f
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#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20
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#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_hpd2_dispdec
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// base address: 0x40
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#define mmHPD2_DC_HPD_INT_STATUS 0x1f24
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#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD2_DC_HPD_INT_CONTROL 0x1f25
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#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD2_DC_HPD_CONTROL 0x1f26
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#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27
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#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28
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#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_hpd3_dispdec
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// base address: 0x60
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#define mmHPD3_DC_HPD_INT_STATUS 0x1f2c
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#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d
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#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD3_DC_HPD_CONTROL 0x1f2e
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#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f
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#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30
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#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_hpd4_dispdec
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// base address: 0x80
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#define mmHPD4_DC_HPD_INT_STATUS 0x1f34
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#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD4_DC_HPD_INT_CONTROL 0x1f35
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#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD4_DC_HPD_CONTROL 0x1f36
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#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37
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#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38
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#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_hpd5_dispdec
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// base address: 0xa0
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#define mmHPD5_DC_HPD_INT_STATUS 0x1f3c
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#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2
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#define mmHPD5_DC_HPD_INT_CONTROL 0x1f3d
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#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2
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#define mmHPD5_DC_HPD_CONTROL 0x1f3e
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#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2
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#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x1f3f
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#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2
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#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x1f40
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#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2
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// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec
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// base address: 0x7d10
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#define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x1f44
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#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2
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#define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x1f45
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#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON19_PERFCOUNTER_STATE 0x1f46
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#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2
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#define mmDC_PERFMON19_PERFMON_CNTL 0x1f47
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#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2
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#define mmDC_PERFMON19_PERFMON_CNTL2 0x1f48
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#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2
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#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x1f49
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#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2
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#define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x1f4a
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#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2
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#define mmDC_PERFMON19_PERFMON_HI 0x1f4b
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#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2
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#define mmDC_PERFMON19_PERFMON_LOW 0x1f4c
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#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp_aux0_dispdec
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// base address: 0x0
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#define mmDP_AUX0_AUX_CONTROL 0x1f50
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#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51
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#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52
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#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53
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#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_SW_STATUS 0x1f54
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#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2
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#define mmDP_AUX0_AUX_LS_STATUS 0x1f55
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#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2
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#define mmDP_AUX0_AUX_SW_DATA 0x1f56
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#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX0_AUX_LS_DATA 0x1f57
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#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58
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#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59
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#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a
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#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b
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#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
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#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c
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#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d
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#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f
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#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60
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#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
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#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61
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#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp_aux1_dispdec
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// base address: 0x70
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#define mmDP_AUX1_AUX_CONTROL 0x1f6c
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#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d
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#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e
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#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f
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#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_SW_STATUS 0x1f70
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#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2
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#define mmDP_AUX1_AUX_LS_STATUS 0x1f71
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#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2
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#define mmDP_AUX1_AUX_SW_DATA 0x1f72
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#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX1_AUX_LS_DATA 0x1f73
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#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74
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#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75
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#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76
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#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77
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#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78
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#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79
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#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b
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#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c
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#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
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#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d
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#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp_aux2_dispdec
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// base address: 0xe0
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#define mmDP_AUX2_AUX_CONTROL 0x1f88
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#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2
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#define mmDP_AUX2_AUX_SW_CONTROL 0x1f89
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#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a
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#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b
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#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX2_AUX_SW_STATUS 0x1f8c
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#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
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#define mmDP_AUX2_AUX_LS_STATUS 0x1f8d
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#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2
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#define mmDP_AUX2_AUX_SW_DATA 0x1f8e
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#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX2_AUX_LS_DATA 0x1f8f
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#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90
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#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
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#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91
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#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92
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#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93
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#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
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#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94
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#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95
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#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97
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#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98
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#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
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#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99
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#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp_aux3_dispdec
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// base address: 0x150
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#define mmDP_AUX3_AUX_CONTROL 0x1fa4
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#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5
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#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6
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#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7
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#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_SW_STATUS 0x1fa8
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#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2
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#define mmDP_AUX3_AUX_LS_STATUS 0x1fa9
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#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2
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#define mmDP_AUX3_AUX_SW_DATA 0x1faa
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#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX3_AUX_LS_DATA 0x1fab
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#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac
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#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad
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#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae
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#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf
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#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0
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#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1
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#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3
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#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4
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#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
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#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5
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#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp_aux4_dispdec
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// base address: 0x1c0
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#define mmDP_AUX4_AUX_CONTROL 0x1fc0
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#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1
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#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2
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#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3
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#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_SW_STATUS 0x1fc4
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#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2
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#define mmDP_AUX4_AUX_LS_STATUS 0x1fc5
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#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2
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#define mmDP_AUX4_AUX_SW_DATA 0x1fc6
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#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX4_AUX_LS_DATA 0x1fc7
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#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8
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#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9
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#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca
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#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb
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#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
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#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc
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#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd
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#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf
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#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0
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#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
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#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1
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#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp_aux5_dispdec
|
// base address: 0x230
|
#define mmDP_AUX5_AUX_CONTROL 0x1fdc
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#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2
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#define mmDP_AUX5_AUX_SW_CONTROL 0x1fdd
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#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX5_AUX_ARB_CONTROL 0x1fde
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#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x1fdf
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#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX5_AUX_SW_STATUS 0x1fe0
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#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2
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#define mmDP_AUX5_AUX_LS_STATUS 0x1fe1
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#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2
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#define mmDP_AUX5_AUX_SW_DATA 0x1fe2
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#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX5_AUX_LS_DATA 0x1fe3
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#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x1fe4
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#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x1fe5
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#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2
|
#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x1fe6
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#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x1fe7
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#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
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#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x1fe8
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#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x1fe9
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#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1feb
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#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fec
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#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
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#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1fed
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#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp_aux6_dispdec
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// base address: 0x2a0
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#define mmDP_AUX6_AUX_CONTROL 0x1ff8
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#define mmDP_AUX6_AUX_CONTROL_BASE_IDX 2
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#define mmDP_AUX6_AUX_SW_CONTROL 0x1ff9
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#define mmDP_AUX6_AUX_SW_CONTROL_BASE_IDX 2
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#define mmDP_AUX6_AUX_ARB_CONTROL 0x1ffa
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#define mmDP_AUX6_AUX_ARB_CONTROL_BASE_IDX 2
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#define mmDP_AUX6_AUX_INTERRUPT_CONTROL 0x1ffb
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#define mmDP_AUX6_AUX_INTERRUPT_CONTROL_BASE_IDX 2
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#define mmDP_AUX6_AUX_SW_STATUS 0x1ffc
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#define mmDP_AUX6_AUX_SW_STATUS_BASE_IDX 2
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#define mmDP_AUX6_AUX_LS_STATUS 0x1ffd
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#define mmDP_AUX6_AUX_LS_STATUS_BASE_IDX 2
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#define mmDP_AUX6_AUX_SW_DATA 0x1ffe
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#define mmDP_AUX6_AUX_SW_DATA_BASE_IDX 2
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#define mmDP_AUX6_AUX_LS_DATA 0x1fff
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#define mmDP_AUX6_AUX_LS_DATA_BASE_IDX 2
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#define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL 0x2000
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#define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2
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#define mmDP_AUX6_AUX_DPHY_TX_CONTROL 0x2001
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#define mmDP_AUX6_AUX_DPHY_TX_CONTROL_BASE_IDX 2
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#define mmDP_AUX6_AUX_DPHY_RX_CONTROL0 0x2002
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#define mmDP_AUX6_AUX_DPHY_RX_CONTROL0_BASE_IDX 2
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#define mmDP_AUX6_AUX_DPHY_RX_CONTROL1 0x2003
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#define mmDP_AUX6_AUX_DPHY_RX_CONTROL1_BASE_IDX 2
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#define mmDP_AUX6_AUX_DPHY_TX_STATUS 0x2004
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#define mmDP_AUX6_AUX_DPHY_TX_STATUS_BASE_IDX 2
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#define mmDP_AUX6_AUX_DPHY_RX_STATUS 0x2005
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#define mmDP_AUX6_AUX_DPHY_RX_STATUS_BASE_IDX 2
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#define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL 0x2007
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#define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2
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#define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS 0x2008
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#define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2
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#define mmDP_AUX6_AUX_GTC_SYNC_STATUS 0x2009
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#define mmDP_AUX6_AUX_GTC_SYNC_STATUS_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig0_dispdec
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// base address: 0x0
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#define mmDIG0_DIG_FE_CNTL 0x2068
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#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x2069
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#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x206a
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#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG0_DIG_CLOCK_PATTERN 0x206b
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#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG0_DIG_TEST_PATTERN 0x206c
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#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x206d
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#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG0_DIG_FIFO_STATUS 0x206e
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#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG0_HDMI_CONTROL 0x2071
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#define mmDIG0_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_STATUS 0x2072
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#define mmDIG0_HDMI_STATUS_BASE_IDX 2
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#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2073
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#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2074
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#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2075
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#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2076
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#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2077
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#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x2078
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG0_AFMT_INTERRUPT_STATUS 0x2079
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#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIG0_HDMI_GC 0x207b
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#define mmDIG0_HDMI_GC_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x207c
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#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC1_0 0x207d
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#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC1_1 0x207e
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#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC1_2 0x207f
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#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC1_3 0x2080
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#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC1_4 0x2081
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#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC2_0 0x2082
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#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC2_1 0x2083
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#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC2_2 0x2084
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#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2
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#define mmDIG0_AFMT_ISRC2_3 0x2085
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#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x2086
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x2087
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
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#define mmDIG0_HDMI_DB_CONTROL 0x2088
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#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2
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#define mmDIG0_AFMT_MPEG_INFO0 0x208a
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#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2
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#define mmDIG0_AFMT_MPEG_INFO1 0x208b
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#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_HDR 0x208c
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#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_0 0x208d
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#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_1 0x208e
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#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_2 0x208f
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#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_3 0x2090
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#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_4 0x2091
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#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_5 0x2092
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#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_6 0x2093
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#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2
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#define mmDIG0_AFMT_GENERIC_7 0x2094
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#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x2095
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#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_32_0 0x2096
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#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_32_1 0x2097
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#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_44_0 0x2098
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#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_44_1 0x2099
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#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_48_0 0x209a
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#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_48_1 0x209b
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#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_STATUS_0 0x209c
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#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG0_HDMI_ACR_STATUS_1 0x209d
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#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_INFO0 0x209e
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#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_INFO1 0x209f
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#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG0_AFMT_60958_0 0x20a0
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#define mmDIG0_AFMT_60958_0_BASE_IDX 2
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#define mmDIG0_AFMT_60958_1 0x20a1
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#define mmDIG0_AFMT_60958_1_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x20a2
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#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG0_AFMT_RAMP_CONTROL0 0x20a3
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#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG0_AFMT_RAMP_CONTROL1 0x20a4
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#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG0_AFMT_RAMP_CONTROL2 0x20a5
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#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG0_AFMT_RAMP_CONTROL3 0x20a6
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#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG0_AFMT_60958_2 0x20a7
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#define mmDIG0_AFMT_60958_2_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x20a8
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#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG0_AFMT_STATUS 0x20a9
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#define mmDIG0_AFMT_STATUS_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x20aa
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#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x20ab
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#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x20ac
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#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x20ad
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#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG0_DIG_BE_CNTL 0x20af
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#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_BE_EN_CNTL 0x20b0
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#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG0_TMDS_CNTL 0x20d3
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#define mmDIG0_TMDS_CNTL_BASE_IDX 2
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#define mmDIG0_TMDS_CONTROL_CHAR 0x20d4
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#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d5
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#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20d6
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#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20d7
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#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20d8
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#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG0_TMDS_CTL_BITS 0x20da
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#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20db
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#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20dd
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#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20de
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#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG0_DIG_VERSION 0x20e0
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#define mmDIG0_DIG_VERSION_BASE_IDX 2
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#define mmDIG0_DIG_LANE_ENABLE 0x20e1
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#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG0_AFMT_CNTL 0x20e6
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#define mmDIG0_AFMT_CNTL_BASE_IDX 2
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#define mmDIG0_AFMT_VBI_PACKET_CONTROL1 0x20e7
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#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp0_dispdec
|
// base address: 0x0
|
#define mmDP0_DP_LINK_CNTL 0x2108
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#define mmDP0_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP0_DP_PIXEL_FORMAT 0x2109
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#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP0_DP_MSA_COLORIMETRY 0x210a
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#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP0_DP_CONFIG 0x210b
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#define mmDP0_DP_CONFIG_BASE_IDX 2
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#define mmDP0_DP_VID_STREAM_CNTL 0x210c
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#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP0_DP_STEER_FIFO 0x210d
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#define mmDP0_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP0_DP_MSA_MISC 0x210e
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#define mmDP0_DP_MSA_MISC_BASE_IDX 2
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#define mmDP0_DP_VID_TIMING 0x2110
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#define mmDP0_DP_VID_TIMING_BASE_IDX 2
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#define mmDP0_DP_VID_N 0x2111
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#define mmDP0_DP_VID_N_BASE_IDX 2
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#define mmDP0_DP_VID_M 0x2112
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#define mmDP0_DP_VID_M_BASE_IDX 2
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#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113
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#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114
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#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP0_DP_VID_MSA_VBID 0x2115
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#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116
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#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_CNTL 0x2117
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#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118
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#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP0_DP_DPHY_SYM0 0x2119
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#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP0_DP_DPHY_SYM1 0x211a
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#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP0_DP_DPHY_SYM2 0x211b
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#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c
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#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d
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#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e
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#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_CRC_EN 0x211f
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#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP0_DP_DPHY_CRC_CNTL 0x2120
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#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_CRC_RESULT 0x2121
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#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122
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#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123
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#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124
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#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125
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#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL 0x212b
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#define mmDP0_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL1 0x212c
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#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP0_DP_SEC_FRAMING1 0x212d
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#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP0_DP_SEC_FRAMING2 0x212e
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#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP0_DP_SEC_FRAMING3 0x212f
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#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP0_DP_SEC_FRAMING4 0x2130
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#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP0_DP_SEC_AUD_N 0x2131
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#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132
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#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP0_DP_SEC_AUD_M 0x2133
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#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134
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#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP0_DP_SEC_TIMESTAMP 0x2135
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#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP0_DP_SEC_PACKET_CNTL 0x2136
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#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP0_DP_MSE_RATE_CNTL 0x2137
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#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP0_DP_MSE_RATE_UPDATE 0x2139
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#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT0 0x213a
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#define mmDP0_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT1 0x213b
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#define mmDP0_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT2 0x213c
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#define mmDP0_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT_UPDATE 0x213d
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#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP0_DP_MSE_LINK_TIMING 0x213e
|
#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP0_DP_MSE_MISC_CNTL 0x213f
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#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144
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#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145
|
#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT0_STATUS 0x2147
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#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT1_STATUS 0x2148
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#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP0_DP_MSE_SAT2_STATUS 0x2149
|
#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2
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#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c
|
#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2
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#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d
|
#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2
|
#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e
|
#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2
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#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f
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#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2
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#define mmDP0_DP_MSO_CNTL 0x2150
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#define mmDP0_DP_MSO_CNTL_BASE_IDX 2
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#define mmDP0_DP_MSO_CNTL1 0x2151
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#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2
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#define mmDP0_DP_DSC_CNTL 0x2152
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#define mmDP0_DP_DSC_CNTL_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL2 0x2153
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#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL3 0x2154
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#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL4 0x2155
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#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL5 0x2156
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#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL6 0x2157
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#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2
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#define mmDP0_DP_SEC_CNTL7 0x2158
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#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2
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#define mmDP0_DP_DB_CNTL 0x2159
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#define mmDP0_DP_DB_CNTL_BASE_IDX 2
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#define mmDP0_DP_MSA_VBID_MISC 0x215a
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#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2
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|
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// addressBlock: dce_dc_dio_dig1_dispdec
|
// base address: 0x400
|
#define mmDIG1_DIG_FE_CNTL 0x2168
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#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x2169
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#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x216a
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#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG1_DIG_CLOCK_PATTERN 0x216b
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#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG1_DIG_TEST_PATTERN 0x216c
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#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x216d
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#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG1_DIG_FIFO_STATUS 0x216e
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#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG1_HDMI_CONTROL 0x2171
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#define mmDIG1_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_STATUS 0x2172
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#define mmDIG1_HDMI_STATUS_BASE_IDX 2
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#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2173
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#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2174
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#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2175
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#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2176
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#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2177
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#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x2178
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG1_AFMT_INTERRUPT_STATUS 0x2179
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#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIG1_HDMI_GC 0x217b
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#define mmDIG1_HDMI_GC_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x217c
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#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC1_0 0x217d
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#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC1_1 0x217e
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#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC1_2 0x217f
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#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC1_3 0x2180
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#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC1_4 0x2181
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#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC2_0 0x2182
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#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC2_1 0x2183
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#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC2_2 0x2184
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#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2
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#define mmDIG1_AFMT_ISRC2_3 0x2185
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#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x2186
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x2187
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
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#define mmDIG1_HDMI_DB_CONTROL 0x2188
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#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2
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#define mmDIG1_AFMT_MPEG_INFO0 0x218a
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#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2
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#define mmDIG1_AFMT_MPEG_INFO1 0x218b
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#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_HDR 0x218c
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#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_0 0x218d
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#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_1 0x218e
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#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_2 0x218f
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#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_3 0x2190
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#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_4 0x2191
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#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_5 0x2192
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#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_6 0x2193
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#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2
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#define mmDIG1_AFMT_GENERIC_7 0x2194
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#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x2195
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#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_32_0 0x2196
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#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_32_1 0x2197
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#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_44_0 0x2198
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#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_44_1 0x2199
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#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_48_0 0x219a
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#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_48_1 0x219b
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#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_STATUS_0 0x219c
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#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG1_HDMI_ACR_STATUS_1 0x219d
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#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_INFO0 0x219e
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#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_INFO1 0x219f
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#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG1_AFMT_60958_0 0x21a0
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#define mmDIG1_AFMT_60958_0_BASE_IDX 2
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#define mmDIG1_AFMT_60958_1 0x21a1
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#define mmDIG1_AFMT_60958_1_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x21a2
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#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG1_AFMT_RAMP_CONTROL0 0x21a3
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#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG1_AFMT_RAMP_CONTROL1 0x21a4
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#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG1_AFMT_RAMP_CONTROL2 0x21a5
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#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG1_AFMT_RAMP_CONTROL3 0x21a6
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#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG1_AFMT_60958_2 0x21a7
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#define mmDIG1_AFMT_60958_2_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x21a8
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#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG1_AFMT_STATUS 0x21a9
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#define mmDIG1_AFMT_STATUS_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x21aa
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#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x21ab
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#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x21ac
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#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x21ad
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#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG1_DIG_BE_CNTL 0x21af
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#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_BE_EN_CNTL 0x21b0
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#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG1_TMDS_CNTL 0x21d3
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#define mmDIG1_TMDS_CNTL_BASE_IDX 2
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#define mmDIG1_TMDS_CONTROL_CHAR 0x21d4
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#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d5
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#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21d6
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#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21d7
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#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21d8
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#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG1_TMDS_CTL_BITS 0x21da
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#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21db
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#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21dd
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#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21de
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#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG1_DIG_VERSION 0x21e0
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#define mmDIG1_DIG_VERSION_BASE_IDX 2
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#define mmDIG1_DIG_LANE_ENABLE 0x21e1
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#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG1_AFMT_CNTL 0x21e6
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#define mmDIG1_AFMT_CNTL_BASE_IDX 2
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#define mmDIG1_AFMT_VBI_PACKET_CONTROL1 0x21e7
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#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
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|
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// addressBlock: dce_dc_dio_dp1_dispdec
|
// base address: 0x400
|
#define mmDP1_DP_LINK_CNTL 0x2208
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#define mmDP1_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP1_DP_PIXEL_FORMAT 0x2209
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#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP1_DP_MSA_COLORIMETRY 0x220a
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#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP1_DP_CONFIG 0x220b
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#define mmDP1_DP_CONFIG_BASE_IDX 2
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#define mmDP1_DP_VID_STREAM_CNTL 0x220c
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#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP1_DP_STEER_FIFO 0x220d
|
#define mmDP1_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP1_DP_MSA_MISC 0x220e
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#define mmDP1_DP_MSA_MISC_BASE_IDX 2
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#define mmDP1_DP_VID_TIMING 0x2210
|
#define mmDP1_DP_VID_TIMING_BASE_IDX 2
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#define mmDP1_DP_VID_N 0x2211
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#define mmDP1_DP_VID_N_BASE_IDX 2
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#define mmDP1_DP_VID_M 0x2212
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#define mmDP1_DP_VID_M_BASE_IDX 2
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#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213
|
#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2
|
#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214
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#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2
|
#define mmDP1_DP_VID_MSA_VBID 0x2215
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#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216
|
#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CNTL 0x2217
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#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218
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#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_SYM0 0x2219
|
#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2
|
#define mmDP1_DP_DPHY_SYM1 0x221a
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#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP1_DP_DPHY_SYM2 0x221b
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#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2
|
#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c
|
#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d
|
#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e
|
#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_EN 0x221f
|
#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP1_DP_DPHY_CRC_CNTL 0x2220
|
#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_RESULT 0x2221
|
#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222
|
#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
|
#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223
|
#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
|
#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224
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#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2
|
#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225
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#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP1_DP_SEC_CNTL 0x222b
|
#define mmDP1_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP1_DP_SEC_CNTL1 0x222c
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#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2
|
#define mmDP1_DP_SEC_FRAMING1 0x222d
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#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP1_DP_SEC_FRAMING2 0x222e
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#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP1_DP_SEC_FRAMING3 0x222f
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#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2
|
#define mmDP1_DP_SEC_FRAMING4 0x2230
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#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP1_DP_SEC_AUD_N 0x2231
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#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232
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#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP1_DP_SEC_AUD_M 0x2233
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#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234
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#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP1_DP_SEC_TIMESTAMP 0x2235
|
#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP1_DP_SEC_PACKET_CNTL 0x2236
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#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP1_DP_MSE_RATE_CNTL 0x2237
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#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP1_DP_MSE_RATE_UPDATE 0x2239
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#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT0 0x223a
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#define mmDP1_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP1_DP_MSE_SAT1 0x223b
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#define mmDP1_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP1_DP_MSE_SAT2 0x223c
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#define mmDP1_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP1_DP_MSE_SAT_UPDATE 0x223d
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#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP1_DP_MSE_LINK_TIMING 0x223e
|
#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP1_DP_MSE_MISC_CNTL 0x223f
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#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244
|
#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245
|
#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP1_DP_MSE_SAT0_STATUS 0x2247
|
#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP1_DP_MSE_SAT1_STATUS 0x2248
|
#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2
|
#define mmDP1_DP_MSE_SAT2_STATUS 0x2249
|
#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2
|
#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c
|
#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2
|
#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d
|
#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2
|
#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e
|
#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2
|
#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f
|
#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2
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#define mmDP1_DP_MSO_CNTL 0x2250
|
#define mmDP1_DP_MSO_CNTL_BASE_IDX 2
|
#define mmDP1_DP_MSO_CNTL1 0x2251
|
#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2
|
#define mmDP1_DP_DSC_CNTL 0x2252
|
#define mmDP1_DP_DSC_CNTL_BASE_IDX 2
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#define mmDP1_DP_SEC_CNTL2 0x2253
|
#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL3 0x2254
|
#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL4 0x2255
|
#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL5 0x2256
|
#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL6 0x2257
|
#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2
|
#define mmDP1_DP_SEC_CNTL7 0x2258
|
#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2
|
#define mmDP1_DP_DB_CNTL 0x2259
|
#define mmDP1_DP_DB_CNTL_BASE_IDX 2
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#define mmDP1_DP_MSA_VBID_MISC 0x225a
|
#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2
|
|
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// addressBlock: dce_dc_dio_dig2_dispdec
|
// base address: 0x800
|
#define mmDIG2_DIG_FE_CNTL 0x2268
|
#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2
|
#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x2269
|
#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x226a
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#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG2_DIG_CLOCK_PATTERN 0x226b
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#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG2_DIG_TEST_PATTERN 0x226c
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#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x226d
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#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG2_DIG_FIFO_STATUS 0x226e
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#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG2_HDMI_CONTROL 0x2271
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#define mmDIG2_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_STATUS 0x2272
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#define mmDIG2_HDMI_STATUS_BASE_IDX 2
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#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2273
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#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2274
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#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2275
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#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2276
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#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2277
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#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x2278
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG2_AFMT_INTERRUPT_STATUS 0x2279
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#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIG2_HDMI_GC 0x227b
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#define mmDIG2_HDMI_GC_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x227c
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#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC1_0 0x227d
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#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC1_1 0x227e
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#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC1_2 0x227f
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#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC1_3 0x2280
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#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC1_4 0x2281
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#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC2_0 0x2282
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#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC2_1 0x2283
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#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC2_2 0x2284
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#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2
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#define mmDIG2_AFMT_ISRC2_3 0x2285
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#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x2286
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x2287
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
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#define mmDIG2_HDMI_DB_CONTROL 0x2288
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#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2
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#define mmDIG2_AFMT_MPEG_INFO0 0x228a
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#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2
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#define mmDIG2_AFMT_MPEG_INFO1 0x228b
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#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_HDR 0x228c
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#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_0 0x228d
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#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_1 0x228e
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#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_2 0x228f
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#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_3 0x2290
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#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_4 0x2291
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#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_5 0x2292
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#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_6 0x2293
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#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2
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#define mmDIG2_AFMT_GENERIC_7 0x2294
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#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x2295
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#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_32_0 0x2296
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#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_32_1 0x2297
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#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_44_0 0x2298
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#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_44_1 0x2299
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#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_48_0 0x229a
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#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_48_1 0x229b
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#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_STATUS_0 0x229c
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#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG2_HDMI_ACR_STATUS_1 0x229d
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#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_INFO0 0x229e
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#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_INFO1 0x229f
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#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG2_AFMT_60958_0 0x22a0
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#define mmDIG2_AFMT_60958_0_BASE_IDX 2
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#define mmDIG2_AFMT_60958_1 0x22a1
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#define mmDIG2_AFMT_60958_1_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x22a2
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#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG2_AFMT_RAMP_CONTROL0 0x22a3
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#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG2_AFMT_RAMP_CONTROL1 0x22a4
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#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG2_AFMT_RAMP_CONTROL2 0x22a5
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#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG2_AFMT_RAMP_CONTROL3 0x22a6
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#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG2_AFMT_60958_2 0x22a7
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#define mmDIG2_AFMT_60958_2_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x22a8
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#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG2_AFMT_STATUS 0x22a9
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#define mmDIG2_AFMT_STATUS_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x22aa
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#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x22ab
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#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x22ac
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#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x22ad
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#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG2_DIG_BE_CNTL 0x22af
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#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG2_DIG_BE_EN_CNTL 0x22b0
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#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG2_TMDS_CNTL 0x22d3
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#define mmDIG2_TMDS_CNTL_BASE_IDX 2
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#define mmDIG2_TMDS_CONTROL_CHAR 0x22d4
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#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d5
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#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22d6
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#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22d7
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#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22d8
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#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG2_TMDS_CTL_BITS 0x22da
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#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22db
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#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22dd
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#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22de
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#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG2_DIG_VERSION 0x22e0
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#define mmDIG2_DIG_VERSION_BASE_IDX 2
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#define mmDIG2_DIG_LANE_ENABLE 0x22e1
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#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG2_AFMT_CNTL 0x22e6
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#define mmDIG2_AFMT_CNTL_BASE_IDX 2
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#define mmDIG2_AFMT_VBI_PACKET_CONTROL1 0x22e7
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#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp2_dispdec
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// base address: 0x800
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#define mmDP2_DP_LINK_CNTL 0x2308
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#define mmDP2_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP2_DP_PIXEL_FORMAT 0x2309
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#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP2_DP_MSA_COLORIMETRY 0x230a
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#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP2_DP_CONFIG 0x230b
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#define mmDP2_DP_CONFIG_BASE_IDX 2
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#define mmDP2_DP_VID_STREAM_CNTL 0x230c
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#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP2_DP_STEER_FIFO 0x230d
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#define mmDP2_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP2_DP_MSA_MISC 0x230e
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#define mmDP2_DP_MSA_MISC_BASE_IDX 2
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#define mmDP2_DP_VID_TIMING 0x2310
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#define mmDP2_DP_VID_TIMING_BASE_IDX 2
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#define mmDP2_DP_VID_N 0x2311
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#define mmDP2_DP_VID_N_BASE_IDX 2
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#define mmDP2_DP_VID_M 0x2312
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#define mmDP2_DP_VID_M_BASE_IDX 2
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#define mmDP2_DP_LINK_FRAMING_CNTL 0x2313
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#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP2_DP_HBR2_EYE_PATTERN 0x2314
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#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP2_DP_VID_MSA_VBID 0x2315
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#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316
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#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_CNTL 0x2317
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#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318
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#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP2_DP_DPHY_SYM0 0x2319
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#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP2_DP_DPHY_SYM1 0x231a
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#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP2_DP_DPHY_SYM2 0x231b
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#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP2_DP_DPHY_8B10B_CNTL 0x231c
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#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_PRBS_CNTL 0x231d
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#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e
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#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_EN 0x231f
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#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_CNTL 0x2320
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#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_RESULT 0x2321
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#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322
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#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323
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#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP2_DP_DPHY_FAST_TRAINING 0x2324
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#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325
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#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL 0x232b
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#define mmDP2_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL1 0x232c
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#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP2_DP_SEC_FRAMING1 0x232d
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#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP2_DP_SEC_FRAMING2 0x232e
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#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP2_DP_SEC_FRAMING3 0x232f
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#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP2_DP_SEC_FRAMING4 0x2330
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#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP2_DP_SEC_AUD_N 0x2331
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#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP2_DP_SEC_AUD_N_READBACK 0x2332
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#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP2_DP_SEC_AUD_M 0x2333
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#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP2_DP_SEC_AUD_M_READBACK 0x2334
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#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP2_DP_SEC_TIMESTAMP 0x2335
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#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP2_DP_SEC_PACKET_CNTL 0x2336
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#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP2_DP_MSE_RATE_CNTL 0x2337
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#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP2_DP_MSE_RATE_UPDATE 0x2339
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#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT0 0x233a
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#define mmDP2_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT1 0x233b
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#define mmDP2_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT2 0x233c
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#define mmDP2_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT_UPDATE 0x233d
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#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP2_DP_MSE_LINK_TIMING 0x233e
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#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP2_DP_MSE_MISC_CNTL 0x233f
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#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344
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#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345
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#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT0_STATUS 0x2347
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#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT1_STATUS 0x2348
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#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP2_DP_MSE_SAT2_STATUS 0x2349
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#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2
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#define mmDP2_DP_MSA_TIMING_PARAM1 0x234c
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#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2
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#define mmDP2_DP_MSA_TIMING_PARAM2 0x234d
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#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2
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#define mmDP2_DP_MSA_TIMING_PARAM3 0x234e
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#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2
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#define mmDP2_DP_MSA_TIMING_PARAM4 0x234f
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#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2
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#define mmDP2_DP_MSO_CNTL 0x2350
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#define mmDP2_DP_MSO_CNTL_BASE_IDX 2
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#define mmDP2_DP_MSO_CNTL1 0x2351
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#define mmDP2_DP_MSO_CNTL1_BASE_IDX 2
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#define mmDP2_DP_DSC_CNTL 0x2352
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#define mmDP2_DP_DSC_CNTL_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL2 0x2353
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#define mmDP2_DP_SEC_CNTL2_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL3 0x2354
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#define mmDP2_DP_SEC_CNTL3_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL4 0x2355
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#define mmDP2_DP_SEC_CNTL4_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL5 0x2356
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#define mmDP2_DP_SEC_CNTL5_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL6 0x2357
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#define mmDP2_DP_SEC_CNTL6_BASE_IDX 2
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#define mmDP2_DP_SEC_CNTL7 0x2358
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#define mmDP2_DP_SEC_CNTL7_BASE_IDX 2
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#define mmDP2_DP_DB_CNTL 0x2359
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#define mmDP2_DP_DB_CNTL_BASE_IDX 2
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#define mmDP2_DP_MSA_VBID_MISC 0x235a
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#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2
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|
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// addressBlock: dce_dc_dio_dig3_dispdec
|
// base address: 0xc00
|
#define mmDIG3_DIG_FE_CNTL 0x2368
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#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x2369
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#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x236a
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#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG3_DIG_CLOCK_PATTERN 0x236b
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#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG3_DIG_TEST_PATTERN 0x236c
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#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x236d
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#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG3_DIG_FIFO_STATUS 0x236e
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#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG3_HDMI_CONTROL 0x2371
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#define mmDIG3_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_STATUS 0x2372
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#define mmDIG3_HDMI_STATUS_BASE_IDX 2
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#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2373
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#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2374
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#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2375
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#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2376
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#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2377
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#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2378
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG3_AFMT_INTERRUPT_STATUS 0x2379
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#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIG3_HDMI_GC 0x237b
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#define mmDIG3_HDMI_GC_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x237c
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#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC1_0 0x237d
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#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC1_1 0x237e
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#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC1_2 0x237f
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#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC1_3 0x2380
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#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC1_4 0x2381
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#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC2_0 0x2382
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#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC2_1 0x2383
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#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC2_2 0x2384
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#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2
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#define mmDIG3_AFMT_ISRC2_3 0x2385
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#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2386
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2387
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
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#define mmDIG3_HDMI_DB_CONTROL 0x2388
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#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2
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#define mmDIG3_AFMT_MPEG_INFO0 0x238a
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#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2
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#define mmDIG3_AFMT_MPEG_INFO1 0x238b
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#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_HDR 0x238c
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#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_0 0x238d
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#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_1 0x238e
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#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_2 0x238f
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#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_3 0x2390
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#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_4 0x2391
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#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_5 0x2392
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#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_6 0x2393
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#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2
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#define mmDIG3_AFMT_GENERIC_7 0x2394
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#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2395
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#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_32_0 0x2396
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#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_32_1 0x2397
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#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_44_0 0x2398
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#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_44_1 0x2399
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#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_48_0 0x239a
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#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_48_1 0x239b
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#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_STATUS_0 0x239c
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#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG3_HDMI_ACR_STATUS_1 0x239d
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#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_INFO0 0x239e
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#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_INFO1 0x239f
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#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG3_AFMT_60958_0 0x23a0
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#define mmDIG3_AFMT_60958_0_BASE_IDX 2
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#define mmDIG3_AFMT_60958_1 0x23a1
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#define mmDIG3_AFMT_60958_1_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x23a2
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#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG3_AFMT_RAMP_CONTROL0 0x23a3
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#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG3_AFMT_RAMP_CONTROL1 0x23a4
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#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG3_AFMT_RAMP_CONTROL2 0x23a5
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#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG3_AFMT_RAMP_CONTROL3 0x23a6
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#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG3_AFMT_60958_2 0x23a7
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#define mmDIG3_AFMT_60958_2_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x23a8
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#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG3_AFMT_STATUS 0x23a9
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#define mmDIG3_AFMT_STATUS_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x23aa
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#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x23ab
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#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x23ac
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#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x23ad
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#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG3_DIG_BE_CNTL 0x23af
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#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_BE_EN_CNTL 0x23b0
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#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG3_TMDS_CNTL 0x23d3
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#define mmDIG3_TMDS_CNTL_BASE_IDX 2
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#define mmDIG3_TMDS_CONTROL_CHAR 0x23d4
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#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d5
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#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23d6
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#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23d7
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#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23d8
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#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG3_TMDS_CTL_BITS 0x23da
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#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23db
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#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23dd
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#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23de
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#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG3_DIG_VERSION 0x23e0
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#define mmDIG3_DIG_VERSION_BASE_IDX 2
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#define mmDIG3_DIG_LANE_ENABLE 0x23e1
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#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG3_AFMT_CNTL 0x23e6
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#define mmDIG3_AFMT_CNTL_BASE_IDX 2
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#define mmDIG3_AFMT_VBI_PACKET_CONTROL1 0x23e7
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#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp3_dispdec
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// base address: 0xc00
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#define mmDP3_DP_LINK_CNTL 0x2408
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#define mmDP3_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP3_DP_PIXEL_FORMAT 0x2409
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#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP3_DP_MSA_COLORIMETRY 0x240a
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#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP3_DP_CONFIG 0x240b
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#define mmDP3_DP_CONFIG_BASE_IDX 2
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#define mmDP3_DP_VID_STREAM_CNTL 0x240c
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#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP3_DP_STEER_FIFO 0x240d
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#define mmDP3_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP3_DP_MSA_MISC 0x240e
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#define mmDP3_DP_MSA_MISC_BASE_IDX 2
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#define mmDP3_DP_VID_TIMING 0x2410
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#define mmDP3_DP_VID_TIMING_BASE_IDX 2
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#define mmDP3_DP_VID_N 0x2411
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#define mmDP3_DP_VID_N_BASE_IDX 2
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#define mmDP3_DP_VID_M 0x2412
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#define mmDP3_DP_VID_M_BASE_IDX 2
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#define mmDP3_DP_LINK_FRAMING_CNTL 0x2413
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#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP3_DP_HBR2_EYE_PATTERN 0x2414
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#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP3_DP_VID_MSA_VBID 0x2415
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#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416
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#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_CNTL 0x2417
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#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418
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#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP3_DP_DPHY_SYM0 0x2419
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#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP3_DP_DPHY_SYM1 0x241a
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#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP3_DP_DPHY_SYM2 0x241b
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#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP3_DP_DPHY_8B10B_CNTL 0x241c
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#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_PRBS_CNTL 0x241d
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#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e
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#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_EN 0x241f
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#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_CNTL 0x2420
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#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_RESULT 0x2421
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#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422
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#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423
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#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP3_DP_DPHY_FAST_TRAINING 0x2424
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#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425
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#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL 0x242b
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#define mmDP3_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL1 0x242c
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#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP3_DP_SEC_FRAMING1 0x242d
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#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP3_DP_SEC_FRAMING2 0x242e
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#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP3_DP_SEC_FRAMING3 0x242f
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#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP3_DP_SEC_FRAMING4 0x2430
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#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP3_DP_SEC_AUD_N 0x2431
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#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP3_DP_SEC_AUD_N_READBACK 0x2432
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#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP3_DP_SEC_AUD_M 0x2433
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#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP3_DP_SEC_AUD_M_READBACK 0x2434
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#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP3_DP_SEC_TIMESTAMP 0x2435
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#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP3_DP_SEC_PACKET_CNTL 0x2436
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#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP3_DP_MSE_RATE_CNTL 0x2437
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#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP3_DP_MSE_RATE_UPDATE 0x2439
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#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT0 0x243a
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#define mmDP3_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT1 0x243b
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#define mmDP3_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT2 0x243c
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#define mmDP3_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT_UPDATE 0x243d
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#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP3_DP_MSE_LINK_TIMING 0x243e
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#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP3_DP_MSE_MISC_CNTL 0x243f
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#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444
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#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445
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#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT0_STATUS 0x2447
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#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT1_STATUS 0x2448
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#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP3_DP_MSE_SAT2_STATUS 0x2449
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#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2
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#define mmDP3_DP_MSA_TIMING_PARAM1 0x244c
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#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2
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#define mmDP3_DP_MSA_TIMING_PARAM2 0x244d
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#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2
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#define mmDP3_DP_MSA_TIMING_PARAM3 0x244e
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#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2
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#define mmDP3_DP_MSA_TIMING_PARAM4 0x244f
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#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2
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#define mmDP3_DP_MSO_CNTL 0x2450
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#define mmDP3_DP_MSO_CNTL_BASE_IDX 2
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#define mmDP3_DP_MSO_CNTL1 0x2451
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#define mmDP3_DP_MSO_CNTL1_BASE_IDX 2
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#define mmDP3_DP_DSC_CNTL 0x2452
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#define mmDP3_DP_DSC_CNTL_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL2 0x2453
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#define mmDP3_DP_SEC_CNTL2_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL3 0x2454
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#define mmDP3_DP_SEC_CNTL3_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL4 0x2455
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#define mmDP3_DP_SEC_CNTL4_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL5 0x2456
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#define mmDP3_DP_SEC_CNTL5_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL6 0x2457
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#define mmDP3_DP_SEC_CNTL6_BASE_IDX 2
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#define mmDP3_DP_SEC_CNTL7 0x2458
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#define mmDP3_DP_SEC_CNTL7_BASE_IDX 2
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#define mmDP3_DP_DB_CNTL 0x2459
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#define mmDP3_DP_DB_CNTL_BASE_IDX 2
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#define mmDP3_DP_MSA_VBID_MISC 0x245a
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#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2
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// addressBlock: dce_dc_dio_dig4_dispdec
|
// base address: 0x1000
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#define mmDIG4_DIG_FE_CNTL 0x2468
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#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x2469
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#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x246a
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#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
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#define mmDIG4_DIG_CLOCK_PATTERN 0x246b
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#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2
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#define mmDIG4_DIG_TEST_PATTERN 0x246c
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#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2
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#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x246d
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#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
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#define mmDIG4_DIG_FIFO_STATUS 0x246e
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#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2
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#define mmDIG4_HDMI_CONTROL 0x2471
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#define mmDIG4_HDMI_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_STATUS 0x2472
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#define mmDIG4_HDMI_STATUS_BASE_IDX 2
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#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2473
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#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2474
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#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2475
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#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2476
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#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2477
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#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2478
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
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#define mmDIG4_AFMT_INTERRUPT_STATUS 0x2479
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#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2
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#define mmDIG4_HDMI_GC 0x247b
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#define mmDIG4_HDMI_GC_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x247c
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#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC1_0 0x247d
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#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC1_1 0x247e
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#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC1_2 0x247f
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#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC1_3 0x2480
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#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC1_4 0x2481
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#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC2_0 0x2482
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#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC2_1 0x2483
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#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC2_2 0x2484
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#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2
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#define mmDIG4_AFMT_ISRC2_3 0x2485
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#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x2486
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x2487
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
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#define mmDIG4_HDMI_DB_CONTROL 0x2488
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#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2
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#define mmDIG4_AFMT_MPEG_INFO0 0x248a
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#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2
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#define mmDIG4_AFMT_MPEG_INFO1 0x248b
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#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_HDR 0x248c
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#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_0 0x248d
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#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_1 0x248e
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#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_2 0x248f
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#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_3 0x2490
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#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_4 0x2491
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#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_5 0x2492
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#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_6 0x2493
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#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2
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#define mmDIG4_AFMT_GENERIC_7 0x2494
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#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2495
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#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_32_0 0x2496
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#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_32_1 0x2497
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#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_44_0 0x2498
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#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_44_1 0x2499
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#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_48_0 0x249a
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#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_48_1 0x249b
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#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_STATUS_0 0x249c
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#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG4_HDMI_ACR_STATUS_1 0x249d
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#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_INFO0 0x249e
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#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_INFO1 0x249f
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#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG4_AFMT_60958_0 0x24a0
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#define mmDIG4_AFMT_60958_0_BASE_IDX 2
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#define mmDIG4_AFMT_60958_1 0x24a1
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#define mmDIG4_AFMT_60958_1_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x24a2
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#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG4_AFMT_RAMP_CONTROL0 0x24a3
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#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG4_AFMT_RAMP_CONTROL1 0x24a4
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#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG4_AFMT_RAMP_CONTROL2 0x24a5
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#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG4_AFMT_RAMP_CONTROL3 0x24a6
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#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG4_AFMT_60958_2 0x24a7
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#define mmDIG4_AFMT_60958_2_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x24a8
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#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG4_AFMT_STATUS 0x24a9
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#define mmDIG4_AFMT_STATUS_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x24aa
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#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x24ab
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#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x24ac
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#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x24ad
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#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG4_DIG_BE_CNTL 0x24af
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#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_BE_EN_CNTL 0x24b0
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#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG4_TMDS_CNTL 0x24d3
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#define mmDIG4_TMDS_CNTL_BASE_IDX 2
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#define mmDIG4_TMDS_CONTROL_CHAR 0x24d4
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#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d5
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#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24d6
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#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24d7
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#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24d8
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#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG4_TMDS_CTL_BITS 0x24da
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#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24db
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#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24dd
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#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24de
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#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG4_DIG_VERSION 0x24e0
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#define mmDIG4_DIG_VERSION_BASE_IDX 2
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#define mmDIG4_DIG_LANE_ENABLE 0x24e1
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#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG4_AFMT_CNTL 0x24e6
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#define mmDIG4_AFMT_CNTL_BASE_IDX 2
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#define mmDIG4_AFMT_VBI_PACKET_CONTROL1 0x24e7
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#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
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// addressBlock: dce_dc_dio_dp4_dispdec
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// base address: 0x1000
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#define mmDP4_DP_LINK_CNTL 0x2508
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#define mmDP4_DP_LINK_CNTL_BASE_IDX 2
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#define mmDP4_DP_PIXEL_FORMAT 0x2509
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#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP4_DP_MSA_COLORIMETRY 0x250a
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#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP4_DP_CONFIG 0x250b
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#define mmDP4_DP_CONFIG_BASE_IDX 2
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#define mmDP4_DP_VID_STREAM_CNTL 0x250c
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#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP4_DP_STEER_FIFO 0x250d
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#define mmDP4_DP_STEER_FIFO_BASE_IDX 2
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#define mmDP4_DP_MSA_MISC 0x250e
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#define mmDP4_DP_MSA_MISC_BASE_IDX 2
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#define mmDP4_DP_VID_TIMING 0x2510
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#define mmDP4_DP_VID_TIMING_BASE_IDX 2
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#define mmDP4_DP_VID_N 0x2511
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#define mmDP4_DP_VID_N_BASE_IDX 2
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#define mmDP4_DP_VID_M 0x2512
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#define mmDP4_DP_VID_M_BASE_IDX 2
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#define mmDP4_DP_LINK_FRAMING_CNTL 0x2513
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#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2
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#define mmDP4_DP_HBR2_EYE_PATTERN 0x2514
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#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2
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#define mmDP4_DP_VID_MSA_VBID 0x2515
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#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516
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#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_CNTL 0x2517
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#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518
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#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
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#define mmDP4_DP_DPHY_SYM0 0x2519
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#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2
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#define mmDP4_DP_DPHY_SYM1 0x251a
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#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2
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#define mmDP4_DP_DPHY_SYM2 0x251b
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#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2
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#define mmDP4_DP_DPHY_8B10B_CNTL 0x251c
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#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_PRBS_CNTL 0x251d
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#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e
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#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_EN 0x251f
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#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_CNTL 0x2520
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#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_RESULT 0x2521
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#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522
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#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523
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#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
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#define mmDP4_DP_DPHY_FAST_TRAINING 0x2524
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#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525
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#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL 0x252b
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#define mmDP4_DP_SEC_CNTL_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL1 0x252c
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#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2
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#define mmDP4_DP_SEC_FRAMING1 0x252d
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#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP4_DP_SEC_FRAMING2 0x252e
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#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP4_DP_SEC_FRAMING3 0x252f
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#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP4_DP_SEC_FRAMING4 0x2530
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#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP4_DP_SEC_AUD_N 0x2531
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#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP4_DP_SEC_AUD_N_READBACK 0x2532
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#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP4_DP_SEC_AUD_M 0x2533
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#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP4_DP_SEC_AUD_M_READBACK 0x2534
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#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP4_DP_SEC_TIMESTAMP 0x2535
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#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP4_DP_SEC_PACKET_CNTL 0x2536
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#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP4_DP_MSE_RATE_CNTL 0x2537
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#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP4_DP_MSE_RATE_UPDATE 0x2539
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#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT0 0x253a
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#define mmDP4_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT1 0x253b
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#define mmDP4_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT2 0x253c
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#define mmDP4_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT_UPDATE 0x253d
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#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP4_DP_MSE_LINK_TIMING 0x253e
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#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP4_DP_MSE_MISC_CNTL 0x253f
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#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544
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#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545
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#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT0_STATUS 0x2547
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#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT1_STATUS 0x2548
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#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP4_DP_MSE_SAT2_STATUS 0x2549
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#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2
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#define mmDP4_DP_MSA_TIMING_PARAM1 0x254c
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#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2
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#define mmDP4_DP_MSA_TIMING_PARAM2 0x254d
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#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2
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#define mmDP4_DP_MSA_TIMING_PARAM3 0x254e
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#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2
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#define mmDP4_DP_MSA_TIMING_PARAM4 0x254f
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#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2
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#define mmDP4_DP_MSO_CNTL 0x2550
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#define mmDP4_DP_MSO_CNTL_BASE_IDX 2
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#define mmDP4_DP_MSO_CNTL1 0x2551
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#define mmDP4_DP_MSO_CNTL1_BASE_IDX 2
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#define mmDP4_DP_DSC_CNTL 0x2552
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#define mmDP4_DP_DSC_CNTL_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL2 0x2553
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#define mmDP4_DP_SEC_CNTL2_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL3 0x2554
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#define mmDP4_DP_SEC_CNTL3_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL4 0x2555
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#define mmDP4_DP_SEC_CNTL4_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL5 0x2556
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#define mmDP4_DP_SEC_CNTL5_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL6 0x2557
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#define mmDP4_DP_SEC_CNTL6_BASE_IDX 2
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#define mmDP4_DP_SEC_CNTL7 0x2558
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#define mmDP4_DP_SEC_CNTL7_BASE_IDX 2
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#define mmDP4_DP_DB_CNTL 0x2559
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#define mmDP4_DP_DB_CNTL_BASE_IDX 2
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#define mmDP4_DP_MSA_VBID_MISC 0x255a
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#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2
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|
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// addressBlock: dce_dc_dio_dig5_dispdec
|
// base address: 0x1400
|
#define mmDIG5_DIG_FE_CNTL 0x2568
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#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2
|
#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x2569
|
#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
|
#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x256a
|
#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
|
#define mmDIG5_DIG_CLOCK_PATTERN 0x256b
|
#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2
|
#define mmDIG5_DIG_TEST_PATTERN 0x256c
|
#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2
|
#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x256d
|
#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
|
#define mmDIG5_DIG_FIFO_STATUS 0x256e
|
#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2
|
#define mmDIG5_HDMI_CONTROL 0x2571
|
#define mmDIG5_HDMI_CONTROL_BASE_IDX 2
|
#define mmDIG5_HDMI_STATUS 0x2572
|
#define mmDIG5_HDMI_STATUS_BASE_IDX 2
|
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x2573
|
#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x2574
|
#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x2575
|
#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x2576
|
#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x2577
|
#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x2578
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
|
#define mmDIG5_AFMT_INTERRUPT_STATUS 0x2579
|
#define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDIG5_HDMI_GC 0x257b
|
#define mmDIG5_HDMI_GC_BASE_IDX 2
|
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x257c
|
#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC1_0 0x257d
|
#define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC1_1 0x257e
|
#define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC1_2 0x257f
|
#define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC1_3 0x2580
|
#define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC1_4 0x2581
|
#define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC2_0 0x2582
|
#define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC2_1 0x2583
|
#define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC2_2 0x2584
|
#define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2
|
#define mmDIG5_AFMT_ISRC2_3 0x2585
|
#define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0x2586
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0x2587
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
|
#define mmDIG5_HDMI_DB_CONTROL 0x2588
|
#define mmDIG5_HDMI_DB_CONTROL_BASE_IDX 2
|
#define mmDIG5_AFMT_MPEG_INFO0 0x258a
|
#define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2
|
#define mmDIG5_AFMT_MPEG_INFO1 0x258b
|
#define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_HDR 0x258c
|
#define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_0 0x258d
|
#define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_1 0x258e
|
#define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_2 0x258f
|
#define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_3 0x2590
|
#define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_4 0x2591
|
#define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_5 0x2592
|
#define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_6 0x2593
|
#define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2
|
#define mmDIG5_AFMT_GENERIC_7 0x2594
|
#define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x2595
|
#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_32_0 0x2596
|
#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_32_1 0x2597
|
#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_44_0 0x2598
|
#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2
|
#define mmDIG5_HDMI_ACR_44_1 0x2599
|
#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_48_0 0x259a
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#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_48_1 0x259b
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#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_STATUS_0 0x259c
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#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2
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#define mmDIG5_HDMI_ACR_STATUS_1 0x259d
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#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_INFO0 0x259e
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#define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_INFO1 0x259f
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#define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2
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#define mmDIG5_AFMT_60958_0 0x25a0
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#define mmDIG5_AFMT_60958_0_BASE_IDX 2
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#define mmDIG5_AFMT_60958_1 0x25a1
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#define mmDIG5_AFMT_60958_1_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x25a2
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#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
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#define mmDIG5_AFMT_RAMP_CONTROL0 0x25a3
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#define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2
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#define mmDIG5_AFMT_RAMP_CONTROL1 0x25a4
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#define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2
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#define mmDIG5_AFMT_RAMP_CONTROL2 0x25a5
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#define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2
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#define mmDIG5_AFMT_RAMP_CONTROL3 0x25a6
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#define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2
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#define mmDIG5_AFMT_60958_2 0x25a7
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#define mmDIG5_AFMT_60958_2_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x25a8
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#define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
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#define mmDIG5_AFMT_STATUS 0x25a9
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#define mmDIG5_AFMT_STATUS_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x25aa
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#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x25ab
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#define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
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#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x25ac
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#define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
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#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x25ad
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#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
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#define mmDIG5_DIG_BE_CNTL 0x25af
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#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2
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#define mmDIG5_DIG_BE_EN_CNTL 0x25b0
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#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2
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#define mmDIG5_TMDS_CNTL 0x25d3
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#define mmDIG5_TMDS_CNTL_BASE_IDX 2
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#define mmDIG5_TMDS_CONTROL_CHAR 0x25d4
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#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2
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#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x25d5
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#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
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#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x25d6
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#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
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#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x25d7
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#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
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#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x25d8
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#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
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#define mmDIG5_TMDS_CTL_BITS 0x25da
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#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2
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#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x25db
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#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
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#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x25dd
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#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
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#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x25de
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#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
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#define mmDIG5_DIG_VERSION 0x25e0
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#define mmDIG5_DIG_VERSION_BASE_IDX 2
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#define mmDIG5_DIG_LANE_ENABLE 0x25e1
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#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2
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#define mmDIG5_AFMT_CNTL 0x25e6
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#define mmDIG5_AFMT_CNTL_BASE_IDX 2
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#define mmDIG5_AFMT_VBI_PACKET_CONTROL1 0x25e7
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#define mmDIG5_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
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|
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// addressBlock: dce_dc_dio_dp5_dispdec
|
// base address: 0x1400
|
#define mmDP5_DP_LINK_CNTL 0x2608
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#define mmDP5_DP_LINK_CNTL_BASE_IDX 2
|
#define mmDP5_DP_PIXEL_FORMAT 0x2609
|
#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2
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#define mmDP5_DP_MSA_COLORIMETRY 0x260a
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#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2
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#define mmDP5_DP_CONFIG 0x260b
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#define mmDP5_DP_CONFIG_BASE_IDX 2
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#define mmDP5_DP_VID_STREAM_CNTL 0x260c
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#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2
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#define mmDP5_DP_STEER_FIFO 0x260d
|
#define mmDP5_DP_STEER_FIFO_BASE_IDX 2
|
#define mmDP5_DP_MSA_MISC 0x260e
|
#define mmDP5_DP_MSA_MISC_BASE_IDX 2
|
#define mmDP5_DP_VID_TIMING 0x2610
|
#define mmDP5_DP_VID_TIMING_BASE_IDX 2
|
#define mmDP5_DP_VID_N 0x2611
|
#define mmDP5_DP_VID_N_BASE_IDX 2
|
#define mmDP5_DP_VID_M 0x2612
|
#define mmDP5_DP_VID_M_BASE_IDX 2
|
#define mmDP5_DP_LINK_FRAMING_CNTL 0x2613
|
#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2
|
#define mmDP5_DP_HBR2_EYE_PATTERN 0x2614
|
#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2
|
#define mmDP5_DP_VID_MSA_VBID 0x2615
|
#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2
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#define mmDP5_DP_VID_INTERRUPT_CNTL 0x2616
|
#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CNTL 0x2617
|
#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2
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#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x2618
|
#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_SYM0 0x2619
|
#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2
|
#define mmDP5_DP_DPHY_SYM1 0x261a
|
#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2
|
#define mmDP5_DP_DPHY_SYM2 0x261b
|
#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2
|
#define mmDP5_DP_DPHY_8B10B_CNTL 0x261c
|
#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_PRBS_CNTL 0x261d
|
#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_SCRAM_CNTL 0x261e
|
#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_EN 0x261f
|
#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_CNTL 0x2620
|
#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_RESULT 0x2621
|
#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x2622
|
#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
|
#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x2623
|
#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
|
#define mmDP5_DP_DPHY_FAST_TRAINING 0x2624
|
#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2
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#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x2625
|
#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
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#define mmDP5_DP_SEC_CNTL 0x262b
|
#define mmDP5_DP_SEC_CNTL_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL1 0x262c
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#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2
|
#define mmDP5_DP_SEC_FRAMING1 0x262d
|
#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2
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#define mmDP5_DP_SEC_FRAMING2 0x262e
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#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2
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#define mmDP5_DP_SEC_FRAMING3 0x262f
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#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2
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#define mmDP5_DP_SEC_FRAMING4 0x2630
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#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2
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#define mmDP5_DP_SEC_AUD_N 0x2631
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#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2
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#define mmDP5_DP_SEC_AUD_N_READBACK 0x2632
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#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2
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#define mmDP5_DP_SEC_AUD_M 0x2633
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#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2
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#define mmDP5_DP_SEC_AUD_M_READBACK 0x2634
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#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2
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#define mmDP5_DP_SEC_TIMESTAMP 0x2635
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#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2
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#define mmDP5_DP_SEC_PACKET_CNTL 0x2636
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#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2
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#define mmDP5_DP_MSE_RATE_CNTL 0x2637
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#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2
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#define mmDP5_DP_MSE_RATE_UPDATE 0x2639
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#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT0 0x263a
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#define mmDP5_DP_MSE_SAT0_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT1 0x263b
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#define mmDP5_DP_MSE_SAT1_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT2 0x263c
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#define mmDP5_DP_MSE_SAT2_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT_UPDATE 0x263d
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#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2
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#define mmDP5_DP_MSE_LINK_TIMING 0x263e
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#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2
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#define mmDP5_DP_MSE_MISC_CNTL 0x263f
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#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2
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#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x2644
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#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
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#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x2645
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#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT0_STATUS 0x2647
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#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT1_STATUS 0x2648
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#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2
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#define mmDP5_DP_MSE_SAT2_STATUS 0x2649
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#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2
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#define mmDP5_DP_MSA_TIMING_PARAM1 0x264c
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#define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 2
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#define mmDP5_DP_MSA_TIMING_PARAM2 0x264d
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#define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX 2
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#define mmDP5_DP_MSA_TIMING_PARAM3 0x264e
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#define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX 2
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#define mmDP5_DP_MSA_TIMING_PARAM4 0x264f
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#define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX 2
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#define mmDP5_DP_MSO_CNTL 0x2650
|
#define mmDP5_DP_MSO_CNTL_BASE_IDX 2
|
#define mmDP5_DP_MSO_CNTL1 0x2651
|
#define mmDP5_DP_MSO_CNTL1_BASE_IDX 2
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#define mmDP5_DP_DSC_CNTL 0x2652
|
#define mmDP5_DP_DSC_CNTL_BASE_IDX 2
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#define mmDP5_DP_SEC_CNTL2 0x2653
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#define mmDP5_DP_SEC_CNTL2_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL3 0x2654
|
#define mmDP5_DP_SEC_CNTL3_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL4 0x2655
|
#define mmDP5_DP_SEC_CNTL4_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL5 0x2656
|
#define mmDP5_DP_SEC_CNTL5_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL6 0x2657
|
#define mmDP5_DP_SEC_CNTL6_BASE_IDX 2
|
#define mmDP5_DP_SEC_CNTL7 0x2658
|
#define mmDP5_DP_SEC_CNTL7_BASE_IDX 2
|
#define mmDP5_DP_DB_CNTL 0x2659
|
#define mmDP5_DP_DB_CNTL_BASE_IDX 2
|
#define mmDP5_DP_MSA_VBID_MISC 0x265a
|
#define mmDP5_DP_MSA_VBID_MISC_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dig6_dispdec
|
// base address: 0x1800
|
#define mmDIG6_DIG_FE_CNTL 0x2668
|
#define mmDIG6_DIG_FE_CNTL_BASE_IDX 2
|
#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x2669
|
#define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2
|
#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x266a
|
#define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2
|
#define mmDIG6_DIG_CLOCK_PATTERN 0x266b
|
#define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX 2
|
#define mmDIG6_DIG_TEST_PATTERN 0x266c
|
#define mmDIG6_DIG_TEST_PATTERN_BASE_IDX 2
|
#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x266d
|
#define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2
|
#define mmDIG6_DIG_FIFO_STATUS 0x266e
|
#define mmDIG6_DIG_FIFO_STATUS_BASE_IDX 2
|
#define mmDIG6_HDMI_CONTROL 0x2671
|
#define mmDIG6_HDMI_CONTROL_BASE_IDX 2
|
#define mmDIG6_HDMI_STATUS 0x2672
|
#define mmDIG6_HDMI_STATUS_BASE_IDX 2
|
#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x2673
|
#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x2674
|
#define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x2675
|
#define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x2676
|
#define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x2677
|
#define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2
|
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x2678
|
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2
|
#define mmDIG6_AFMT_INTERRUPT_STATUS 0x2679
|
#define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX 2
|
#define mmDIG6_HDMI_GC 0x267b
|
#define mmDIG6_HDMI_GC_BASE_IDX 2
|
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x267c
|
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG6_AFMT_ISRC1_0 0x267d
|
#define mmDIG6_AFMT_ISRC1_0_BASE_IDX 2
|
#define mmDIG6_AFMT_ISRC1_1 0x267e
|
#define mmDIG6_AFMT_ISRC1_1_BASE_IDX 2
|
#define mmDIG6_AFMT_ISRC1_2 0x267f
|
#define mmDIG6_AFMT_ISRC1_2_BASE_IDX 2
|
#define mmDIG6_AFMT_ISRC1_3 0x2680
|
#define mmDIG6_AFMT_ISRC1_3_BASE_IDX 2
|
#define mmDIG6_AFMT_ISRC1_4 0x2681
|
#define mmDIG6_AFMT_ISRC1_4_BASE_IDX 2
|
#define mmDIG6_AFMT_ISRC2_0 0x2682
|
#define mmDIG6_AFMT_ISRC2_0_BASE_IDX 2
|
#define mmDIG6_AFMT_ISRC2_1 0x2683
|
#define mmDIG6_AFMT_ISRC2_1_BASE_IDX 2
|
#define mmDIG6_AFMT_ISRC2_2 0x2684
|
#define mmDIG6_AFMT_ISRC2_2_BASE_IDX 2
|
#define mmDIG6_AFMT_ISRC2_3 0x2685
|
#define mmDIG6_AFMT_ISRC2_3_BASE_IDX 2
|
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2 0x2686
|
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2
|
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3 0x2687
|
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2
|
#define mmDIG6_HDMI_DB_CONTROL 0x2688
|
#define mmDIG6_HDMI_DB_CONTROL_BASE_IDX 2
|
#define mmDIG6_AFMT_MPEG_INFO0 0x268a
|
#define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX 2
|
#define mmDIG6_AFMT_MPEG_INFO1 0x268b
|
#define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX 2
|
#define mmDIG6_AFMT_GENERIC_HDR 0x268c
|
#define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX 2
|
#define mmDIG6_AFMT_GENERIC_0 0x268d
|
#define mmDIG6_AFMT_GENERIC_0_BASE_IDX 2
|
#define mmDIG6_AFMT_GENERIC_1 0x268e
|
#define mmDIG6_AFMT_GENERIC_1_BASE_IDX 2
|
#define mmDIG6_AFMT_GENERIC_2 0x268f
|
#define mmDIG6_AFMT_GENERIC_2_BASE_IDX 2
|
#define mmDIG6_AFMT_GENERIC_3 0x2690
|
#define mmDIG6_AFMT_GENERIC_3_BASE_IDX 2
|
#define mmDIG6_AFMT_GENERIC_4 0x2691
|
#define mmDIG6_AFMT_GENERIC_4_BASE_IDX 2
|
#define mmDIG6_AFMT_GENERIC_5 0x2692
|
#define mmDIG6_AFMT_GENERIC_5_BASE_IDX 2
|
#define mmDIG6_AFMT_GENERIC_6 0x2693
|
#define mmDIG6_AFMT_GENERIC_6_BASE_IDX 2
|
#define mmDIG6_AFMT_GENERIC_7 0x2694
|
#define mmDIG6_AFMT_GENERIC_7_BASE_IDX 2
|
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x2695
|
#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2
|
#define mmDIG6_HDMI_ACR_32_0 0x2696
|
#define mmDIG6_HDMI_ACR_32_0_BASE_IDX 2
|
#define mmDIG6_HDMI_ACR_32_1 0x2697
|
#define mmDIG6_HDMI_ACR_32_1_BASE_IDX 2
|
#define mmDIG6_HDMI_ACR_44_0 0x2698
|
#define mmDIG6_HDMI_ACR_44_0_BASE_IDX 2
|
#define mmDIG6_HDMI_ACR_44_1 0x2699
|
#define mmDIG6_HDMI_ACR_44_1_BASE_IDX 2
|
#define mmDIG6_HDMI_ACR_48_0 0x269a
|
#define mmDIG6_HDMI_ACR_48_0_BASE_IDX 2
|
#define mmDIG6_HDMI_ACR_48_1 0x269b
|
#define mmDIG6_HDMI_ACR_48_1_BASE_IDX 2
|
#define mmDIG6_HDMI_ACR_STATUS_0 0x269c
|
#define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX 2
|
#define mmDIG6_HDMI_ACR_STATUS_1 0x269d
|
#define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX 2
|
#define mmDIG6_AFMT_AUDIO_INFO0 0x269e
|
#define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX 2
|
#define mmDIG6_AFMT_AUDIO_INFO1 0x269f
|
#define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX 2
|
#define mmDIG6_AFMT_60958_0 0x26a0
|
#define mmDIG6_AFMT_60958_0_BASE_IDX 2
|
#define mmDIG6_AFMT_60958_1 0x26a1
|
#define mmDIG6_AFMT_60958_1_BASE_IDX 2
|
#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x26a2
|
#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2
|
#define mmDIG6_AFMT_RAMP_CONTROL0 0x26a3
|
#define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX 2
|
#define mmDIG6_AFMT_RAMP_CONTROL1 0x26a4
|
#define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX 2
|
#define mmDIG6_AFMT_RAMP_CONTROL2 0x26a5
|
#define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX 2
|
#define mmDIG6_AFMT_RAMP_CONTROL3 0x26a6
|
#define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX 2
|
#define mmDIG6_AFMT_60958_2 0x26a7
|
#define mmDIG6_AFMT_60958_2_BASE_IDX 2
|
#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x26a8
|
#define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2
|
#define mmDIG6_AFMT_STATUS 0x26a9
|
#define mmDIG6_AFMT_STATUS_BASE_IDX 2
|
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x26aa
|
#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x26ab
|
#define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2
|
#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x26ac
|
#define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2
|
#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x26ad
|
#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2
|
#define mmDIG6_DIG_BE_CNTL 0x26af
|
#define mmDIG6_DIG_BE_CNTL_BASE_IDX 2
|
#define mmDIG6_DIG_BE_EN_CNTL 0x26b0
|
#define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX 2
|
#define mmDIG6_TMDS_CNTL 0x26d3
|
#define mmDIG6_TMDS_CNTL_BASE_IDX 2
|
#define mmDIG6_TMDS_CONTROL_CHAR 0x26d4
|
#define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX 2
|
#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x26d5
|
#define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2
|
#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x26d6
|
#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2
|
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x26d7
|
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2
|
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x26d8
|
#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2
|
#define mmDIG6_TMDS_CTL_BITS 0x26da
|
#define mmDIG6_TMDS_CTL_BITS_BASE_IDX 2
|
#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x26db
|
#define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX 2
|
#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x26dd
|
#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2
|
#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x26de
|
#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2
|
#define mmDIG6_DIG_VERSION 0x26e0
|
#define mmDIG6_DIG_VERSION_BASE_IDX 2
|
#define mmDIG6_DIG_LANE_ENABLE 0x26e1
|
#define mmDIG6_DIG_LANE_ENABLE_BASE_IDX 2
|
#define mmDIG6_AFMT_CNTL 0x26e6
|
#define mmDIG6_AFMT_CNTL_BASE_IDX 2
|
#define mmDIG6_AFMT_VBI_PACKET_CONTROL1 0x26e7
|
#define mmDIG6_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dio_dp6_dispdec
|
// base address: 0x1800
|
#define mmDP6_DP_LINK_CNTL 0x2708
|
#define mmDP6_DP_LINK_CNTL_BASE_IDX 2
|
#define mmDP6_DP_PIXEL_FORMAT 0x2709
|
#define mmDP6_DP_PIXEL_FORMAT_BASE_IDX 2
|
#define mmDP6_DP_MSA_COLORIMETRY 0x270a
|
#define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX 2
|
#define mmDP6_DP_CONFIG 0x270b
|
#define mmDP6_DP_CONFIG_BASE_IDX 2
|
#define mmDP6_DP_VID_STREAM_CNTL 0x270c
|
#define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX 2
|
#define mmDP6_DP_STEER_FIFO 0x270d
|
#define mmDP6_DP_STEER_FIFO_BASE_IDX 2
|
#define mmDP6_DP_MSA_MISC 0x270e
|
#define mmDP6_DP_MSA_MISC_BASE_IDX 2
|
#define mmDP6_DP_VID_TIMING 0x2710
|
#define mmDP6_DP_VID_TIMING_BASE_IDX 2
|
#define mmDP6_DP_VID_N 0x2711
|
#define mmDP6_DP_VID_N_BASE_IDX 2
|
#define mmDP6_DP_VID_M 0x2712
|
#define mmDP6_DP_VID_M_BASE_IDX 2
|
#define mmDP6_DP_LINK_FRAMING_CNTL 0x2713
|
#define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX 2
|
#define mmDP6_DP_HBR2_EYE_PATTERN 0x2714
|
#define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX 2
|
#define mmDP6_DP_VID_MSA_VBID 0x2715
|
#define mmDP6_DP_VID_MSA_VBID_BASE_IDX 2
|
#define mmDP6_DP_VID_INTERRUPT_CNTL 0x2716
|
#define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX 2
|
#define mmDP6_DP_DPHY_CNTL 0x2717
|
#define mmDP6_DP_DPHY_CNTL_BASE_IDX 2
|
#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x2718
|
#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
|
#define mmDP6_DP_DPHY_SYM0 0x2719
|
#define mmDP6_DP_DPHY_SYM0_BASE_IDX 2
|
#define mmDP6_DP_DPHY_SYM1 0x271a
|
#define mmDP6_DP_DPHY_SYM1_BASE_IDX 2
|
#define mmDP6_DP_DPHY_SYM2 0x271b
|
#define mmDP6_DP_DPHY_SYM2_BASE_IDX 2
|
#define mmDP6_DP_DPHY_8B10B_CNTL 0x271c
|
#define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX 2
|
#define mmDP6_DP_DPHY_PRBS_CNTL 0x271d
|
#define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX 2
|
#define mmDP6_DP_DPHY_SCRAM_CNTL 0x271e
|
#define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX 2
|
#define mmDP6_DP_DPHY_CRC_EN 0x271f
|
#define mmDP6_DP_DPHY_CRC_EN_BASE_IDX 2
|
#define mmDP6_DP_DPHY_CRC_CNTL 0x2720
|
#define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX 2
|
#define mmDP6_DP_DPHY_CRC_RESULT 0x2721
|
#define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX 2
|
#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x2722
|
#define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2
|
#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x2723
|
#define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2
|
#define mmDP6_DP_DPHY_FAST_TRAINING 0x2724
|
#define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX 2
|
#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x2725
|
#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2
|
#define mmDP6_DP_SEC_CNTL 0x272b
|
#define mmDP6_DP_SEC_CNTL_BASE_IDX 2
|
#define mmDP6_DP_SEC_CNTL1 0x272c
|
#define mmDP6_DP_SEC_CNTL1_BASE_IDX 2
|
#define mmDP6_DP_SEC_FRAMING1 0x272d
|
#define mmDP6_DP_SEC_FRAMING1_BASE_IDX 2
|
#define mmDP6_DP_SEC_FRAMING2 0x272e
|
#define mmDP6_DP_SEC_FRAMING2_BASE_IDX 2
|
#define mmDP6_DP_SEC_FRAMING3 0x272f
|
#define mmDP6_DP_SEC_FRAMING3_BASE_IDX 2
|
#define mmDP6_DP_SEC_FRAMING4 0x2730
|
#define mmDP6_DP_SEC_FRAMING4_BASE_IDX 2
|
#define mmDP6_DP_SEC_AUD_N 0x2731
|
#define mmDP6_DP_SEC_AUD_N_BASE_IDX 2
|
#define mmDP6_DP_SEC_AUD_N_READBACK 0x2732
|
#define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX 2
|
#define mmDP6_DP_SEC_AUD_M 0x2733
|
#define mmDP6_DP_SEC_AUD_M_BASE_IDX 2
|
#define mmDP6_DP_SEC_AUD_M_READBACK 0x2734
|
#define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX 2
|
#define mmDP6_DP_SEC_TIMESTAMP 0x2735
|
#define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX 2
|
#define mmDP6_DP_SEC_PACKET_CNTL 0x2736
|
#define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX 2
|
#define mmDP6_DP_MSE_RATE_CNTL 0x2737
|
#define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX 2
|
#define mmDP6_DP_MSE_RATE_UPDATE 0x2739
|
#define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX 2
|
#define mmDP6_DP_MSE_SAT0 0x273a
|
#define mmDP6_DP_MSE_SAT0_BASE_IDX 2
|
#define mmDP6_DP_MSE_SAT1 0x273b
|
#define mmDP6_DP_MSE_SAT1_BASE_IDX 2
|
#define mmDP6_DP_MSE_SAT2 0x273c
|
#define mmDP6_DP_MSE_SAT2_BASE_IDX 2
|
#define mmDP6_DP_MSE_SAT_UPDATE 0x273d
|
#define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX 2
|
#define mmDP6_DP_MSE_LINK_TIMING 0x273e
|
#define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX 2
|
#define mmDP6_DP_MSE_MISC_CNTL 0x273f
|
#define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX 2
|
#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x2744
|
#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2
|
#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x2745
|
#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
|
#define mmDP6_DP_MSE_SAT0_STATUS 0x2747
|
#define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX 2
|
#define mmDP6_DP_MSE_SAT1_STATUS 0x2748
|
#define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX 2
|
#define mmDP6_DP_MSE_SAT2_STATUS 0x2749
|
#define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX 2
|
#define mmDP6_DP_MSA_TIMING_PARAM1 0x274c
|
#define mmDP6_DP_MSA_TIMING_PARAM1_BASE_IDX 2
|
#define mmDP6_DP_MSA_TIMING_PARAM2 0x274d
|
#define mmDP6_DP_MSA_TIMING_PARAM2_BASE_IDX 2
|
#define mmDP6_DP_MSA_TIMING_PARAM3 0x274e
|
#define mmDP6_DP_MSA_TIMING_PARAM3_BASE_IDX 2
|
#define mmDP6_DP_MSA_TIMING_PARAM4 0x274f
|
#define mmDP6_DP_MSA_TIMING_PARAM4_BASE_IDX 2
|
#define mmDP6_DP_MSO_CNTL 0x2750
|
#define mmDP6_DP_MSO_CNTL_BASE_IDX 2
|
#define mmDP6_DP_MSO_CNTL1 0x2751
|
#define mmDP6_DP_MSO_CNTL1_BASE_IDX 2
|
#define mmDP6_DP_DSC_CNTL 0x2752
|
#define mmDP6_DP_DSC_CNTL_BASE_IDX 2
|
#define mmDP6_DP_SEC_CNTL2 0x2753
|
#define mmDP6_DP_SEC_CNTL2_BASE_IDX 2
|
#define mmDP6_DP_SEC_CNTL3 0x2754
|
#define mmDP6_DP_SEC_CNTL3_BASE_IDX 2
|
#define mmDP6_DP_SEC_CNTL4 0x2755
|
#define mmDP6_DP_SEC_CNTL4_BASE_IDX 2
|
#define mmDP6_DP_SEC_CNTL5 0x2756
|
#define mmDP6_DP_SEC_CNTL5_BASE_IDX 2
|
#define mmDP6_DP_SEC_CNTL6 0x2757
|
#define mmDP6_DP_SEC_CNTL6_BASE_IDX 2
|
#define mmDP6_DP_SEC_CNTL7 0x2758
|
#define mmDP6_DP_SEC_CNTL7_BASE_IDX 2
|
#define mmDP6_DP_DB_CNTL 0x2759
|
#define mmDP6_DP_DB_CNTL_BASE_IDX 2
|
#define mmDP6_DP_MSA_VBID_MISC 0x275a
|
#define mmDP6_DP_MSA_VBID_MISC_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcio_dcio_dispdec
|
// base address: 0x0
|
#define mmDC_GENERICA 0x2868
|
#define mmDC_GENERICA_BASE_IDX 2
|
#define mmDC_GENERICB 0x2869
|
#define mmDC_GENERICB_BASE_IDX 2
|
#define mmDC_REF_CLK_CNTL 0x286b
|
#define mmDC_REF_CLK_CNTL_BASE_IDX 2
|
#define mmDC_GPIO_DEBUG 0x286c
|
#define mmDC_GPIO_DEBUG_BASE_IDX 2
|
#define mmUNIPHYA_LINK_CNTL 0x286d
|
#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e
|
#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYB_LINK_CNTL 0x286f
|
#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870
|
#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYC_LINK_CNTL 0x2871
|
#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872
|
#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYD_LINK_CNTL 0x2873
|
#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874
|
#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYE_LINK_CNTL 0x2875
|
#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876
|
#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYF_LINK_CNTL 0x2877
|
#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x2878
|
#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmUNIPHYG_LINK_CNTL 0x2879
|
#define mmUNIPHYG_LINK_CNTL_BASE_IDX 2
|
#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x287a
|
#define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2
|
#define mmDCIO_WRCMD_DELAY 0x287e
|
#define mmDCIO_WRCMD_DELAY_BASE_IDX 2
|
#define mmDC_PINSTRAPS 0x2880
|
#define mmDC_PINSTRAPS_BASE_IDX 2
|
#define mmDC_DVODATA_CONFIG 0x2882
|
#define mmDC_DVODATA_CONFIG_BASE_IDX 2
|
#define mmLVTMA_PWRSEQ_CNTL 0x2883
|
#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2
|
#define mmLVTMA_PWRSEQ_STATE 0x2884
|
#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2
|
#define mmLVTMA_PWRSEQ_REF_DIV 0x2885
|
#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2
|
#define mmLVTMA_PWRSEQ_DELAY1 0x2886
|
#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2
|
#define mmLVTMA_PWRSEQ_DELAY2 0x2887
|
#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2
|
#define mmBL_PWM_CNTL 0x2888
|
#define mmBL_PWM_CNTL_BASE_IDX 2
|
#define mmBL_PWM_CNTL2 0x2889
|
#define mmBL_PWM_CNTL2_BASE_IDX 2
|
#define mmBL_PWM_PERIOD_CNTL 0x288a
|
#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2
|
#define mmBL_PWM_GRP1_REG_LOCK 0x288b
|
#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2
|
#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c
|
#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2
|
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d
|
#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2
|
#define mmDCIO_CLOCK_CNTL 0x2895
|
#define mmDCIO_CLOCK_CNTL_BASE_IDX 2
|
#define mmDIO_OTG_EXT_VSYNC_CNTL 0x2898
|
#define mmDIO_OTG_EXT_VSYNC_CNTL_BASE_IDX 2
|
#define mmDCIO_SOFT_RESET 0x289e
|
#define mmDCIO_SOFT_RESET_BASE_IDX 2
|
#define mmDCIO_DPHY_SEL 0x289f
|
#define mmDCIO_DPHY_SEL_BASE_IDX 2
|
#define mmUNIPHY_IMPCAL_LINKA 0x28a0
|
#define mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2
|
#define mmUNIPHY_IMPCAL_LINKB 0x28a1
|
#define mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2
|
#define mmUNIPHY_IMPCAL_PERIOD 0x28a2
|
#define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2
|
#define mmAUXP_IMPCAL 0x28a3
|
#define mmAUXP_IMPCAL_BASE_IDX 2
|
#define mmAUXN_IMPCAL 0x28a4
|
#define mmAUXN_IMPCAL_BASE_IDX 2
|
#define mmDCIO_IMPCAL_CNTL 0x28a5
|
#define mmDCIO_IMPCAL_CNTL_BASE_IDX 2
|
#define mmUNIPHY_IMPCAL_PSW_AB 0x28a6
|
#define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2
|
#define mmUNIPHY_IMPCAL_LINKC 0x28a7
|
#define mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2
|
#define mmUNIPHY_IMPCAL_LINKD 0x28a8
|
#define mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2
|
#define mmDCIO_IMPCAL_CNTL_CD 0x28a9
|
#define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2
|
#define mmUNIPHY_IMPCAL_PSW_CD 0x28aa
|
#define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2
|
#define mmUNIPHY_IMPCAL_LINKE 0x28ab
|
#define mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2
|
#define mmUNIPHY_IMPCAL_LINKF 0x28ac
|
#define mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2
|
#define mmDCIO_IMPCAL_CNTL_EF 0x28ad
|
#define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2
|
#define mmUNIPHY_IMPCAL_PSW_EF 0x28ae
|
#define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2
|
#define mmDCIO_DPCS_TX_INTERRUPT 0x28b3
|
#define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2
|
#define mmDCIO_DPCS_RX_INTERRUPT 0x28b4
|
#define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2
|
#define mmDCIO_SEMAPHORE0 0x28b5
|
#define mmDCIO_SEMAPHORE0_BASE_IDX 2
|
#define mmDCIO_SEMAPHORE1 0x28b6
|
#define mmDCIO_SEMAPHORE1_BASE_IDX 2
|
#define mmDCIO_SEMAPHORE2 0x28b7
|
#define mmDCIO_SEMAPHORE2_BASE_IDX 2
|
#define mmDCIO_SEMAPHORE3 0x28b8
|
#define mmDCIO_SEMAPHORE3_BASE_IDX 2
|
#define mmDCIO_SEMAPHORE4 0x28b9
|
#define mmDCIO_SEMAPHORE4_BASE_IDX 2
|
#define mmDCIO_SEMAPHORE5 0x28ba
|
#define mmDCIO_SEMAPHORE5_BASE_IDX 2
|
#define mmDCIO_SEMAPHORE6 0x28bb
|
#define mmDCIO_SEMAPHORE6_BASE_IDX 2
|
#define mmDCIO_SEMAPHORE7 0x28bc
|
#define mmDCIO_SEMAPHORE7_BASE_IDX 2
|
#define mmDCIO_USBC_FLIP_EN_SEL 0x28bd
|
#define mmDCIO_USBC_FLIP_EN_SEL_BASE_IDX 2
|
|
|
// addressBlock: dce_dc_dcio_dcio_chip_dispdec
|
// base address: 0x0
|
#define mmDC_GPIO_GENERIC_MASK 0x28c8
|
#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2
|
#define mmDC_GPIO_GENERIC_A 0x28c9
|
#define mmDC_GPIO_GENERIC_A_BASE_IDX 2
|
#define mmDC_GPIO_GENERIC_EN 0x28ca
|
#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2
|
#define mmDC_GPIO_GENERIC_Y 0x28cb
|
#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2
|
#define mmDC_GPIO_DVODATA_MASK 0x28cc
|
#define mmDC_GPIO_DVODATA_MASK_BASE_IDX 2
|
#define mmDC_GPIO_DVODATA_A 0x28cd
|
#define mmDC_GPIO_DVODATA_A_BASE_IDX 2
|
#define mmDC_GPIO_DVODATA_EN 0x28ce
|
#define mmDC_GPIO_DVODATA_EN_BASE_IDX 2
|
#define mmDC_GPIO_DVODATA_Y 0x28cf
|
#define mmDC_GPIO_DVODATA_Y_BASE_IDX 2
|
#define mmDC_GPIO_DDC1_MASK 0x28d0
|
#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2
|
#define mmDC_GPIO_DDC1_A 0x28d1
|
#define mmDC_GPIO_DDC1_A_BASE_IDX 2
|
#define mmDC_GPIO_DDC1_EN 0x28d2
|
#define mmDC_GPIO_DDC1_EN_BASE_IDX 2
|
#define mmDC_GPIO_DDC1_Y 0x28d3
|
#define mmDC_GPIO_DDC1_Y_BASE_IDX 2
|
#define mmDC_GPIO_DDC2_MASK 0x28d4
|
#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2
|
#define mmDC_GPIO_DDC2_A 0x28d5
|
#define mmDC_GPIO_DDC2_A_BASE_IDX 2
|
#define mmDC_GPIO_DDC2_EN 0x28d6
|
#define mmDC_GPIO_DDC2_EN_BASE_IDX 2
|
#define mmDC_GPIO_DDC2_Y 0x28d7
|
#define mmDC_GPIO_DDC2_Y_BASE_IDX 2
|
#define mmDC_GPIO_DDC3_MASK 0x28d8
|
#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2
|
#define mmDC_GPIO_DDC3_A 0x28d9
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#define mmDC_GPIO_DDC3_A_BASE_IDX 2
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#define mmDC_GPIO_DDC3_EN 0x28da
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#define mmDC_GPIO_DDC3_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC3_Y 0x28db
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#define mmDC_GPIO_DDC3_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC4_MASK 0x28dc
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#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC4_A 0x28dd
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#define mmDC_GPIO_DDC4_A_BASE_IDX 2
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#define mmDC_GPIO_DDC4_EN 0x28de
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#define mmDC_GPIO_DDC4_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC4_Y 0x28df
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#define mmDC_GPIO_DDC4_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC5_MASK 0x28e0
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#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC5_A 0x28e1
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#define mmDC_GPIO_DDC5_A_BASE_IDX 2
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#define mmDC_GPIO_DDC5_EN 0x28e2
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#define mmDC_GPIO_DDC5_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC5_Y 0x28e3
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#define mmDC_GPIO_DDC5_Y_BASE_IDX 2
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#define mmDC_GPIO_DDC6_MASK 0x28e4
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#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDC6_A 0x28e5
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#define mmDC_GPIO_DDC6_A_BASE_IDX 2
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#define mmDC_GPIO_DDC6_EN 0x28e6
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#define mmDC_GPIO_DDC6_EN_BASE_IDX 2
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#define mmDC_GPIO_DDC6_Y 0x28e7
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#define mmDC_GPIO_DDC6_Y_BASE_IDX 2
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#define mmDC_GPIO_DDCVGA_MASK 0x28e8
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#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2
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#define mmDC_GPIO_DDCVGA_A 0x28e9
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#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2
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#define mmDC_GPIO_DDCVGA_EN 0x28ea
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#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2
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#define mmDC_GPIO_DDCVGA_Y 0x28eb
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#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2
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#define mmDC_GPIO_SYNCA_MASK 0x28ec
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#define mmDC_GPIO_SYNCA_MASK_BASE_IDX 2
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#define mmDC_GPIO_SYNCA_A 0x28ed
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#define mmDC_GPIO_SYNCA_A_BASE_IDX 2
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#define mmDC_GPIO_SYNCA_EN 0x28ee
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#define mmDC_GPIO_SYNCA_EN_BASE_IDX 2
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#define mmDC_GPIO_SYNCA_Y 0x28ef
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#define mmDC_GPIO_SYNCA_Y_BASE_IDX 2
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#define mmDC_GPIO_GENLK_MASK 0x28f0
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#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2
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#define mmDC_GPIO_GENLK_A 0x28f1
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#define mmDC_GPIO_GENLK_A_BASE_IDX 2
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#define mmDC_GPIO_GENLK_EN 0x28f2
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#define mmDC_GPIO_GENLK_EN_BASE_IDX 2
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#define mmDC_GPIO_GENLK_Y 0x28f3
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#define mmDC_GPIO_GENLK_Y_BASE_IDX 2
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#define mmDC_GPIO_HPD_MASK 0x28f4
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#define mmDC_GPIO_HPD_MASK_BASE_IDX 2
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#define mmDC_GPIO_HPD_A 0x28f5
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#define mmDC_GPIO_HPD_A_BASE_IDX 2
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#define mmDC_GPIO_HPD_EN 0x28f6
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#define mmDC_GPIO_HPD_EN_BASE_IDX 2
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#define mmDC_GPIO_HPD_Y 0x28f7
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#define mmDC_GPIO_HPD_Y_BASE_IDX 2
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#define mmDC_GPIO_PWRSEQ_MASK 0x28f8
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#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2
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#define mmDC_GPIO_PWRSEQ_A 0x28f9
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#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2
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#define mmDC_GPIO_PWRSEQ_EN 0x28fa
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#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2
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#define mmDC_GPIO_PWRSEQ_Y 0x28fb
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#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2
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#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc
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#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2
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#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd
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#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2
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#define mmPHY_AUX_CNTL 0x28ff
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#define mmPHY_AUX_CNTL_BASE_IDX 2
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#define mmDC_GPIO_I2CPAD_MASK 0x2900
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#define mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2
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#define mmDC_GPIO_I2CPAD_A 0x2901
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#define mmDC_GPIO_I2CPAD_A_BASE_IDX 2
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#define mmDC_GPIO_I2CPAD_EN 0x2902
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#define mmDC_GPIO_I2CPAD_EN_BASE_IDX 2
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#define mmDC_GPIO_I2CPAD_Y 0x2903
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#define mmDC_GPIO_I2CPAD_Y_BASE_IDX 2
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#define mmDC_GPIO_I2CPAD_STRENGTH 0x2904
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#define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2
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#define mmDVO_STRENGTH_CONTROL 0x2905
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#define mmDVO_STRENGTH_CONTROL_BASE_IDX 2
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#define mmDVO_VREF_CONTROL 0x2906
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#define mmDVO_VREF_CONTROL_BASE_IDX 2
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#define mmDVO_SKEW_ADJUST 0x2907
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#define mmDVO_SKEW_ADJUST_BASE_IDX 2
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#define mmDC_GPIO_I2S_SPDIF_MASK 0x2910
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#define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2
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#define mmDC_GPIO_I2S_SPDIF_A 0x2911
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#define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2
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#define mmDC_GPIO_I2S_SPDIF_EN 0x2912
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#define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2
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#define mmDC_GPIO_I2S_SPDIF_Y 0x2913
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#define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2
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#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x2914
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#define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2
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#define mmDC_GPIO_TX12_EN 0x2915
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#define mmDC_GPIO_TX12_EN_BASE_IDX 2
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#define mmDC_GPIO_AUX_CTRL_0 0x2916
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#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2
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#define mmDC_GPIO_AUX_CTRL_1 0x2917
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#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2
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#define mmDC_GPIO_AUX_CTRL_2 0x2918
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#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2
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#define mmDC_GPIO_RXEN 0x2919
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#define mmDC_GPIO_RXEN_BASE_IDX 2
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#define mmDC_GPIO_PULLUPEN 0x291a
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#define mmDC_GPIO_PULLUPEN_BASE_IDX 2
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// addressBlock: dce_dc_dcio_dcio_dac_dispdec
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// base address: 0x0
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#define mmDAC_MACRO_CNTL_RESERVED0 0x2920
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#define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDAC_MACRO_CNTL_RESERVED1 0x2921
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#define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDAC_MACRO_CNTL_RESERVED2 0x2922
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#define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDAC_MACRO_CNTL_RESERVED3 0x2923
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#define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2
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// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec
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// base address: 0x0
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x2958
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x2959
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x295a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x295b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x295c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x295d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x295e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x295f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2960
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2961
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x2962
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x2963
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x2964
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x2965
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x2966
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x2967
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x2968
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x2969
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x296a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x296b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x296c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x296d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x296e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x296f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x2970
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x2971
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x2972
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x2973
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x2974
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x2975
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x2976
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x2977
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x2978
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x2979
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x297a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x297b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x297c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x297d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x297e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x297f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x2980
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x2981
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x2982
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x2983
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x2984
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x2985
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x2986
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x2987
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x2988
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x2989
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x298a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x298b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x298c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x298d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x298e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x298f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x2990
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x2991
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x2992
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x2993
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x2994
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x2995
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x2996
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x2997
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x2998
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x2999
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x299a
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x299b
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x299c
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x299d
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x299e
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x299f
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x29a0
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x29a1
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x29a2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x29a3
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x29a4
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x29a5
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x29a6
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x29a7
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x29a8
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x29a9
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x29aa
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x29ab
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x29ac
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x29ad
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x29ae
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x29af
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x29b0
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x29b1
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x29b2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x29b3
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x29b4
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x29b5
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x29b6
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x29b7
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x29b8
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x29b9
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x29ba
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x29bb
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x29bc
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x29bd
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x29be
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x29bf
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x29c0
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x29c1
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x29c2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x29c3
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x29c4
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x29c5
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x29c6
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x29c7
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#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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// addressBlock: dce_dc_combophy_dc_combophycmregs0_dispdec
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// base address: 0x0
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#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0x2928
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#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0x2929
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#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0x292a
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#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x292b
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#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x292c
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#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x292d
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#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x292e
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#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x292f
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#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x2930
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#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x2931
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x2932
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x2933
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x2934
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x2935
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x2936
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x2937
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#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX 2
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// addressBlock: dce_dc_combophy_dc_combophytxregs0_dispdec
|
// base address: 0x0
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x2948
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x2949
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x294a
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x294b
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x294c
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x294d
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x294e
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x294f
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x2950
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x2951
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x2952
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x2953
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x2954
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x2955
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x2956
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x2957
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x2958
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x2959
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x295a
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x295b
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x295c
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x295d
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x295e
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x295f
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x2960
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x2961
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x2962
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x2963
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x2964
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x2965
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x2966
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x2967
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x2968
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x2969
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x296a
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x296b
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x296c
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x296d
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x296e
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x296f
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x2970
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x2971
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x2972
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x2973
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x2974
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x2975
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x2976
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x2977
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x2978
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x2979
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#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x297a
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#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x297b
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x297c
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x297d
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x297e
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x297f
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x2980
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x2981
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x2982
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x2983
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x2984
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x2985
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x2986
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x2987
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#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX 2
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// addressBlock: dce_dc_combophy_dc_combophypllregs0_dispdec
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// base address: 0x0
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x2988
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x2989
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x298a
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x298b
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#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x298c
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#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x298d
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#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x298e
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#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x298f
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#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x2991
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#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x2992
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#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x2993
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#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x2994
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#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1 0x29c6
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#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL 0x29c7
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#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL_BASE_IDX 2
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// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec
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// base address: 0x360
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32
|
#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x2a3a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x2a3b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x2a3c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x2a3d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x2a3e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x2a3f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x2a40
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x2a41
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x2a42
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x2a43
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x2a44
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x2a45
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x2a46
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x2a47
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x2a48
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x2a49
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x2a4a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x2a4b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x2a4c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x2a4d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x2a4e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x2a4f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x2a50
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x2a51
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x2a52
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x2a53
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x2a54
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x2a55
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x2a56
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x2a57
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x2a58
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x2a59
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x2a5a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x2a5b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x2a5c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x2a5d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x2a5e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x2a5f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x2a60
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x2a61
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x2a62
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x2a63
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x2a64
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x2a65
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x2a66
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x2a67
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x2a68
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x2a69
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x2a6a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x2a6b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x2a6c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x2a6d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x2a6e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x2a6f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x2a70
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x2a71
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x2a72
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x2a73
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x2a74
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x2a75
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x2a76
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x2a77
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x2a78
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x2a79
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x2a7a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x2a7b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x2a7c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x2a7d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x2a7e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x2a7f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x2a80
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x2a81
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x2a82
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x2a83
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x2a84
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x2a85
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x2a86
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x2a87
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x2a88
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x2a89
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x2a8a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x2a8b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x2a8c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x2a8d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x2a8e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x2a8f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x2a90
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x2a91
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x2a92
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x2a93
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x2a94
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x2a95
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x2a96
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x2a97
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x2a98
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x2a99
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x2a9a
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x2a9b
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x2a9c
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x2a9d
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x2a9e
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x2a9f
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#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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// addressBlock: dce_dc_combophy_dc_combophycmregs1_dispdec
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// base address: 0x360
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#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0x2a00
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#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0x2a01
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#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0x2a02
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#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x2a03
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#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x2a04
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#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x2a05
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#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x2a06
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#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x2a07
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#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x2a08
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#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x2a09
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x2a0a
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x2a0b
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x2a0c
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x2a0d
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x2a0e
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x2a0f
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#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX 2
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// addressBlock: dce_dc_combophy_dc_combophytxregs1_dispdec
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// base address: 0x360
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x2a20
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x2a21
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2a22
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x2a23
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x2a24
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x2a25
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x2a26
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x2a27
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x2a28
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x2a29
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x2a2a
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x2a2b
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x2a2c
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x2a2d
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x2a2e
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x2a2f
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x2a30
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x2a31
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2a32
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x2a33
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x2a34
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x2a35
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x2a36
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x2a37
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x2a38
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x2a39
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x2a3a
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x2a3b
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x2a3c
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x2a3d
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x2a3e
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x2a3f
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x2a40
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x2a41
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2a42
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x2a43
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x2a44
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x2a45
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x2a46
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x2a47
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x2a48
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x2a49
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x2a4a
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x2a4b
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x2a4c
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x2a4d
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x2a4e
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x2a4f
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x2a50
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x2a51
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#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2a52
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#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x2a53
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x2a54
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x2a55
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x2a56
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x2a57
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x2a58
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x2a59
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x2a5a
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x2a5b
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x2a5c
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x2a5d
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x2a5e
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x2a5f
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#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX 2
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// addressBlock: dce_dc_combophy_dc_combophypllregs1_dispdec
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// base address: 0x360
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x2a60
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x2a61
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x2a62
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x2a63
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#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x2a64
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#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x2a65
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#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x2a66
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#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x2a67
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#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x2a69
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#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x2a6a
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#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x2a6b
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#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x2a6c
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#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1 0x2a9e
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#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL 0x2a9f
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#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL_BASE_IDX 2
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// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec
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// base address: 0x6c0
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x2b12
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x2b13
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x2b14
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x2b15
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x2b16
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x2b17
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x2b18
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x2b19
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x2b1a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x2b1b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x2b1c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x2b1d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x2b1e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x2b1f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x2b20
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x2b21
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x2b22
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x2b23
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x2b24
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x2b25
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x2b26
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x2b27
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x2b28
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x2b29
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x2b2a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x2b2b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x2b2c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x2b2d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x2b2e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x2b2f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x2b30
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x2b31
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x2b32
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x2b33
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x2b34
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x2b35
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x2b36
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x2b37
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x2b38
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x2b39
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x2b3a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x2b3b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x2b3c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x2b3d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x2b3e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x2b3f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x2b40
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x2b41
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x2b42
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x2b43
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x2b44
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x2b45
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x2b46
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x2b47
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x2b48
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x2b49
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x2b4a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x2b4b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x2b4c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x2b4d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x2b4e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x2b4f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x2b50
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x2b51
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x2b52
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x2b53
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x2b54
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x2b55
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x2b56
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x2b57
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x2b58
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x2b59
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x2b5a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x2b5b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x2b5c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x2b5d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x2b5e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x2b5f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x2b60
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x2b61
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x2b62
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x2b63
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x2b64
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x2b65
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x2b66
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x2b67
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x2b68
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x2b69
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x2b6a
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x2b6b
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x2b6c
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x2b6d
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x2b6e
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x2b6f
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x2b70
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x2b71
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x2b72
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x2b73
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x2b74
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x2b75
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x2b76
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x2b77
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#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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// addressBlock: dce_dc_combophy_dc_combophycmregs2_dispdec
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// base address: 0x6c0
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#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0x2ad8
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#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0x2ad9
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#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0x2ada
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#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x2adb
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#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x2adc
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#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x2add
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#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x2ade
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#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x2adf
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#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x2ae0
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#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x2ae1
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x2ae2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x2ae3
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x2ae4
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x2ae5
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x2ae6
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x2ae7
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#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX 2
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// addressBlock: dce_dc_combophy_dc_combophytxregs2_dispdec
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// base address: 0x6c0
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x2af8
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x2af9
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2afa
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x2afb
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x2afc
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x2afd
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x2afe
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x2aff
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x2b00
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x2b01
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x2b02
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x2b03
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x2b04
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x2b05
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x2b06
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x2b07
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x2b08
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x2b09
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2b0a
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x2b0b
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x2b0c
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x2b0d
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x2b0e
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x2b0f
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x2b10
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x2b11
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x2b12
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x2b13
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x2b14
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x2b15
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x2b16
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x2b17
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x2b18
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x2b19
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2b1a
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x2b1b
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x2b1c
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x2b1d
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x2b1e
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x2b1f
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x2b20
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x2b21
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x2b22
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x2b23
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x2b24
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x2b25
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x2b26
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x2b27
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x2b28
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x2b29
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#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2b2a
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#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x2b2b
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x2b2c
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x2b2d
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x2b2e
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x2b2f
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x2b30
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x2b31
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x2b32
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x2b33
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x2b34
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x2b35
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x2b36
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x2b37
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#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX 2
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// addressBlock: dce_dc_combophy_dc_combophypllregs2_dispdec
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// base address: 0x6c0
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x2b38
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x2b39
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x2b3a
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x2b3b
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#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x2b3c
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#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x2b3d
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#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x2b3e
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#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x2b3f
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#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x2b41
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#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x2b42
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#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x2b43
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#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x2b44
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#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1 0x2b76
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#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL 0x2b77
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#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL_BASE_IDX 2
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// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec
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// base address: 0xa20
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x2bea
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x2beb
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x2bec
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x2bed
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x2bee
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x2bef
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x2bf0
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x2bf1
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x2bf2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x2bf3
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x2bf4
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x2bf5
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x2bf6
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x2bf7
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x2bf8
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x2bf9
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x2bfa
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x2bfb
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x2bfc
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x2bfd
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x2bfe
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x2bff
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x2c00
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x2c01
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x2c02
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x2c03
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x2c04
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x2c05
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x2c06
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x2c07
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x2c08
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x2c09
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x2c0a
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x2c0b
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x2c0c
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x2c0d
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x2c0e
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x2c0f
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x2c10
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x2c11
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x2c12
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x2c13
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x2c14
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x2c15
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x2c16
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x2c17
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x2c18
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x2c19
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x2c1a
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x2c1b
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x2c1c
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x2c1d
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x2c1e
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x2c1f
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x2c20
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x2c21
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x2c22
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x2c23
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x2c24
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x2c25
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x2c26
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x2c27
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x2c28
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x2c29
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x2c2a
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x2c2b
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x2c2c
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x2c2d
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x2c2e
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x2c2f
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x2c30
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x2c31
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x2c32
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x2c33
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x2c34
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x2c35
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x2c36
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x2c37
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x2c38
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x2c39
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x2c3a
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x2c3b
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x2c3c
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x2c3d
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x2c3e
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x2c3f
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x2c40
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x2c41
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x2c42
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x2c43
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x2c44
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x2c45
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x2c46
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x2c47
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x2c48
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x2c49
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x2c4a
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x2c4b
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x2c4c
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x2c4d
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x2c4e
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x2c4f
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#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2
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// addressBlock: dce_dc_combophy_dc_combophycmregs3_dispdec
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// base address: 0xa20
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#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0x2bb0
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#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0x2bb1
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#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0x2bb2
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#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x2bb3
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#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x2bb4
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#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x2bb5
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#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x2bb6
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#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x2bb7
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#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x2bb8
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#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x2bb9
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x2bba
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x2bbb
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x2bbc
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x2bbd
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x2bbe
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX 2
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x2bbf
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#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX 2
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// addressBlock: dce_dc_combophy_dc_combophytxregs3_dispdec
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// base address: 0xa20
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x2bd0
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x2bd1
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2bd2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x2bd3
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x2bd4
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x2bd5
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x2bd6
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x2bd7
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x2bd8
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x2bd9
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x2bda
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x2bdb
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x2bdc
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x2bdd
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x2bde
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x2bdf
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x2be0
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x2be1
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2be2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x2be3
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x2be4
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x2be5
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x2be6
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x2be7
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x2be8
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x2be9
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x2bea
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x2beb
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x2bec
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x2bed
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x2bee
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x2bef
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x2bf0
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x2bf1
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2bf2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x2bf3
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x2bf4
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x2bf5
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x2bf6
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x2bf7
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x2bf8
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x2bf9
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x2bfa
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x2bfb
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x2bfc
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x2bfd
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x2bfe
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x2bff
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x2c00
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x2c01
|
#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2c02
|
#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x2c03
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x2c04
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x2c05
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX 2
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x2c06
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x2c07
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x2c08
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x2c09
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x2c0a
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x2c0b
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x2c0c
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x2c0d
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x2c0e
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX 2
|
#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x2c0f
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#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX 2
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// addressBlock: dce_dc_combophy_dc_combophypllregs3_dispdec
|
// base address: 0xa20
|
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x2c10
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#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX 2
|
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x2c11
|
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x2c12
|
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x2c13
|
#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x2c14
|
#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x2c15
|
#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x2c16
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#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX 2
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#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x2c17
|
#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX 2
|
#define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x2c19
|
#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX 2
|
#define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x2c1a
|
#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX 2
|
#define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x2c1b
|
#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX 2
|
#define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x2c1c
|
#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX 2
|
#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1 0x2c4e
|
#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1_BASE_IDX 2
|
#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL 0x2c4f
|
#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL_BASE_IDX 2
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// addressBlock: dce_dc_dcio_dcio_zcal_dispdec
|
// base address: 0x0
|
#define mmZCAL_MACRO_CNTL_RESERVED0 0x2fe8
|
#define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX 2
|
#define mmZCAL_MACRO_CNTL_RESERVED1 0x2fe9
|
#define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX 2
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#define mmZCAL_MACRO_CNTL_RESERVED2 0x2fea
|
#define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX 2
|
#define mmZCAL_MACRO_CNTL_RESERVED3 0x2feb
|
#define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX 2
|
#define mmZCAL_MACRO_CNTL_RESERVED4 0x2fec
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#define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX 2
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|
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// addressBlock: dce_dc_zcal_dc_zcalregs_dispdec
|
// base address: 0x0
|
#define mmCOMP_EN_CTL 0x2fe8
|
#define mmCOMP_EN_CTL_BASE_IDX 2
|
#define mmCOMP_EN_DFX 0x2fe9
|
#define mmCOMP_EN_DFX_BASE_IDX 2
|
#define mmZCAL_FUSES 0x2fea
|
#define mmZCAL_FUSES_BASE_IDX 2
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|
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// addressBlock: vga_vgaseqind
|
// base address: 0x0
|
#define ixSEQ00 0x0000
|
#define ixSEQ01 0x0001
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#define ixSEQ02 0x0002
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#define ixSEQ03 0x0003
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#define ixSEQ04 0x0004
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|
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// addressBlock: vga_vgacrtind
|
// base address: 0x0
|
#define ixCRT00 0x0000
|
#define ixCRT01 0x0001
|
#define ixCRT02 0x0002
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#define ixCRT03 0x0003
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#define ixCRT04 0x0004
|
#define ixCRT05 0x0005
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#define ixCRT06 0x0006
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#define ixCRT07 0x0007
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#define ixCRT08 0x0008
|
#define ixCRT09 0x0009
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#define ixCRT0A 0x000a
|
#define ixCRT0B 0x000b
|
#define ixCRT0C 0x000c
|
#define ixCRT0D 0x000d
|
#define ixCRT0E 0x000e
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#define ixCRT0F 0x000f
|
#define ixCRT10 0x0010
|
#define ixCRT11 0x0011
|
#define ixCRT12 0x0012
|
#define ixCRT13 0x0013
|
#define ixCRT14 0x0014
|
#define ixCRT15 0x0015
|
#define ixCRT16 0x0016
|
#define ixCRT17 0x0017
|
#define ixCRT18 0x0018
|
#define ixCRT1E 0x001e
|
#define ixCRT1F 0x001f
|
#define ixCRT22 0x0022
|
|
|
// addressBlock: vga_vgagrphind
|
// base address: 0x0
|
#define ixGRA00 0x0000
|
#define ixGRA01 0x0001
|
#define ixGRA02 0x0002
|
#define ixGRA03 0x0003
|
#define ixGRA04 0x0004
|
#define ixGRA05 0x0005
|
#define ixGRA06 0x0006
|
#define ixGRA07 0x0007
|
#define ixGRA08 0x0008
|
|
|
// addressBlock: vga_vgaattrind
|
// base address: 0x0
|
#define ixATTR00 0x0000
|
#define ixATTR01 0x0001
|
#define ixATTR02 0x0002
|
#define ixATTR03 0x0003
|
#define ixATTR04 0x0004
|
#define ixATTR05 0x0005
|
#define ixATTR06 0x0006
|
#define ixATTR07 0x0007
|
#define ixATTR08 0x0008
|
#define ixATTR09 0x0009
|
#define ixATTR0A 0x000a
|
#define ixATTR0B 0x000b
|
#define ixATTR0C 0x000c
|
#define ixATTR0D 0x000d
|
#define ixATTR0E 0x000e
|
#define ixATTR0F 0x000f
|
#define ixATTR10 0x0010
|
#define ixATTR11 0x0011
|
#define ixATTR12 0x0012
|
#define ixATTR13 0x0013
|
#define ixATTR14 0x0014
|
|
|
// base address: 0x0
|
|
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// base address: 0x0
|
|
|
// base address: 0x0
|
|
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// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
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// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
|
// base address: 0x0
|
|
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// base address: 0x0
|
|
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// base address: 0x0
|
|
|
// addressBlock: azendpoint_f2codecind
|
// base address: 0x0
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e
|
#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770
|
#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771
|
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09
|
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a
|
#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791
|
#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792
|
#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e
|
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09
|
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c
|
#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e
|
|
|
// addressBlock: azendpoint_descriptorind
|
// base address: 0x0
|
#define ixAUDIO_DESCRIPTOR0 0x0001
|
#define ixAUDIO_DESCRIPTOR1 0x0002
|
#define ixAUDIO_DESCRIPTOR2 0x0003
|
#define ixAUDIO_DESCRIPTOR3 0x0004
|
#define ixAUDIO_DESCRIPTOR4 0x0005
|
#define ixAUDIO_DESCRIPTOR5 0x0006
|
#define ixAUDIO_DESCRIPTOR6 0x0007
|
#define ixAUDIO_DESCRIPTOR7 0x0008
|
#define ixAUDIO_DESCRIPTOR8 0x0009
|
#define ixAUDIO_DESCRIPTOR9 0x000a
|
#define ixAUDIO_DESCRIPTOR10 0x000b
|
#define ixAUDIO_DESCRIPTOR11 0x000c
|
#define ixAUDIO_DESCRIPTOR12 0x000d
|
#define ixAUDIO_DESCRIPTOR13 0x000e
|
|
|
// addressBlock: azendpoint_sinkinfoind
|
// base address: 0x0
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003
|
#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004
|
#define ixSINK_DESCRIPTION0 0x0005
|
#define ixSINK_DESCRIPTION1 0x0006
|
#define ixSINK_DESCRIPTION2 0x0007
|
#define ixSINK_DESCRIPTION3 0x0008
|
#define ixSINK_DESCRIPTION4 0x0009
|
#define ixSINK_DESCRIPTION5 0x000a
|
#define ixSINK_DESCRIPTION6 0x000b
|
#define ixSINK_DESCRIPTION7 0x000c
|
#define ixSINK_DESCRIPTION8 0x000d
|
#define ixSINK_DESCRIPTION9 0x000e
|
#define ixSINK_DESCRIPTION10 0x000f
|
#define ixSINK_DESCRIPTION11 0x0010
|
#define ixSINK_DESCRIPTION12 0x0011
|
#define ixSINK_DESCRIPTION13 0x0012
|
#define ixSINK_DESCRIPTION14 0x0013
|
#define ixSINK_DESCRIPTION15 0x0014
|
#define ixSINK_DESCRIPTION16 0x0015
|
#define ixSINK_DESCRIPTION17 0x0016
|
|
|
// addressBlock: azf0controller_azinputcrc0resultind
|
// base address: 0x0
|
#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000
|
#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001
|
#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002
|
#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003
|
#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004
|
#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005
|
#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006
|
#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007
|
|
|
// addressBlock: azf0controller_azinputcrc1resultind
|
// base address: 0x0
|
#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000
|
#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001
|
#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002
|
#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003
|
#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004
|
#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005
|
#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006
|
#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007
|
|
|
// addressBlock: azf0controller_azcrc0resultind
|
// base address: 0x0
|
#define ixAZALIA_CRC0_CHANNEL0 0x0000
|
#define ixAZALIA_CRC0_CHANNEL1 0x0001
|
#define ixAZALIA_CRC0_CHANNEL2 0x0002
|
#define ixAZALIA_CRC0_CHANNEL3 0x0003
|
#define ixAZALIA_CRC0_CHANNEL4 0x0004
|
#define ixAZALIA_CRC0_CHANNEL5 0x0005
|
#define ixAZALIA_CRC0_CHANNEL6 0x0006
|
#define ixAZALIA_CRC0_CHANNEL7 0x0007
|
|
|
// addressBlock: azf0controller_azcrc1resultind
|
// base address: 0x0
|
#define ixAZALIA_CRC1_CHANNEL0 0x0000
|
#define ixAZALIA_CRC1_CHANNEL1 0x0001
|
#define ixAZALIA_CRC1_CHANNEL2 0x0002
|
#define ixAZALIA_CRC1_CHANNEL3 0x0003
|
#define ixAZALIA_CRC1_CHANNEL4 0x0004
|
#define ixAZALIA_CRC1_CHANNEL5 0x0005
|
#define ixAZALIA_CRC1_CHANNEL6 0x0006
|
#define ixAZALIA_CRC1_CHANNEL7 0x0007
|
|
|
// addressBlock: azinputendpoint_f2codecind
|
// base address: 0x0
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a
|
#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709
|
#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d
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#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e
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#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09
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#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c
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// addressBlock: azroot_f2codecind
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// base address: 0x0
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#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00
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#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02
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#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770
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#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff
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#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04
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#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05
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#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a
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#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b
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#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f
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// addressBlock: azf0stream0_streamind
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// base address: 0x0
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#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream1_streamind
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// base address: 0x0
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#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream2_streamind
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// base address: 0x0
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#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream3_streamind
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// base address: 0x0
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#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream4_streamind
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// base address: 0x0
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#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream5_streamind
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// base address: 0x0
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#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream6_streamind
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// base address: 0x0
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#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream7_streamind
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// base address: 0x0
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#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream8_streamind
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// base address: 0x0
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#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream9_streamind
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// base address: 0x0
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#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream10_streamind
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// base address: 0x0
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#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream11_streamind
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// base address: 0x0
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#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream12_streamind
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// base address: 0x0
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#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream13_streamind
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// base address: 0x0
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#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream14_streamind
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// base address: 0x0
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#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0stream15_streamind
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// base address: 0x0
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#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000
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#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001
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#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002
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#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003
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#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004
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// addressBlock: azf0endpoint0_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint1_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
|
#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint2_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint3_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint4_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint5_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint6_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0endpoint7_endpointind
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// base address: 0x0
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060
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#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069
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#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a
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#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b
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#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c
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#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d
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#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e
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// addressBlock: azf0inputendpoint0_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint1_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint2_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint3_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint4_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint5_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint6_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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// addressBlock: azf0inputendpoint7_inputendpointind
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// base address: 0x0
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067
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#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068
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#endif
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