/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dc_bios_types.h"
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#include "dcn30_dio_stream_encoder.h"
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#include "reg_helper.h"
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#include "hw_shared.h"
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#include "core_types.h"
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#include <linux/delay.h>
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#define DC_LOGGER \
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enc1->base.ctx->logger
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#define REG(reg)\
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(enc1->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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enc1->se_shift->field_name, enc1->se_mask->field_name
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#define VBI_LINE_0 0
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#define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
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#define CTX \
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enc1->base.ctx
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void convert_dc_info_packet_to_128(
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const struct dc_info_packet *info_packet,
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struct dc_info_packet_128 *info_packet_128)
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{
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unsigned int i;
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info_packet_128->hb0 = info_packet->hb0;
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info_packet_128->hb1 = info_packet->hb1;
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info_packet_128->hb2 = info_packet->hb2;
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info_packet_128->hb3 = info_packet->hb3;
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for (i = 0; i < 32; i++) {
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info_packet_128->sb[i] = info_packet->sb[i];
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}
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}
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static void enc3_update_hdmi_info_packet(
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struct dcn10_stream_encoder *enc1,
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uint32_t packet_index,
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const struct dc_info_packet *info_packet)
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{
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uint32_t cont, send, line;
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if (info_packet->valid) {
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enc1->base.vpg->funcs->update_generic_info_packet(
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enc1->base.vpg,
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packet_index,
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info_packet);
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/* enable transmission of packet(s) -
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* packet transmission begins on the next frame */
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cont = 1;
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/* send packet(s) every frame */
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send = 1;
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/* select line number to send packets on */
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line = 2;
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} else {
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cont = 0;
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send = 0;
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line = 0;
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}
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/* DP_SEC_GSP[x]_LINE_REFERENCE - keep default value REFER_TO_DP_SOF */
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/* choose which generic packet control to use */
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switch (packet_index) {
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case 0:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC0_CONT, cont,
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HDMI_GENERIC0_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
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HDMI_GENERIC0_LINE, line);
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break;
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case 1:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC1_CONT, cont,
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HDMI_GENERIC1_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
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HDMI_GENERIC1_LINE, line);
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break;
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case 2:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC2_CONT, cont,
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HDMI_GENERIC2_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
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HDMI_GENERIC2_LINE, line);
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break;
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case 3:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC3_CONT, cont,
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HDMI_GENERIC3_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
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HDMI_GENERIC3_LINE, line);
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break;
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case 4:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC4_CONT, cont,
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HDMI_GENERIC4_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
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HDMI_GENERIC4_LINE, line);
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break;
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case 5:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC5_CONT, cont,
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HDMI_GENERIC5_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
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HDMI_GENERIC5_LINE, line);
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break;
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case 6:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC6_CONT, cont,
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HDMI_GENERIC6_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
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HDMI_GENERIC6_LINE, line);
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break;
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case 7:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
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HDMI_GENERIC7_CONT, cont,
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HDMI_GENERIC7_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
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HDMI_GENERIC7_LINE, line);
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break;
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case 8:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
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HDMI_GENERIC8_CONT, cont,
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HDMI_GENERIC8_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7,
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HDMI_GENERIC8_LINE, line);
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break;
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case 9:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
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HDMI_GENERIC9_CONT, cont,
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HDMI_GENERIC9_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7,
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HDMI_GENERIC9_LINE, line);
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break;
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case 10:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
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HDMI_GENERIC10_CONT, cont,
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HDMI_GENERIC10_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8,
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HDMI_GENERIC10_LINE, line);
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break;
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case 11:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
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HDMI_GENERIC11_CONT, cont,
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HDMI_GENERIC11_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8,
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HDMI_GENERIC11_LINE, line);
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break;
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case 12:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
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HDMI_GENERIC12_CONT, cont,
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HDMI_GENERIC12_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9,
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HDMI_GENERIC12_LINE, line);
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break;
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case 13:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
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HDMI_GENERIC13_CONT, cont,
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HDMI_GENERIC13_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9,
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HDMI_GENERIC13_LINE, line);
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break;
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case 14:
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REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
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HDMI_GENERIC14_CONT, cont,
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HDMI_GENERIC14_SEND, send);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10,
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HDMI_GENERIC14_LINE, line);
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break;
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default:
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/* invalid HW packet index */
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DC_LOG_WARNING(
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"Invalid HW packet index: %s()\n",
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__func__);
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return;
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}
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}
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static void enc3_stream_encoder_update_hdmi_info_packets(
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struct stream_encoder *enc,
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const struct encoder_info_frame *info_frame)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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/* for bring up, disable dp double TODO */
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REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
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REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
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/*Always add mandatory packets first followed by optional ones*/
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enc3_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
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enc3_update_hdmi_info_packet(enc1, 5, &info_frame->hfvsif);
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enc3_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
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enc3_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
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enc3_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
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enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
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}
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static void enc3_stream_encoder_stop_hdmi_info_packets(
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struct stream_encoder *enc)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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/* stop generic packets 0,1 on HDMI */
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REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
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HDMI_GENERIC0_CONT, 0,
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HDMI_GENERIC0_SEND, 0,
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HDMI_GENERIC1_CONT, 0,
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HDMI_GENERIC1_SEND, 0);
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REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0,
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HDMI_GENERIC0_LINE, 0,
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HDMI_GENERIC1_LINE, 0);
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/* stop generic packets 2,3 on HDMI */
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REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
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HDMI_GENERIC2_CONT, 0,
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HDMI_GENERIC2_SEND, 0,
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HDMI_GENERIC3_CONT, 0,
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HDMI_GENERIC3_SEND, 0);
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REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0,
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HDMI_GENERIC2_LINE, 0,
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HDMI_GENERIC3_LINE, 0);
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/* stop generic packets 4,5 on HDMI */
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REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
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HDMI_GENERIC4_CONT, 0,
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HDMI_GENERIC4_SEND, 0,
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HDMI_GENERIC5_CONT, 0,
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HDMI_GENERIC5_SEND, 0);
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REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0,
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HDMI_GENERIC4_LINE, 0,
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HDMI_GENERIC5_LINE, 0);
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/* stop generic packets 6,7 on HDMI */
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REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
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HDMI_GENERIC6_CONT, 0,
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HDMI_GENERIC6_SEND, 0,
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HDMI_GENERIC7_CONT, 0,
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HDMI_GENERIC7_SEND, 0);
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REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0,
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HDMI_GENERIC6_LINE, 0,
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HDMI_GENERIC7_LINE, 0);
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/* stop generic packets 8,9 on HDMI */
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REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
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HDMI_GENERIC8_CONT, 0,
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HDMI_GENERIC8_SEND, 0,
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HDMI_GENERIC9_CONT, 0,
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HDMI_GENERIC9_SEND, 0);
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REG_SET_2(HDMI_GENERIC_PACKET_CONTROL7, 0,
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HDMI_GENERIC8_LINE, 0,
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HDMI_GENERIC9_LINE, 0);
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/* stop generic packets 10,11 on HDMI */
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REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
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HDMI_GENERIC10_CONT, 0,
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HDMI_GENERIC10_SEND, 0,
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HDMI_GENERIC11_CONT, 0,
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HDMI_GENERIC11_SEND, 0);
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REG_SET_2(HDMI_GENERIC_PACKET_CONTROL8, 0,
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HDMI_GENERIC10_LINE, 0,
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HDMI_GENERIC11_LINE, 0);
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/* stop generic packets 12,13 on HDMI */
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REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
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HDMI_GENERIC12_CONT, 0,
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HDMI_GENERIC12_SEND, 0,
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HDMI_GENERIC13_CONT, 0,
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HDMI_GENERIC13_SEND, 0);
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REG_SET_2(HDMI_GENERIC_PACKET_CONTROL9, 0,
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HDMI_GENERIC12_LINE, 0,
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HDMI_GENERIC13_LINE, 0);
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/* stop generic packet 14 on HDMI */
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REG_SET_2(HDMI_GENERIC_PACKET_CONTROL6, 0,
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HDMI_GENERIC14_CONT, 0,
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HDMI_GENERIC14_SEND, 0);
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REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10,
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HDMI_GENERIC14_LINE, 0);
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}
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/* Set DSC-related configuration.
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* dsc_mode: 0 disables DSC, other values enable DSC in specified format
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* sc_bytes_per_pixel: Bytes per pixel in u3.28 format
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* dsc_slice_width: Slice width in pixels
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*/
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static void enc3_dp_set_dsc_config(struct stream_encoder *enc,
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enum optc_dsc_mode dsc_mode,
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uint32_t dsc_bytes_per_pixel,
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uint32_t dsc_slice_width)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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REG_UPDATE_2(DP_DSC_CNTL,
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DP_DSC_MODE, dsc_mode,
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DP_DSC_SLICE_WIDTH, dsc_slice_width);
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REG_SET(DP_DSC_BYTES_PER_PIXEL, 0,
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DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
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}
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static void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
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bool enable,
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uint8_t *dsc_packed_pps)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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if (enable) {
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struct dc_info_packet pps_sdp;
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int i;
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/* Configure for PPS packet size (128 bytes) */
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REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 1);
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/* We need turn on clock before programming AFMT block
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*
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* TODO: We may not need this here anymore since update_generic_info_packet
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* no longer touches AFMT
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*/
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REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
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/* Load PPS into infoframe (SDP) registers */
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pps_sdp.valid = true;
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pps_sdp.hb0 = 0;
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pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS;
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pps_sdp.hb2 = 127;
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pps_sdp.hb3 = 0;
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for (i = 0; i < 4; i++) {
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memcpy(pps_sdp.sb, &dsc_packed_pps[i * 32], 32);
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enc1->base.vpg->funcs->update_generic_info_packet(
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enc1->base.vpg,
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11 + i,
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&pps_sdp);
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}
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/* SW should make sure VBID[6] update line number is bigger
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* than PPS transmit line number
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*/
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REG_UPDATE(DP_GSP11_CNTL,
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DP_SEC_GSP11_LINE_NUM, 2);
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REG_UPDATE_2(DP_MSA_VBID_MISC,
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DP_VBID6_LINE_REFERENCE, 0,
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DP_VBID6_LINE_NUM, 3);
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/* Send PPS data at the line number specified above.
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* DP spec requires PPS to be sent only when it changes, however since
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* decoder has to be able to handle its change on every frame, we're
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* sending it always (i.e. on every frame) to reduce the chance it'd be
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* missed by decoder. If it turns out required to send PPS only when it
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* changes, we can use DP_SEC_GSP11_SEND register.
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*/
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REG_UPDATE(DP_GSP11_CNTL,
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DP_SEC_GSP11_ENABLE, 1);
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REG_UPDATE(DP_SEC_CNTL,
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DP_SEC_STREAM_ENABLE, 1);
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} else {
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/* Disable Generic Stream Packet 11 (GSP) transmission */
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REG_UPDATE(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, 0);
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REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 0);
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}
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}
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|
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/* this function read dsc related register fields to be logged later in dcn10_log_hw_state
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* into a dcn_dsc_state struct.
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*/
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static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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//if dsc is enabled, continue to read
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REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
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if (s->dsc_mode) {
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REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
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REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
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REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
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REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
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REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
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REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
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}
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}
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static void enc3_stream_encoder_update_dp_info_packets(
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struct stream_encoder *enc,
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const struct encoder_info_frame *info_frame)
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{
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struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
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uint32_t value = 0;
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uint32_t dmdata_packet_enabled = 0;
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if (info_frame->vsc.valid) {
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enc->vpg->funcs->update_generic_info_packet(
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enc->vpg,
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0, /* packetIndex */
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&info_frame->vsc);
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}
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if (info_frame->spd.valid) {
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enc->vpg->funcs->update_generic_info_packet(
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enc->vpg,
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2, /* packetIndex */
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&info_frame->spd);
|
}
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if (info_frame->hdrsmd.valid) {
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enc->vpg->funcs->update_generic_info_packet(
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enc->vpg,
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3, /* packetIndex */
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&info_frame->hdrsmd);
|
}
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/* packetIndex 4 is used for send immediate sdp message, and please
|
* use other packetIndex (such as 5,6) for other info packet
|
*/
|
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/* enable/disable transmission of packet(s).
|
* If enabled, packet transmission begins on the next frame
|
*/
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REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
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REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
|
REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
|
|
|
/* This bit is the master enable bit.
|
* When enabling secondary stream engine,
|
* this master bit must also be set.
|
* This register shared with audio info frame.
|
* Therefore we need to enable master bit
|
* if at least on of the fields is not 0
|
*/
|
value = REG_READ(DP_SEC_CNTL);
|
if (value)
|
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
|
|
/* check if dynamic metadata packet transmission is enabled */
|
REG_GET(DP_SEC_METADATA_TRANSMISSION,
|
DP_SEC_METADATA_PACKET_ENABLE, &dmdata_packet_enabled);
|
|
if (dmdata_packet_enabled)
|
REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
|
}
|
|
static void enc3_dp_set_odm_combine(
|
struct stream_encoder *enc,
|
bool odm_combine)
|
{
|
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
|
|
REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);
|
}
|
|
/* setup stream encoder in dvi mode */
|
void enc3_stream_encoder_dvi_set_stream_attribute(
|
struct stream_encoder *enc,
|
struct dc_crtc_timing *crtc_timing,
|
bool is_dual_link)
|
{
|
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
|
|
if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
|
struct bp_encoder_control cntl = {0};
|
|
cntl.action = ENCODER_CONTROL_SETUP;
|
cntl.engine_id = enc1->base.id;
|
cntl.signal = is_dual_link ?
|
SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
|
cntl.enable_dp_audio = false;
|
cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
|
cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
|
|
if (enc1->base.bp->funcs->encoder_control(
|
enc1->base.bp, &cntl) != BP_RESULT_OK)
|
return;
|
|
} else {
|
|
//Set pattern for clock channel, default vlue 0x63 does not work
|
REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
|
|
//DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup
|
|
//DIG_SOURCE_SELECT is already set in dig_connect_to_otg
|
|
/* set DIG_START to 0x1 to reset FIFO */
|
REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
|
udelay(1);
|
|
/* write 0 to take the FIFO out of reset */
|
REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
|
udelay(1);
|
}
|
|
ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
|
ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
|
enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
|
}
|
|
/* setup stream encoder in hdmi mode */
|
static void enc3_stream_encoder_hdmi_set_stream_attribute(
|
struct stream_encoder *enc,
|
struct dc_crtc_timing *crtc_timing,
|
int actual_pix_clk_khz,
|
bool enable_audio)
|
{
|
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
|
|
if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
|
struct bp_encoder_control cntl = {0};
|
|
cntl.action = ENCODER_CONTROL_SETUP;
|
cntl.engine_id = enc1->base.id;
|
cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
|
cntl.enable_dp_audio = enable_audio;
|
cntl.pixel_clock = actual_pix_clk_khz;
|
cntl.lanes_number = LANE_COUNT_FOUR;
|
|
if (enc1->base.bp->funcs->encoder_control(
|
enc1->base.bp, &cntl) != BP_RESULT_OK)
|
return;
|
|
} else {
|
|
//Set pattern for clock channel, default vlue 0x63 does not work
|
REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
|
|
//DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup
|
|
//DIG_SOURCE_SELECT is already set in dig_connect_to_otg
|
|
/* set DIG_START to 0x1 to reset FIFO */
|
REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
|
udelay(1);
|
|
/* write 0 to take the FIFO out of reset */
|
REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
|
udelay(1);
|
}
|
|
/* Configure pixel encoding */
|
enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
|
|
/* setup HDMI engine */
|
REG_UPDATE_6(HDMI_CONTROL,
|
HDMI_PACKET_GEN_VERSION, 1,
|
HDMI_KEEPOUT_MODE, 1,
|
HDMI_DEEP_COLOR_ENABLE, 0,
|
HDMI_DATA_SCRAMBLE_EN, 0,
|
HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
|
HDMI_CLOCK_CHANNEL_RATE, 0);
|
|
/* Configure color depth */
|
switch (crtc_timing->display_color_depth) {
|
case COLOR_DEPTH_888:
|
REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
|
break;
|
case COLOR_DEPTH_101010:
|
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
|
REG_UPDATE_2(HDMI_CONTROL,
|
HDMI_DEEP_COLOR_DEPTH, 1,
|
HDMI_DEEP_COLOR_ENABLE, 0);
|
} else {
|
REG_UPDATE_2(HDMI_CONTROL,
|
HDMI_DEEP_COLOR_DEPTH, 1,
|
HDMI_DEEP_COLOR_ENABLE, 1);
|
}
|
break;
|
case COLOR_DEPTH_121212:
|
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
|
REG_UPDATE_2(HDMI_CONTROL,
|
HDMI_DEEP_COLOR_DEPTH, 2,
|
HDMI_DEEP_COLOR_ENABLE, 0);
|
} else {
|
REG_UPDATE_2(HDMI_CONTROL,
|
HDMI_DEEP_COLOR_DEPTH, 2,
|
HDMI_DEEP_COLOR_ENABLE, 1);
|
}
|
break;
|
case COLOR_DEPTH_161616:
|
REG_UPDATE_2(HDMI_CONTROL,
|
HDMI_DEEP_COLOR_DEPTH, 3,
|
HDMI_DEEP_COLOR_ENABLE, 1);
|
break;
|
default:
|
break;
|
}
|
|
if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
|
/* enable HDMI data scrambler
|
* HDMI_CLOCK_CHANNEL_RATE_MORE_340M
|
* Clock channel frequency is 1/4 of character rate.
|
*/
|
REG_UPDATE_2(HDMI_CONTROL,
|
HDMI_DATA_SCRAMBLE_EN, 1,
|
HDMI_CLOCK_CHANNEL_RATE, 1);
|
} else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
|
|
/* TODO: New feature for DCE11, still need to implement */
|
|
/* enable HDMI data scrambler
|
* HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
|
* Clock channel frequency is the same
|
* as character rate
|
*/
|
REG_UPDATE_2(HDMI_CONTROL,
|
HDMI_DATA_SCRAMBLE_EN, 1,
|
HDMI_CLOCK_CHANNEL_RATE, 0);
|
}
|
|
|
/* Enable transmission of General Control packet on every frame */
|
REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
|
HDMI_GC_CONT, 1,
|
HDMI_GC_SEND, 1,
|
HDMI_NULL_SEND, 1);
|
|
/* following belongs to audio */
|
/* Enable Audio InfoFrame packet transmission. */
|
REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
|
|
/* update double-buffered AUDIO_INFO registers immediately */
|
ASSERT (enc->afmt);
|
enc->afmt->funcs->audio_info_immediate_update(enc->afmt);
|
|
/* Select line number on which to send Audio InfoFrame packets */
|
REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
|
VBI_LINE_0 + 2);
|
|
/* set HDMI GC AVMUTE */
|
REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
|
}
|
|
static void enc3_audio_mute_control(
|
struct stream_encoder *enc,
|
bool mute)
|
{
|
ASSERT (enc->afmt);
|
enc->afmt->funcs->audio_mute_control(enc->afmt, mute);
|
}
|
|
static void enc3_se_dp_audio_setup(
|
struct stream_encoder *enc,
|
unsigned int az_inst,
|
struct audio_info *info)
|
{
|
ASSERT (enc->afmt);
|
enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info);
|
}
|
|
#define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
|
#define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
|
|
static void enc3_se_setup_dp_audio(
|
struct stream_encoder *enc)
|
{
|
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
|
|
/* --- DP Audio packet configurations --- */
|
|
/* ATP Configuration */
|
REG_SET(DP_SEC_AUD_N, 0,
|
DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
|
|
/* Async/auto-calc timestamp mode */
|
REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
|
DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
|
|
ASSERT (enc->afmt);
|
enc->afmt->funcs->setup_dp_audio(enc->afmt);
|
}
|
|
static void enc3_se_dp_audio_enable(
|
struct stream_encoder *enc)
|
{
|
enc1_se_enable_audio_clock(enc, true);
|
enc3_se_setup_dp_audio(enc);
|
enc1_se_enable_dp_audio(enc);
|
}
|
|
static void enc3_se_setup_hdmi_audio(
|
struct stream_encoder *enc,
|
const struct audio_crtc_info *crtc_info)
|
{
|
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
|
|
struct audio_clock_info audio_clock_info = {0};
|
|
/* Setup audio in AFMT - program AFMT block associated with DIO */
|
ASSERT (enc->afmt);
|
enc->afmt->funcs->setup_hdmi_audio(enc->afmt);
|
|
/* HDMI_AUDIO_PACKET_CONTROL */
|
REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
|
HDMI_AUDIO_DELAY_EN, 1);
|
|
/* HDMI_ACR_PACKET_CONTROL */
|
REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
|
HDMI_ACR_AUTO_SEND, 1,
|
HDMI_ACR_SOURCE, 0,
|
HDMI_ACR_AUDIO_PRIORITY, 0);
|
|
/* Program audio clock sample/regeneration parameters */
|
get_audio_clock_info(crtc_info->color_depth,
|
crtc_info->requested_pixel_clock_100Hz,
|
crtc_info->calculated_pixel_clock_100Hz,
|
&audio_clock_info);
|
DC_LOG_HW_AUDIO(
|
"\n%s:Input::requested_pixel_clock_100Hz = %d" \
|
"calculated_pixel_clock_100Hz = %d \n", __func__, \
|
crtc_info->requested_pixel_clock_100Hz, \
|
crtc_info->calculated_pixel_clock_100Hz);
|
|
/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
|
REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
|
|
/* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
|
REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
|
|
/* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
|
REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
|
|
/* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
|
REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
|
|
/* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
|
REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
|
|
/* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
|
REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
|
|
/* Video driver cannot know in advance which sample rate will
|
* be used by HD Audio driver
|
* HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
|
* programmed below in interruppt callback
|
*/
|
}
|
|
static void enc3_se_hdmi_audio_setup(
|
struct stream_encoder *enc,
|
unsigned int az_inst,
|
struct audio_info *info,
|
struct audio_crtc_info *audio_crtc_info)
|
{
|
enc1_se_enable_audio_clock(enc, true);
|
enc3_se_setup_hdmi_audio(enc, audio_crtc_info);
|
ASSERT (enc->afmt);
|
enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info);
|
}
|
|
|
static const struct stream_encoder_funcs dcn30_str_enc_funcs = {
|
.dp_set_odm_combine =
|
enc3_dp_set_odm_combine,
|
.dp_set_stream_attribute =
|
enc2_stream_encoder_dp_set_stream_attribute,
|
.hdmi_set_stream_attribute =
|
enc3_stream_encoder_hdmi_set_stream_attribute,
|
.dvi_set_stream_attribute =
|
enc3_stream_encoder_dvi_set_stream_attribute,
|
.set_throttled_vcp_size =
|
enc1_stream_encoder_set_throttled_vcp_size,
|
.update_hdmi_info_packets =
|
enc3_stream_encoder_update_hdmi_info_packets,
|
.stop_hdmi_info_packets =
|
enc3_stream_encoder_stop_hdmi_info_packets,
|
.update_dp_info_packets =
|
enc3_stream_encoder_update_dp_info_packets,
|
.stop_dp_info_packets =
|
enc1_stream_encoder_stop_dp_info_packets,
|
.dp_blank =
|
enc1_stream_encoder_dp_blank,
|
.dp_unblank =
|
enc2_stream_encoder_dp_unblank,
|
.audio_mute_control = enc3_audio_mute_control,
|
|
.dp_audio_setup = enc3_se_dp_audio_setup,
|
.dp_audio_enable = enc3_se_dp_audio_enable,
|
.dp_audio_disable = enc1_se_dp_audio_disable,
|
|
.hdmi_audio_setup = enc3_se_hdmi_audio_setup,
|
.hdmi_audio_disable = enc1_se_hdmi_audio_disable,
|
.setup_stereo_sync = enc1_setup_stereo_sync,
|
.set_avmute = enc1_stream_encoder_set_avmute,
|
.dig_connect_to_otg = enc1_dig_connect_to_otg,
|
.dig_source_otg = enc1_dig_source_otg,
|
|
.dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format,
|
|
.enc_read_state = enc3_read_state,
|
.dp_set_dsc_config = enc3_dp_set_dsc_config,
|
.dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
|
.set_dynamic_metadata = enc2_set_dynamic_metadata,
|
.hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
|
};
|
|
void dcn30_dio_stream_encoder_construct(
|
struct dcn10_stream_encoder *enc1,
|
struct dc_context *ctx,
|
struct dc_bios *bp,
|
enum engine_id eng_id,
|
struct vpg *vpg,
|
struct afmt *afmt,
|
const struct dcn10_stream_enc_registers *regs,
|
const struct dcn10_stream_encoder_shift *se_shift,
|
const struct dcn10_stream_encoder_mask *se_mask)
|
{
|
enc1->base.funcs = &dcn30_str_enc_funcs;
|
enc1->base.ctx = ctx;
|
enc1->base.id = eng_id;
|
enc1->base.bp = bp;
|
enc1->base.vpg = vpg;
|
enc1->base.afmt = afmt;
|
enc1->regs = regs;
|
enc1->se_shift = se_shift;
|
enc1->se_mask = se_mask;
|
enc1->base.stream_enc_inst = vpg->inst;
|
}
|
