/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_LINK_ENCODER__DCN30_H__
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#define __DC_LINK_ENCODER__DCN30_H__
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#include "dcn20/dcn20_link_encoder.h"
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#define LE_DCN3_REG_LIST(id)\
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SRI(DIG_BE_CNTL, DIG, id), \
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SRI(DIG_BE_EN_CNTL, DIG, id), \
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SRI(TMDS_CTL_BITS, DIG, id), \
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SRI(TMDS_DCBALANCER_CONTROL, DIG, id), \
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SRI(DP_CONFIG, DP, id), \
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SRI(DP_DPHY_CNTL, DP, id), \
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SRI(DP_DPHY_PRBS_CNTL, DP, id), \
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SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
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SRI(DP_DPHY_SYM0, DP, id), \
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SRI(DP_DPHY_SYM1, DP, id), \
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SRI(DP_DPHY_SYM2, DP, id), \
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SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \
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SRI(DP_LINK_CNTL, DP, id), \
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SRI(DP_LINK_FRAMING_CNTL, DP, id), \
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SRI(DP_MSE_SAT0, DP, id), \
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SRI(DP_MSE_SAT1, DP, id), \
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SRI(DP_MSE_SAT2, DP, id), \
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SRI(DP_MSE_SAT_UPDATE, DP, id), \
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SRI(DP_SEC_CNTL, DP, id), \
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SRI(DP_VID_STREAM_CNTL, DP, id), \
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SRI(DP_DPHY_FAST_TRAINING, DP, id), \
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SRI(DP_SEC_CNTL1, DP, id), \
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SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
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SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
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#define LINK_ENCODER_MASK_SH_LIST_DCN30(mask_sh) \
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LINK_ENCODER_MASK_SH_LIST_DCN20(mask_sh)
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#define DPCS_DCN3_MASK_SH_LIST(mask_sh)\
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DPCS_DCN2_MASK_SH_LIST(mask_sh),\
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LE_SF(DPCSTX0_DPCSTX_TX_CNTL, DPCS_TX_DATA_ORDER_INVERT_18_BIT, mask_sh),\
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LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL0, RDPCS_PHY_TX_VBOOST_LVL, mask_sh),\
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LE_SF(RDPCSTX0_RDPCSTX_CLOCK_CNTL, RDPCS_TX_CLK_EN, mask_sh),\
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LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, mask_sh),\
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LE_SF(RDPCSTX0_RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, mask_sh)
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void dcn30_link_encoder_construct(
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struct dcn20_link_encoder *enc20,
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const struct encoder_init_data *init_data,
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const struct encoder_feature_support *enc_features,
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const struct dcn10_link_enc_registers *link_regs,
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const struct dcn10_link_enc_aux_registers *aux_regs,
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const struct dcn10_link_enc_hpd_registers *hpd_regs,
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const struct dcn10_link_enc_shift *link_shift,
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const struct dcn10_link_enc_mask *link_mask);
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void enc3_hw_init(struct link_encoder *enc);
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#endif /* __DC_LINK_ENCODER__DCN30_H__ */
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