/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_PANEL_CNTL__DCE_H__
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#define __DC_PANEL_CNTL__DCE_H__
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#include "panel_cntl.h"
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/* set register offset with instance */
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#define DCE_PANEL_CNTL_SR(reg_name, block)\
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.reg_name = mm ## block ## _ ## reg_name
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#define DCE_PANEL_CNTL_REG_LIST()\
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DCE_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
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DCE_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
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DCE_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
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SR(BL_PWM_CNTL), \
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SR(BL_PWM_CNTL2), \
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SR(BL_PWM_PERIOD_CNTL), \
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SR(BL_PWM_GRP1_REG_LOCK), \
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SR(BIOS_SCRATCH_2)
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#define DCN_PANEL_CNTL_SR(reg_name, block)\
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.reg_name = BASE(mm ## block ## _ ## reg_name ## _BASE_IDX) + \
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mm ## block ## _ ## reg_name
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#define DCN_PANEL_CNTL_REG_LIST()\
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DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
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DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
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DCN_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
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SR(BL_PWM_CNTL), \
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SR(BL_PWM_CNTL2), \
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SR(BL_PWM_PERIOD_CNTL), \
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SR(BL_PWM_GRP1_REG_LOCK), \
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NBIO_SR(BIOS_SCRATCH_2)
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#define DCE_PANEL_CNTL_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define DCE_PANEL_CNTL_MASK_SH_LIST(mask_sh) \
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DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh),\
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DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_BLON_OVRD, mask_sh),\
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DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON, mask_sh),\
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DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_DIGON_OVRD, mask_sh),\
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DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, mask_sh), \
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DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh), \
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DCE_PANEL_CNTL_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \
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DCE_PANEL_CNTL_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \
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DCE_PANEL_CNTL_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \
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DCE_PANEL_CNTL_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \
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DCE_PANEL_CNTL_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \
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DCE_PANEL_CNTL_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \
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DCE_PANEL_CNTL_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \
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DCE_PANEL_CNTL_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \
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DCE_PANEL_CNTL_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh)
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#define DCE_PANEL_CNTL_REG_FIELD_LIST(type) \
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type LVTMA_BLON;\
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type LVTMA_BLON_OVRD;\
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type LVTMA_DIGON;\
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type LVTMA_DIGON_OVRD;\
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type LVTMA_PWRSEQ_TARGET_STATE; \
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type LVTMA_PWRSEQ_TARGET_STATE_R; \
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type BL_PWM_REF_DIV; \
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type BL_PWM_EN; \
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type BL_ACTIVE_INT_FRAC_CNT; \
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type BL_PWM_FRACTIONAL_EN; \
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type BL_PWM_PERIOD; \
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type BL_PWM_PERIOD_BITCNT; \
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type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \
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type BL_PWM_GRP1_REG_LOCK; \
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type BL_PWM_GRP1_REG_UPDATE_PENDING
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struct dce_panel_cntl_shift {
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DCE_PANEL_CNTL_REG_FIELD_LIST(uint8_t);
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};
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struct dce_panel_cntl_mask {
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DCE_PANEL_CNTL_REG_FIELD_LIST(uint32_t);
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};
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struct dce_panel_cntl_registers {
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uint32_t PWRSEQ_CNTL;
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uint32_t PWRSEQ_STATE;
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uint32_t BL_PWM_CNTL;
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uint32_t BL_PWM_CNTL2;
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uint32_t BL_PWM_PERIOD_CNTL;
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uint32_t BL_PWM_GRP1_REG_LOCK;
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uint32_t PWRSEQ_REF_DIV;
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uint32_t BIOS_SCRATCH_2;
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};
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struct dce_panel_cntl {
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struct panel_cntl base;
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const struct dce_panel_cntl_registers *regs;
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const struct dce_panel_cntl_shift *shift;
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const struct dce_panel_cntl_mask *mask;
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};
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void dce_panel_cntl_construct(
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struct dce_panel_cntl *panel_cntl,
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const struct panel_cntl_init_data *init_data,
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const struct dce_panel_cntl_registers *regs,
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const struct dce_panel_cntl_shift *shift,
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const struct dce_panel_cntl_mask *mask);
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#endif /* __DC_PANEL_CNTL__DCE_H__ */
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