/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "reg_helper.h"
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#include "core_types.h"
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#include "dc_dmub_srv.h"
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#include "panel_cntl.h"
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#include "dce_panel_cntl.h"
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#include "atom.h"
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#define TO_DCE_PANEL_CNTL(panel_cntl)\
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container_of(panel_cntl, struct dce_panel_cntl, base)
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#define CTX \
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dce_panel_cntl->base.ctx
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#define DC_LOGGER \
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dce_panel_cntl->base.ctx->logger
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#define REG(reg)\
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dce_panel_cntl->regs->reg
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#undef FN
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#define FN(reg_name, field_name) \
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dce_panel_cntl->shift->field_name, dce_panel_cntl->mask->field_name
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static unsigned int dce_get_16_bit_backlight_from_pwm(struct panel_cntl *panel_cntl)
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{
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uint64_t current_backlight;
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uint32_t round_result;
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uint32_t pwm_period_cntl, bl_period, bl_int_count;
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uint32_t bl_pwm_cntl, bl_pwm, fractional_duty_cycle_en;
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uint32_t bl_period_mask, bl_pwm_mask;
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struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
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pwm_period_cntl = REG_READ(BL_PWM_PERIOD_CNTL);
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REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period);
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REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count);
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bl_pwm_cntl = REG_READ(BL_PWM_CNTL);
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REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm));
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REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en);
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if (bl_int_count == 0)
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bl_int_count = 16;
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bl_period_mask = (1 << bl_int_count) - 1;
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bl_period &= bl_period_mask;
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bl_pwm_mask = bl_period_mask << (16 - bl_int_count);
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if (fractional_duty_cycle_en == 0)
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bl_pwm &= bl_pwm_mask;
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else
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bl_pwm &= 0xFFFF;
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current_backlight = (uint64_t)bl_pwm << (1 + bl_int_count);
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if (bl_period == 0)
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bl_period = 0xFFFF;
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current_backlight = div_u64(current_backlight, bl_period);
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current_backlight = (current_backlight + 1) >> 1;
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current_backlight = (uint64_t)(current_backlight) * bl_period;
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round_result = (uint32_t)(current_backlight & 0xFFFFFFFF);
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round_result = (round_result >> (bl_int_count-1)) & 1;
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current_backlight >>= bl_int_count;
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current_backlight += round_result;
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return (uint32_t)(current_backlight);
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}
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static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl)
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{
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struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
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uint32_t value;
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uint32_t current_backlight;
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/* It must not be 0, so we have to restore them
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* Bios bug w/a - period resets to zero,
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* restoring to cache values which is always correct
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*/
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REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value);
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if (value == 0 || value == 1) {
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if (panel_cntl->stored_backlight_registers.BL_PWM_CNTL != 0) {
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REG_WRITE(BL_PWM_CNTL,
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panel_cntl->stored_backlight_registers.BL_PWM_CNTL);
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REG_WRITE(BL_PWM_CNTL2,
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panel_cntl->stored_backlight_registers.BL_PWM_CNTL2);
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REG_WRITE(BL_PWM_PERIOD_CNTL,
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panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
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REG_UPDATE(PWRSEQ_REF_DIV,
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BL_PWM_REF_DIV,
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panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
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} else {
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/* TODO: Note: This should not really happen since VBIOS
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* should have initialized PWM registers on boot.
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*/
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REG_WRITE(BL_PWM_CNTL, 0xC000FA00);
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REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
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}
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} else {
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panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
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REG_READ(BL_PWM_CNTL);
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panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
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REG_READ(BL_PWM_CNTL2);
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panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
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REG_READ(BL_PWM_PERIOD_CNTL);
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REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
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&panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
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}
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// Have driver take backlight control
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// TakeBacklightControl(true)
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value = REG_READ(BIOS_SCRATCH_2);
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value |= ATOM_S2_VRI_BRIGHT_ENABLE;
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REG_WRITE(BIOS_SCRATCH_2, value);
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// Enable the backlight output
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REG_UPDATE(BL_PWM_CNTL, BL_PWM_EN, 1);
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// Unlock group 2 backlight registers
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REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
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BL_PWM_GRP1_REG_LOCK, 0);
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current_backlight = dce_get_16_bit_backlight_from_pwm(panel_cntl);
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return current_backlight;
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}
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static bool dce_is_panel_backlight_on(struct panel_cntl *panel_cntl)
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{
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struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
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uint32_t blon, blon_ovrd, pwrseq_target_state;
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REG_GET_2(PWRSEQ_CNTL, LVTMA_BLON, &blon, LVTMA_BLON_OVRD, &blon_ovrd);
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REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state);
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if (blon_ovrd)
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return blon;
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else
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return pwrseq_target_state;
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}
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static bool dce_is_panel_powered_on(struct panel_cntl *panel_cntl)
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{
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struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
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uint32_t pwr_seq_state, dig_on, dig_on_ovrd;
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REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state);
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REG_GET_2(PWRSEQ_CNTL, LVTMA_DIGON, &dig_on, LVTMA_DIGON_OVRD, &dig_on_ovrd);
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return (pwr_seq_state == 1) || (dig_on == 1 && dig_on_ovrd == 1);
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}
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static void dce_store_backlight_level(struct panel_cntl *panel_cntl)
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{
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struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
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panel_cntl->stored_backlight_registers.BL_PWM_CNTL =
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REG_READ(BL_PWM_CNTL);
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panel_cntl->stored_backlight_registers.BL_PWM_CNTL2 =
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REG_READ(BL_PWM_CNTL2);
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panel_cntl->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
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REG_READ(BL_PWM_PERIOD_CNTL);
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REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
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&panel_cntl->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
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}
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static void dce_driver_set_backlight(struct panel_cntl *panel_cntl,
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uint32_t backlight_pwm_u16_16)
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{
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uint32_t backlight_16bit;
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uint32_t masked_pwm_period;
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uint8_t bit_count;
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uint64_t active_duty_cycle;
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uint32_t pwm_period_bitcnt;
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struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(panel_cntl);
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/*
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* 1. Find 16 bit backlight active duty cycle, where 0 <= backlight
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* active duty cycle <= backlight period
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*/
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/* 1.1 Apply bitmask for backlight period value based on value of BITCNT
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*/
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REG_GET_2(BL_PWM_PERIOD_CNTL,
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BL_PWM_PERIOD_BITCNT, &pwm_period_bitcnt,
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BL_PWM_PERIOD, &masked_pwm_period);
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if (pwm_period_bitcnt == 0)
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bit_count = 16;
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else
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bit_count = pwm_period_bitcnt;
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/* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
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masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
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/* 1.2 Calculate integer active duty cycle required upper 16 bits
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* contain integer component, lower 16 bits contain fractional component
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* of active duty cycle e.g. 0x21BDC0 = 0xEFF0 * 0x24
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*/
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active_duty_cycle = backlight_pwm_u16_16 * masked_pwm_period;
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/* 1.3 Calculate 16 bit active duty cycle from integer and fractional
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* components shift by bitCount then mask 16 bits and add rounding bit
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* from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
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*/
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backlight_16bit = active_duty_cycle >> bit_count;
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backlight_16bit &= 0xFFFF;
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backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
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/*
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* 2. Program register with updated value
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*/
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/* 2.1 Lock group 2 backlight registers */
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REG_UPDATE_2(BL_PWM_GRP1_REG_LOCK,
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BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, 1,
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BL_PWM_GRP1_REG_LOCK, 1);
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// 2.2 Write new active duty cycle
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REG_UPDATE(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, backlight_16bit);
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/* 2.3 Unlock group 2 backlight registers */
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REG_UPDATE(BL_PWM_GRP1_REG_LOCK,
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BL_PWM_GRP1_REG_LOCK, 0);
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/* 3 Wait for pending bit to be cleared */
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REG_WAIT(BL_PWM_GRP1_REG_LOCK,
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BL_PWM_GRP1_REG_UPDATE_PENDING, 0,
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1, 10000);
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}
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static void dce_panel_cntl_destroy(struct panel_cntl **panel_cntl)
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{
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struct dce_panel_cntl *dce_panel_cntl = TO_DCE_PANEL_CNTL(*panel_cntl);
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kfree(dce_panel_cntl);
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*panel_cntl = NULL;
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}
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static const struct panel_cntl_funcs dce_link_panel_cntl_funcs = {
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.destroy = dce_panel_cntl_destroy,
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.hw_init = dce_panel_cntl_hw_init,
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.is_panel_backlight_on = dce_is_panel_backlight_on,
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.is_panel_powered_on = dce_is_panel_powered_on,
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.store_backlight_level = dce_store_backlight_level,
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.driver_set_backlight = dce_driver_set_backlight,
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.get_current_backlight = dce_get_16_bit_backlight_from_pwm,
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};
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void dce_panel_cntl_construct(
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struct dce_panel_cntl *dce_panel_cntl,
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const struct panel_cntl_init_data *init_data,
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const struct dce_panel_cntl_registers *regs,
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const struct dce_panel_cntl_shift *shift,
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const struct dce_panel_cntl_mask *mask)
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{
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struct panel_cntl *base = &dce_panel_cntl->base;
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base->stored_backlight_registers.BL_PWM_CNTL = 0;
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base->stored_backlight_registers.BL_PWM_CNTL2 = 0;
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base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0;
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base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 0;
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dce_panel_cntl->regs = regs;
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dce_panel_cntl->shift = shift;
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dce_panel_cntl->mask = mask;
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dce_panel_cntl->base.funcs = &dce_link_panel_cntl_funcs;
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dce_panel_cntl->base.ctx = init_data->ctx;
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dce_panel_cntl->base.inst = init_data->inst;
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}
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