/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/delay.h>
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#include "dce_i2c.h"
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#include "dce_i2c_sw.h"
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#include "include/gpio_service_interface.h"
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#define SCL false
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#define SDA true
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void dce_i2c_sw_construct(
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struct dce_i2c_sw *dce_i2c_sw,
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struct dc_context *ctx)
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{
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dce_i2c_sw->ctx = ctx;
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}
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static inline bool read_bit_from_ddc(
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struct ddc *ddc,
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bool data_nor_clock)
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{
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uint32_t value = 0;
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if (data_nor_clock)
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dal_gpio_get_value(ddc->pin_data, &value);
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else
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dal_gpio_get_value(ddc->pin_clock, &value);
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return (value != 0);
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}
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static inline void write_bit_to_ddc(
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struct ddc *ddc,
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bool data_nor_clock,
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bool bit)
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{
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uint32_t value = bit ? 1 : 0;
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if (data_nor_clock)
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dal_gpio_set_value(ddc->pin_data, value);
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else
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dal_gpio_set_value(ddc->pin_clock, value);
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}
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static void release_engine_dce_sw(
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struct resource_pool *pool,
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struct dce_i2c_sw *dce_i2c_sw)
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{
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dal_ddc_close(dce_i2c_sw->ddc);
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dce_i2c_sw->ddc = NULL;
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}
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static bool wait_for_scl_high_sw(
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struct dc_context *ctx,
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struct ddc *ddc,
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uint16_t clock_delay_div_4)
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{
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uint32_t scl_retry = 0;
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uint32_t scl_retry_max = I2C_SW_TIMEOUT_DELAY / clock_delay_div_4;
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udelay(clock_delay_div_4);
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do {
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if (read_bit_from_ddc(ddc, SCL))
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return true;
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udelay(clock_delay_div_4);
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++scl_retry;
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} while (scl_retry <= scl_retry_max);
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return false;
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}
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static bool write_byte_sw(
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struct dc_context *ctx,
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struct ddc *ddc_handle,
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uint16_t clock_delay_div_4,
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uint8_t byte)
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{
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int32_t shift = 7;
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bool ack;
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/* bits are transmitted serially, starting from MSB */
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do {
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SDA, (byte >> shift) & 1);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SCL, true);
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if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
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return false;
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write_bit_to_ddc(ddc_handle, SCL, false);
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--shift;
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} while (shift >= 0);
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/* The display sends ACK by preventing the SDA from going high
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* after the SCL pulse we use to send our last data bit.
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* If the SDA goes high after that bit, it's a NACK
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*/
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SDA, true);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SCL, true);
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if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
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return false;
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/* read ACK bit */
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ack = !read_bit_from_ddc(ddc_handle, SDA);
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udelay(clock_delay_div_4 << 1);
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write_bit_to_ddc(ddc_handle, SCL, false);
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udelay(clock_delay_div_4 << 1);
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return ack;
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}
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static bool read_byte_sw(
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struct dc_context *ctx,
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struct ddc *ddc_handle,
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uint16_t clock_delay_div_4,
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uint8_t *byte,
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bool more)
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{
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int32_t shift = 7;
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uint8_t data = 0;
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/* The data bits are read from MSB to LSB;
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* bit is read while SCL is high
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*/
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do {
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write_bit_to_ddc(ddc_handle, SCL, true);
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if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
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return false;
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if (read_bit_from_ddc(ddc_handle, SDA))
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data |= (1 << shift);
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write_bit_to_ddc(ddc_handle, SCL, false);
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udelay(clock_delay_div_4 << 1);
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--shift;
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} while (shift >= 0);
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/* read only whole byte */
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*byte = data;
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udelay(clock_delay_div_4);
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/* send the acknowledge bit:
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* SDA low means ACK, SDA high means NACK
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*/
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write_bit_to_ddc(ddc_handle, SDA, !more);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SCL, true);
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if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
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return false;
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write_bit_to_ddc(ddc_handle, SCL, false);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SDA, true);
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udelay(clock_delay_div_4);
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return true;
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}
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static bool stop_sync_sw(
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struct dc_context *ctx,
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struct ddc *ddc_handle,
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uint16_t clock_delay_div_4)
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{
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uint32_t retry = 0;
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/* The I2C communications stop signal is:
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* the SDA going high from low, while the SCL is high.
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*/
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write_bit_to_ddc(ddc_handle, SCL, false);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SDA, false);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SCL, true);
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if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
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return false;
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write_bit_to_ddc(ddc_handle, SDA, true);
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do {
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udelay(clock_delay_div_4);
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if (read_bit_from_ddc(ddc_handle, SDA))
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return true;
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++retry;
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} while (retry <= 2);
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return false;
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}
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static bool i2c_write_sw(
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struct dc_context *ctx,
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struct ddc *ddc_handle,
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uint16_t clock_delay_div_4,
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uint8_t address,
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uint32_t length,
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const uint8_t *data)
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{
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uint32_t i = 0;
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if (!write_byte_sw(ctx, ddc_handle, clock_delay_div_4, address))
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return false;
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while (i < length) {
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if (!write_byte_sw(ctx, ddc_handle, clock_delay_div_4, data[i]))
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return false;
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++i;
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}
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return true;
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}
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static bool i2c_read_sw(
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struct dc_context *ctx,
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struct ddc *ddc_handle,
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uint16_t clock_delay_div_4,
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uint8_t address,
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uint32_t length,
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uint8_t *data)
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{
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uint32_t i = 0;
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if (!write_byte_sw(ctx, ddc_handle, clock_delay_div_4, address))
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return false;
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while (i < length) {
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if (!read_byte_sw(ctx, ddc_handle, clock_delay_div_4, data + i,
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i < length - 1))
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return false;
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++i;
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}
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return true;
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}
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static bool start_sync_sw(
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struct dc_context *ctx,
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struct ddc *ddc_handle,
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uint16_t clock_delay_div_4)
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{
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uint32_t retry = 0;
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/* The I2C communications start signal is:
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* the SDA going low from high, while the SCL is high.
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*/
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write_bit_to_ddc(ddc_handle, SCL, true);
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udelay(clock_delay_div_4);
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do {
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write_bit_to_ddc(ddc_handle, SDA, true);
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if (!read_bit_from_ddc(ddc_handle, SDA)) {
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++retry;
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continue;
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}
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SCL, true);
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if (!wait_for_scl_high_sw(ctx, ddc_handle, clock_delay_div_4))
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break;
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write_bit_to_ddc(ddc_handle, SDA, false);
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udelay(clock_delay_div_4);
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write_bit_to_ddc(ddc_handle, SCL, false);
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udelay(clock_delay_div_4);
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return true;
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} while (retry <= I2C_SW_RETRIES);
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return false;
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}
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void dce_i2c_sw_engine_set_speed(
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struct dce_i2c_sw *engine,
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uint32_t speed)
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{
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ASSERT(speed);
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engine->speed = speed ? speed : DCE_I2C_DEFAULT_I2C_SW_SPEED;
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engine->clock_delay = 1000 / engine->speed;
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if (engine->clock_delay < 12)
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engine->clock_delay = 12;
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}
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bool dce_i2c_sw_engine_acquire_engine(
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struct dce_i2c_sw *engine,
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struct ddc *ddc)
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{
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enum gpio_result result;
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result = dal_ddc_open(ddc, GPIO_MODE_FAST_OUTPUT,
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GPIO_DDC_CONFIG_TYPE_MODE_I2C);
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if (result != GPIO_RESULT_OK)
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return false;
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engine->ddc = ddc;
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return true;
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}
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bool dce_i2c_engine_acquire_sw(
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struct dce_i2c_sw *dce_i2c_sw,
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struct ddc *ddc_handle)
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{
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uint32_t counter = 0;
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bool result;
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do {
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result = dce_i2c_sw_engine_acquire_engine(
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dce_i2c_sw, ddc_handle);
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if (result)
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break;
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/* i2c_engine is busy by VBios, lets wait and retry */
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udelay(10);
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++counter;
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} while (counter < 2);
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return result;
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}
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void dce_i2c_sw_engine_submit_channel_request(
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struct dce_i2c_sw *engine,
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struct i2c_request_transaction_data *req)
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{
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struct ddc *ddc = engine->ddc;
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uint16_t clock_delay_div_4 = engine->clock_delay >> 2;
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/* send sync (start / repeated start) */
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bool result = start_sync_sw(engine->ctx, ddc, clock_delay_div_4);
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/* process payload */
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if (result) {
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switch (req->action) {
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case DCE_I2C_TRANSACTION_ACTION_I2C_WRITE:
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case DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT:
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result = i2c_write_sw(engine->ctx, ddc, clock_delay_div_4,
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req->address, req->length, req->data);
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break;
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case DCE_I2C_TRANSACTION_ACTION_I2C_READ:
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case DCE_I2C_TRANSACTION_ACTION_I2C_READ_MOT:
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result = i2c_read_sw(engine->ctx, ddc, clock_delay_div_4,
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req->address, req->length, req->data);
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break;
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default:
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result = false;
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break;
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}
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}
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/* send stop if not 'mot' or operation failed */
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if (!result ||
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(req->action == DCE_I2C_TRANSACTION_ACTION_I2C_WRITE) ||
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(req->action == DCE_I2C_TRANSACTION_ACTION_I2C_READ))
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if (!stop_sync_sw(engine->ctx, ddc, clock_delay_div_4))
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result = false;
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req->status = result ?
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I2C_CHANNEL_OPERATION_SUCCEEDED :
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I2C_CHANNEL_OPERATION_FAILED;
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}
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bool dce_i2c_sw_engine_submit_payload(
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struct dce_i2c_sw *engine,
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struct i2c_payload *payload,
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bool middle_of_transaction)
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{
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struct i2c_request_transaction_data request;
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if (!payload->write)
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request.action = middle_of_transaction ?
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DCE_I2C_TRANSACTION_ACTION_I2C_READ_MOT :
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DCE_I2C_TRANSACTION_ACTION_I2C_READ;
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else
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request.action = middle_of_transaction ?
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DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT :
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DCE_I2C_TRANSACTION_ACTION_I2C_WRITE;
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request.address = (uint8_t) ((payload->address << 1) | !payload->write);
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request.length = payload->length;
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request.data = payload->data;
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dce_i2c_sw_engine_submit_channel_request(engine, &request);
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if ((request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY) ||
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(request.status == I2C_CHANNEL_OPERATION_FAILED))
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return false;
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return true;
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}
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bool dce_i2c_submit_command_sw(
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struct resource_pool *pool,
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struct ddc *ddc,
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struct i2c_command *cmd,
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struct dce_i2c_sw *dce_i2c_sw)
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{
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uint8_t index_of_payload = 0;
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bool result;
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dce_i2c_sw_engine_set_speed(dce_i2c_sw, cmd->speed);
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result = true;
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while (index_of_payload < cmd->number_of_payloads) {
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bool mot = (index_of_payload != cmd->number_of_payloads - 1);
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struct i2c_payload *payload = cmd->payloads + index_of_payload;
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if (!dce_i2c_sw_engine_submit_payload(
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dce_i2c_sw, payload, mot)) {
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result = false;
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break;
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}
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++index_of_payload;
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}
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release_engine_dce_sw(pool, dce_i2c_sw);
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return result;
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}
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