/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/delay.h>
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#include "resource.h"
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#include "dce_i2c.h"
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#include "dce_i2c_hw.h"
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#include "reg_helper.h"
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#include "include/gpio_service_interface.h"
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#define CTX \
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dce_i2c_hw->ctx
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#define REG(reg)\
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dce_i2c_hw->regs->reg
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#undef FN
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#define FN(reg_name, field_name) \
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dce_i2c_hw->shifts->field_name, dce_i2c_hw->masks->field_name
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static void execute_transaction(
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struct dce_i2c_hw *dce_i2c_hw)
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{
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REG_UPDATE_N(SETUP, 5,
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FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_EN), 0,
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FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_CLK_DRIVE_EN), 0,
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FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL), 0,
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FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY), 0,
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FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY), 0);
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REG_UPDATE_5(DC_I2C_CONTROL,
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DC_I2C_SOFT_RESET, 0,
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DC_I2C_SW_STATUS_RESET, 0,
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DC_I2C_SEND_RESET, 0,
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DC_I2C_GO, 0,
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DC_I2C_TRANSACTION_COUNT, dce_i2c_hw->transaction_count - 1);
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/* start I2C transfer */
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REG_UPDATE(DC_I2C_CONTROL, DC_I2C_GO, 1);
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/* all transactions were executed and HW buffer became empty
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* (even though it actually happens when status becomes DONE)
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*/
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dce_i2c_hw->transaction_count = 0;
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dce_i2c_hw->buffer_used_bytes = 0;
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}
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static enum i2c_channel_operation_result get_channel_status(
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struct dce_i2c_hw *dce_i2c_hw,
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uint8_t *returned_bytes)
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{
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uint32_t i2c_sw_status = 0;
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uint32_t value =
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REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
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if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_SW)
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return I2C_CHANNEL_OPERATION_ENGINE_BUSY;
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else if (value & dce_i2c_hw->masks->DC_I2C_SW_STOPPED_ON_NACK)
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return I2C_CHANNEL_OPERATION_NO_RESPONSE;
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else if (value & dce_i2c_hw->masks->DC_I2C_SW_TIMEOUT)
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return I2C_CHANNEL_OPERATION_TIMEOUT;
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else if (value & dce_i2c_hw->masks->DC_I2C_SW_ABORTED)
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return I2C_CHANNEL_OPERATION_FAILED;
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else if (value & dce_i2c_hw->masks->DC_I2C_SW_DONE)
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return I2C_CHANNEL_OPERATION_SUCCEEDED;
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/*
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* this is the case when HW used for communication, I2C_SW_STATUS
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* could be zero
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*/
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return I2C_CHANNEL_OPERATION_SUCCEEDED;
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}
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static uint32_t get_hw_buffer_available_size(
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const struct dce_i2c_hw *dce_i2c_hw)
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{
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return dce_i2c_hw->buffer_size -
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dce_i2c_hw->buffer_used_bytes;
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}
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static void process_channel_reply(
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struct dce_i2c_hw *dce_i2c_hw,
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struct i2c_payload *reply)
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{
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uint32_t length = reply->length;
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uint8_t *buffer = reply->data;
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REG_SET_3(DC_I2C_DATA, 0,
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DC_I2C_INDEX, dce_i2c_hw->buffer_used_write,
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DC_I2C_DATA_RW, 1,
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DC_I2C_INDEX_WRITE, 1);
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while (length) {
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/* after reading the status,
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* if the I2C operation executed successfully
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* (i.e. DC_I2C_STATUS_DONE = 1) then the I2C controller
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* should read data bytes from I2C circular data buffer
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*/
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uint32_t i2c_data;
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REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data);
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*buffer++ = i2c_data;
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--length;
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}
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}
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static bool is_engine_available(struct dce_i2c_hw *dce_i2c_hw)
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{
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unsigned int arbitrate;
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unsigned int i2c_hw_status;
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REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status);
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if (i2c_hw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW)
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return false;
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REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
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if (arbitrate == DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY)
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return false;
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return true;
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}
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static bool is_hw_busy(struct dce_i2c_hw *dce_i2c_hw)
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{
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uint32_t i2c_sw_status = 0;
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REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
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if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
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return false;
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if (is_engine_available(dce_i2c_hw))
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return false;
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return true;
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}
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static bool process_transaction(
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struct dce_i2c_hw *dce_i2c_hw,
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struct i2c_request_transaction_data *request)
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{
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uint32_t length = request->length;
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uint8_t *buffer = request->data;
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bool last_transaction = false;
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uint32_t value = 0;
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if (is_hw_busy(dce_i2c_hw)) {
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request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
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return false;
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}
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last_transaction = ((dce_i2c_hw->transaction_count == 3) ||
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(request->action == DCE_I2C_TRANSACTION_ACTION_I2C_WRITE) ||
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(request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ));
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switch (dce_i2c_hw->transaction_count) {
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case 0:
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REG_UPDATE_5(DC_I2C_TRANSACTION0,
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DC_I2C_STOP_ON_NACK0, 1,
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DC_I2C_START0, 1,
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DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
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DC_I2C_COUNT0, length,
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DC_I2C_STOP0, last_transaction ? 1 : 0);
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break;
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case 1:
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REG_UPDATE_5(DC_I2C_TRANSACTION1,
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DC_I2C_STOP_ON_NACK0, 1,
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DC_I2C_START0, 1,
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DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
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DC_I2C_COUNT0, length,
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DC_I2C_STOP0, last_transaction ? 1 : 0);
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break;
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case 2:
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REG_UPDATE_5(DC_I2C_TRANSACTION2,
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DC_I2C_STOP_ON_NACK0, 1,
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DC_I2C_START0, 1,
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DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
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DC_I2C_COUNT0, length,
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DC_I2C_STOP0, last_transaction ? 1 : 0);
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break;
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case 3:
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REG_UPDATE_5(DC_I2C_TRANSACTION3,
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DC_I2C_STOP_ON_NACK0, 1,
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DC_I2C_START0, 1,
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DC_I2C_RW0, 0 != (request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ),
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DC_I2C_COUNT0, length,
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DC_I2C_STOP0, last_transaction ? 1 : 0);
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break;
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default:
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/* TODO Warning ? */
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break;
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}
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/* Write the I2C address and I2C data
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* into the hardware circular buffer, one byte per entry.
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* As an example, the 7-bit I2C slave address for CRT monitor
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* for reading DDC/EDID information is 0b1010001.
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* For an I2C send operation, the LSB must be programmed to 0;
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* for I2C receive operation, the LSB must be programmed to 1.
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*/
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if (dce_i2c_hw->transaction_count == 0) {
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value = REG_SET_4(DC_I2C_DATA, 0,
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DC_I2C_DATA_RW, false,
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DC_I2C_DATA, request->address,
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DC_I2C_INDEX, 0,
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DC_I2C_INDEX_WRITE, 1);
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dce_i2c_hw->buffer_used_write = 0;
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} else
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value = REG_SET_2(DC_I2C_DATA, 0,
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DC_I2C_DATA_RW, false,
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DC_I2C_DATA, request->address);
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dce_i2c_hw->buffer_used_write++;
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if (!(request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ)) {
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while (length) {
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REG_SET_2(DC_I2C_DATA, value,
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DC_I2C_INDEX_WRITE, 0,
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DC_I2C_DATA, *buffer++);
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dce_i2c_hw->buffer_used_write++;
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--length;
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}
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}
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++dce_i2c_hw->transaction_count;
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dce_i2c_hw->buffer_used_bytes += length + 1;
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return last_transaction;
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}
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static inline void reset_hw_engine(struct dce_i2c_hw *dce_i2c_hw)
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{
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REG_UPDATE_2(DC_I2C_CONTROL,
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DC_I2C_SW_STATUS_RESET, 1,
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DC_I2C_SW_STATUS_RESET, 1);
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}
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static void set_speed(
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struct dce_i2c_hw *dce_i2c_hw,
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uint32_t speed)
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{
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uint32_t xtal_ref_div = 0;
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uint32_t prescale = 0;
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if (speed == 0)
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return;
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REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div);
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if (xtal_ref_div == 0)
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xtal_ref_div = 2;
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prescale = ((dce_i2c_hw->reference_frequency * 2) / xtal_ref_div) / speed;
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if (dce_i2c_hw->masks->DC_I2C_DDC1_START_STOP_TIMING_CNTL)
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REG_UPDATE_N(SPEED, 3,
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FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), prescale,
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FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2,
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FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_START_STOP_TIMING_CNTL), speed > 50 ? 2:1);
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else
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REG_UPDATE_N(SPEED, 2,
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FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_PRESCALE), prescale,
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FN(DC_I2C_DDC1_SPEED, DC_I2C_DDC1_THRESHOLD), 2);
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}
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static bool setup_engine(
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struct dce_i2c_hw *dce_i2c_hw)
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{
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uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
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uint32_t reset_length = 0;
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/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
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REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
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/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/
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REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
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if (dce_i2c_hw->setup_limit != 0)
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i2c_setup_limit = dce_i2c_hw->setup_limit;
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/* Program pin select */
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REG_UPDATE_6(DC_I2C_CONTROL,
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DC_I2C_GO, 0,
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DC_I2C_SOFT_RESET, 0,
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DC_I2C_SEND_RESET, 0,
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DC_I2C_SW_STATUS_RESET, 1,
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DC_I2C_TRANSACTION_COUNT, 0,
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DC_I2C_DDC_SELECT, dce_i2c_hw->engine_id);
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/* Program time limit */
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if (dce_i2c_hw->send_reset_length == 0) {
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/*pre-dcn*/
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REG_UPDATE_N(SETUP, 2,
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FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
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FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
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} else {
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reset_length = dce_i2c_hw->send_reset_length;
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REG_UPDATE_N(SETUP, 3,
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FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT), i2c_setup_limit,
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FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH), reset_length,
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FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
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}
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/* Program HW priority
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* set to High - interrupt software I2C at any time
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* Enable restart of SW I2C that was interrupted by HW
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* disable queuing of software while I2C is in use by HW
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*/
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REG_UPDATE(DC_I2C_ARBITRATION,
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DC_I2C_NO_QUEUED_SW_GO, 0);
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return true;
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}
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static void release_engine(
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struct dce_i2c_hw *dce_i2c_hw)
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{
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bool safe_to_reset;
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/* Restore original HW engine speed */
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set_speed(dce_i2c_hw, dce_i2c_hw->default_speed);
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/* Reset HW engine */
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{
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uint32_t i2c_sw_status = 0;
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REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
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/* if used by SW, safe to reset */
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safe_to_reset = (i2c_sw_status == 1);
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}
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if (safe_to_reset)
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REG_UPDATE_2(DC_I2C_CONTROL,
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DC_I2C_SOFT_RESET, 1,
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DC_I2C_SW_STATUS_RESET, 1);
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else
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REG_UPDATE(DC_I2C_CONTROL, DC_I2C_SW_STATUS_RESET, 1);
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/* HW I2c engine - clock gating feature */
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if (!dce_i2c_hw->engine_keep_power_up_count)
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REG_UPDATE_N(SETUP, 1, FN(SETUP, DC_I2C_DDC1_ENABLE), 0);
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/* Release I2C after reset, so HW or DMCU could use it */
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REG_UPDATE_2(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, 1,
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DC_I2C_SW_USE_I2C_REG_REQ, 0);
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}
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struct dce_i2c_hw *acquire_i2c_hw_engine(
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struct resource_pool *pool,
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struct ddc *ddc)
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{
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uint32_t counter = 0;
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enum gpio_result result;
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struct dce_i2c_hw *dce_i2c_hw = NULL;
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if (!ddc)
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return NULL;
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if (ddc->hw_info.hw_supported) {
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enum gpio_ddc_line line = dal_ddc_get_line(ddc);
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if (line < pool->res_cap->num_ddc)
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dce_i2c_hw = pool->hw_i2cs[line];
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}
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if (!dce_i2c_hw)
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return NULL;
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if (pool->i2c_hw_buffer_in_use || !is_engine_available(dce_i2c_hw))
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return NULL;
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do {
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result = dal_ddc_open(ddc, GPIO_MODE_HARDWARE,
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GPIO_DDC_CONFIG_TYPE_MODE_I2C);
|
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if (result == GPIO_RESULT_OK)
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break;
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/* i2c_engine is busy by VBios, lets wait and retry */
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udelay(10);
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++counter;
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} while (counter < 2);
|
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if (result != GPIO_RESULT_OK)
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return NULL;
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dce_i2c_hw->ddc = ddc;
|
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if (!setup_engine(dce_i2c_hw)) {
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release_engine(dce_i2c_hw);
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return NULL;
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}
|
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pool->i2c_hw_buffer_in_use = true;
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return dce_i2c_hw;
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}
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enum i2c_channel_operation_result dce_i2c_hw_engine_wait_on_operation_result(
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struct dce_i2c_hw *dce_i2c_hw,
|
uint32_t timeout,
|
enum i2c_channel_operation_result expected_result)
|
{
|
enum i2c_channel_operation_result result;
|
uint32_t i = 0;
|
|
if (!timeout)
|
return I2C_CHANNEL_OPERATION_SUCCEEDED;
|
|
do {
|
|
result = get_channel_status(
|
dce_i2c_hw, NULL);
|
|
if (result != expected_result)
|
break;
|
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udelay(1);
|
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++i;
|
} while (i < timeout);
|
return result;
|
}
|
|
static void submit_channel_request_hw(
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struct dce_i2c_hw *dce_i2c_hw,
|
struct i2c_request_transaction_data *request)
|
{
|
request->status = I2C_CHANNEL_OPERATION_SUCCEEDED;
|
|
if (!process_transaction(dce_i2c_hw, request))
|
return;
|
|
if (is_hw_busy(dce_i2c_hw)) {
|
request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
|
return;
|
}
|
reset_hw_engine(dce_i2c_hw);
|
|
execute_transaction(dce_i2c_hw);
|
|
|
}
|
|
static uint32_t get_transaction_timeout_hw(
|
const struct dce_i2c_hw *dce_i2c_hw,
|
uint32_t length,
|
uint32_t speed)
|
{
|
uint32_t period_timeout;
|
uint32_t num_of_clock_stretches;
|
|
if (!speed)
|
return 0;
|
|
period_timeout = (1000 * TRANSACTION_TIMEOUT_IN_I2C_CLOCKS) / speed;
|
|
num_of_clock_stretches = 1 + (length << 3) + 1;
|
num_of_clock_stretches +=
|
(dce_i2c_hw->buffer_used_bytes << 3) +
|
(dce_i2c_hw->transaction_count << 1);
|
|
return period_timeout * num_of_clock_stretches;
|
}
|
|
bool dce_i2c_hw_engine_submit_payload(
|
struct dce_i2c_hw *dce_i2c_hw,
|
struct i2c_payload *payload,
|
bool middle_of_transaction,
|
uint32_t speed)
|
{
|
|
struct i2c_request_transaction_data request;
|
|
uint32_t transaction_timeout;
|
|
enum i2c_channel_operation_result operation_result;
|
|
bool result = false;
|
|
/* We need following:
|
* transaction length will not exceed
|
* the number of free bytes in HW buffer (minus one for address)
|
*/
|
|
if (payload->length >=
|
get_hw_buffer_available_size(dce_i2c_hw)) {
|
return false;
|
}
|
|
if (!payload->write)
|
request.action = middle_of_transaction ?
|
DCE_I2C_TRANSACTION_ACTION_I2C_READ_MOT :
|
DCE_I2C_TRANSACTION_ACTION_I2C_READ;
|
else
|
request.action = middle_of_transaction ?
|
DCE_I2C_TRANSACTION_ACTION_I2C_WRITE_MOT :
|
DCE_I2C_TRANSACTION_ACTION_I2C_WRITE;
|
|
|
request.address = (uint8_t) ((payload->address << 1) | !payload->write);
|
request.length = payload->length;
|
request.data = payload->data;
|
|
/* obtain timeout value before submitting request */
|
|
transaction_timeout = get_transaction_timeout_hw(
|
dce_i2c_hw, payload->length + 1, speed);
|
|
submit_channel_request_hw(
|
dce_i2c_hw, &request);
|
|
if ((request.status == I2C_CHANNEL_OPERATION_FAILED) ||
|
(request.status == I2C_CHANNEL_OPERATION_ENGINE_BUSY))
|
return false;
|
|
/* wait until transaction proceed */
|
|
operation_result = dce_i2c_hw_engine_wait_on_operation_result(
|
dce_i2c_hw,
|
transaction_timeout,
|
I2C_CHANNEL_OPERATION_ENGINE_BUSY);
|
|
/* update transaction status */
|
|
if (operation_result == I2C_CHANNEL_OPERATION_SUCCEEDED)
|
result = true;
|
|
if (result && (!payload->write))
|
process_channel_reply(dce_i2c_hw, payload);
|
|
return result;
|
}
|
|
bool dce_i2c_submit_command_hw(
|
struct resource_pool *pool,
|
struct ddc *ddc,
|
struct i2c_command *cmd,
|
struct dce_i2c_hw *dce_i2c_hw)
|
{
|
uint8_t index_of_payload = 0;
|
bool result;
|
|
set_speed(dce_i2c_hw, cmd->speed);
|
|
result = true;
|
|
while (index_of_payload < cmd->number_of_payloads) {
|
bool mot = (index_of_payload != cmd->number_of_payloads - 1);
|
|
struct i2c_payload *payload = cmd->payloads + index_of_payload;
|
|
if (!dce_i2c_hw_engine_submit_payload(
|
dce_i2c_hw, payload, mot, cmd->speed)) {
|
result = false;
|
break;
|
}
|
|
++index_of_payload;
|
}
|
|
pool->i2c_hw_buffer_in_use = false;
|
|
release_engine(dce_i2c_hw);
|
dal_ddc_close(dce_i2c_hw->ddc);
|
|
dce_i2c_hw->ddc = NULL;
|
|
return result;
|
}
|
|
void dce_i2c_hw_construct(
|
struct dce_i2c_hw *dce_i2c_hw,
|
struct dc_context *ctx,
|
uint32_t engine_id,
|
const struct dce_i2c_registers *regs,
|
const struct dce_i2c_shift *shifts,
|
const struct dce_i2c_mask *masks)
|
{
|
dce_i2c_hw->ctx = ctx;
|
dce_i2c_hw->engine_id = engine_id;
|
dce_i2c_hw->reference_frequency = (ctx->dc_bios->fw_info.pll_info.crystal_frequency) >> 1;
|
dce_i2c_hw->regs = regs;
|
dce_i2c_hw->shifts = shifts;
|
dce_i2c_hw->masks = masks;
|
dce_i2c_hw->buffer_used_bytes = 0;
|
dce_i2c_hw->transaction_count = 0;
|
dce_i2c_hw->engine_keep_power_up_count = 1;
|
dce_i2c_hw->default_speed = DEFAULT_I2C_HW_SPEED;
|
dce_i2c_hw->send_reset_length = 0;
|
dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
|
dce_i2c_hw->buffer_size = I2C_HW_BUFFER_SIZE_DCE;
|
}
|
|
void dce100_i2c_hw_construct(
|
struct dce_i2c_hw *dce_i2c_hw,
|
struct dc_context *ctx,
|
uint32_t engine_id,
|
const struct dce_i2c_registers *regs,
|
const struct dce_i2c_shift *shifts,
|
const struct dce_i2c_mask *masks)
|
{
|
dce_i2c_hw_construct(dce_i2c_hw,
|
ctx,
|
engine_id,
|
regs,
|
shifts,
|
masks);
|
dce_i2c_hw->buffer_size = I2C_HW_BUFFER_SIZE_DCE100;
|
}
|
|
void dce112_i2c_hw_construct(
|
struct dce_i2c_hw *dce_i2c_hw,
|
struct dc_context *ctx,
|
uint32_t engine_id,
|
const struct dce_i2c_registers *regs,
|
const struct dce_i2c_shift *shifts,
|
const struct dce_i2c_mask *masks)
|
{
|
dce100_i2c_hw_construct(dce_i2c_hw,
|
ctx,
|
engine_id,
|
regs,
|
shifts,
|
masks);
|
dce_i2c_hw->default_speed = DEFAULT_I2C_HW_SPEED_100KHZ;
|
}
|
|
void dcn1_i2c_hw_construct(
|
struct dce_i2c_hw *dce_i2c_hw,
|
struct dc_context *ctx,
|
uint32_t engine_id,
|
const struct dce_i2c_registers *regs,
|
const struct dce_i2c_shift *shifts,
|
const struct dce_i2c_mask *masks)
|
{
|
dce112_i2c_hw_construct(dce_i2c_hw,
|
ctx,
|
engine_id,
|
regs,
|
shifts,
|
masks);
|
dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCN;
|
}
|
|
void dcn2_i2c_hw_construct(
|
struct dce_i2c_hw *dce_i2c_hw,
|
struct dc_context *ctx,
|
uint32_t engine_id,
|
const struct dce_i2c_registers *regs,
|
const struct dce_i2c_shift *shifts,
|
const struct dce_i2c_mask *masks)
|
{
|
dcn1_i2c_hw_construct(dce_i2c_hw,
|
ctx,
|
engine_id,
|
regs,
|
shifts,
|
masks);
|
dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_9;
|
if (ctx->dc->debug.scl_reset_length10)
|
dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_10;
|
}
|
