/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_SDMA_H__
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#define __AMDGPU_SDMA_H__
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/* max number of IP instances */
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#define AMDGPU_MAX_SDMA_INSTANCES 8
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enum amdgpu_sdma_irq {
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AMDGPU_SDMA_IRQ_INSTANCE0 = 0,
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AMDGPU_SDMA_IRQ_INSTANCE1,
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AMDGPU_SDMA_IRQ_INSTANCE2,
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AMDGPU_SDMA_IRQ_INSTANCE3,
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AMDGPU_SDMA_IRQ_INSTANCE4,
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AMDGPU_SDMA_IRQ_INSTANCE5,
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AMDGPU_SDMA_IRQ_INSTANCE6,
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AMDGPU_SDMA_IRQ_INSTANCE7,
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AMDGPU_SDMA_IRQ_LAST
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};
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struct amdgpu_sdma_instance {
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/* SDMA firmware */
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const struct firmware *fw;
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uint32_t fw_version;
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uint32_t feature_version;
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struct amdgpu_ring ring;
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struct amdgpu_ring page;
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bool burst_nop;
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};
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struct amdgpu_sdma_ras_funcs {
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int (*ras_late_init)(struct amdgpu_device *adev,
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void *ras_ih_info);
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void (*ras_fini)(struct amdgpu_device *adev);
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int (*query_ras_error_count)(struct amdgpu_device *adev,
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uint32_t instance, void *ras_error_status);
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void (*reset_ras_error_count)(struct amdgpu_device *adev);
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};
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struct amdgpu_sdma {
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struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
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struct amdgpu_irq_src trap_irq;
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struct amdgpu_irq_src illegal_inst_irq;
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struct amdgpu_irq_src ecc_irq;
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int num_instances;
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uint32_t srbm_soft_reset;
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bool has_page_queue;
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struct ras_common_if *ras_if;
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const struct amdgpu_sdma_ras_funcs *funcs;
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};
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/*
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* Provided by hw blocks that can move/clear data. e.g., gfx or sdma
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* But currently, we use sdma to move data.
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*/
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struct amdgpu_buffer_funcs {
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/* maximum bytes in a single operation */
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uint32_t copy_max_bytes;
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/* number of dw to reserve per operation */
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unsigned copy_num_dw;
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/* used for buffer migration */
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void (*emit_copy_buffer)(struct amdgpu_ib *ib,
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/* src addr in bytes */
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uint64_t src_offset,
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/* dst addr in bytes */
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uint64_t dst_offset,
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/* number of byte to transfer */
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uint32_t byte_count,
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bool tmz);
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/* maximum bytes in a single operation */
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uint32_t fill_max_bytes;
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/* number of dw to reserve per operation */
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unsigned fill_num_dw;
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/* used for buffer clearing */
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void (*emit_fill_buffer)(struct amdgpu_ib *ib,
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/* value to write to memory */
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uint32_t src_data,
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/* dst addr in bytes */
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uint64_t dst_offset,
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/* number of byte to fill */
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uint32_t byte_count);
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};
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#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t))
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#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
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struct amdgpu_sdma_instance *
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amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
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int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
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uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
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int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
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void *ras_ih_info);
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void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
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int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
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void *err_data,
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struct amdgpu_iv_entry *entry);
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int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry);
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#endif
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