// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the R-Car V3U (R8A779A0) SoC
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a779a0-sysc.h>
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/ {
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compatible = "renesas,r8a779a0";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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a76_0: cpu@0 {
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compatible = "arm,cortex-a76";
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reg = <0>;
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device_type = "cpu";
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power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
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next-level-cache = <&L3_CA76_0>;
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};
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L3_CA76_0: cache-controller-0 {
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compatible = "cache";
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power-domains = <&sysc R8A779A0_PD_A2E0D0>;
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cache-unified;
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cache-level = <3>;
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};
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};
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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extalr_clk: extalr {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board */
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clock-frequency = <0>;
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};
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pmu_a76 {
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compatible = "arm,cortex-a76-pmu";
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interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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/* External SCIF clock - to be overridden by boards that provide it */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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soc: soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a779a0-cpg-mssr";
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reg = <0 0xe6150000 0 0x4000>;
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clocks = <&extal_clk>, <&extalr_clk>;
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clock-names = "extal", "extalr";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a779a0-rst";
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reg = <0 0xe6160000 0 0x4000>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a779a0-sysc";
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reg = <0 0xe6180000 0 0x4000>;
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#power-domain-cells = <1>;
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a779a0",
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"renesas,rcar-gen3-scif", "renesas,scif";
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reg = <0 0xe6e60000 0 64>;
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interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 702>,
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<&cpg CPG_CORE R8A779A0_CLK_S1D2>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
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resets = <&cpg 702>;
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status = "disabled";
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};
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gic: interrupt-controller@f1000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xf1000000 0 0x20000>,
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<0x0 0xf1060000 0 0x110000>;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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prr: chipid@fff00044 {
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compatible = "renesas,prr";
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reg = <0 0xfff00044 0 4>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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};
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};
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