/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
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*/
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#include <linux/linkage.h>
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#include <soc/tegra/flowctrl.h>
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#include <soc/tegra/fuse.h>
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#include <asm/asm-offsets.h>
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#include <asm/assembler.h>
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#include <asm/cache.h>
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#include "irammap.h"
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#include "sleep.h"
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#define EMC_CFG 0xc
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#define EMC_ADR_CFG 0x10
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#define EMC_TIMING_CONTROL 0x28
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#define EMC_NOP 0xdc
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#define EMC_SELF_REF 0xe0
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#define EMC_MRW 0xe8
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#define EMC_FBIO_CFG5 0x104
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#define EMC_AUTO_CAL_CONFIG 0x2a4
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#define EMC_AUTO_CAL_INTERVAL 0x2a8
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#define EMC_AUTO_CAL_STATUS 0x2ac
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#define EMC_REQ_CTRL 0x2b0
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#define EMC_CFG_DIG_DLL 0x2bc
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#define EMC_EMC_STATUS 0x2b4
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#define EMC_ZCAL_INTERVAL 0x2e0
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#define EMC_ZQ_CAL 0x2ec
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#define EMC_XM2VTTGENPADCTRL 0x310
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#define EMC_XM2VTTGENPADCTRL2 0x314
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#define PMC_CTRL 0x0
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#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
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#define PMC_PLLP_WB0_OVERRIDE 0xf8
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#define PMC_IO_DPD_REQ 0x1b8
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#define PMC_IO_DPD_STATUS 0x1bc
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#define CLK_RESET_CCLK_BURST 0x20
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#define CLK_RESET_CCLK_DIVIDER 0x24
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#define CLK_RESET_SCLK_BURST 0x28
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#define CLK_RESET_SCLK_DIVIDER 0x2c
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#define CLK_RESET_PLLC_BASE 0x80
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#define CLK_RESET_PLLC_MISC 0x8c
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#define CLK_RESET_PLLM_BASE 0x90
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#define CLK_RESET_PLLM_MISC 0x9c
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#define CLK_RESET_PLLP_BASE 0xa0
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#define CLK_RESET_PLLP_MISC 0xac
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#define CLK_RESET_PLLA_BASE 0xb0
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#define CLK_RESET_PLLA_MISC 0xbc
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#define CLK_RESET_PLLX_BASE 0xe0
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#define CLK_RESET_PLLX_MISC 0xe4
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#define CLK_RESET_PLLX_MISC3 0x518
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#define CLK_RESET_PLLX_MISC3_IDDQ 3
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#define CLK_RESET_PLLM_MISC_IDDQ 5
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#define CLK_RESET_PLLC_MISC_IDDQ 26
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#define CLK_RESET_PLLP_RESHIFT 0x528
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#define CLK_RESET_PLLP_RESHIFT_DEFAULT 0x3b
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#define CLK_RESET_PLLP_RESHIFT_ENABLE 0x3
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#define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
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#define MSELECT_CLKM (0x3 << 30)
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#define LOCK_DELAY 50 /* safety delay after lock is detected */
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#define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
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.macro emc_device_mask, rd, base
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ldr \rd, [\base, #EMC_ADR_CFG]
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tst \rd, #0x1
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moveq \rd, #(0x1 << 8) @ just 1 device
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movne \rd, #(0x3 << 8) @ 2 devices
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.endm
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.macro emc_timing_update, rd, base
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mov \rd, #1
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str \rd, [\base, #EMC_TIMING_CONTROL]
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1001:
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ldr \rd, [\base, #EMC_EMC_STATUS]
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tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
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bne 1001b
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.endm
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.macro pll_enable, rd, r_car_base, pll_base, pll_misc
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ldr \rd, [\r_car_base, #\pll_base]
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tst \rd, #(1 << 30)
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orreq \rd, \rd, #(1 << 30)
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streq \rd, [\r_car_base, #\pll_base]
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/* Enable lock detector */
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.if \pll_misc
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ldr \rd, [\r_car_base, #\pll_misc]
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bic \rd, \rd, #(1 << 18)
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str \rd, [\r_car_base, #\pll_misc]
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ldr \rd, [\r_car_base, #\pll_misc]
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ldr \rd, [\r_car_base, #\pll_misc]
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orr \rd, \rd, #(1 << 18)
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str \rd, [\r_car_base, #\pll_misc]
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.endif
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.endm
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.macro pll_locked, rd, r_car_base, pll_base
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1:
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ldr \rd, [\r_car_base, #\pll_base]
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tst \rd, #(1 << 27)
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beq 1b
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.endm
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.macro pll_iddq_exit, rd, car, iddq, iddq_bit
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ldr \rd, [\car, #\iddq]
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bic \rd, \rd, #(1<<\iddq_bit)
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str \rd, [\car, #\iddq]
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.endm
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.macro pll_iddq_entry, rd, car, iddq, iddq_bit
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ldr \rd, [\car, #\iddq]
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orr \rd, \rd, #(1<<\iddq_bit)
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str \rd, [\car, #\iddq]
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.endm
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#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
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/*
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* tegra30_hotplug_shutdown(void)
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*
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* Powergates the current CPU.
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* Should never return.
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*/
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ENTRY(tegra30_hotplug_shutdown)
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/* Powergate this CPU */
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mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
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bl tegra30_cpu_shutdown
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ret lr @ should never get here
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ENDPROC(tegra30_hotplug_shutdown)
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/*
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* tegra30_cpu_shutdown(unsigned long flags)
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*
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* Puts the current CPU in wait-for-event mode on the flow controller
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* and powergates it -- flags (in R0) indicate the request type.
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*
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* r10 = SoC ID
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* corrupts r0-r4, r10-r12
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*/
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ENTRY(tegra30_cpu_shutdown)
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cpu_id r3
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tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
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cmp r10, #TEGRA30
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bne _no_cpu0_chk @ It's not Tegra30
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cmp r3, #0
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reteq lr @ Must never be called for CPU 0
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_no_cpu0_chk:
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ldr r12, =TEGRA_FLOW_CTRL_VIRT
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cpu_to_csr_reg r1, r3
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add r1, r1, r12 @ virtual CSR address for this CPU
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cpu_to_halt_reg r2, r3
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add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
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/*
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* Clear this CPU's "event" and "interrupt" flags and power gate
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* it when halting but not before it is in the "WFE" state.
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*/
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movw r12, \
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FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
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FLOW_CTRL_CSR_ENABLE
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cmp r10, #TEGRA30
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moveq r4, #(1 << 4) @ wfe bitmap
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movne r4, #(1 << 8) @ wfi bitmap
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ARM( orr r12, r12, r4, lsl r3 )
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THUMB( lsl r4, r4, r3 )
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THUMB( orr r12, r12, r4 )
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str r12, [r1]
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/* Halt this CPU. */
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mov r3, #0x400
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delay_1:
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subs r3, r3, #1 @ delay as a part of wfe war.
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bge delay_1;
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cpsid a @ disable imprecise aborts.
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ldr r3, [r1] @ read CSR
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str r3, [r1] @ clear CSR
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tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
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beq flow_ctrl_setting_for_lp2
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/* flow controller set up for hotplug */
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mov r3, #FLOW_CTRL_WAITEVENT @ For hotplug
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b flow_ctrl_done
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flow_ctrl_setting_for_lp2:
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/* flow controller set up for LP2 */
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cmp r10, #TEGRA30
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moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
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movne r3, #FLOW_CTRL_WAITEVENT
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orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
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orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
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flow_ctrl_done:
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cmp r10, #TEGRA30
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str r3, [r2]
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ldr r0, [r2]
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b wfe_war
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__cpu_reset_again:
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dsb
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.align 5
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wfeeq @ CPU should be power gated here
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wfine
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wfe_war:
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b __cpu_reset_again
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/*
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* 38 nop's, which fills rest of wfe cache line and
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* 4 more cachelines with nop
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*/
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.rept 38
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nop
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.endr
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b . @ should never get here
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ENDPROC(tegra30_cpu_shutdown)
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#endif
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#ifdef CONFIG_PM_SLEEP
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/*
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* tegra30_sleep_core_finish(unsigned long v2p)
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*
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* Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
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* tegra30_tear_down_core in IRAM
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*/
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ENTRY(tegra30_sleep_core_finish)
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mov r4, r0
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/* Flush, disable the L1 data cache and exit SMP */
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mov r0, #TEGRA_FLUSH_CACHE_ALL
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bl tegra_disable_clean_inv_dcache
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mov r0, r4
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/*
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* Preload all the address literals that are needed for the
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* CPU power-gating process, to avoid loading from SDRAM which
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* are not supported once SDRAM is put into self-refresh.
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* LP0 / LP1 use physical address, since the MMU needs to be
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* disabled before putting SDRAM into self-refresh to avoid
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* memory access due to page table walks.
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*/
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mov32 r4, TEGRA_PMC_BASE
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mov32 r5, TEGRA_CLK_RESET_BASE
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mov32 r6, TEGRA_FLOW_CTRL_BASE
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mov32 r7, TEGRA_TMRUS_BASE
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mov32 r3, tegra_shut_off_mmu
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add r3, r3, r0
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mov32 r0, tegra30_tear_down_core
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mov32 r1, tegra30_iram_start
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sub r0, r0, r1
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mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA
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add r0, r0, r1
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ret r3
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ENDPROC(tegra30_sleep_core_finish)
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/*
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* tegra30_pm_secondary_cpu_suspend(unsigned long unused_arg)
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*
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* Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
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*/
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ENTRY(tegra30_pm_secondary_cpu_suspend)
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mov r7, lr
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/* Flush and disable the L1 data cache */
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mov r0, #TEGRA_FLUSH_CACHE_LOUIS
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bl tegra_disable_clean_inv_dcache
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/* Powergate this CPU. */
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mov r0, #0 @ power mode flags (!hotplug)
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bl tegra30_cpu_shutdown
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mov r0, #1 @ never return here
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ret r7
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ENDPROC(tegra30_pm_secondary_cpu_suspend)
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/*
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* tegra30_tear_down_cpu
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*
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* Switches the CPU to enter sleep.
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*/
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ENTRY(tegra30_tear_down_cpu)
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mov32 r6, TEGRA_FLOW_CTRL_BASE
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b tegra30_enter_sleep
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ENDPROC(tegra30_tear_down_cpu)
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/* START OF ROUTINES COPIED TO IRAM */
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.align L1_CACHE_SHIFT
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.globl tegra30_iram_start
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tegra30_iram_start:
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/*
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* tegra30_lp1_reset
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*
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* reset vector for LP1 restore; copied into IRAM during suspend.
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* Brings the system back up to a safe staring point (SDRAM out of
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* self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
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* system clock running on the same PLL that it suspended at), and
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* jumps to tegra_resume to restore virtual addressing.
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* The physical address of tegra_resume expected to be stored in
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* PMC_SCRATCH41.
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*
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* NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
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*/
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ENTRY(tegra30_lp1_reset)
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/*
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* The CPU and system bus are running at 32KHz and executing from
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* IRAM when this code is executed; immediately switch to CLKM and
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* enable PLLP, PLLM, PLLC, PLLA and PLLX.
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*/
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mov32 r0, TEGRA_CLK_RESET_BASE
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mov r1, #(1 << 28)
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str r1, [r0, #CLK_RESET_SCLK_BURST]
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str r1, [r0, #CLK_RESET_CCLK_BURST]
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mov r1, #0
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str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
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str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
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tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
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cmp r10, #TEGRA30
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beq _no_pll_iddq_exit
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pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
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pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
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pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
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mov32 r7, TEGRA_TMRUS_BASE
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ldr r1, [r7]
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add r1, r1, #2
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wait_until r1, r7, r3
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/* enable PLLM via PMC */
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mov32 r2, TEGRA_PMC_BASE
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ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
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orr r1, r1, #(1 << 12)
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str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
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pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
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pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
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pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
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b _pll_m_c_x_done
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_no_pll_iddq_exit:
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/* enable PLLM via PMC */
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mov32 r2, TEGRA_PMC_BASE
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ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
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orr r1, r1, #(1 << 12)
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str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
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pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
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pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
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_pll_m_c_x_done:
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pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
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pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
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pll_locked r1, r0, CLK_RESET_PLLM_BASE
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pll_locked r1, r0, CLK_RESET_PLLP_BASE
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pll_locked r1, r0, CLK_RESET_PLLA_BASE
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pll_locked r1, r0, CLK_RESET_PLLC_BASE
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/*
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* CPUFreq driver could select other PLL for CPU. PLLX will be
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* enabled by the Tegra30 CLK driver on an as-needed basis, see
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* tegra30_cpu_clock_resume().
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*/
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tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
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cmp r1, #TEGRA30
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beq 1f
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pll_locked r1, r0, CLK_RESET_PLLX_BASE
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ldr r1, [r0, #CLK_RESET_PLLP_BASE]
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bic r1, r1, #(1<<31) @ disable PllP bypass
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str r1, [r0, #CLK_RESET_PLLP_BASE]
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mov r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
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str r1, [r0, #CLK_RESET_PLLP_RESHIFT]
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1:
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mov32 r7, TEGRA_TMRUS_BASE
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ldr r1, [r7]
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add r1, r1, #LOCK_DELAY
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wait_until r1, r7, r3
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adr r5, tegra_sdram_pad_save
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ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
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str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
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ldr r4, [r5, #0x1C] @ restore SCLK_BURST
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str r4, [r0, #CLK_RESET_SCLK_BURST]
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movw r4, #:lower16:((1 << 28) | (0x4)) @ burst policy is PLLP
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movt r4, #:upper16:((1 << 28) | (0x4))
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str r4, [r0, #CLK_RESET_CCLK_BURST]
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/* Restore pad power state to normal */
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ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
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mvn r1, r1
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bic r1, r1, #(1 << 31)
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orr r1, r1, #(1 << 30)
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str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
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cmp r10, #TEGRA30
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movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
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movteq r0, #:upper16:TEGRA_EMC_BASE
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cmp r10, #TEGRA114
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movweq r0, #:lower16:TEGRA_EMC0_BASE
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movteq r0, #:upper16:TEGRA_EMC0_BASE
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cmp r10, #TEGRA124
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movweq r0, #:lower16:TEGRA124_EMC_BASE
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movteq r0, #:upper16:TEGRA124_EMC_BASE
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exit_self_refresh:
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ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
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str r1, [r0, #EMC_XM2VTTGENPADCTRL]
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ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
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str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
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ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
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str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
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/* Relock DLL */
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ldr r1, [r0, #EMC_CFG_DIG_DLL]
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orr r1, r1, #(1 << 30) @ set DLL_RESET
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str r1, [r0, #EMC_CFG_DIG_DLL]
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emc_timing_update r1, r0
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cmp r10, #TEGRA114
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movweq r1, #:lower16:TEGRA_EMC1_BASE
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movteq r1, #:upper16:TEGRA_EMC1_BASE
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cmpeq r0, r1
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ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
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orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
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orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
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str r1, [r0, #EMC_AUTO_CAL_CONFIG]
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emc_wait_auto_cal_onetime:
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ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
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tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
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bne emc_wait_auto_cal_onetime
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ldr r1, [r0, #EMC_CFG]
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bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
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str r1, [r0, #EMC_CFG]
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mov r1, #0
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str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
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mov r1, #1
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cmp r10, #TEGRA30
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streq r1, [r0, #EMC_NOP]
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streq r1, [r0, #EMC_NOP]
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emc_device_mask r1, r0
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exit_selfrefresh_loop:
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ldr r2, [r0, #EMC_EMC_STATUS]
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ands r2, r2, r1
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bne exit_selfrefresh_loop
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lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
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mov32 r7, TEGRA_TMRUS_BASE
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ldr r2, [r0, #EMC_FBIO_CFG5]
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and r2, r2, #3 @ check DRAM_TYPE
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cmp r2, #2
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beq emc_lpddr2
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/* Issue a ZQ_CAL for dev0 - DDR3 */
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mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
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str r2, [r0, #EMC_ZQ_CAL]
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ldr r2, [r7]
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add r2, r2, #10
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wait_until r2, r7, r3
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tst r1, #2
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beq zcal_done
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/* Issue a ZQ_CAL for dev1 - DDR3 */
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mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
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str r2, [r0, #EMC_ZQ_CAL]
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ldr r2, [r7]
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add r2, r2, #10
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wait_until r2, r7, r3
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b zcal_done
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emc_lpddr2:
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/* Issue a ZQ_CAL for dev0 - LPDDR2 */
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mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB
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str r2, [r0, #EMC_MRW]
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ldr r2, [r7]
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add r2, r2, #1
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wait_until r2, r7, r3
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tst r1, #2
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beq zcal_done
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/* Issue a ZQ_CAL for dev0 - LPDDR2 */
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mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB
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str r2, [r0, #EMC_MRW]
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ldr r2, [r7]
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add r2, r2, #1
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wait_until r2, r7, r3
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zcal_done:
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mov r1, #0 @ unstall all transactions
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str r1, [r0, #EMC_REQ_CTRL]
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ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
|
str r1, [r0, #EMC_ZCAL_INTERVAL]
|
ldr r1, [r5, #0x0] @ restore EMC_CFG
|
str r1, [r0, #EMC_CFG]
|
|
emc_timing_update r1, r0
|
|
/* Tegra114 had dual EMC channel, now config the other one */
|
cmp r10, #TEGRA114
|
bne __no_dual_emc_chanl
|
mov32 r1, TEGRA_EMC1_BASE
|
cmp r0, r1
|
movne r0, r1
|
addne r5, r5, #0x20
|
bne exit_self_refresh
|
__no_dual_emc_chanl:
|
|
mov32 r0, TEGRA_PMC_BASE
|
ldr r0, [r0, #PMC_SCRATCH41]
|
ret r0 @ jump to tegra_resume
|
ENDPROC(tegra30_lp1_reset)
|
|
.align L1_CACHE_SHIFT
|
tegra30_sdram_pad_address:
|
.word TEGRA_EMC_BASE + EMC_CFG @0x0
|
.word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
|
.word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
|
.word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
|
.word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
|
.word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
|
.word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
|
.word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
|
tegra30_sdram_pad_address_end:
|
|
tegra114_sdram_pad_address:
|
.word TEGRA_EMC0_BASE + EMC_CFG @0x0
|
.word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
|
.word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8
|
.word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc
|
.word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
|
.word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
|
.word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
|
.word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
|
.word TEGRA_EMC1_BASE + EMC_CFG @0x20
|
.word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
|
.word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
|
.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
|
.word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
|
tegra114_sdram_pad_adress_end:
|
|
tegra124_sdram_pad_address:
|
.word TEGRA124_EMC_BASE + EMC_CFG @0x0
|
.word TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
|
.word TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
|
.word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
|
.word TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
|
.word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
|
.word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
|
.word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
|
tegra124_sdram_pad_address_end:
|
|
tegra30_sdram_pad_size:
|
.word tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
|
|
tegra114_sdram_pad_size:
|
.word tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
|
|
.type tegra_sdram_pad_save, %object
|
tegra_sdram_pad_save:
|
.rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
|
.long 0
|
.endr
|
|
/*
|
* tegra30_tear_down_core
|
*
|
* copied into and executed from IRAM
|
* puts memory in self-refresh for LP0 and LP1
|
*/
|
tegra30_tear_down_core:
|
bl tegra30_sdram_self_refresh
|
bl tegra30_switch_cpu_to_clk32k
|
b tegra30_enter_sleep
|
|
/*
|
* tegra30_switch_cpu_to_clk32k
|
*
|
* In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
|
* to the 32KHz clock.
|
* r4 = TEGRA_PMC_BASE
|
* r5 = TEGRA_CLK_RESET_BASE
|
* r6 = TEGRA_FLOW_CTRL_BASE
|
* r7 = TEGRA_TMRUS_BASE
|
* r10= SoC ID
|
*/
|
tegra30_switch_cpu_to_clk32k:
|
/*
|
* start by jumping to CLKM to safely disable PLLs, then jump to
|
* CLKS.
|
*/
|
mov r0, #(1 << 28)
|
str r0, [r5, #CLK_RESET_SCLK_BURST]
|
/* 2uS delay delay between changing SCLK and CCLK */
|
ldr r1, [r7]
|
add r1, r1, #2
|
wait_until r1, r7, r9
|
str r0, [r5, #CLK_RESET_CCLK_BURST]
|
mov r0, #0
|
str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
|
str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
|
|
/* switch the clock source of mselect to be CLK_M */
|
ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
|
orr r0, r0, #MSELECT_CLKM
|
str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
|
|
/* 2uS delay delay between changing SCLK and disabling PLLs */
|
ldr r1, [r7]
|
add r1, r1, #2
|
wait_until r1, r7, r9
|
|
/* disable PLLM via PMC in LP1 */
|
ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
|
bic r0, r0, #(1 << 12)
|
str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
|
|
/* disable PLLP, PLLA, PLLC and PLLX */
|
tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
|
cmp r1, #TEGRA30
|
ldr r0, [r5, #CLK_RESET_PLLP_BASE]
|
orrne r0, r0, #(1 << 31) @ enable PllP bypass on fast cluster
|
bic r0, r0, #(1 << 30)
|
str r0, [r5, #CLK_RESET_PLLP_BASE]
|
beq 1f
|
mov r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
|
str r0, [r5, #CLK_RESET_PLLP_RESHIFT]
|
1:
|
ldr r0, [r5, #CLK_RESET_PLLA_BASE]
|
bic r0, r0, #(1 << 30)
|
str r0, [r5, #CLK_RESET_PLLA_BASE]
|
ldr r0, [r5, #CLK_RESET_PLLC_BASE]
|
bic r0, r0, #(1 << 30)
|
str r0, [r5, #CLK_RESET_PLLC_BASE]
|
ldr r0, [r5, #CLK_RESET_PLLX_BASE]
|
bic r0, r0, #(1 << 30)
|
str r0, [r5, #CLK_RESET_PLLX_BASE]
|
|
cmp r10, #TEGRA30
|
beq _no_pll_in_iddq
|
pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
|
_no_pll_in_iddq:
|
|
/*
|
* Switch to clk_s (32KHz); bits 28:31=0
|
* Enable burst on CPU IRQ; bit 24=1
|
* Set IRQ burst clock source to clk_m; bits 10:8=0
|
*/
|
mov r0, #(1 << 24)
|
str r0, [r5, #CLK_RESET_SCLK_BURST]
|
|
ret lr
|
|
/*
|
* tegra30_enter_sleep
|
*
|
* uses flow controller to enter sleep state
|
* executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
|
* executes from SDRAM with target state is LP2
|
* r6 = TEGRA_FLOW_CTRL_BASE
|
*/
|
tegra30_enter_sleep:
|
cpu_id r1
|
|
cpu_to_csr_reg r2, r1
|
ldr r0, [r6, r2]
|
orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
|
orr r0, r0, #FLOW_CTRL_CSR_ENABLE
|
str r0, [r6, r2]
|
|
tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
|
cmp r10, #TEGRA30
|
mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
|
orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
|
orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
|
|
cpu_to_halt_reg r2, r1
|
str r0, [r6, r2]
|
dsb
|
ldr r0, [r6, r2] /* memory barrier */
|
|
cmp r10, #TEGRA30
|
halted:
|
isb
|
dsb
|
wfine /* CPU should be power gated here */
|
wfeeq
|
|
/* !!!FIXME!!! Implement halt failure handler */
|
b halted
|
|
/*
|
* tegra30_sdram_self_refresh
|
*
|
* called with MMU off and caches disabled
|
* must be executed from IRAM
|
* r4 = TEGRA_PMC_BASE
|
* r5 = TEGRA_CLK_RESET_BASE
|
* r6 = TEGRA_FLOW_CTRL_BASE
|
* r7 = TEGRA_TMRUS_BASE
|
* r10= SoC ID
|
*/
|
tegra30_sdram_self_refresh:
|
|
adr r8, tegra_sdram_pad_save
|
tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
|
cmp r10, #TEGRA30
|
adreq r2, tegra30_sdram_pad_address
|
ldreq r3, tegra30_sdram_pad_size
|
cmp r10, #TEGRA114
|
adreq r2, tegra114_sdram_pad_address
|
ldreq r3, tegra114_sdram_pad_size
|
cmp r10, #TEGRA124
|
adreq r2, tegra124_sdram_pad_address
|
ldreq r3, tegra30_sdram_pad_size
|
|
mov r9, #0
|
|
padsave:
|
ldr r0, [r2, r9] @ r0 is the addr in the pad_address
|
|
ldr r1, [r0]
|
str r1, [r8, r9] @ save the content of the addr
|
|
add r9, r9, #4
|
cmp r3, r9
|
bne padsave
|
padsave_done:
|
|
dsb
|
|
cmp r10, #TEGRA30
|
ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
|
cmp r10, #TEGRA114
|
ldreq r0, =TEGRA_EMC0_BASE
|
cmp r10, #TEGRA124
|
ldreq r0, =TEGRA124_EMC_BASE
|
|
enter_self_refresh:
|
cmp r10, #TEGRA30
|
mov r1, #0
|
str r1, [r0, #EMC_ZCAL_INTERVAL]
|
str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
|
ldr r1, [r0, #EMC_CFG]
|
bic r1, r1, #(1 << 28)
|
bicne r1, r1, #(1 << 29)
|
str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
|
|
emc_timing_update r1, r0
|
|
ldr r1, [r7]
|
add r1, r1, #5
|
wait_until r1, r7, r2
|
|
emc_wait_auto_cal:
|
ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
|
tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
|
bne emc_wait_auto_cal
|
|
mov r1, #3
|
str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
|
|
emcidle:
|
ldr r1, [r0, #EMC_EMC_STATUS]
|
tst r1, #4
|
beq emcidle
|
|
mov r1, #1
|
str r1, [r0, #EMC_SELF_REF]
|
|
emc_device_mask r1, r0
|
|
emcself:
|
ldr r2, [r0, #EMC_EMC_STATUS]
|
and r2, r2, r1
|
cmp r2, r1
|
bne emcself @ loop until DDR in self-refresh
|
|
/* Put VTTGEN in the lowest power mode */
|
ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
|
mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
|
and r1, r1, r2
|
str r1, [r0, #EMC_XM2VTTGENPADCTRL]
|
ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
|
cmp r10, #TEGRA30
|
orreq r1, r1, #7 @ set E_NO_VTTGEN
|
orrne r1, r1, #0x3f
|
str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
|
|
emc_timing_update r1, r0
|
|
/* Tegra114 had dual EMC channel, now config the other one */
|
cmp r10, #TEGRA114
|
bne no_dual_emc_chanl
|
mov32 r1, TEGRA_EMC1_BASE
|
cmp r0, r1
|
movne r0, r1
|
bne enter_self_refresh
|
no_dual_emc_chanl:
|
|
ldr r1, [r4, #PMC_CTRL]
|
tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
|
bne pmc_io_dpd_skip
|
/*
|
* Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
|
* and COMP in the lowest power mode when LP1.
|
*/
|
mov32 r1, 0x8EC00000
|
str r1, [r4, #PMC_IO_DPD_REQ]
|
pmc_io_dpd_skip:
|
|
dsb
|
|
ret lr
|
|
.ltorg
|
/* dummy symbol for end of IRAM */
|
.align L1_CACHE_SHIFT
|
.global tegra30_iram_end
|
tegra30_iram_end:
|
b .
|
#endif
|
