/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Debugging macro include header
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*
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* Copyright (C) 2011 Xilinx
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*/
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#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
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#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
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#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
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#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
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#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
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#define UART0_PHYS 0xE0000000
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#define UART0_VIRT 0xF0800000
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#define UART1_PHYS 0xE0001000
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#define UART1_VIRT 0xF0801000
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#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
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# define LL_UART_PADDR UART1_PHYS
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# define LL_UART_VADDR UART1_VIRT
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#else
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# define LL_UART_PADDR UART0_PHYS
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# define LL_UART_VADDR UART0_VIRT
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#endif
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.macro addruart, rp, rv, tmp
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ldr \rp, =LL_UART_PADDR @ physical
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ldr \rv, =LL_UART_VADDR @ virtual
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.endm
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.macro senduart,rd,rx
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strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
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.endm
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.macro waituartcts,rd,rx
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.endm
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.macro waituarttxrdy,rd,rx
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1001: ldr \rd, [\rx, #UART_SR_OFFSET]
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ARM_BE8( rev \rd, \rd )
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tst \rd, #UART_SR_TXEMPTY
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beq 1001b
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.endm
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.macro busyuart,rd,rx
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1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
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ARM_BE8( rev \rd, \rd )
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tst \rd, #UART_SR_TXFULL @
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bne 1002b @ wait if FIFO is full
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.endm
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