/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
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#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H
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/* DISP_CC clock registers */
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#define DISP_CC_MDSS_AHB_CLK 0
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#define DISP_CC_MDSS_AXI_CLK 1
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#define DISP_CC_MDSS_BYTE0_CLK 2
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 4
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#define DISP_CC_MDSS_BYTE1_CLK 5
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#define DISP_CC_MDSS_BYTE1_CLK_SRC 6
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#define DISP_CC_MDSS_BYTE1_INTF_CLK 7
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#define DISP_CC_MDSS_ESC0_CLK 8
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#define DISP_CC_MDSS_ESC0_CLK_SRC 9
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#define DISP_CC_MDSS_ESC1_CLK 10
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#define DISP_CC_MDSS_ESC1_CLK_SRC 11
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#define DISP_CC_MDSS_MDP_CLK 12
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#define DISP_CC_MDSS_MDP_CLK_SRC 13
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#define DISP_CC_MDSS_MDP_LUT_CLK 14
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#define DISP_CC_MDSS_PCLK0_CLK 15
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 16
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#define DISP_CC_MDSS_PCLK1_CLK 17
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#define DISP_CC_MDSS_PCLK1_CLK_SRC 18
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#define DISP_CC_MDSS_ROT_CLK 19
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#define DISP_CC_MDSS_ROT_CLK_SRC 20
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#define DISP_CC_MDSS_RSCC_AHB_CLK 21
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22
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#define DISP_CC_MDSS_VSYNC_CLK 23
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 24
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#define DISP_CC_PLL0 25
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26
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#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27
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/* DISP_CC Reset */
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#define DISP_CC_MDSS_RSCC_BCR 0
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/* DISP_CC GDSCR */
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#define MDSS_GDSC 0
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#endif
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