// SPDX-License-Identifier: GPL-2.0
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clk/mmp.h>
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#include "addr-map.h"
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#include "common.h"
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#include "clock.h"
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/*
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* APB Clock register offsets for PXA910
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*/
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#define APBC_UART0 APBC_REG(0x000)
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#define APBC_UART1 APBC_REG(0x004)
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#define APBC_GPIO APBC_REG(0x008)
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#define APBC_PWM1 APBC_REG(0x00c)
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#define APBC_PWM2 APBC_REG(0x010)
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#define APBC_PWM3 APBC_REG(0x014)
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#define APBC_PWM4 APBC_REG(0x018)
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#define APBC_SSP1 APBC_REG(0x01c)
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#define APBC_SSP2 APBC_REG(0x020)
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#define APBC_RTC APBC_REG(0x028)
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#define APBC_TWSI0 APBC_REG(0x02c)
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#define APBC_KPC APBC_REG(0x030)
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#define APBC_SSP3 APBC_REG(0x04c)
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#define APBC_TWSI1 APBC_REG(0x06c)
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#define APMU_NAND APMU_REG(0x060)
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#define APMU_USB APMU_REG(0x05c)
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static APBC_CLK(uart1, UART0, 1, 14745600);
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static APBC_CLK(uart2, UART1, 1, 14745600);
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static APBC_CLK(twsi0, TWSI0, 1, 33000000);
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static APBC_CLK(twsi1, TWSI1, 1, 33000000);
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static APBC_CLK(pwm1, PWM1, 1, 13000000);
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static APBC_CLK(pwm2, PWM2, 1, 13000000);
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static APBC_CLK(pwm3, PWM3, 1, 13000000);
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static APBC_CLK(pwm4, PWM4, 1, 13000000);
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static APBC_CLK(gpio, GPIO, 0, 13000000);
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static APBC_CLK(rtc, RTC, 8, 32768);
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static APMU_CLK(nand, NAND, 0x19b, 156000000);
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static APMU_CLK(u2o, USB, 0x1b, 480000000);
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/* device and clock bindings */
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static struct clk_lookup pxa910_clkregs[] = {
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INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
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INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
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INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
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INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
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INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
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INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
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INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL),
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INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
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INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
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};
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void __init pxa910_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
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phys_addr_t apbc_phys, phys_addr_t apbcp_phys)
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{
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clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
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}
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