/* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/if_vlan.h>
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#include <linux/of_net.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#include "mtk_eth_soc.h"
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#include "gsw_mt7620.h"
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#include "mdio.h"
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#define MT7620_CDMA_CSG_CFG 0x400
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#define MT7621_CDMP_IG_CTRL (MT7620_CDMA_CSG_CFG + 0x00)
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#define MT7621_CDMP_EG_CTRL (MT7620_CDMA_CSG_CFG + 0x04)
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#define MT7621_RESET_FE BIT(6)
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#define MT7621_L4_VALID BIT(24)
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#define MT7621_TX_DMA_UDF BIT(19)
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#define CDMA_ICS_EN BIT(2)
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#define CDMA_UCS_EN BIT(1)
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#define CDMA_TCS_EN BIT(0)
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#define GDMA_ICS_EN BIT(22)
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#define GDMA_TCS_EN BIT(21)
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#define GDMA_UCS_EN BIT(20)
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/* frame engine counters */
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#define MT7621_REG_MIB_OFFSET 0x2000
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#define MT7621_PPE_AC_BCNT0 (MT7621_REG_MIB_OFFSET + 0x00)
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#define MT7621_GDM1_TX_GBCNT (MT7621_REG_MIB_OFFSET + 0x400)
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#define MT7621_GDM2_TX_GBCNT (MT7621_GDM1_TX_GBCNT + 0x40)
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#define GSW_REG_GDMA1_MAC_ADRL 0x508
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#define GSW_REG_GDMA1_MAC_ADRH 0x50C
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#define GSW_REG_GDMA2_MAC_ADRL 0x1508
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#define GSW_REG_GDMA2_MAC_ADRH 0x150C
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#define MT7621_MTK_RST_GL 0x04
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#define MT7620_MTK_INT_STATUS2 0x08
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/* MTK_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
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* but after test it should be BIT(13).
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*/
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#define MT7621_MTK_GDM1_AF BIT(28)
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#define MT7621_MTK_GDM2_AF BIT(29)
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static const u16 mt7621_reg_table[MTK_REG_COUNT] = {
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[MTK_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
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[MTK_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
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[MTK_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
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[MTK_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
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[MTK_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
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[MTK_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
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[MTK_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
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[MTK_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
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[MTK_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
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[MTK_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
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[MTK_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
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[MTK_REG_MTK_INT_ENABLE] = RT5350_MTK_INT_ENABLE,
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[MTK_REG_MTK_INT_STATUS] = RT5350_MTK_INT_STATUS,
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[MTK_REG_MTK_DMA_VID_BASE] = 0,
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[MTK_REG_MTK_COUNTER_BASE] = MT7621_GDM1_TX_GBCNT,
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[MTK_REG_MTK_RST_GL] = MT7621_MTK_RST_GL,
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[MTK_REG_MTK_INT_STATUS2] = MT7620_MTK_INT_STATUS2,
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};
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static void mt7621_mtk_reset(struct mtk_eth *eth)
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{
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mtk_reset(eth, MT7621_RESET_FE);
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}
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static int mt7621_fwd_config(struct mtk_eth *eth)
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{
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/* Setup GMAC1 only, there is no support for GMAC2 yet */
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mtk_w32(eth, mtk_r32(eth, MT7620_GDMA1_FWD_CFG) & ~0xffff,
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MT7620_GDMA1_FWD_CFG);
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/* Enable RX checksum */
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mtk_w32(eth, mtk_r32(eth, MT7620_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
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GDMA_TCS_EN | GDMA_UCS_EN),
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MT7620_GDMA1_FWD_CFG);
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/* Enable RX VLan Offloading */
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mtk_w32(eth, 0, MT7621_CDMP_EG_CTRL);
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return 0;
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}
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static void mt7621_set_mac(struct mtk_mac *mac, unsigned char *hwaddr)
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{
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unsigned long flags;
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spin_lock_irqsave(&mac->hw->page_lock, flags);
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if (mac->id == 0) {
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mtk_w32(mac->hw, (hwaddr[0] << 8) | hwaddr[1],
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GSW_REG_GDMA1_MAC_ADRH);
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mtk_w32(mac->hw, (hwaddr[2] << 24) | (hwaddr[3] << 16) |
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(hwaddr[4] << 8) | hwaddr[5],
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GSW_REG_GDMA1_MAC_ADRL);
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}
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if (mac->id == 1) {
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mtk_w32(mac->hw, (hwaddr[0] << 8) | hwaddr[1],
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GSW_REG_GDMA2_MAC_ADRH);
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mtk_w32(mac->hw, (hwaddr[2] << 24) | (hwaddr[3] << 16) |
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(hwaddr[4] << 8) | hwaddr[5],
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GSW_REG_GDMA2_MAC_ADRL);
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}
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spin_unlock_irqrestore(&mac->hw->page_lock, flags);
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}
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static struct mtk_soc_data mt7621_data = {
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.hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
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NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
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NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
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NETIF_F_IPV6_CSUM,
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.dma_type = MTK_PDMA,
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.dma_ring_size = 256,
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.napi_weight = 64,
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.new_stats = 1,
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.padding_64b = 1,
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.rx_2b_offset = 1,
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.rx_sg_dma = 1,
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.has_switch = 1,
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.mac_count = 2,
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.reset_fe = mt7621_mtk_reset,
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.set_mac = mt7621_set_mac,
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.fwd_config = mt7621_fwd_config,
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.switch_init = mtk_gsw_init,
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.reg_table = mt7621_reg_table,
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.pdma_glo_cfg = MTK_PDMA_SIZE_16DWORDS,
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.rx_int = RT5350_RX_DONE_INT,
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.tx_int = RT5350_TX_DONE_INT,
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.status_int = MT7621_MTK_GDM1_AF | MT7621_MTK_GDM2_AF,
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.checksum_bit = MT7621_L4_VALID,
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.has_carrier = mt7620_has_carrier,
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.mdio_read = mt7620_mdio_read,
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.mdio_write = mt7620_mdio_write,
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.mdio_adjust_link = mt7620_mdio_link_adjust,
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};
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const struct of_device_id of_mtk_match[] = {
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{ .compatible = "mediatek,mt7621-eth", .data = &mt7621_data },
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{},
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};
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MODULE_DEVICE_TABLE(of, of_mtk_match);
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