/* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/platform_device.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <ralink_regs.h>
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#include "mtk_eth_soc.h"
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#include "gsw_mt7620.h"
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void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned int reg)
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{
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iowrite32(val, gsw->base + reg);
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}
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EXPORT_SYMBOL_GPL(mtk_switch_w32);
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u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned int reg)
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{
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return ioread32(gsw->base + reg);
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}
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EXPORT_SYMBOL_GPL(mtk_switch_r32);
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static irqreturn_t gsw_interrupt_mt7621(int irq, void *_eth)
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{
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struct mtk_eth *eth = (struct mtk_eth *)_eth;
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struct mt7620_gsw *gsw = (struct mt7620_gsw *)eth->sw_priv;
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u32 reg, i;
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reg = mt7530_mdio_r32(gsw, MT7530_SYS_INT_STS);
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for (i = 0; i < 5; i++) {
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unsigned int link;
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if ((reg & BIT(i)) == 0)
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continue;
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link = mt7530_mdio_r32(gsw, MT7530_PMSR_P(i)) & 0x1;
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if (link == eth->link[i])
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continue;
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eth->link[i] = link;
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if (link)
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netdev_info(*eth->netdev,
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"port %d link up\n", i);
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else
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netdev_info(*eth->netdev,
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"port %d link down\n", i);
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}
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mt7530_mdio_w32(gsw, MT7530_SYS_INT_STS, 0x1f);
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return IRQ_HANDLED;
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}
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static void mt7621_hw_init(struct mtk_eth *eth, struct mt7620_gsw *gsw,
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struct device_node *np)
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{
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u32 i;
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u32 val;
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/* hardware reset the switch */
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mtk_reset(eth, RST_CTRL_MCM);
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mdelay(10);
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/* reduce RGMII2 PAD driving strength */
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rt_sysc_m32(MT7621_MDIO_DRV_MASK, 0, SYSC_PAD_RGMII2_MDIO);
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/* gpio mux - RGMII1=Normal mode */
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rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
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/* set GMAC1 RGMII mode */
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rt_sysc_m32(MT7621_GE1_MODE_MASK, 0, SYSC_REG_CFG1);
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/* enable MDIO to control MT7530 */
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rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
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/* turn off all PHYs */
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for (i = 0; i <= 4; i++) {
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val = _mt7620_mii_read(gsw, i, 0x0);
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val |= BIT(11);
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_mt7620_mii_write(gsw, i, 0x0, val);
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}
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/* reset the switch */
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mt7530_mdio_w32(gsw, MT7530_SYS_CTRL,
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SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
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usleep_range(10, 20);
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if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
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/* GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536 */
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mtk_switch_w32(gsw, MAC_MCR_FIXED_LINK, MTK_MAC_P2_MCR);
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mt7530_mdio_w32(gsw, MT7530_PMCR_P(6), PMCR_FIXED_LINK);
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} else {
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/* GE1, Force 1000M/FD, FC ON, MAX_RX_LENGTH 1536 */
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mtk_switch_w32(gsw, MAC_MCR_FIXED_LINK_FC, MTK_MAC_P1_MCR);
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mt7530_mdio_w32(gsw, MT7530_PMCR_P(6), PMCR_FIXED_LINK_FC);
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}
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/* GE2, Link down */
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mtk_switch_w32(gsw, MAC_MCR_FORCE_MODE, MTK_MAC_P2_MCR);
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/* Enable Port 6, P5 as GMAC5, P5 disable */
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val = mt7530_mdio_r32(gsw, MT7530_MHWTRAP);
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/* Enable Port 6 */
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val &= ~MHWTRAP_P6_DIS;
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/* Disable Port 5 */
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val |= MHWTRAP_P5_DIS;
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/* manual override of HW-Trap */
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val |= MHWTRAP_MANUAL;
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mt7530_mdio_w32(gsw, MT7530_MHWTRAP, val);
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val = rt_sysc_r32(SYSC_REG_CFG);
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val = (val >> MT7621_XTAL_SHIFT) & MT7621_XTAL_MASK;
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if (val < MT7621_XTAL_25 && val >= MT7621_XTAL_40) {
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/* 40Mhz */
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/* disable MT7530 core clock */
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_mt7620_mii_write(gsw, 0, 13, 0x1f);
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_mt7620_mii_write(gsw, 0, 14, 0x410);
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_mt7620_mii_write(gsw, 0, 13, 0x401f);
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_mt7620_mii_write(gsw, 0, 14, 0x0);
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/* disable MT7530 PLL */
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_mt7620_mii_write(gsw, 0, 13, 0x1f);
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_mt7620_mii_write(gsw, 0, 14, 0x40d);
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_mt7620_mii_write(gsw, 0, 13, 0x401f);
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_mt7620_mii_write(gsw, 0, 14, 0x2020);
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/* for MT7530 core clock = 500Mhz */
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_mt7620_mii_write(gsw, 0, 13, 0x1f);
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_mt7620_mii_write(gsw, 0, 14, 0x40e);
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_mt7620_mii_write(gsw, 0, 13, 0x401f);
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_mt7620_mii_write(gsw, 0, 14, 0x119);
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/* enable MT7530 PLL */
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_mt7620_mii_write(gsw, 0, 13, 0x1f);
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_mt7620_mii_write(gsw, 0, 14, 0x40d);
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_mt7620_mii_write(gsw, 0, 13, 0x401f);
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_mt7620_mii_write(gsw, 0, 14, 0x2820);
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usleep_range(20, 40);
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/* enable MT7530 core clock */
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_mt7620_mii_write(gsw, 0, 13, 0x1f);
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_mt7620_mii_write(gsw, 0, 14, 0x410);
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_mt7620_mii_write(gsw, 0, 13, 0x401f);
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}
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/* RGMII */
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_mt7620_mii_write(gsw, 0, 14, 0x1);
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/* set MT7530 central align */
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mt7530_mdio_m32(gsw, BIT(0), P6ECR_INTF_MODE_RGMII, MT7530_P6ECR);
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mt7530_mdio_m32(gsw, TRGMII_TXCTRL_TXC_INV, 0,
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MT7530_TRGMII_TXCTRL);
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mt7530_mdio_w32(gsw, MT7530_TRGMII_TCK_CTRL, 0x855);
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/* delay setting for 10/1000M */
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mt7530_mdio_w32(gsw, MT7530_P5RGMIIRXCR,
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P5RGMIIRXCR_C_ALIGN | P5RGMIIRXCR_DELAY_2);
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mt7530_mdio_w32(gsw, MT7530_P5RGMIITXCR, 0x14);
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/* lower Tx Driving*/
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mt7530_mdio_w32(gsw, MT7530_TRGMII_TD0_ODT, 0x44);
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mt7530_mdio_w32(gsw, MT7530_TRGMII_TD1_ODT, 0x44);
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mt7530_mdio_w32(gsw, MT7530_TRGMII_TD2_ODT, 0x44);
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mt7530_mdio_w32(gsw, MT7530_TRGMII_TD3_ODT, 0x44);
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mt7530_mdio_w32(gsw, MT7530_TRGMII_TD4_ODT, 0x44);
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mt7530_mdio_w32(gsw, MT7530_TRGMII_TD5_ODT, 0x44);
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/* turn on all PHYs */
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for (i = 0; i <= 4; i++) {
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val = _mt7620_mii_read(gsw, i, 0);
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val &= ~BIT(11);
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_mt7620_mii_write(gsw, i, 0, val);
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}
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#define MT7530_NUM_PORTS 8
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#define REG_ESW_PORT_PCR(x) (0x2004 | ((x) << 8))
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#define REG_ESW_PORT_PVC(x) (0x2010 | ((x) << 8))
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#define REG_ESW_PORT_PPBV1(x) (0x2014 | ((x) << 8))
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#define MT7530_CPU_PORT 6
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/* This is copied from mt7530_apply_config in libreCMC driver */
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{
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int i;
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for (i = 0; i < MT7530_NUM_PORTS; i++)
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mt7530_mdio_w32(gsw, REG_ESW_PORT_PCR(i), 0x00400000);
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mt7530_mdio_w32(gsw, REG_ESW_PORT_PCR(MT7530_CPU_PORT),
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0x00ff0000);
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for (i = 0; i < MT7530_NUM_PORTS; i++)
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mt7530_mdio_w32(gsw, REG_ESW_PORT_PVC(i), 0x810000c0);
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}
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/* enable irq */
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mt7530_mdio_m32(gsw, 0, 3 << 16, MT7530_TOP_SIG_CTRL);
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mt7530_mdio_w32(gsw, MT7530_SYS_INT_EN, 0x1f);
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}
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static const struct of_device_id mediatek_gsw_match[] = {
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{ .compatible = "mediatek,mt7621-gsw" },
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{},
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};
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MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
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int mtk_gsw_init(struct mtk_eth *eth)
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{
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struct device_node *np = eth->switch_np;
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struct platform_device *pdev = of_find_device_by_node(np);
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struct mt7620_gsw *gsw;
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if (!pdev)
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return -ENODEV;
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if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
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return -EINVAL;
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gsw = platform_get_drvdata(pdev);
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eth->sw_priv = gsw;
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if (!gsw->irq)
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return -EINVAL;
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request_irq(gsw->irq, gsw_interrupt_mt7621, 0,
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"gsw", eth);
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disable_irq(gsw->irq);
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mt7621_hw_init(eth, gsw, np);
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enable_irq(gsw->irq);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mtk_gsw_init);
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static int mt7621_gsw_probe(struct platform_device *pdev)
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{
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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struct mt7620_gsw *gsw;
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gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
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if (!gsw)
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return -ENOMEM;
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gsw->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(gsw->base))
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return PTR_ERR(gsw->base);
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gsw->dev = &pdev->dev;
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gsw->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
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platform_set_drvdata(pdev, gsw);
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return 0;
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}
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static int mt7621_gsw_remove(struct platform_device *pdev)
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{
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver gsw_driver = {
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.probe = mt7621_gsw_probe,
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.remove = mt7621_gsw_remove,
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.driver = {
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.name = "mt7621-gsw",
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.owner = THIS_MODULE,
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.of_match_table = mediatek_gsw_match,
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},
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};
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module_platform_driver(gsw_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
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MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7621 SoC");
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