// SPDX-License-Identifier: GPL-2.0
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2010 Realtek Corporation. All rights reserved.
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*
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* Modifications for inclusion into the Linux staging tree are
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* Copyright(c) 2010 Larry Finger. All rights reserved.
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*
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* Contact information:
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* WLAN FAE <wlanfae@realtek.com>
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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******************************************************************************/
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#define _RTL871X_MP_C_
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#include "osdep_service.h"
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#include "drv_types.h"
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#include "rtl871x_mp_phy_regdef.h"
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#include "rtl8712_cmd.h"
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static void _init_mp_priv_(struct mp_priv *pmp_priv)
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{
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pmp_priv->mode = _LOOPBOOK_MODE_;
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pmp_priv->curr_ch = 1;
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pmp_priv->curr_modem = MIXED_PHY;
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pmp_priv->curr_rateidx = 0;
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pmp_priv->curr_txpoweridx = 0x14;
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pmp_priv->antenna_tx = ANTENNA_A;
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pmp_priv->antenna_rx = ANTENNA_AB;
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pmp_priv->check_mp_pkt = 0;
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pmp_priv->tx_pktcount = 0;
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pmp_priv->rx_pktcount = 0;
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pmp_priv->rx_crcerrpktcount = 0;
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}
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static int init_mp_priv(struct mp_priv *pmp_priv)
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{
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int i;
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struct mp_xmit_frame *pmp_xmitframe;
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_init_mp_priv_(pmp_priv);
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_init_queue(&pmp_priv->free_mp_xmitqueue);
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pmp_priv->pallocated_mp_xmitframe_buf = NULL;
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pmp_priv->pallocated_mp_xmitframe_buf = kmalloc(NR_MP_XMITFRAME *
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sizeof(struct mp_xmit_frame) + 4,
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GFP_ATOMIC);
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if (!pmp_priv->pallocated_mp_xmitframe_buf)
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return -ENOMEM;
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pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf +
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4 -
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((addr_t)(pmp_priv->pallocated_mp_xmitframe_buf) & 3);
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pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf;
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for (i = 0; i < NR_MP_XMITFRAME; i++) {
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INIT_LIST_HEAD(&(pmp_xmitframe->list));
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list_add_tail(&(pmp_xmitframe->list),
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&(pmp_priv->free_mp_xmitqueue.queue));
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pmp_xmitframe->pkt = NULL;
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pmp_xmitframe->frame_tag = MP_FRAMETAG;
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pmp_xmitframe->padapter = pmp_priv->papdater;
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pmp_xmitframe++;
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}
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pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
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return 0;
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}
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static int free_mp_priv(struct mp_priv *pmp_priv)
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{
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kfree(pmp_priv->pallocated_mp_xmitframe_buf);
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return 0;
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}
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void mp871xinit(struct _adapter *padapter)
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{
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struct mp_priv *pmppriv = &padapter->mppriv;
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pmppriv->papdater = padapter;
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init_mp_priv(pmppriv);
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}
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void mp871xdeinit(struct _adapter *padapter)
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{
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struct mp_priv *pmppriv = &padapter->mppriv;
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free_mp_priv(pmppriv);
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}
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/*
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* Special for bb and rf reg read/write
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*/
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static u32 fw_iocmd_read(struct _adapter *pAdapter, struct IOCMD_STRUCT iocmd)
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{
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u32 cmd32 = 0, val32 = 0;
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u8 iocmd_class = iocmd.cmdclass;
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u16 iocmd_value = iocmd.value;
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u8 iocmd_idx = iocmd.index;
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cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
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if (r8712_fw_cmd(pAdapter, cmd32))
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r8712_fw_cmd_data(pAdapter, &val32, 1);
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else
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val32 = 0;
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return val32;
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}
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static u8 fw_iocmd_write(struct _adapter *pAdapter,
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struct IOCMD_STRUCT iocmd, u32 value)
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{
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u32 cmd32 = 0;
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u8 iocmd_class = iocmd.cmdclass;
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u32 iocmd_value = iocmd.value;
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u8 iocmd_idx = iocmd.index;
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r8712_fw_cmd_data(pAdapter, &value, 0);
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msleep(100);
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cmd32 = (iocmd_class << 24) | (iocmd_value << 8) | iocmd_idx;
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return r8712_fw_cmd(pAdapter, cmd32);
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}
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/* offset : 0X800~0XFFF */
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u32 r8712_bb_reg_read(struct _adapter *pAdapter, u16 offset)
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{
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u8 shift = offset & 0x0003; /* 4 byte access */
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u16 bb_addr = offset & 0x0FFC; /* 4 byte access */
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u32 bb_val = 0;
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struct IOCMD_STRUCT iocmd;
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iocmd.cmdclass = IOCMD_CLASS_BB_RF;
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iocmd.value = bb_addr;
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iocmd.index = IOCMD_BB_READ_IDX;
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bb_val = fw_iocmd_read(pAdapter, iocmd);
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if (shift != 0) {
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u32 bb_val2 = 0;
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bb_val >>= (shift * 8);
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iocmd.value += 4;
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bb_val2 = fw_iocmd_read(pAdapter, iocmd);
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bb_val2 <<= ((4 - shift) * 8);
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bb_val |= bb_val2;
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}
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return bb_val;
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}
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/* offset : 0X800~0XFFF */
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u8 r8712_bb_reg_write(struct _adapter *pAdapter, u16 offset, u32 value)
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{
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u8 shift = offset & 0x0003; /* 4 byte access */
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u16 bb_addr = offset & 0x0FFC; /* 4 byte access */
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struct IOCMD_STRUCT iocmd;
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iocmd.cmdclass = IOCMD_CLASS_BB_RF;
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iocmd.value = bb_addr;
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iocmd.index = IOCMD_BB_WRITE_IDX;
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if (shift != 0) {
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u32 oldValue = 0;
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u32 newValue = value;
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oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
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oldValue &= (0xFFFFFFFF >> ((4 - shift) * 8));
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value = oldValue | (newValue << (shift * 8));
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if (!fw_iocmd_write(pAdapter, iocmd, value))
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return false;
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iocmd.value += 4;
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oldValue = r8712_bb_reg_read(pAdapter, iocmd.value);
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oldValue &= (0xFFFFFFFF << (shift * 8));
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value = oldValue | (newValue >> ((4 - shift) * 8));
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}
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return fw_iocmd_write(pAdapter, iocmd, value);
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}
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/* offset : 0x00 ~ 0xFF */
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u32 r8712_rf_reg_read(struct _adapter *pAdapter, u8 path, u8 offset)
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{
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u16 rf_addr = (path << 8) | offset;
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struct IOCMD_STRUCT iocmd;
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iocmd.cmdclass = IOCMD_CLASS_BB_RF;
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iocmd.value = rf_addr;
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iocmd.index = IOCMD_RF_READ_IDX;
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return fw_iocmd_read(pAdapter, iocmd);
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}
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u8 r8712_rf_reg_write(struct _adapter *pAdapter, u8 path, u8 offset, u32 value)
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{
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u16 rf_addr = (path << 8) | offset;
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struct IOCMD_STRUCT iocmd;
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iocmd.cmdclass = IOCMD_CLASS_BB_RF;
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iocmd.value = rf_addr;
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iocmd.index = IOCMD_RF_WRIT_IDX;
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return fw_iocmd_write(pAdapter, iocmd, value);
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}
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static u32 bitshift(u32 bitmask)
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{
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u32 i;
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for (i = 0; i <= 31; i++)
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if (((bitmask >> i) & 0x1) == 1)
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break;
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return i;
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}
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static u32 get_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask)
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{
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u32 org_value, bit_shift;
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org_value = r8712_bb_reg_read(pAdapter, offset);
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bit_shift = bitshift(bitmask);
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return (org_value & bitmask) >> bit_shift;
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}
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static u8 set_bb_reg(struct _adapter *pAdapter,
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u16 offset,
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u32 bitmask,
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u32 value)
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{
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u32 org_value, bit_shift, new_value;
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if (bitmask != bMaskDWord) {
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org_value = r8712_bb_reg_read(pAdapter, offset);
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bit_shift = bitshift(bitmask);
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new_value = (org_value & (~bitmask)) | (value << bit_shift);
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} else {
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new_value = value;
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}
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return r8712_bb_reg_write(pAdapter, offset, new_value);
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}
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static u32 get_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset,
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u32 bitmask)
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{
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u32 org_value, bit_shift;
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org_value = r8712_rf_reg_read(pAdapter, path, offset);
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bit_shift = bitshift(bitmask);
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return (org_value & bitmask) >> bit_shift;
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}
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static u8 set_rf_reg(struct _adapter *pAdapter, u8 path, u8 offset, u32 bitmask,
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u32 value)
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{
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u32 org_value, bit_shift, new_value;
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if (bitmask != bMaskDWord) {
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org_value = r8712_rf_reg_read(pAdapter, path, offset);
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bit_shift = bitshift(bitmask);
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new_value = (org_value & (~bitmask)) | (value << bit_shift);
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} else {
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new_value = value;
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}
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return r8712_rf_reg_write(pAdapter, path, offset, new_value);
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}
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/*
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* SetChannel
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* Description
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* Use H2C command to change channel,
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* not only modify rf register, but also other setting need to be done.
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*/
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void r8712_SetChannel(struct _adapter *pAdapter)
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{
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struct cmd_priv *pcmdpriv = &pAdapter->cmdpriv;
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struct cmd_obj *pcmd = NULL;
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struct SetChannel_parm *pparm = NULL;
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u16 code = GEN_CMD_CODE(_SetChannel);
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pcmd = kmalloc(sizeof(*pcmd), GFP_ATOMIC);
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if (!pcmd)
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return;
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pparm = kmalloc(sizeof(*pparm), GFP_ATOMIC);
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if (!pparm) {
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kfree(pcmd);
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return;
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}
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pparm->curr_ch = pAdapter->mppriv.curr_ch;
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init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code);
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r8712_enqueue_cmd(pcmdpriv, pcmd);
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}
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static void SetCCKTxPower(struct _adapter *pAdapter, u8 TxPower)
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{
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u16 TxAGC = 0;
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TxAGC = TxPower;
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set_bb_reg(pAdapter, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
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}
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static void SetOFDMTxPower(struct _adapter *pAdapter, u8 TxPower)
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{
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u32 TxAGC = 0;
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TxAGC |= ((TxPower << 24) | (TxPower << 16) | (TxPower << 8) |
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TxPower);
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set_bb_reg(pAdapter, rTxAGC_Rate18_06, bTxAGCRate18_06, TxAGC);
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set_bb_reg(pAdapter, rTxAGC_Rate54_24, bTxAGCRate54_24, TxAGC);
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set_bb_reg(pAdapter, rTxAGC_Mcs03_Mcs00, bTxAGCRateMCS3_MCS0, TxAGC);
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set_bb_reg(pAdapter, rTxAGC_Mcs07_Mcs04, bTxAGCRateMCS7_MCS4, TxAGC);
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set_bb_reg(pAdapter, rTxAGC_Mcs11_Mcs08, bTxAGCRateMCS11_MCS8, TxAGC);
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set_bb_reg(pAdapter, rTxAGC_Mcs15_Mcs12, bTxAGCRateMCS15_MCS12, TxAGC);
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}
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void r8712_SetTxPower(struct _adapter *pAdapter)
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{
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u8 TxPower = pAdapter->mppriv.curr_txpoweridx;
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SetCCKTxPower(pAdapter, TxPower);
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SetOFDMTxPower(pAdapter, TxPower);
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}
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void r8712_SetTxAGCOffset(struct _adapter *pAdapter, u32 ulTxAGCOffset)
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{
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u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
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TxAGCOffset_B = ulTxAGCOffset & 0x000000ff;
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TxAGCOffset_C = (ulTxAGCOffset & 0x0000ff00) >> 8;
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TxAGCOffset_D = (ulTxAGCOffset & 0x00ff0000) >> 16;
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tmpAGC = TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B;
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set_bb_reg(pAdapter, rFPGA0_TxGainStage,
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(bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
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}
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void r8712_SetDataRate(struct _adapter *pAdapter)
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{
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u8 path = RF_PATH_A;
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u8 offset = RF_SYN_G2;
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u32 value;
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value = (pAdapter->mppriv.curr_rateidx < 4) ? 0x4440 : 0xF200;
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r8712_rf_reg_write(pAdapter, path, offset, value);
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}
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void r8712_SwitchBandwidth(struct _adapter *pAdapter)
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{
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/* 3 1.Set MAC register : BWOPMODE bit2:1 20MhzBW */
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u8 regBwOpMode = 0;
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u8 Bandwidth = pAdapter->mppriv.curr_bandwidth;
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regBwOpMode = r8712_read8(pAdapter, 0x10250203);
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if (Bandwidth == HT_CHANNEL_WIDTH_20)
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regBwOpMode |= BIT(2);
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else
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regBwOpMode &= ~(BIT(2));
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r8712_write8(pAdapter, 0x10250203, regBwOpMode);
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/* 3 2.Set PHY related register */
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switch (Bandwidth) {
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/* 20 MHz channel*/
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case HT_CHANNEL_WIDTH_20:
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set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0);
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set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x0);
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/* Use PHY_REG.txt default value. Do not need to change.
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* Correct the tx power for CCK rate in 40M.
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* It is set in Tx descriptor for 8192x series
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*/
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set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x58);
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break;
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/* 40 MHz channel*/
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case HT_CHANNEL_WIDTH_40:
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set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1);
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set_bb_reg(pAdapter, rFPGA1_RFMOD, bRFMOD, 0x1);
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/* Use PHY_REG.txt default value. Do not need to change.
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* Correct the tx power for CCK rate in 40M.
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* Set Control channel to upper or lower. These settings are
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* required only for 40MHz
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*/
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set_bb_reg(pAdapter, rCCK0_System, bCCKSideBand,
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(HAL_PRIME_CHNL_OFFSET_DONT_CARE >> 1));
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set_bb_reg(pAdapter, rOFDM1_LSTF, 0xC00,
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HAL_PRIME_CHNL_OFFSET_DONT_CARE);
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set_bb_reg(pAdapter, rFPGA0_AnalogParameter2, bMaskDWord, 0x18);
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break;
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default:
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break;
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}
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/* 3 3.Set RF related register */
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switch (Bandwidth) {
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case HT_CHANNEL_WIDTH_20:
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set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
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BIT(10) | BIT(11), 0x01);
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break;
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case HT_CHANNEL_WIDTH_40:
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set_rf_reg(pAdapter, RF_PATH_A, RF_CHNLBW,
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BIT(10) | BIT(11), 0x00);
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break;
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default:
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break;
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}
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}
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/*------------------------------Define structure----------------------------*/
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struct R_ANTENNA_SELECT_OFDM {
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u32 r_tx_antenna:4;
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u32 r_ant_l:4;
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u32 r_ant_non_ht:4;
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u32 r_ant_ht1:4;
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u32 r_ant_ht2:4;
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u32 r_ant_ht_s1:4;
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u32 r_ant_non_ht_s1:4;
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u32 OFDM_TXSC:2;
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u32 Reserved:2;
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};
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struct R_ANTENNA_SELECT_CCK {
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u8 r_cckrx_enable_2:2;
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u8 r_cckrx_enable:2;
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u8 r_ccktx_enable:4;
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};
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void r8712_SwitchAntenna(struct _adapter *pAdapter)
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{
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u32 ofdm_tx_en_val = 0, ofdm_tx_ant_sel_val = 0;
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u8 ofdm_rx_ant_sel_val = 0;
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u8 cck_ant_select_val = 0;
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u32 cck_ant_sel_val = 0;
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struct R_ANTENNA_SELECT_CCK *p_cck_txrx;
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p_cck_txrx = (struct R_ANTENNA_SELECT_CCK *)&cck_ant_select_val;
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switch (pAdapter->mppriv.antenna_tx) {
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case ANTENNA_A:
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/* From SD3 Willis suggestion !!! Set RF A=TX and B as standby*/
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set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
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set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1);
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ofdm_tx_en_val = 0x3;
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ofdm_tx_ant_sel_val = 0x11111111;/* Power save */
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p_cck_txrx->r_ccktx_enable = 0x8;
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break;
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case ANTENNA_B:
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set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1);
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set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
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ofdm_tx_en_val = 0x3;
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ofdm_tx_ant_sel_val = 0x22222222;/* Power save */
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p_cck_txrx->r_ccktx_enable = 0x4;
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break;
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case ANTENNA_AB: /* For 8192S */
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set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2);
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set_bb_reg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2);
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ofdm_tx_en_val = 0x3;
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ofdm_tx_ant_sel_val = 0x3321333; /* Disable Power save */
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p_cck_txrx->r_ccktx_enable = 0xC;
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break;
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default:
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break;
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}
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/*OFDM Tx*/
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set_bb_reg(pAdapter, rFPGA1_TxInfo, 0xffffffff, ofdm_tx_ant_sel_val);
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/*OFDM Tx*/
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set_bb_reg(pAdapter, rFPGA0_TxInfo, 0x0000000f, ofdm_tx_en_val);
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switch (pAdapter->mppriv.antenna_rx) {
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case ANTENNA_A:
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ofdm_rx_ant_sel_val = 0x1; /* A */
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p_cck_txrx->r_cckrx_enable = 0x0; /* default: A */
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p_cck_txrx->r_cckrx_enable_2 = 0x0; /* option: A */
|
break;
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case ANTENNA_B:
|
ofdm_rx_ant_sel_val = 0x2; /* B */
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p_cck_txrx->r_cckrx_enable = 0x1; /* default: B */
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p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option: B */
|
break;
|
case ANTENNA_AB:
|
ofdm_rx_ant_sel_val = 0x3; /* AB */
|
p_cck_txrx->r_cckrx_enable = 0x0; /* default:A */
|
p_cck_txrx->r_cckrx_enable_2 = 0x1; /* option:B */
|
break;
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default:
|
break;
|
}
|
/*OFDM Rx*/
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set_bb_reg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f,
|
ofdm_rx_ant_sel_val);
|
/*OFDM Rx*/
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set_bb_reg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f,
|
ofdm_rx_ant_sel_val);
|
|
cck_ant_sel_val = cck_ant_select_val;
|
/*CCK TxRx*/
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set_bb_reg(pAdapter, rCCK0_AFESetting, bMaskByte3, cck_ant_sel_val);
|
}
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|
static void TriggerRFThermalMeter(struct _adapter *pAdapter)
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{
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/* 0x24: RF Reg[6:5] */
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set_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
|
}
|
|
static u32 ReadRFThermalMeter(struct _adapter *pAdapter)
|
{
|
/* 0x24: RF Reg[4:0] */
|
return get_rf_reg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F);
|
}
|
|
void r8712_GetThermalMeter(struct _adapter *pAdapter, u32 *value)
|
{
|
TriggerRFThermalMeter(pAdapter);
|
msleep(1000);
|
*value = ReadRFThermalMeter(pAdapter);
|
}
|
|
void r8712_SetSingleCarrierTx(struct _adapter *pAdapter, u8 bStart)
|
{
|
if (bStart) { /* Start Single Carrier. */
|
/* 1. if OFDM block on? */
|
if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn))
|
/*set OFDM block on*/
|
set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
|
/* 2. set CCK test mode off, set to CCK normal mode */
|
set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
|
/* 3. turn on scramble setting */
|
set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
|
/* 4. Turn On Single Carrier Tx and off the other test modes. */
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable);
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
} else { /* Stop Single Carrier.*/
|
/* Turn off all test modes.*/
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
|
bDisable);
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
msleep(20);
|
/*BB Reset*/
|
set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
}
|
}
|
|
void r8712_SetSingleToneTx(struct _adapter *pAdapter, u8 bStart)
|
{
|
u8 rfPath;
|
|
switch (pAdapter->mppriv.antenna_tx) {
|
case ANTENNA_B:
|
rfPath = RF_PATH_B;
|
break;
|
case ANTENNA_A:
|
default:
|
rfPath = RF_PATH_A;
|
break;
|
}
|
if (bStart) { /* Start Single Tone.*/
|
set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable);
|
set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable);
|
set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
|
0xd4000);
|
msleep(100);
|
/* PAD all on.*/
|
set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x2001f);
|
msleep(100);
|
} else { /* Stop Single Tone.*/
|
set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
|
set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
|
set_rf_reg(pAdapter, rfPath, RF_TX_G2, bRFRegOffsetMask,
|
0x54000);
|
msleep(100);
|
/* PAD all on.*/
|
set_rf_reg(pAdapter, rfPath, RF_AC, bRFRegOffsetMask, 0x30000);
|
msleep(100);
|
}
|
}
|
|
void r8712_SetCarrierSuppressionTx(struct _adapter *pAdapter, u8 bStart)
|
{
|
if (bStart) { /* Start Carrier Suppression.*/
|
if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
|
/* 1. if CCK block on? */
|
if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
|
/*set CCK block on*/
|
set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn,
|
bEnable);
|
}
|
/* Turn Off All Test Mode */
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx,
|
bDisable);
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
|
bDisable);
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone,
|
bDisable);
|
/*transmit mode*/
|
set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
|
/*turn off scramble setting*/
|
set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
|
bDisable);
|
/*Set CCK Tx Test Rate*/
|
/*Set FTxRate to 1Mbps*/
|
set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, 0x0);
|
}
|
} else { /* Stop Carrier Suppression. */
|
if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M) {
|
/*normal mode*/
|
set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
|
/*turn on scramble setting*/
|
set_bb_reg(pAdapter, rCCK0_System, bCCKScramble,
|
bEnable);
|
/*BB Reset*/
|
set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
}
|
}
|
}
|
|
static void SetCCKContinuousTx(struct _adapter *pAdapter, u8 bStart)
|
{
|
u32 cckrate;
|
|
if (bStart) {
|
/* 1. if CCK block on? */
|
if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) {
|
/*set CCK block on*/
|
set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);
|
}
|
/* Turn Off All Test Mode */
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
/*Set CCK Tx Test Rate*/
|
cckrate = pAdapter->mppriv.curr_rateidx;
|
set_bb_reg(pAdapter, rCCK0_System, bCCKTxRate, cckrate);
|
/*transmit mode*/
|
set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x2);
|
/*turn on scramble setting*/
|
set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
|
} else {
|
/*normal mode*/
|
set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, 0x0);
|
/*turn on scramble setting*/
|
set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
|
/*BB Reset*/
|
set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
}
|
} /* mpt_StartCckContTx */
|
|
static void SetOFDMContinuousTx(struct _adapter *pAdapter, u8 bStart)
|
{
|
if (bStart) {
|
/* 1. if OFDM block on? */
|
if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) {
|
/*set OFDM block on*/
|
set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);
|
}
|
/* 2. set CCK test mode off, set to CCK normal mode*/
|
set_bb_reg(pAdapter, rCCK0_System, bCCKBBMode, bDisable);
|
/* 3. turn on scramble setting */
|
set_bb_reg(pAdapter, rCCK0_System, bCCKScramble, bEnable);
|
/* 4. Turn On Continue Tx and turn off the other test modes.*/
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable);
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable);
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
} else {
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable);
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier,
|
bDisable);
|
set_bb_reg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable);
|
msleep(20);
|
/*BB Reset*/
|
set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x0);
|
set_bb_reg(pAdapter, rPMAC_Reset, bBBResetB, 0x1);
|
}
|
} /* mpt_StartOfdmContTx */
|
|
void r8712_SetContinuousTx(struct _adapter *pAdapter, u8 bStart)
|
{
|
/* ADC turn off [bit24-21] adc port0 ~ port1 */
|
if (bStart) {
|
r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
|
r8712_bb_reg_read(pAdapter,
|
rRx_Wait_CCCA) & 0xFE1FFFFF);
|
msleep(100);
|
}
|
if (pAdapter->mppriv.curr_rateidx <= MPT_RATE_11M)
|
SetCCKContinuousTx(pAdapter, bStart);
|
else if ((pAdapter->mppriv.curr_rateidx >= MPT_RATE_6M) &&
|
(pAdapter->mppriv.curr_rateidx <= MPT_RATE_MCS15))
|
SetOFDMContinuousTx(pAdapter, bStart);
|
/* ADC turn on [bit24-21] adc port0 ~ port1 */
|
if (!bStart)
|
r8712_bb_reg_write(pAdapter, rRx_Wait_CCCA,
|
r8712_bb_reg_read(pAdapter,
|
rRx_Wait_CCCA) | 0x01E00000);
|
}
|
|
void r8712_ResetPhyRxPktCount(struct _adapter *pAdapter)
|
{
|
u32 i, phyrx_set = 0;
|
|
for (i = OFDM_PPDU_BIT; i <= HT_MPDU_FAIL_BIT; i++) {
|
phyrx_set = 0;
|
phyrx_set |= (i << 28); /*select*/
|
phyrx_set |= 0x08000000; /* set counter to zero*/
|
r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
|
}
|
}
|
|
static u32 GetPhyRxPktCounts(struct _adapter *pAdapter, u32 selbit)
|
{
|
/*selection*/
|
u32 phyrx_set = 0;
|
u32 SelectBit;
|
|
SelectBit = selbit << 28;
|
phyrx_set |= (SelectBit & 0xF0000000);
|
r8712_write32(pAdapter, RXERR_RPT, phyrx_set);
|
/*Read packet count*/
|
return r8712_read32(pAdapter, RXERR_RPT) & RPTMaxCount;
|
}
|
|
u32 r8712_GetPhyRxPktReceived(struct _adapter *pAdapter)
|
{
|
u32 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_OK_BIT);
|
u32 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_OK_BIT);
|
u32 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_OK_BIT);
|
|
return OFDM_cnt + CCK_cnt + HT_cnt;
|
}
|
|
u32 r8712_GetPhyRxPktCRC32Error(struct _adapter *pAdapter)
|
{
|
u32 OFDM_cnt = GetPhyRxPktCounts(pAdapter, OFDM_MPDU_FAIL_BIT);
|
u32 CCK_cnt = GetPhyRxPktCounts(pAdapter, CCK_MPDU_FAIL_BIT);
|
u32 HT_cnt = GetPhyRxPktCounts(pAdapter, HT_MPDU_FAIL_BIT);
|
|
return OFDM_cnt + CCK_cnt + HT_cnt;
|
}
|
