// SPDX-License-Identifier: GPL-2.0-only
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/*
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* An I2C and SPI driver for the NXP PCF2127/29 RTC
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* Copyright 2013 Til-Technologies
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*
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* Author: Renaud Cerrato <r.cerrato@til-technologies.fr>
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*
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* Watchdog and tamper functions
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* Author: Bruno Thomsen <bruno.thomsen@gmail.com>
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*
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* based on the other drivers in this same directory.
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*
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* Datasheet: http://cache.nxp.com/documents/data_sheet/PCF2127.pdf
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*/
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#include <linux/i2c.h>
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#include <linux/spi/spi.h>
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#include <linux/bcd.h>
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#include <linux/rtc.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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#include <linux/watchdog.h>
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/* Control register 1 */
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#define PCF2127_REG_CTRL1 0x00
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#define PCF2127_BIT_CTRL1_TSF1 BIT(4)
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/* Control register 2 */
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#define PCF2127_REG_CTRL2 0x01
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#define PCF2127_BIT_CTRL2_AIE BIT(1)
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#define PCF2127_BIT_CTRL2_TSIE BIT(2)
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#define PCF2127_BIT_CTRL2_AF BIT(4)
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#define PCF2127_BIT_CTRL2_TSF2 BIT(5)
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#define PCF2127_BIT_CTRL2_WDTF BIT(6)
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/* Control register 3 */
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#define PCF2127_REG_CTRL3 0x02
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#define PCF2127_BIT_CTRL3_BLIE BIT(0)
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#define PCF2127_BIT_CTRL3_BIE BIT(1)
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#define PCF2127_BIT_CTRL3_BLF BIT(2)
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#define PCF2127_BIT_CTRL3_BF BIT(3)
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#define PCF2127_BIT_CTRL3_BTSE BIT(4)
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/* Time and date registers */
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#define PCF2127_REG_SC 0x03
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#define PCF2127_BIT_SC_OSF BIT(7)
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#define PCF2127_REG_MN 0x04
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#define PCF2127_REG_HR 0x05
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#define PCF2127_REG_DM 0x06
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#define PCF2127_REG_DW 0x07
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#define PCF2127_REG_MO 0x08
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#define PCF2127_REG_YR 0x09
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/* Alarm registers */
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#define PCF2127_REG_ALARM_SC 0x0A
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#define PCF2127_REG_ALARM_MN 0x0B
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#define PCF2127_REG_ALARM_HR 0x0C
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#define PCF2127_REG_ALARM_DM 0x0D
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#define PCF2127_REG_ALARM_DW 0x0E
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#define PCF2127_BIT_ALARM_AE BIT(7)
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/* Watchdog registers */
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#define PCF2127_REG_WD_CTL 0x10
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#define PCF2127_BIT_WD_CTL_TF0 BIT(0)
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#define PCF2127_BIT_WD_CTL_TF1 BIT(1)
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#define PCF2127_BIT_WD_CTL_CD0 BIT(6)
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#define PCF2127_BIT_WD_CTL_CD1 BIT(7)
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#define PCF2127_REG_WD_VAL 0x11
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/* Tamper timestamp registers */
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#define PCF2127_REG_TS_CTRL 0x12
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#define PCF2127_BIT_TS_CTRL_TSOFF BIT(6)
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#define PCF2127_BIT_TS_CTRL_TSM BIT(7)
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#define PCF2127_REG_TS_SC 0x13
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#define PCF2127_REG_TS_MN 0x14
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#define PCF2127_REG_TS_HR 0x15
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#define PCF2127_REG_TS_DM 0x16
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#define PCF2127_REG_TS_MO 0x17
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#define PCF2127_REG_TS_YR 0x18
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/*
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* RAM registers
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* PCF2127 has 512 bytes general-purpose static RAM (SRAM) that is
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* battery backed and can survive a power outage.
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* PCF2129 doesn't have this feature.
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*/
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#define PCF2127_REG_RAM_ADDR_MSB 0x1A
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#define PCF2127_REG_RAM_WRT_CMD 0x1C
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#define PCF2127_REG_RAM_RD_CMD 0x1D
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/* Watchdog timer value constants */
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#define PCF2127_WD_VAL_STOP 0
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#define PCF2127_WD_VAL_MIN 2
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#define PCF2127_WD_VAL_MAX 255
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#define PCF2127_WD_VAL_DEFAULT 60
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struct pcf2127 {
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struct rtc_device *rtc;
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struct watchdog_device wdd;
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struct regmap *regmap;
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};
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/*
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* In the routines that deal directly with the pcf2127 hardware, we use
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* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch.
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*/
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static int pcf2127_rtc_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
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unsigned char buf[10];
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int ret;
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/*
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* Avoid reading CTRL2 register as it causes WD_VAL register
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* value to reset to 0 which means watchdog is stopped.
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*/
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ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL3,
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(buf + PCF2127_REG_CTRL3),
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ARRAY_SIZE(buf) - PCF2127_REG_CTRL3);
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if (ret) {
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dev_err(dev, "%s: read error\n", __func__);
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return ret;
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}
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if (buf[PCF2127_REG_CTRL3] & PCF2127_BIT_CTRL3_BLF)
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dev_info(dev,
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"low voltage detected, check/replace RTC battery.\n");
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/* Clock integrity is not guaranteed when OSF flag is set. */
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if (buf[PCF2127_REG_SC] & PCF2127_BIT_SC_OSF) {
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/*
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* no need clear the flag here,
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* it will be cleared once the new date is saved
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*/
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dev_warn(dev,
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"oscillator stop detected, date/time is not reliable\n");
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return -EINVAL;
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}
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dev_dbg(dev,
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"%s: raw data is cr3=%02x, sec=%02x, min=%02x, hr=%02x, "
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"mday=%02x, wday=%02x, mon=%02x, year=%02x\n",
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__func__, buf[PCF2127_REG_CTRL3], buf[PCF2127_REG_SC],
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buf[PCF2127_REG_MN], buf[PCF2127_REG_HR],
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buf[PCF2127_REG_DM], buf[PCF2127_REG_DW],
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buf[PCF2127_REG_MO], buf[PCF2127_REG_YR]);
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tm->tm_sec = bcd2bin(buf[PCF2127_REG_SC] & 0x7F);
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tm->tm_min = bcd2bin(buf[PCF2127_REG_MN] & 0x7F);
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tm->tm_hour = bcd2bin(buf[PCF2127_REG_HR] & 0x3F); /* rtc hr 0-23 */
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tm->tm_mday = bcd2bin(buf[PCF2127_REG_DM] & 0x3F);
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tm->tm_wday = buf[PCF2127_REG_DW] & 0x07;
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tm->tm_mon = bcd2bin(buf[PCF2127_REG_MO] & 0x1F) - 1; /* rtc mn 1-12 */
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tm->tm_year = bcd2bin(buf[PCF2127_REG_YR]);
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tm->tm_year += 100;
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dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
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"mday=%d, mon=%d, year=%d, wday=%d\n",
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__func__,
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tm->tm_sec, tm->tm_min, tm->tm_hour,
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tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
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return 0;
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}
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static int pcf2127_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
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unsigned char buf[7];
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int i = 0, err;
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dev_dbg(dev, "%s: secs=%d, mins=%d, hours=%d, "
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"mday=%d, mon=%d, year=%d, wday=%d\n",
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__func__,
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tm->tm_sec, tm->tm_min, tm->tm_hour,
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tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
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/* hours, minutes and seconds */
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buf[i++] = bin2bcd(tm->tm_sec); /* this will also clear OSF flag */
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buf[i++] = bin2bcd(tm->tm_min);
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buf[i++] = bin2bcd(tm->tm_hour);
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buf[i++] = bin2bcd(tm->tm_mday);
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buf[i++] = tm->tm_wday & 0x07;
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/* month, 1 - 12 */
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buf[i++] = bin2bcd(tm->tm_mon + 1);
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/* year */
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buf[i++] = bin2bcd(tm->tm_year - 100);
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/* write register's data */
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err = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_SC, buf, i);
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if (err) {
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dev_err(dev,
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"%s: err=%d", __func__, err);
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return err;
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}
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return 0;
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}
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static int pcf2127_rtc_ioctl(struct device *dev,
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unsigned int cmd, unsigned long arg)
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{
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struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
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int val, touser = 0;
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int ret;
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switch (cmd) {
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case RTC_VL_READ:
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ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL3, &val);
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if (ret)
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return ret;
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if (val & PCF2127_BIT_CTRL3_BLF)
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touser |= RTC_VL_BACKUP_LOW;
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if (val & PCF2127_BIT_CTRL3_BF)
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touser |= RTC_VL_BACKUP_SWITCH;
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return put_user(touser, (unsigned int __user *)arg);
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case RTC_VL_CLR:
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return regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
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PCF2127_BIT_CTRL3_BF, 0);
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default:
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return -ENOIOCTLCMD;
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}
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}
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static const struct rtc_class_ops pcf2127_rtc_ops = {
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.ioctl = pcf2127_rtc_ioctl,
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.read_time = pcf2127_rtc_read_time,
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.set_time = pcf2127_rtc_set_time,
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};
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static int pcf2127_nvmem_read(void *priv, unsigned int offset,
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void *val, size_t bytes)
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{
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struct pcf2127 *pcf2127 = priv;
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int ret;
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unsigned char offsetbuf[] = { offset >> 8, offset };
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ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
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offsetbuf, 2);
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if (ret)
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return ret;
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return regmap_bulk_read(pcf2127->regmap, PCF2127_REG_RAM_RD_CMD,
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val, bytes);
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}
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static int pcf2127_nvmem_write(void *priv, unsigned int offset,
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void *val, size_t bytes)
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{
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struct pcf2127 *pcf2127 = priv;
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int ret;
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unsigned char offsetbuf[] = { offset >> 8, offset };
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ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_ADDR_MSB,
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offsetbuf, 2);
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if (ret)
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return ret;
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return regmap_bulk_write(pcf2127->regmap, PCF2127_REG_RAM_WRT_CMD,
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val, bytes);
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}
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/* watchdog driver */
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static int pcf2127_wdt_ping(struct watchdog_device *wdd)
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{
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struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
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return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL, wdd->timeout);
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}
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/*
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* Restart watchdog timer if feature is active.
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*
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* Note: Reading CTRL2 register causes watchdog to stop which is unfortunate,
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* since register also contain control/status flags for other features.
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* Always call this function after reading CTRL2 register.
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*/
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static int pcf2127_wdt_active_ping(struct watchdog_device *wdd)
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{
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int ret = 0;
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if (watchdog_active(wdd)) {
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ret = pcf2127_wdt_ping(wdd);
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if (ret)
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dev_err(wdd->parent,
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"%s: watchdog restart failed, ret=%d\n",
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__func__, ret);
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}
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return ret;
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}
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static int pcf2127_wdt_start(struct watchdog_device *wdd)
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{
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return pcf2127_wdt_ping(wdd);
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}
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static int pcf2127_wdt_stop(struct watchdog_device *wdd)
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{
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struct pcf2127 *pcf2127 = watchdog_get_drvdata(wdd);
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return regmap_write(pcf2127->regmap, PCF2127_REG_WD_VAL,
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PCF2127_WD_VAL_STOP);
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}
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static int pcf2127_wdt_set_timeout(struct watchdog_device *wdd,
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unsigned int new_timeout)
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{
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dev_dbg(wdd->parent, "new watchdog timeout: %is (old: %is)\n",
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new_timeout, wdd->timeout);
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wdd->timeout = new_timeout;
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return pcf2127_wdt_active_ping(wdd);
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}
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static const struct watchdog_info pcf2127_wdt_info = {
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.identity = "NXP PCF2127/PCF2129 Watchdog",
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.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
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};
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static const struct watchdog_ops pcf2127_watchdog_ops = {
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.owner = THIS_MODULE,
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.start = pcf2127_wdt_start,
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.stop = pcf2127_wdt_stop,
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.ping = pcf2127_wdt_ping,
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.set_timeout = pcf2127_wdt_set_timeout,
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};
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static int pcf2127_watchdog_init(struct device *dev, struct pcf2127 *pcf2127)
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{
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u32 wdd_timeout;
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int ret;
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if (!IS_ENABLED(CONFIG_WATCHDOG) ||
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!device_property_read_bool(dev, "reset-source"))
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return 0;
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pcf2127->wdd.parent = dev;
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pcf2127->wdd.info = &pcf2127_wdt_info;
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pcf2127->wdd.ops = &pcf2127_watchdog_ops;
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pcf2127->wdd.min_timeout = PCF2127_WD_VAL_MIN;
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pcf2127->wdd.max_timeout = PCF2127_WD_VAL_MAX;
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pcf2127->wdd.timeout = PCF2127_WD_VAL_DEFAULT;
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pcf2127->wdd.min_hw_heartbeat_ms = 500;
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pcf2127->wdd.status = WATCHDOG_NOWAYOUT_INIT_STATUS;
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watchdog_set_drvdata(&pcf2127->wdd, pcf2127);
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/* Test if watchdog timer is started by bootloader */
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ret = regmap_read(pcf2127->regmap, PCF2127_REG_WD_VAL, &wdd_timeout);
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if (ret)
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return ret;
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if (wdd_timeout)
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set_bit(WDOG_HW_RUNNING, &pcf2127->wdd.status);
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return devm_watchdog_register_device(dev, &pcf2127->wdd);
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}
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/* Alarm */
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static int pcf2127_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
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u8 buf[5];
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unsigned int ctrl2;
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int ret;
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ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
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if (ret)
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return ret;
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ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
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if (ret)
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return ret;
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ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf,
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sizeof(buf));
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if (ret)
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return ret;
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alrm->enabled = ctrl2 & PCF2127_BIT_CTRL2_AIE;
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alrm->pending = ctrl2 & PCF2127_BIT_CTRL2_AF;
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alrm->time.tm_sec = bcd2bin(buf[0] & 0x7F);
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alrm->time.tm_min = bcd2bin(buf[1] & 0x7F);
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alrm->time.tm_hour = bcd2bin(buf[2] & 0x3F);
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alrm->time.tm_mday = bcd2bin(buf[3] & 0x3F);
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return 0;
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}
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static int pcf2127_rtc_alarm_irq_enable(struct device *dev, u32 enable)
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{
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struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
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int ret;
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ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
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PCF2127_BIT_CTRL2_AIE,
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enable ? PCF2127_BIT_CTRL2_AIE : 0);
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if (ret)
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return ret;
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return pcf2127_wdt_active_ping(&pcf2127->wdd);
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}
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static int pcf2127_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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{
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struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
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uint8_t buf[5];
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int ret;
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ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
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PCF2127_BIT_CTRL2_AF, 0);
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if (ret)
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return ret;
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ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
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if (ret)
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return ret;
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buf[0] = bin2bcd(alrm->time.tm_sec);
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buf[1] = bin2bcd(alrm->time.tm_min);
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buf[2] = bin2bcd(alrm->time.tm_hour);
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buf[3] = bin2bcd(alrm->time.tm_mday);
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buf[4] = PCF2127_BIT_ALARM_AE; /* Do not match on week day */
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ret = regmap_bulk_write(pcf2127->regmap, PCF2127_REG_ALARM_SC, buf,
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sizeof(buf));
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if (ret)
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return ret;
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return pcf2127_rtc_alarm_irq_enable(dev, alrm->enabled);
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}
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static irqreturn_t pcf2127_rtc_irq(int irq, void *dev)
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{
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struct pcf2127 *pcf2127 = dev_get_drvdata(dev);
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unsigned int ctrl2 = 0;
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int ret = 0;
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ret = regmap_read(pcf2127->regmap, PCF2127_REG_CTRL2, &ctrl2);
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if (ret)
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return IRQ_NONE;
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if (!(ctrl2 & PCF2127_BIT_CTRL2_AF))
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return IRQ_NONE;
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regmap_write(pcf2127->regmap, PCF2127_REG_CTRL2,
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ctrl2 & ~(PCF2127_BIT_CTRL2_AF | PCF2127_BIT_CTRL2_WDTF));
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rtc_update_irq(pcf2127->rtc, 1, RTC_IRQF | RTC_AF);
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pcf2127_wdt_active_ping(&pcf2127->wdd);
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return IRQ_HANDLED;
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}
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static const struct rtc_class_ops pcf2127_rtc_alrm_ops = {
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.ioctl = pcf2127_rtc_ioctl,
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.read_time = pcf2127_rtc_read_time,
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.set_time = pcf2127_rtc_set_time,
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.read_alarm = pcf2127_rtc_read_alarm,
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.set_alarm = pcf2127_rtc_set_alarm,
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.alarm_irq_enable = pcf2127_rtc_alarm_irq_enable,
|
};
|
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/* sysfs interface */
|
|
static ssize_t timestamp0_store(struct device *dev,
|
struct device_attribute *attr,
|
const char *buf, size_t count)
|
{
|
struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
|
int ret;
|
|
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
|
PCF2127_BIT_CTRL1_TSF1, 0);
|
if (ret) {
|
dev_err(dev, "%s: update ctrl1 ret=%d\n", __func__, ret);
|
return ret;
|
}
|
|
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
|
PCF2127_BIT_CTRL2_TSF2, 0);
|
if (ret) {
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dev_err(dev, "%s: update ctrl2 ret=%d\n", __func__, ret);
|
return ret;
|
}
|
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ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
|
if (ret)
|
return ret;
|
|
return count;
|
};
|
|
static ssize_t timestamp0_show(struct device *dev,
|
struct device_attribute *attr, char *buf)
|
{
|
struct pcf2127 *pcf2127 = dev_get_drvdata(dev->parent);
|
struct rtc_time tm;
|
int ret;
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unsigned char data[25];
|
|
ret = regmap_bulk_read(pcf2127->regmap, PCF2127_REG_CTRL1, data,
|
sizeof(data));
|
if (ret) {
|
dev_err(dev, "%s: read error ret=%d\n", __func__, ret);
|
return ret;
|
}
|
|
dev_dbg(dev,
|
"%s: raw data is cr1=%02x, cr2=%02x, cr3=%02x, ts_sc=%02x, "
|
"ts_mn=%02x, ts_hr=%02x, ts_dm=%02x, ts_mo=%02x, ts_yr=%02x\n",
|
__func__, data[PCF2127_REG_CTRL1], data[PCF2127_REG_CTRL2],
|
data[PCF2127_REG_CTRL3], data[PCF2127_REG_TS_SC],
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data[PCF2127_REG_TS_MN], data[PCF2127_REG_TS_HR],
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data[PCF2127_REG_TS_DM], data[PCF2127_REG_TS_MO],
|
data[PCF2127_REG_TS_YR]);
|
|
ret = pcf2127_wdt_active_ping(&pcf2127->wdd);
|
if (ret)
|
return ret;
|
|
if (!(data[PCF2127_REG_CTRL1] & PCF2127_BIT_CTRL1_TSF1) &&
|
!(data[PCF2127_REG_CTRL2] & PCF2127_BIT_CTRL2_TSF2))
|
return 0;
|
|
tm.tm_sec = bcd2bin(data[PCF2127_REG_TS_SC] & 0x7F);
|
tm.tm_min = bcd2bin(data[PCF2127_REG_TS_MN] & 0x7F);
|
tm.tm_hour = bcd2bin(data[PCF2127_REG_TS_HR] & 0x3F);
|
tm.tm_mday = bcd2bin(data[PCF2127_REG_TS_DM] & 0x3F);
|
/* TS_MO register (month) value range: 1-12 */
|
tm.tm_mon = bcd2bin(data[PCF2127_REG_TS_MO] & 0x1F) - 1;
|
tm.tm_year = bcd2bin(data[PCF2127_REG_TS_YR]);
|
if (tm.tm_year < 70)
|
tm.tm_year += 100; /* assume we are in 1970...2069 */
|
|
ret = rtc_valid_tm(&tm);
|
if (ret)
|
return ret;
|
|
return sprintf(buf, "%llu\n",
|
(unsigned long long)rtc_tm_to_time64(&tm));
|
};
|
|
static DEVICE_ATTR_RW(timestamp0);
|
|
static struct attribute *pcf2127_attrs[] = {
|
&dev_attr_timestamp0.attr,
|
NULL
|
};
|
|
static const struct attribute_group pcf2127_attr_group = {
|
.attrs = pcf2127_attrs,
|
};
|
|
static int pcf2127_probe(struct device *dev, struct regmap *regmap,
|
int alarm_irq, const char *name, bool has_nvmem)
|
{
|
struct pcf2127 *pcf2127;
|
int ret = 0;
|
|
dev_dbg(dev, "%s\n", __func__);
|
|
pcf2127 = devm_kzalloc(dev, sizeof(*pcf2127), GFP_KERNEL);
|
if (!pcf2127)
|
return -ENOMEM;
|
|
pcf2127->regmap = regmap;
|
|
dev_set_drvdata(dev, pcf2127);
|
|
pcf2127->rtc = devm_rtc_allocate_device(dev);
|
if (IS_ERR(pcf2127->rtc))
|
return PTR_ERR(pcf2127->rtc);
|
|
pcf2127->rtc->ops = &pcf2127_rtc_ops;
|
pcf2127->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
|
pcf2127->rtc->range_max = RTC_TIMESTAMP_END_2099;
|
pcf2127->rtc->set_start_time = true; /* Sets actual start to 1970 */
|
pcf2127->rtc->uie_unsupported = 1;
|
|
if (alarm_irq > 0) {
|
ret = devm_request_threaded_irq(dev, alarm_irq, NULL,
|
pcf2127_rtc_irq,
|
IRQF_TRIGGER_LOW | IRQF_ONESHOT,
|
dev_name(dev), dev);
|
if (ret) {
|
dev_err(dev, "failed to request alarm irq\n");
|
return ret;
|
}
|
}
|
|
if (alarm_irq > 0 || device_property_read_bool(dev, "wakeup-source")) {
|
device_init_wakeup(dev, true);
|
pcf2127->rtc->ops = &pcf2127_rtc_alrm_ops;
|
}
|
|
if (has_nvmem) {
|
struct nvmem_config nvmem_cfg = {
|
.priv = pcf2127,
|
.reg_read = pcf2127_nvmem_read,
|
.reg_write = pcf2127_nvmem_write,
|
.size = 512,
|
};
|
|
ret = rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
|
}
|
|
/*
|
* Watchdog timer enabled and reset pin /RST activated when timed out.
|
* Select 1Hz clock source for watchdog timer.
|
* Note: Countdown timer disabled and not available.
|
*/
|
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_WD_CTL,
|
PCF2127_BIT_WD_CTL_CD1 |
|
PCF2127_BIT_WD_CTL_CD0 |
|
PCF2127_BIT_WD_CTL_TF1 |
|
PCF2127_BIT_WD_CTL_TF0,
|
PCF2127_BIT_WD_CTL_CD1 |
|
PCF2127_BIT_WD_CTL_CD0 |
|
PCF2127_BIT_WD_CTL_TF1);
|
if (ret) {
|
dev_err(dev, "%s: watchdog config (wd_ctl) failed\n", __func__);
|
return ret;
|
}
|
|
pcf2127_watchdog_init(dev, pcf2127);
|
|
/*
|
* Disable battery low/switch-over timestamp and interrupts.
|
* Clear battery interrupt flags which can block new trigger events.
|
* Note: This is the default chip behaviour but added to ensure
|
* correct tamper timestamp and interrupt function.
|
*/
|
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL3,
|
PCF2127_BIT_CTRL3_BTSE |
|
PCF2127_BIT_CTRL3_BIE |
|
PCF2127_BIT_CTRL3_BLIE, 0);
|
if (ret) {
|
dev_err(dev, "%s: interrupt config (ctrl3) failed\n",
|
__func__);
|
return ret;
|
}
|
|
/*
|
* Enable timestamp function and store timestamp of first trigger
|
* event until TSF1 and TFS2 interrupt flags are cleared.
|
*/
|
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_TS_CTRL,
|
PCF2127_BIT_TS_CTRL_TSOFF |
|
PCF2127_BIT_TS_CTRL_TSM,
|
PCF2127_BIT_TS_CTRL_TSM);
|
if (ret) {
|
dev_err(dev, "%s: tamper detection config (ts_ctrl) failed\n",
|
__func__);
|
return ret;
|
}
|
|
/*
|
* Enable interrupt generation when TSF1 or TSF2 timestamp flags
|
* are set. Interrupt signal is an open-drain output and can be
|
* left floating if unused.
|
*/
|
ret = regmap_update_bits(pcf2127->regmap, PCF2127_REG_CTRL2,
|
PCF2127_BIT_CTRL2_TSIE,
|
PCF2127_BIT_CTRL2_TSIE);
|
if (ret) {
|
dev_err(dev, "%s: tamper detection config (ctrl2) failed\n",
|
__func__);
|
return ret;
|
}
|
|
ret = rtc_add_group(pcf2127->rtc, &pcf2127_attr_group);
|
if (ret) {
|
dev_err(dev, "%s: tamper sysfs registering failed\n",
|
__func__);
|
return ret;
|
}
|
|
return rtc_register_device(pcf2127->rtc);
|
}
|
|
#ifdef CONFIG_OF
|
static const struct of_device_id pcf2127_of_match[] = {
|
{ .compatible = "nxp,pcf2127" },
|
{ .compatible = "nxp,pcf2129" },
|
{ .compatible = "nxp,pca2129" },
|
{}
|
};
|
MODULE_DEVICE_TABLE(of, pcf2127_of_match);
|
#endif
|
|
#if IS_ENABLED(CONFIG_I2C)
|
|
static int pcf2127_i2c_write(void *context, const void *data, size_t count)
|
{
|
struct device *dev = context;
|
struct i2c_client *client = to_i2c_client(dev);
|
int ret;
|
|
ret = i2c_master_send(client, data, count);
|
if (ret != count)
|
return ret < 0 ? ret : -EIO;
|
|
return 0;
|
}
|
|
static int pcf2127_i2c_gather_write(void *context,
|
const void *reg, size_t reg_size,
|
const void *val, size_t val_size)
|
{
|
struct device *dev = context;
|
struct i2c_client *client = to_i2c_client(dev);
|
int ret;
|
void *buf;
|
|
if (WARN_ON(reg_size != 1))
|
return -EINVAL;
|
|
buf = kmalloc(val_size + 1, GFP_KERNEL);
|
if (!buf)
|
return -ENOMEM;
|
|
memcpy(buf, reg, 1);
|
memcpy(buf + 1, val, val_size);
|
|
ret = i2c_master_send(client, buf, val_size + 1);
|
|
kfree(buf);
|
|
if (ret != val_size + 1)
|
return ret < 0 ? ret : -EIO;
|
|
return 0;
|
}
|
|
static int pcf2127_i2c_read(void *context, const void *reg, size_t reg_size,
|
void *val, size_t val_size)
|
{
|
struct device *dev = context;
|
struct i2c_client *client = to_i2c_client(dev);
|
int ret;
|
|
if (WARN_ON(reg_size != 1))
|
return -EINVAL;
|
|
ret = i2c_master_send(client, reg, 1);
|
if (ret != 1)
|
return ret < 0 ? ret : -EIO;
|
|
ret = i2c_master_recv(client, val, val_size);
|
if (ret != val_size)
|
return ret < 0 ? ret : -EIO;
|
|
return 0;
|
}
|
|
/*
|
* The reason we need this custom regmap_bus instead of using regmap_init_i2c()
|
* is that the STOP condition is required between set register address and
|
* read register data when reading from registers.
|
*/
|
static const struct regmap_bus pcf2127_i2c_regmap = {
|
.write = pcf2127_i2c_write,
|
.gather_write = pcf2127_i2c_gather_write,
|
.read = pcf2127_i2c_read,
|
};
|
|
static struct i2c_driver pcf2127_i2c_driver;
|
|
static int pcf2127_i2c_probe(struct i2c_client *client,
|
const struct i2c_device_id *id)
|
{
|
struct regmap *regmap;
|
static const struct regmap_config config = {
|
.reg_bits = 8,
|
.val_bits = 8,
|
.max_register = 0x1d,
|
};
|
|
if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
|
return -ENODEV;
|
|
regmap = devm_regmap_init(&client->dev, &pcf2127_i2c_regmap,
|
&client->dev, &config);
|
if (IS_ERR(regmap)) {
|
dev_err(&client->dev, "%s: regmap allocation failed: %ld\n",
|
__func__, PTR_ERR(regmap));
|
return PTR_ERR(regmap);
|
}
|
|
return pcf2127_probe(&client->dev, regmap, client->irq,
|
pcf2127_i2c_driver.driver.name, id->driver_data);
|
}
|
|
static const struct i2c_device_id pcf2127_i2c_id[] = {
|
{ "pcf2127", 1 },
|
{ "pcf2129", 0 },
|
{ "pca2129", 0 },
|
{ }
|
};
|
MODULE_DEVICE_TABLE(i2c, pcf2127_i2c_id);
|
|
static struct i2c_driver pcf2127_i2c_driver = {
|
.driver = {
|
.name = "rtc-pcf2127-i2c",
|
.of_match_table = of_match_ptr(pcf2127_of_match),
|
},
|
.probe = pcf2127_i2c_probe,
|
.id_table = pcf2127_i2c_id,
|
};
|
|
static int pcf2127_i2c_register_driver(void)
|
{
|
return i2c_add_driver(&pcf2127_i2c_driver);
|
}
|
|
static void pcf2127_i2c_unregister_driver(void)
|
{
|
i2c_del_driver(&pcf2127_i2c_driver);
|
}
|
|
#else
|
|
static int pcf2127_i2c_register_driver(void)
|
{
|
return 0;
|
}
|
|
static void pcf2127_i2c_unregister_driver(void)
|
{
|
}
|
|
#endif
|
|
#if IS_ENABLED(CONFIG_SPI_MASTER)
|
|
static struct spi_driver pcf2127_spi_driver;
|
|
static int pcf2127_spi_probe(struct spi_device *spi)
|
{
|
static const struct regmap_config config = {
|
.reg_bits = 8,
|
.val_bits = 8,
|
.read_flag_mask = 0xa0,
|
.write_flag_mask = 0x20,
|
.max_register = 0x1d,
|
};
|
struct regmap *regmap;
|
|
regmap = devm_regmap_init_spi(spi, &config);
|
if (IS_ERR(regmap)) {
|
dev_err(&spi->dev, "%s: regmap allocation failed: %ld\n",
|
__func__, PTR_ERR(regmap));
|
return PTR_ERR(regmap);
|
}
|
|
return pcf2127_probe(&spi->dev, regmap, spi->irq,
|
pcf2127_spi_driver.driver.name,
|
spi_get_device_id(spi)->driver_data);
|
}
|
|
static const struct spi_device_id pcf2127_spi_id[] = {
|
{ "pcf2127", 1 },
|
{ "pcf2129", 0 },
|
{ "pca2129", 0 },
|
{ }
|
};
|
MODULE_DEVICE_TABLE(spi, pcf2127_spi_id);
|
|
static struct spi_driver pcf2127_spi_driver = {
|
.driver = {
|
.name = "rtc-pcf2127-spi",
|
.of_match_table = of_match_ptr(pcf2127_of_match),
|
},
|
.probe = pcf2127_spi_probe,
|
.id_table = pcf2127_spi_id,
|
};
|
|
static int pcf2127_spi_register_driver(void)
|
{
|
return spi_register_driver(&pcf2127_spi_driver);
|
}
|
|
static void pcf2127_spi_unregister_driver(void)
|
{
|
spi_unregister_driver(&pcf2127_spi_driver);
|
}
|
|
#else
|
|
static int pcf2127_spi_register_driver(void)
|
{
|
return 0;
|
}
|
|
static void pcf2127_spi_unregister_driver(void)
|
{
|
}
|
|
#endif
|
|
static int __init pcf2127_init(void)
|
{
|
int ret;
|
|
ret = pcf2127_i2c_register_driver();
|
if (ret) {
|
pr_err("Failed to register pcf2127 i2c driver: %d\n", ret);
|
return ret;
|
}
|
|
ret = pcf2127_spi_register_driver();
|
if (ret) {
|
pr_err("Failed to register pcf2127 spi driver: %d\n", ret);
|
pcf2127_i2c_unregister_driver();
|
}
|
|
return ret;
|
}
|
module_init(pcf2127_init)
|
|
static void __exit pcf2127_exit(void)
|
{
|
pcf2127_spi_unregister_driver();
|
pcf2127_i2c_unregister_driver();
|
}
|
module_exit(pcf2127_exit)
|
|
MODULE_AUTHOR("Renaud Cerrato <r.cerrato@til-technologies.fr>");
|
MODULE_DESCRIPTION("NXP PCF2127/29 RTC driver");
|
MODULE_LICENSE("GPL v2");
|
