// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/* QLogic qed NIC Driver
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* Copyright (c) 2015-2016 QLogic Corporation
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* Copyright (c) 2019-2020 Marvell International Ltd.
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*/
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#include <linux/crc32.h>
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#include "qed.h"
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#include "qed_dev_api.h"
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#include "qed_mcp.h"
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#include "qed_sp.h"
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#include "qed_selftest.h"
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int qed_selftest_memory(struct qed_dev *cdev)
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{
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int rc = 0, i;
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for_each_hwfn(cdev, i) {
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rc = qed_sp_heartbeat_ramrod(&cdev->hwfns[i]);
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if (rc)
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return rc;
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}
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return rc;
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}
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int qed_selftest_interrupt(struct qed_dev *cdev)
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{
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int rc = 0, i;
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for_each_hwfn(cdev, i) {
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rc = qed_sp_heartbeat_ramrod(&cdev->hwfns[i]);
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if (rc)
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return rc;
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}
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return rc;
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}
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int qed_selftest_register(struct qed_dev *cdev)
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{
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struct qed_hwfn *p_hwfn;
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struct qed_ptt *p_ptt;
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int rc = 0, i;
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/* although performed by MCP, this test is per engine */
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for_each_hwfn(cdev, i) {
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p_hwfn = &cdev->hwfns[i];
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p_ptt = qed_ptt_acquire(p_hwfn);
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if (!p_ptt) {
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DP_ERR(p_hwfn, "failed to acquire ptt\n");
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return -EBUSY;
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}
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rc = qed_mcp_bist_register_test(p_hwfn, p_ptt);
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qed_ptt_release(p_hwfn, p_ptt);
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if (rc)
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break;
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}
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return rc;
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}
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int qed_selftest_clock(struct qed_dev *cdev)
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{
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struct qed_hwfn *p_hwfn;
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struct qed_ptt *p_ptt;
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int rc = 0, i;
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/* although performed by MCP, this test is per engine */
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for_each_hwfn(cdev, i) {
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p_hwfn = &cdev->hwfns[i];
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p_ptt = qed_ptt_acquire(p_hwfn);
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if (!p_ptt) {
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DP_ERR(p_hwfn, "failed to acquire ptt\n");
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return -EBUSY;
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}
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rc = qed_mcp_bist_clock_test(p_hwfn, p_ptt);
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qed_ptt_release(p_hwfn, p_ptt);
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if (rc)
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break;
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}
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return rc;
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}
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int qed_selftest_nvram(struct qed_dev *cdev)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn);
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u32 num_images, i, j, nvm_crc, calc_crc;
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struct bist_nvm_image_att image_att;
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u8 *buf = NULL;
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__be32 val;
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int rc;
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if (!p_ptt) {
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DP_ERR(p_hwfn, "failed to acquire ptt\n");
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return -EBUSY;
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}
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/* Acquire from MFW the amount of available images */
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rc = qed_mcp_bist_nvm_get_num_images(p_hwfn, p_ptt, &num_images);
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if (rc || !num_images) {
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DP_ERR(p_hwfn, "Failed getting number of images\n");
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rc = -EINVAL;
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goto err0;
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}
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/* Iterate over images and validate CRC */
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for (i = 0; i < num_images; i++) {
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/* This mailbox returns information about the image required for
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* reading it.
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*/
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rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt,
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&image_att, i);
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if (rc) {
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DP_ERR(p_hwfn,
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"Failed getting image index %d attributes\n",
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i);
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goto err0;
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}
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/* After MFW crash dump is collected - the image's CRC stops
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* being valid.
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*/
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if (image_att.image_type == NVM_TYPE_MDUMP)
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continue;
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DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n",
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i, image_att.len);
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/* Allocate a buffer for holding the nvram image */
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buf = kzalloc(image_att.len, GFP_KERNEL);
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if (!buf) {
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rc = -ENOMEM;
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goto err0;
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}
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/* Read image into buffer */
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rc = qed_mcp_nvm_read(p_hwfn->cdev, image_att.nvm_start_addr,
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buf, image_att.len);
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if (rc) {
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DP_ERR(p_hwfn,
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"Failed reading image index %d from nvm.\n", i);
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goto err1;
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}
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/* Convert the buffer into big-endian format (excluding the
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* closing 4 bytes of CRC).
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*/
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for (j = 0; j < image_att.len - 4; j += 4) {
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val = cpu_to_be32(*(u32 *)&buf[j]);
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*(u32 *)&buf[j] = (__force u32)val;
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}
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/* Calc CRC for the "actual" image buffer, i.e. not including
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* the last 4 CRC bytes.
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*/
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nvm_crc = *(u32 *)(buf + image_att.len - 4);
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calc_crc = crc32(0xffffffff, buf, image_att.len - 4);
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calc_crc = (__force u32)~cpu_to_be32(calc_crc);
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DP_VERBOSE(p_hwfn, QED_MSG_SP,
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"nvm crc 0x%x, calc_crc 0x%x\n", nvm_crc, calc_crc);
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if (calc_crc != nvm_crc) {
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rc = -EINVAL;
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goto err1;
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}
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/* Done with this image; Free to prevent double release
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* on subsequent failure.
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*/
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kfree(buf);
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buf = NULL;
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}
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qed_ptt_release(p_hwfn, p_ptt);
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return 0;
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err1:
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kfree(buf);
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err0:
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qed_ptt_release(p_hwfn, p_ptt);
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return rc;
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}
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