/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/* QLogic qed NIC Driver
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* Copyright (c) 2015-2017 QLogic Corporation
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* Copyright (c) 2019-2020 Marvell International Ltd.
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*/
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#ifndef _QED_RDMA_H
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#define _QED_RDMA_H
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/qed/qed_if.h>
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#include <linux/qed/qed_rdma_if.h>
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#include "qed.h"
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#include "qed_dev_api.h"
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#include "qed_hsi.h"
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#include "qed_iwarp.h"
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#include "qed_roce.h"
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#define QED_RDMA_MAX_P_KEY (1)
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#define QED_RDMA_MAX_WQE (0x7FFF)
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#define QED_RDMA_MAX_SRQ_WQE_ELEM (0x7FFF)
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#define QED_RDMA_PAGE_SIZE_CAPS (0xFFFFF000)
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#define QED_RDMA_ACK_DELAY (15)
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#define QED_RDMA_MAX_MR_SIZE (0x10000000000ULL)
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#define QED_RDMA_MAX_CQS (RDMA_MAX_CQS)
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#define QED_RDMA_MAX_MRS (RDMA_MAX_TIDS)
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/* Add 1 for header element */
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#define QED_RDMA_MAX_SRQ_ELEM_PER_WQE (RDMA_MAX_SGE_PER_RQ_WQE + 1)
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#define QED_RDMA_MAX_SGE_PER_SRQ_WQE (RDMA_MAX_SGE_PER_RQ_WQE)
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#define QED_RDMA_SRQ_WQE_ELEM_SIZE (16)
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#define QED_RDMA_MAX_SRQS (32 * 1024)
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#define QED_RDMA_MAX_CQE_32_BIT (0x7FFFFFFF - 1)
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#define QED_RDMA_MAX_CQE_16_BIT (0x7FFF - 1)
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/* Up to 2^16 XRC Domains are supported, but the actual number of supported XRC
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* SRQs is much smaller so there's no need to have that many domains.
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*/
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#define QED_RDMA_MAX_XRCDS (roundup_pow_of_two(RDMA_MAX_XRC_SRQS))
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enum qed_rdma_toggle_bit {
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QED_RDMA_TOGGLE_BIT_CLEAR = 0,
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QED_RDMA_TOGGLE_BIT_SET = 1
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};
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#define QED_RDMA_MAX_BMAP_NAME (10)
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struct qed_bmap {
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unsigned long *bitmap;
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u32 max_count;
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char name[QED_RDMA_MAX_BMAP_NAME];
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};
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struct qed_rdma_info {
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/* spin lock to protect bitmaps */
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spinlock_t lock;
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struct qed_bmap cq_map;
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struct qed_bmap pd_map;
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struct qed_bmap xrcd_map;
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struct qed_bmap tid_map;
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struct qed_bmap qp_map;
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struct qed_bmap srq_map;
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struct qed_bmap xrc_srq_map;
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struct qed_bmap cid_map;
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struct qed_bmap tcp_cid_map;
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struct qed_bmap real_cid_map;
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struct qed_bmap dpi_map;
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struct qed_bmap toggle_bits;
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struct qed_rdma_events events;
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struct qed_rdma_device *dev;
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struct qed_rdma_port *port;
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u32 last_tid;
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u8 num_cnqs;
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u32 num_qps;
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u32 num_mrs;
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u32 num_srqs;
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u16 srq_id_offset;
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u16 queue_zone_base;
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u16 max_queue_zones;
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enum protocol_type proto;
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struct qed_iwarp_info iwarp;
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u8 active:1;
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};
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struct qed_rdma_qp {
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struct regpair qp_handle;
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struct regpair qp_handle_async;
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u32 qpid;
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u16 icid;
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enum qed_roce_qp_state cur_state;
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enum qed_rdma_qp_type qp_type;
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enum qed_iwarp_qp_state iwarp_state;
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bool use_srq;
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bool signal_all;
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bool fmr_and_reserved_lkey;
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bool incoming_rdma_read_en;
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bool incoming_rdma_write_en;
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bool incoming_atomic_en;
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bool e2e_flow_control_en;
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u16 pd;
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u16 pkey;
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u32 dest_qp;
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u16 mtu;
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u16 srq_id;
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u8 traffic_class_tos;
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u8 hop_limit_ttl;
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u16 dpi;
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u32 flow_label;
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bool lb_indication;
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u16 vlan_id;
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u32 ack_timeout;
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u8 retry_cnt;
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u8 rnr_retry_cnt;
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u8 min_rnr_nak_timer;
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bool sqd_async;
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union qed_gid sgid;
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union qed_gid dgid;
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enum roce_mode roce_mode;
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u16 udp_src_port;
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u8 stats_queue;
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/* requeseter */
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u8 max_rd_atomic_req;
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u32 sq_psn;
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u16 sq_cq_id;
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u16 sq_num_pages;
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dma_addr_t sq_pbl_ptr;
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void *orq;
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dma_addr_t orq_phys_addr;
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u8 orq_num_pages;
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bool req_offloaded;
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bool has_req;
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/* responder */
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u8 max_rd_atomic_resp;
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u32 rq_psn;
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u16 rq_cq_id;
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u16 rq_num_pages;
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u16 xrcd_id;
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dma_addr_t rq_pbl_ptr;
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void *irq;
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dma_addr_t irq_phys_addr;
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u8 irq_num_pages;
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bool resp_offloaded;
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u32 cq_prod;
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bool has_resp;
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u8 remote_mac_addr[6];
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u8 local_mac_addr[6];
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void *shared_queue;
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dma_addr_t shared_queue_phys_addr;
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struct qed_iwarp_ep *ep;
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u8 edpm_mode;
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};
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static inline bool qed_rdma_is_xrc_qp(struct qed_rdma_qp *qp)
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{
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if (qp->qp_type == QED_RDMA_QP_TYPE_XRC_TGT ||
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qp->qp_type == QED_RDMA_QP_TYPE_XRC_INI)
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return true;
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return false;
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}
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#if IS_ENABLED(CONFIG_QED_RDMA)
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void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
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void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
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int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn);
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void qed_rdma_info_free(struct qed_hwfn *p_hwfn);
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#else
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static inline void qed_rdma_dpm_conf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) {}
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static inline void qed_rdma_dpm_bar(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt) {}
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static inline int qed_rdma_info_alloc(struct qed_hwfn *p_hwfn) {return -EINVAL;}
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static inline void qed_rdma_info_free(struct qed_hwfn *p_hwfn) {}
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#endif
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int
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qed_rdma_bmap_alloc(struct qed_hwfn *p_hwfn,
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struct qed_bmap *bmap, u32 max_count, char *name);
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void
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qed_rdma_bmap_free(struct qed_hwfn *p_hwfn, struct qed_bmap *bmap, bool check);
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int
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qed_rdma_bmap_alloc_id(struct qed_hwfn *p_hwfn,
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struct qed_bmap *bmap, u32 *id_num);
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void
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qed_bmap_set_id(struct qed_hwfn *p_hwfn, struct qed_bmap *bmap, u32 id_num);
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void
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qed_bmap_release_id(struct qed_hwfn *p_hwfn, struct qed_bmap *bmap, u32 id_num);
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int
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qed_bmap_test_id(struct qed_hwfn *p_hwfn, struct qed_bmap *bmap, u32 id_num);
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void qed_rdma_set_fw_mac(__le16 *p_fw_mac, const u8 *p_qed_mac);
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bool qed_rdma_allocated_qps(struct qed_hwfn *p_hwfn);
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#endif
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