// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/* QLogic qed NIC Driver
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* Copyright (c) 2015-2017 QLogic Corporation
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* Copyright (c) 2019-2020 Marvell International Ltd.
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*/
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#include <linux/types.h>
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#include "qed.h"
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#include "qed_dev_api.h"
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#include "qed_hw.h"
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#include "qed_l2.h"
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#include "qed_mcp.h"
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#include "qed_ptp.h"
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#include "qed_reg_addr.h"
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/* 16 nano second time quantas to wait before making a Drift adjustment */
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#define QED_DRIFT_CNTR_TIME_QUANTA_SHIFT 0
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/* Nano seconds to add/subtract when making a Drift adjustment */
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#define QED_DRIFT_CNTR_ADJUSTMENT_SHIFT 28
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/* Add/subtract the Adjustment_Value when making a Drift adjustment */
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#define QED_DRIFT_CNTR_DIRECTION_SHIFT 31
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#define QED_TIMESTAMP_MASK BIT(16)
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/* Param mask for Hardware to detect/timestamp the L2/L4 unicast PTP packets */
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#define QED_PTP_UCAST_PARAM_MASK 0x70F
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static enum qed_resc_lock qed_ptcdev_to_resc(struct qed_hwfn *p_hwfn)
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{
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switch (MFW_PORT(p_hwfn)) {
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case 0:
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return QED_RESC_LOCK_PTP_PORT0;
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case 1:
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return QED_RESC_LOCK_PTP_PORT1;
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case 2:
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return QED_RESC_LOCK_PTP_PORT2;
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case 3:
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return QED_RESC_LOCK_PTP_PORT3;
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default:
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return QED_RESC_LOCK_RESC_INVALID;
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}
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}
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static int qed_ptp_res_lock(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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struct qed_resc_lock_params params;
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enum qed_resc_lock resource;
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int rc;
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resource = qed_ptcdev_to_resc(p_hwfn);
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if (resource == QED_RESC_LOCK_RESC_INVALID)
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return -EINVAL;
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qed_mcp_resc_lock_default_init(¶ms, NULL, resource, true);
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rc = qed_mcp_resc_lock(p_hwfn, p_ptt, ¶ms);
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if (rc && rc != -EINVAL) {
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return rc;
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} else if (rc == -EINVAL) {
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/* MFW doesn't support resource locking, first PF on the port
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* has lock ownership.
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*/
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if (p_hwfn->abs_pf_id < p_hwfn->cdev->num_ports_in_engine)
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return 0;
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DP_INFO(p_hwfn, "PF doesn't have lock ownership\n");
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return -EBUSY;
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} else if (!rc && !params.b_granted) {
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DP_INFO(p_hwfn, "Failed to acquire ptp resource lock\n");
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return -EBUSY;
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}
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return rc;
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}
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static int qed_ptp_res_unlock(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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struct qed_resc_unlock_params params;
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enum qed_resc_lock resource;
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int rc;
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resource = qed_ptcdev_to_resc(p_hwfn);
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if (resource == QED_RESC_LOCK_RESC_INVALID)
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return -EINVAL;
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qed_mcp_resc_lock_default_init(NULL, ¶ms, resource, true);
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rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, ¶ms);
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if (rc == -EINVAL) {
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/* MFW doesn't support locking, first PF has lock ownership */
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if (p_hwfn->abs_pf_id < p_hwfn->cdev->num_ports_in_engine) {
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rc = 0;
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} else {
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DP_INFO(p_hwfn, "PF doesn't have lock ownership\n");
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return -EINVAL;
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}
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} else if (rc) {
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DP_INFO(p_hwfn, "Failed to release the ptp resource lock\n");
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}
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return rc;
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}
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/* Read Rx timestamp */
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static int qed_ptp_hw_read_rx_ts(struct qed_dev *cdev, u64 *timestamp)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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u32 val;
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*timestamp = 0;
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val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID);
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if (!(val & QED_TIMESTAMP_MASK)) {
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DP_INFO(p_hwfn, "Invalid Rx timestamp, buf_seqid = %d\n", val);
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return -EINVAL;
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}
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val = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_LSB);
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*timestamp = qed_rd(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_TS_MSB);
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*timestamp <<= 32;
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*timestamp |= val;
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/* Reset timestamp register to allow new timestamp */
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
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QED_TIMESTAMP_MASK);
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return 0;
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}
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/* Read Tx timestamp */
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static int qed_ptp_hw_read_tx_ts(struct qed_dev *cdev, u64 *timestamp)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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u32 val;
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*timestamp = 0;
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val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID);
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if (!(val & QED_TIMESTAMP_MASK)) {
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DP_VERBOSE(p_hwfn, QED_MSG_DEBUG,
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"Invalid Tx timestamp, buf_seqid = %08x\n", val);
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return -EINVAL;
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}
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val = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_LSB);
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*timestamp = qed_rd(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_TS_MSB);
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*timestamp <<= 32;
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*timestamp |= val;
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/* Reset timestamp register to allow new timestamp */
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID, QED_TIMESTAMP_MASK);
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return 0;
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}
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/* Read Phy Hardware Clock */
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static int qed_ptp_hw_read_cc(struct qed_dev *cdev, u64 *phc_cycles)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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u32 temp = 0;
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temp = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_LSB);
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*phc_cycles = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_SYNC_TIME_MSB);
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*phc_cycles <<= 32;
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*phc_cycles |= temp;
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return 0;
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}
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/* Filter PTP protocol packets that need to be timestamped */
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static int qed_ptp_hw_cfg_filters(struct qed_dev *cdev,
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enum qed_ptp_filter_type rx_type,
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enum qed_ptp_hwtstamp_tx_type tx_type)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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u32 rule_mask, enable_cfg = 0x0;
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switch (rx_type) {
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case QED_PTP_FILTER_NONE:
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enable_cfg = 0x0;
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rule_mask = 0x3FFF;
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break;
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case QED_PTP_FILTER_ALL:
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enable_cfg = 0x7;
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rule_mask = 0x3CAA;
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break;
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case QED_PTP_FILTER_V1_L4_EVENT:
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enable_cfg = 0x3;
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rule_mask = 0x3FFA;
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break;
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case QED_PTP_FILTER_V1_L4_GEN:
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enable_cfg = 0x3;
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rule_mask = 0x3FFE;
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break;
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case QED_PTP_FILTER_V2_L4_EVENT:
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enable_cfg = 0x5;
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rule_mask = 0x3FAA;
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break;
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case QED_PTP_FILTER_V2_L4_GEN:
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enable_cfg = 0x5;
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rule_mask = 0x3FEE;
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break;
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case QED_PTP_FILTER_V2_L2_EVENT:
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enable_cfg = 0x5;
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rule_mask = 0x3CFF;
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break;
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case QED_PTP_FILTER_V2_L2_GEN:
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enable_cfg = 0x5;
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rule_mask = 0x3EFF;
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break;
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case QED_PTP_FILTER_V2_EVENT:
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enable_cfg = 0x5;
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rule_mask = 0x3CAA;
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break;
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case QED_PTP_FILTER_V2_GEN:
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enable_cfg = 0x5;
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rule_mask = 0x3EEE;
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break;
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default:
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DP_INFO(p_hwfn, "Invalid PTP filter type %d\n", rx_type);
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return -EINVAL;
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}
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK,
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QED_PTP_UCAST_PARAM_MASK);
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, rule_mask);
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qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, enable_cfg);
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if (tx_type == QED_PTP_HWTSTAMP_TX_OFF) {
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 0x0);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
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} else {
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, enable_cfg);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK,
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QED_PTP_UCAST_PARAM_MASK);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, rule_mask);
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}
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/* Reset possibly old timestamps */
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
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QED_TIMESTAMP_MASK);
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return 0;
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}
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/* Adjust the HW clock by a rate given in parts-per-billion (ppb) units.
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* FW/HW accepts the adjustment value in terms of 3 parameters:
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* Drift period - adjustment happens once in certain number of nano seconds.
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* Drift value - time is adjusted by a certain value, for example by 5 ns.
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* Drift direction - add or subtract the adjustment value.
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* The routine translates ppb into the adjustment triplet in an optimal manner.
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*/
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static int qed_ptp_hw_adjfreq(struct qed_dev *cdev, s32 ppb)
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{
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s64 best_val = 0, val, best_period = 0, period, approx_dev, dif, dif2;
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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u32 drift_ctr_cfg = 0, drift_state;
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int drift_dir = 1;
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if (ppb < 0) {
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ppb = -ppb;
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drift_dir = 0;
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}
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if (ppb > 1) {
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s64 best_dif = ppb, best_approx_dev = 1;
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/* Adjustment value is up to +/-7ns, find an optimal value in
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* this range.
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*/
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for (val = 7; val > 0; val--) {
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period = div_s64(val * 1000000000, ppb);
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period -= 8;
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period >>= 4;
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if (period < 1)
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period = 1;
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if (period > 0xFFFFFFE)
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period = 0xFFFFFFE;
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/* Check both rounding ends for approximate error */
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approx_dev = period * 16 + 8;
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dif = ppb * approx_dev - val * 1000000000;
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dif2 = dif + 16 * ppb;
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if (dif < 0)
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dif = -dif;
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if (dif2 < 0)
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dif2 = -dif2;
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/* Determine which end gives better approximation */
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if (dif * (approx_dev + 16) > dif2 * approx_dev) {
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period++;
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approx_dev += 16;
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dif = dif2;
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}
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/* Track best approximation found so far */
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if (best_dif * approx_dev > dif * best_approx_dev) {
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best_dif = dif;
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best_val = val;
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best_period = period;
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best_approx_dev = approx_dev;
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}
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}
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} else if (ppb == 1) {
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/* This is a special case as its the only value which wouldn't
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* fit in a s64 variable. In order to prevent castings simple
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* handle it seperately.
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*/
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best_val = 4;
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best_period = 0xee6b27f;
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} else {
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best_val = 0;
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best_period = 0xFFFFFFF;
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}
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drift_ctr_cfg = (best_period << QED_DRIFT_CNTR_TIME_QUANTA_SHIFT) |
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(((int)best_val) << QED_DRIFT_CNTR_ADJUSTMENT_SHIFT) |
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(((int)drift_dir) << QED_DRIFT_CNTR_DIRECTION_SHIFT);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x1);
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drift_state = qed_rd(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR);
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if (drift_state & 1) {
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_DRIFT_CNTR_CONF,
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drift_ctr_cfg);
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} else {
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DP_INFO(p_hwfn, "Drift counter is not reset\n");
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return -EINVAL;
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}
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x0);
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return 0;
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}
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static int qed_ptp_hw_enable(struct qed_dev *cdev)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt;
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int rc;
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p_ptt = qed_ptt_acquire(p_hwfn);
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if (!p_ptt) {
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DP_NOTICE(p_hwfn, "Failed to acquire PTT for PTP\n");
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return -EBUSY;
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}
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p_hwfn->p_ptp_ptt = p_ptt;
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rc = qed_ptp_res_lock(p_hwfn, p_ptt);
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if (rc) {
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DP_INFO(p_hwfn,
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"Couldn't acquire the resource lock, skip ptp enable for this PF\n");
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qed_ptt_release(p_hwfn, p_ptt);
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p_hwfn->p_ptp_ptt = NULL;
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return rc;
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}
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/* Reset PTP event detection rules - will be configured in the IOCTL */
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0x7FF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, 0x3FFF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 7);
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qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, 7);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TS_OUTPUT_ENABLE_PDA, 0x1);
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/* Pause free running counter */
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if (QED_IS_BB_B0(p_hwfn->cdev))
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qed_wr(p_hwfn, p_ptt, NIG_REG_TIMESYNC_GEN_REG_BB, 2);
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if (QED_IS_AH(p_hwfn->cdev))
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREECNT_UPDATE_K2, 2);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREE_CNT_VALUE_LSB, 0);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREE_CNT_VALUE_MSB, 0);
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/* Resume free running counter */
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if (QED_IS_BB_B0(p_hwfn->cdev))
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qed_wr(p_hwfn, p_ptt, NIG_REG_TIMESYNC_GEN_REG_BB, 4);
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if (QED_IS_AH(p_hwfn->cdev)) {
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_FREECNT_UPDATE_K2, 4);
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qed_wr(p_hwfn, p_ptt, NIG_REG_PTP_LATCH_OSTS_PKT_TIME, 1);
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}
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/* Disable drift register */
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_DRIFT_CNTR_CONF, 0x0);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TSGEN_RST_DRIFT_CNTR, 0x0);
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/* Reset possibly old timestamps */
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_HOST_BUF_SEQID,
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QED_TIMESTAMP_MASK);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_BUF_SEQID, QED_TIMESTAMP_MASK);
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return 0;
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}
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static int qed_ptp_hw_disable(struct qed_dev *cdev)
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{
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struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
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struct qed_ptt *p_ptt = p_hwfn->p_ptp_ptt;
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qed_ptp_res_unlock(p_hwfn, p_ptt);
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/* Reset PTP event detection rules */
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_PARAM_MASK, 0x7FF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_PTP_RULE_MASK, 0x3FFF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_PARAM_MASK, 0x7FF);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_LLH_PTP_RULE_MASK, 0x3FFF);
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/* Disable the PTP feature */
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qed_wr(p_hwfn, p_ptt, NIG_REG_RX_PTP_EN, 0x0);
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qed_wr(p_hwfn, p_ptt, NIG_REG_TX_PTP_EN, 0x0);
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qed_ptt_release(p_hwfn, p_ptt);
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p_hwfn->p_ptp_ptt = NULL;
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return 0;
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}
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const struct qed_eth_ptp_ops qed_ptp_ops_pass = {
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.cfg_filters = qed_ptp_hw_cfg_filters,
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.read_rx_ts = qed_ptp_hw_read_rx_ts,
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.read_tx_ts = qed_ptp_hw_read_tx_ts,
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.read_cc = qed_ptp_hw_read_cc,
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.adjfreq = qed_ptp_hw_adjfreq,
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.disable = qed_ptp_hw_disable,
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.enable = qed_ptp_hw_enable,
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};
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