// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/* QLogic qed NIC Driver
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* Copyright (c) 2015-2017 QLogic Corporation
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* Copyright (c) 2019-2020 Marvell International Ltd.
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*/
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include "qed.h"
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#include "qed_hsi.h"
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#include "qed_hw.h"
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#include "qed_init_ops.h"
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#include "qed_reg_addr.h"
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#include "qed_sriov.h"
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#define QED_INIT_MAX_POLL_COUNT 100
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#define QED_INIT_POLL_PERIOD_US 500
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static u32 pxp_global_win[] = {
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0,
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0,
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0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
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0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
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0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
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0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
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0x1d02, /* win 6: addr=0x1d02000, size=4096 bytes */
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0x1d80, /* win 7: addr=0x1d80000, size=4096 bytes */
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0x1d81, /* win 8: addr=0x1d81000, size=4096 bytes */
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0x1d82, /* win 9: addr=0x1d82000, size=4096 bytes */
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0x1e00, /* win 10: addr=0x1e00000, size=4096 bytes */
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0x1e01, /* win 11: addr=0x1e01000, size=4096 bytes */
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0x1e80, /* win 12: addr=0x1e80000, size=4096 bytes */
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0x1f00, /* win 13: addr=0x1f00000, size=4096 bytes */
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0x1c08, /* win 14: addr=0x1c08000, size=4096 bytes */
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0,
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0,
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0,
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0,
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};
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/* IRO Array */
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static const u32 iro_arr[] = {
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0x00000000, 0x00000000, 0x00080000,
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0x00003288, 0x00000088, 0x00880000,
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0x000058e8, 0x00000020, 0x00200000,
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0x00000b00, 0x00000008, 0x00040000,
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0x00000a80, 0x00000008, 0x00040000,
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0x00000000, 0x00000008, 0x00020000,
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0x00000080, 0x00000008, 0x00040000,
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0x00000084, 0x00000008, 0x00020000,
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0x00005718, 0x00000004, 0x00040000,
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0x00004dd0, 0x00000000, 0x00780000,
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0x00003e40, 0x00000000, 0x00780000,
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0x00004480, 0x00000000, 0x00780000,
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0x00003210, 0x00000000, 0x00780000,
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0x00003b50, 0x00000000, 0x00780000,
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0x00007f58, 0x00000000, 0x00780000,
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0x00005f58, 0x00000000, 0x00080000,
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0x00007100, 0x00000000, 0x00080000,
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0x0000aea0, 0x00000000, 0x00080000,
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0x00004398, 0x00000000, 0x00080000,
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0x0000a5a0, 0x00000000, 0x00080000,
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0x0000bde8, 0x00000000, 0x00080000,
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0x00000020, 0x00000004, 0x00040000,
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0x000056c8, 0x00000010, 0x00100000,
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0x0000c210, 0x00000030, 0x00300000,
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0x0000b088, 0x00000038, 0x00380000,
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0x00003d20, 0x00000080, 0x00400000,
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0x0000bf60, 0x00000000, 0x00040000,
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0x00004560, 0x00040080, 0x00040000,
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0x000001f8, 0x00000004, 0x00040000,
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0x00003d60, 0x00000080, 0x00200000,
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0x00008960, 0x00000040, 0x00300000,
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0x0000e840, 0x00000060, 0x00600000,
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0x00004618, 0x00000080, 0x00380000,
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0x00010738, 0x000000c0, 0x00c00000,
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0x000001f8, 0x00000002, 0x00020000,
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0x0000a2a0, 0x00000000, 0x01080000,
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0x0000a3a8, 0x00000008, 0x00080000,
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0x000001c0, 0x00000008, 0x00080000,
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0x000001f8, 0x00000008, 0x00080000,
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0x00000ac0, 0x00000008, 0x00080000,
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0x00002578, 0x00000008, 0x00080000,
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0x000024f8, 0x00000008, 0x00080000,
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0x00000280, 0x00000008, 0x00080000,
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0x00000680, 0x00080018, 0x00080000,
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0x00000b78, 0x00080018, 0x00020000,
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0x0000c640, 0x00000050, 0x003c0000,
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0x00012038, 0x00000018, 0x00100000,
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0x00011b00, 0x00000040, 0x00180000,
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0x000095d0, 0x00000050, 0x00200000,
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0x00008b10, 0x00000040, 0x00280000,
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0x00011640, 0x00000018, 0x00100000,
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0x0000c828, 0x00000048, 0x00380000,
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0x00011710, 0x00000020, 0x00200000,
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0x00004650, 0x00000080, 0x00100000,
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0x00003618, 0x00000010, 0x00100000,
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0x0000a968, 0x00000008, 0x00010000,
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0x000097a0, 0x00000008, 0x00010000,
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0x00011990, 0x00000008, 0x00010000,
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0x0000f018, 0x00000008, 0x00010000,
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0x00012628, 0x00000008, 0x00010000,
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0x00011da8, 0x00000008, 0x00010000,
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0x0000aa78, 0x00000030, 0x00100000,
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0x0000d768, 0x00000028, 0x00280000,
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0x00009a58, 0x00000018, 0x00180000,
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0x00009bd8, 0x00000008, 0x00080000,
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0x00013a18, 0x00000008, 0x00080000,
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0x000126e8, 0x00000018, 0x00180000,
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0x0000e608, 0x00500288, 0x00100000,
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0x00012970, 0x00000138, 0x00280000,
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};
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void qed_init_iro_array(struct qed_dev *cdev)
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{
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cdev->iro_arr = iro_arr;
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}
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void qed_init_store_rt_reg(struct qed_hwfn *p_hwfn, u32 rt_offset, u32 val)
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{
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p_hwfn->rt_data.init_val[rt_offset] = val;
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p_hwfn->rt_data.b_valid[rt_offset] = true;
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}
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void qed_init_store_rt_agg(struct qed_hwfn *p_hwfn,
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u32 rt_offset, u32 *p_val, size_t size)
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{
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size_t i;
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for (i = 0; i < size / sizeof(u32); i++) {
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p_hwfn->rt_data.init_val[rt_offset + i] = p_val[i];
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p_hwfn->rt_data.b_valid[rt_offset + i] = true;
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}
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}
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static int qed_init_rt(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 addr, u16 rt_offset, u16 size, bool b_must_dmae)
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{
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u32 *p_init_val = &p_hwfn->rt_data.init_val[rt_offset];
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bool *p_valid = &p_hwfn->rt_data.b_valid[rt_offset];
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u16 i, j, segment;
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int rc = 0;
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/* Since not all RT entries are initialized, go over the RT and
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* for each segment of initialized values use DMA.
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*/
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for (i = 0; i < size; i++) {
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if (!p_valid[i])
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continue;
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/* In case there isn't any wide-bus configuration here,
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* simply write the data instead of using dmae.
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*/
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if (!b_must_dmae) {
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qed_wr(p_hwfn, p_ptt, addr + (i << 2), p_init_val[i]);
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p_valid[i] = false;
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continue;
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}
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/* Start of a new segment */
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for (segment = 1; i + segment < size; segment++)
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if (!p_valid[i + segment])
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break;
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rc = qed_dmae_host2grc(p_hwfn, p_ptt,
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(uintptr_t)(p_init_val + i),
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addr + (i << 2), segment, NULL);
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if (rc)
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return rc;
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/* invalidate after writing */
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for (j = i; j < i + segment; j++)
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p_valid[j] = false;
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/* Jump over the entire segment, including invalid entry */
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i += segment;
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}
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return rc;
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}
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int qed_init_alloc(struct qed_hwfn *p_hwfn)
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{
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struct qed_rt_data *rt_data = &p_hwfn->rt_data;
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if (IS_VF(p_hwfn->cdev))
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return 0;
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rt_data->b_valid = kcalloc(RUNTIME_ARRAY_SIZE, sizeof(bool),
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GFP_KERNEL);
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if (!rt_data->b_valid)
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return -ENOMEM;
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rt_data->init_val = kcalloc(RUNTIME_ARRAY_SIZE, sizeof(u32),
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GFP_KERNEL);
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if (!rt_data->init_val) {
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kfree(rt_data->b_valid);
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rt_data->b_valid = NULL;
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return -ENOMEM;
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}
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return 0;
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}
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void qed_init_free(struct qed_hwfn *p_hwfn)
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{
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kfree(p_hwfn->rt_data.init_val);
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p_hwfn->rt_data.init_val = NULL;
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kfree(p_hwfn->rt_data.b_valid);
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p_hwfn->rt_data.b_valid = NULL;
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}
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static int qed_init_array_dmae(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 addr,
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u32 dmae_data_offset,
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u32 size,
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const u32 *buf,
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bool b_must_dmae,
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bool b_can_dmae)
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{
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int rc = 0;
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/* Perform DMAE only for lengthy enough sections or for wide-bus */
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if (!b_can_dmae || (!b_must_dmae && (size < 16))) {
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const u32 *data = buf + dmae_data_offset;
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u32 i;
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for (i = 0; i < size; i++)
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qed_wr(p_hwfn, p_ptt, addr + (i << 2), data[i]);
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} else {
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rc = qed_dmae_host2grc(p_hwfn, p_ptt,
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(uintptr_t)(buf + dmae_data_offset),
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addr, size, NULL);
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}
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return rc;
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}
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static int qed_init_fill_dmae(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 addr, u32 fill, u32 fill_count)
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{
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static u32 zero_buffer[DMAE_MAX_RW_SIZE];
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struct qed_dmae_params params = {};
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memset(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);
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/* invoke the DMAE virtual/physical buffer API with
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* 1. DMAE init channel
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* 2. addr,
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* 3. p_hwfb->temp_data,
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* 4. fill_count
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*/
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SET_FIELD(params.flags, QED_DMAE_PARAMS_RW_REPL_SRC, 0x1);
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return qed_dmae_host2grc(p_hwfn, p_ptt,
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(uintptr_t)(&zero_buffer[0]),
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addr, fill_count, ¶ms);
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}
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static void qed_init_fill(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 addr, u32 fill, u32 fill_count)
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{
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u32 i;
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for (i = 0; i < fill_count; i++, addr += sizeof(u32))
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qed_wr(p_hwfn, p_ptt, addr, fill);
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}
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static int qed_init_cmd_array(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct init_write_op *cmd,
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bool b_must_dmae, bool b_can_dmae)
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{
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u32 dmae_array_offset = le32_to_cpu(cmd->args.array_offset);
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u32 data = le32_to_cpu(cmd->data);
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u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
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u32 offset, output_len, input_len, max_size;
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struct qed_dev *cdev = p_hwfn->cdev;
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union init_array_hdr *hdr;
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const u32 *array_data;
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int rc = 0;
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u32 size;
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array_data = cdev->fw_data->arr_data;
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hdr = (union init_array_hdr *)(array_data + dmae_array_offset);
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data = le32_to_cpu(hdr->raw.data);
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switch (GET_FIELD(data, INIT_ARRAY_RAW_HDR_TYPE)) {
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case INIT_ARR_ZIPPED:
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offset = dmae_array_offset + 1;
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input_len = GET_FIELD(data,
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INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE);
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max_size = MAX_ZIPPED_SIZE * 4;
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memset(p_hwfn->unzip_buf, 0, max_size);
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output_len = qed_unzip_data(p_hwfn, input_len,
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(u8 *)&array_data[offset],
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max_size, (u8 *)p_hwfn->unzip_buf);
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if (output_len) {
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rc = qed_init_array_dmae(p_hwfn, p_ptt, addr, 0,
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output_len,
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p_hwfn->unzip_buf,
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b_must_dmae, b_can_dmae);
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} else {
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DP_NOTICE(p_hwfn, "Failed to unzip dmae data\n");
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rc = -EINVAL;
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}
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break;
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case INIT_ARR_PATTERN:
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{
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u32 repeats = GET_FIELD(data,
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INIT_ARRAY_PATTERN_HDR_REPETITIONS);
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u32 i;
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size = GET_FIELD(data, INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE);
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for (i = 0; i < repeats; i++, addr += size << 2) {
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rc = qed_init_array_dmae(p_hwfn, p_ptt, addr,
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dmae_array_offset + 1,
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size, array_data,
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b_must_dmae, b_can_dmae);
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if (rc)
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break;
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}
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break;
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}
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case INIT_ARR_STANDARD:
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size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE);
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rc = qed_init_array_dmae(p_hwfn, p_ptt, addr,
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dmae_array_offset + 1,
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size, array_data,
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b_must_dmae, b_can_dmae);
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break;
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}
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return rc;
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}
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/* init_ops write command */
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static int qed_init_cmd_wr(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct init_write_op *p_cmd, bool b_can_dmae)
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{
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u32 data = le32_to_cpu(p_cmd->data);
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bool b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS);
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u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2;
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union init_write_args *arg = &p_cmd->args;
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int rc = 0;
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/* Sanitize */
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if (b_must_dmae && !b_can_dmae) {
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DP_NOTICE(p_hwfn,
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"Need to write to %08x for Wide-bus but DMAE isn't allowed\n",
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addr);
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return -EINVAL;
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}
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switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) {
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case INIT_SRC_INLINE:
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data = le32_to_cpu(p_cmd->args.inline_val);
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qed_wr(p_hwfn, p_ptt, addr, data);
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break;
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case INIT_SRC_ZEROS:
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data = le32_to_cpu(p_cmd->args.zeros_count);
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if (b_must_dmae || (b_can_dmae && (data >= 64)))
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rc = qed_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data);
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else
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qed_init_fill(p_hwfn, p_ptt, addr, 0, data);
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break;
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case INIT_SRC_ARRAY:
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rc = qed_init_cmd_array(p_hwfn, p_ptt, p_cmd,
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b_must_dmae, b_can_dmae);
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break;
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case INIT_SRC_RUNTIME:
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qed_init_rt(p_hwfn, p_ptt, addr,
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le16_to_cpu(arg->runtime.offset),
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le16_to_cpu(arg->runtime.size),
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b_must_dmae);
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break;
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}
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return rc;
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}
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static inline bool comp_eq(u32 val, u32 expected_val)
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{
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return val == expected_val;
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}
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static inline bool comp_and(u32 val, u32 expected_val)
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{
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return (val & expected_val) == expected_val;
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}
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static inline bool comp_or(u32 val, u32 expected_val)
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{
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return (val | expected_val) > 0;
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}
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/* init_ops read/poll commands */
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static void qed_init_cmd_rd(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, struct init_read_op *cmd)
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{
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bool (*comp_check)(u32 val, u32 expected_val);
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u32 delay = QED_INIT_POLL_PERIOD_US, val;
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u32 data, addr, poll;
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int i;
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data = le32_to_cpu(cmd->op_data);
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addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2;
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poll = GET_FIELD(data, INIT_READ_OP_POLL_TYPE);
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|
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val = qed_rd(p_hwfn, p_ptt, addr);
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if (poll == INIT_POLL_NONE)
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return;
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switch (poll) {
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case INIT_POLL_EQ:
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comp_check = comp_eq;
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break;
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case INIT_POLL_OR:
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comp_check = comp_or;
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break;
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case INIT_POLL_AND:
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comp_check = comp_and;
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break;
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default:
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DP_ERR(p_hwfn, "Invalid poll comparison type %08x\n",
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cmd->op_data);
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return;
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}
|
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data = le32_to_cpu(cmd->expected_val);
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for (i = 0;
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i < QED_INIT_MAX_POLL_COUNT && !comp_check(val, data);
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i++) {
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udelay(delay);
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val = qed_rd(p_hwfn, p_ptt, addr);
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}
|
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if (i == QED_INIT_MAX_POLL_COUNT) {
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DP_ERR(p_hwfn,
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"Timeout when polling reg: 0x%08x [ Waiting-for: %08x Got: %08x (comparison %08x)]\n",
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addr, le32_to_cpu(cmd->expected_val),
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val, le32_to_cpu(cmd->op_data));
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}
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}
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/* init_ops callbacks entry point */
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static int qed_init_cmd_cb(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct init_callback_op *p_cmd)
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{
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int rc;
|
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switch (p_cmd->callback_id) {
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case DMAE_READY_CB:
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rc = qed_dmae_sanity(p_hwfn, p_ptt, "engine_phase");
|
break;
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default:
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DP_NOTICE(p_hwfn, "Unexpected init op callback ID %d\n",
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p_cmd->callback_id);
|
return -EINVAL;
|
}
|
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return rc;
|
}
|
|
static u8 qed_init_cmd_mode_match(struct qed_hwfn *p_hwfn,
|
u16 *p_offset, int modes)
|
{
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struct qed_dev *cdev = p_hwfn->cdev;
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const u8 *modes_tree_buf;
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u8 arg1, arg2, tree_val;
|
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modes_tree_buf = cdev->fw_data->modes_tree_buf;
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tree_val = modes_tree_buf[(*p_offset)++];
|
switch (tree_val) {
|
case INIT_MODE_OP_NOT:
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return qed_init_cmd_mode_match(p_hwfn, p_offset, modes) ^ 1;
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case INIT_MODE_OP_OR:
|
arg1 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
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arg2 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
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return arg1 | arg2;
|
case INIT_MODE_OP_AND:
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arg1 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
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arg2 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes);
|
return arg1 & arg2;
|
default:
|
tree_val -= MAX_INIT_MODE_OPS;
|
return (modes & BIT(tree_val)) ? 1 : 0;
|
}
|
}
|
|
static u32 qed_init_cmd_mode(struct qed_hwfn *p_hwfn,
|
struct init_if_mode_op *p_cmd, int modes)
|
{
|
u16 offset = le16_to_cpu(p_cmd->modes_buf_offset);
|
|
if (qed_init_cmd_mode_match(p_hwfn, &offset, modes))
|
return 0;
|
else
|
return GET_FIELD(le32_to_cpu(p_cmd->op_data),
|
INIT_IF_MODE_OP_CMD_OFFSET);
|
}
|
|
static u32 qed_init_cmd_phase(struct qed_hwfn *p_hwfn,
|
struct init_if_phase_op *p_cmd,
|
u32 phase, u32 phase_id)
|
{
|
u32 data = le32_to_cpu(p_cmd->phase_data);
|
u32 op_data = le32_to_cpu(p_cmd->op_data);
|
|
if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase &&
|
(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID ||
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GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id)))
|
return GET_FIELD(op_data, INIT_IF_PHASE_OP_CMD_OFFSET);
|
else
|
return 0;
|
}
|
|
int qed_init_run(struct qed_hwfn *p_hwfn,
|
struct qed_ptt *p_ptt, int phase, int phase_id, int modes)
|
{
|
bool b_dmae = (phase != PHASE_ENGINE);
|
struct qed_dev *cdev = p_hwfn->cdev;
|
u32 cmd_num, num_init_ops;
|
union init_op *init_ops;
|
int rc = 0;
|
|
num_init_ops = cdev->fw_data->init_ops_size;
|
init_ops = cdev->fw_data->init_ops;
|
|
p_hwfn->unzip_buf = kzalloc(MAX_ZIPPED_SIZE * 4, GFP_ATOMIC);
|
if (!p_hwfn->unzip_buf)
|
return -ENOMEM;
|
|
for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) {
|
union init_op *cmd = &init_ops[cmd_num];
|
u32 data = le32_to_cpu(cmd->raw.op_data);
|
|
switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) {
|
case INIT_OP_WRITE:
|
rc = qed_init_cmd_wr(p_hwfn, p_ptt, &cmd->write,
|
b_dmae);
|
break;
|
case INIT_OP_READ:
|
qed_init_cmd_rd(p_hwfn, p_ptt, &cmd->read);
|
break;
|
case INIT_OP_IF_MODE:
|
cmd_num += qed_init_cmd_mode(p_hwfn, &cmd->if_mode,
|
modes);
|
break;
|
case INIT_OP_IF_PHASE:
|
cmd_num += qed_init_cmd_phase(p_hwfn, &cmd->if_phase,
|
phase, phase_id);
|
break;
|
case INIT_OP_DELAY:
|
/* qed_init_run is always invoked from
|
* sleep-able context
|
*/
|
udelay(le32_to_cpu(cmd->delay.delay));
|
break;
|
|
case INIT_OP_CALLBACK:
|
rc = qed_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback);
|
if (phase == PHASE_ENGINE &&
|
cmd->callback.callback_id == DMAE_READY_CB)
|
b_dmae = true;
|
break;
|
}
|
|
if (rc)
|
break;
|
}
|
|
kfree(p_hwfn->unzip_buf);
|
p_hwfn->unzip_buf = NULL;
|
return rc;
|
}
|
|
void qed_gtt_init(struct qed_hwfn *p_hwfn)
|
{
|
u32 gtt_base;
|
u32 i;
|
|
/* Set the global windows */
|
gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START;
|
|
for (i = 0; i < ARRAY_SIZE(pxp_global_win); i++)
|
if (pxp_global_win[i])
|
REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
|
pxp_global_win[i]);
|
}
|
|
int qed_init_fw_data(struct qed_dev *cdev, const u8 *data)
|
{
|
struct qed_fw_data *fw = cdev->fw_data;
|
struct bin_buffer_hdr *buf_hdr;
|
u32 offset, len;
|
|
if (!data) {
|
DP_NOTICE(cdev, "Invalid fw data\n");
|
return -EINVAL;
|
}
|
|
/* First Dword contains metadata and should be skipped */
|
buf_hdr = (struct bin_buffer_hdr *)data;
|
|
offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;
|
fw->fw_ver_info = (struct fw_ver_info *)(data + offset);
|
|
offset = buf_hdr[BIN_BUF_INIT_CMD].offset;
|
fw->init_ops = (union init_op *)(data + offset);
|
|
offset = buf_hdr[BIN_BUF_INIT_VAL].offset;
|
fw->arr_data = (u32 *)(data + offset);
|
|
offset = buf_hdr[BIN_BUF_INIT_MODE_TREE].offset;
|
fw->modes_tree_buf = (u8 *)(data + offset);
|
len = buf_hdr[BIN_BUF_INIT_CMD].length;
|
fw->init_ops_size = len / sizeof(struct init_raw_op);
|
|
offset = buf_hdr[BIN_BUF_INIT_OVERLAYS].offset;
|
fw->fw_overlays = (u32 *)(data + offset);
|
len = buf_hdr[BIN_BUF_INIT_OVERLAYS].length;
|
fw->fw_overlays_len = len;
|
|
return 0;
|
}
|
