// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/* QLogic qed NIC Driver
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* Copyright (c) 2015-2017 QLogic Corporation
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* Copyright (c) 2019-2020 Marvell International Ltd.
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*/
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/qed/qed_chain.h>
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#include "qed.h"
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#include "qed_hsi.h"
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#include "qed_hw.h"
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#include "qed_reg_addr.h"
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#include "qed_sriov.h"
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#define QED_BAR_ACQUIRE_TIMEOUT 1000
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/* Invalid values */
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#define QED_BAR_INVALID_OFFSET (cpu_to_le32(-1))
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struct qed_ptt {
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struct list_head list_entry;
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unsigned int idx;
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struct pxp_ptt_entry pxp;
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u8 hwfn_id;
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};
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struct qed_ptt_pool {
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struct list_head free_list;
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spinlock_t lock; /* ptt synchronized access */
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struct qed_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM];
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};
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int qed_ptt_pool_alloc(struct qed_hwfn *p_hwfn)
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{
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struct qed_ptt_pool *p_pool = kmalloc(sizeof(*p_pool), GFP_KERNEL);
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int i;
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if (!p_pool)
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return -ENOMEM;
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INIT_LIST_HEAD(&p_pool->free_list);
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for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
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p_pool->ptts[i].idx = i;
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p_pool->ptts[i].pxp.offset = QED_BAR_INVALID_OFFSET;
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p_pool->ptts[i].pxp.pretend.control = 0;
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p_pool->ptts[i].hwfn_id = p_hwfn->my_id;
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if (i >= RESERVED_PTT_MAX)
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list_add(&p_pool->ptts[i].list_entry,
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&p_pool->free_list);
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}
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p_hwfn->p_ptt_pool = p_pool;
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spin_lock_init(&p_pool->lock);
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return 0;
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}
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void qed_ptt_invalidate(struct qed_hwfn *p_hwfn)
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{
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struct qed_ptt *p_ptt;
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int i;
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for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) {
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p_ptt = &p_hwfn->p_ptt_pool->ptts[i];
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p_ptt->pxp.offset = QED_BAR_INVALID_OFFSET;
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}
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}
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void qed_ptt_pool_free(struct qed_hwfn *p_hwfn)
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{
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kfree(p_hwfn->p_ptt_pool);
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p_hwfn->p_ptt_pool = NULL;
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}
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struct qed_ptt *qed_ptt_acquire(struct qed_hwfn *p_hwfn)
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{
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struct qed_ptt *p_ptt;
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unsigned int i;
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/* Take the free PTT from the list */
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for (i = 0; i < QED_BAR_ACQUIRE_TIMEOUT; i++) {
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spin_lock_bh(&p_hwfn->p_ptt_pool->lock);
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if (!list_empty(&p_hwfn->p_ptt_pool->free_list)) {
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p_ptt = list_first_entry(&p_hwfn->p_ptt_pool->free_list,
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struct qed_ptt, list_entry);
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list_del(&p_ptt->list_entry);
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spin_unlock_bh(&p_hwfn->p_ptt_pool->lock);
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DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
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"allocated ptt %d\n", p_ptt->idx);
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return p_ptt;
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}
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spin_unlock_bh(&p_hwfn->p_ptt_pool->lock);
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usleep_range(1000, 2000);
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}
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DP_NOTICE(p_hwfn, "PTT acquire timeout - failed to allocate PTT\n");
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return NULL;
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}
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void qed_ptt_release(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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spin_lock_bh(&p_hwfn->p_ptt_pool->lock);
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list_add(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list);
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spin_unlock_bh(&p_hwfn->p_ptt_pool->lock);
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}
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u32 qed_ptt_get_hw_addr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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/* The HW is using DWORDS and we need to translate it to Bytes */
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return le32_to_cpu(p_ptt->pxp.offset) << 2;
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}
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static u32 qed_ptt_config_addr(struct qed_ptt *p_ptt)
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{
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return PXP_PF_WINDOW_ADMIN_PER_PF_START +
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p_ptt->idx * sizeof(struct pxp_ptt_entry);
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}
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u32 qed_ptt_get_bar_addr(struct qed_ptt *p_ptt)
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{
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return PXP_EXTERNAL_BAR_PF_WINDOW_START +
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p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE;
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}
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void qed_ptt_set_win(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u32 new_hw_addr)
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{
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u32 prev_hw_addr;
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prev_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt);
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if (new_hw_addr == prev_hw_addr)
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return;
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/* Update PTT entery in admin window */
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DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
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"Updating PTT entry %d to offset 0x%x\n",
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p_ptt->idx, new_hw_addr);
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/* The HW is using DWORDS and the address is in Bytes */
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p_ptt->pxp.offset = cpu_to_le32(new_hw_addr >> 2);
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REG_WR(p_hwfn,
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qed_ptt_config_addr(p_ptt) +
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offsetof(struct pxp_ptt_entry, offset),
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le32_to_cpu(p_ptt->pxp.offset));
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}
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static u32 qed_set_ptt(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u32 hw_addr)
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{
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u32 win_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt);
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u32 offset;
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offset = hw_addr - win_hw_addr;
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if (p_ptt->hwfn_id != p_hwfn->my_id)
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DP_NOTICE(p_hwfn,
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"ptt[%d] of hwfn[%02x] is used by hwfn[%02x]!\n",
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p_ptt->idx, p_ptt->hwfn_id, p_hwfn->my_id);
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/* Verify the address is within the window */
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if (hw_addr < win_hw_addr ||
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offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) {
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qed_ptt_set_win(p_hwfn, p_ptt, hw_addr);
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offset = 0;
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}
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return qed_ptt_get_bar_addr(p_ptt) + offset;
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}
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struct qed_ptt *qed_get_reserved_ptt(struct qed_hwfn *p_hwfn,
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enum reserved_ptts ptt_idx)
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{
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if (ptt_idx >= RESERVED_PTT_MAX) {
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DP_NOTICE(p_hwfn,
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"Requested PTT %d is out of range\n", ptt_idx);
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return NULL;
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}
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return &p_hwfn->p_ptt_pool->ptts[ptt_idx];
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}
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void qed_wr(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 hw_addr, u32 val)
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{
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u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr);
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REG_WR(p_hwfn, bar_addr, val);
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DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
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"bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
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bar_addr, hw_addr, val);
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}
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u32 qed_rd(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u32 hw_addr)
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{
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u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr);
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u32 val = REG_RD(p_hwfn, bar_addr);
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DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
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"bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
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bar_addr, hw_addr, val);
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return val;
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}
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static void qed_memcpy_hw(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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void *addr, u32 hw_addr, size_t n, bool to_device)
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{
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u32 dw_count, *host_addr, hw_offset;
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size_t quota, done = 0;
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u32 __iomem *reg_addr;
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while (done < n) {
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quota = min_t(size_t, n - done,
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PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE);
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if (IS_PF(p_hwfn->cdev)) {
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qed_ptt_set_win(p_hwfn, p_ptt, hw_addr + done);
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hw_offset = qed_ptt_get_bar_addr(p_ptt);
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} else {
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hw_offset = hw_addr + done;
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}
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dw_count = quota / 4;
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host_addr = (u32 *)((u8 *)addr + done);
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reg_addr = (u32 __iomem *)REG_ADDR(p_hwfn, hw_offset);
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if (to_device)
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while (dw_count--)
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DIRECT_REG_WR(reg_addr++, *host_addr++);
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else
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while (dw_count--)
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*host_addr++ = DIRECT_REG_RD(reg_addr++);
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done += quota;
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}
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}
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void qed_memcpy_from(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, void *dest, u32 hw_addr, size_t n)
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{
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DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
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"hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n",
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hw_addr, dest, hw_addr, (unsigned long)n);
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qed_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false);
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}
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void qed_memcpy_to(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u32 hw_addr, void *src, size_t n)
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{
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DP_VERBOSE(p_hwfn, NETIF_MSG_HW,
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"hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n",
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hw_addr, hw_addr, src, (unsigned long)n);
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qed_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true);
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}
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void qed_fid_pretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 fid)
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{
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u16 control = 0;
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SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
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SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
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/* Every pretend undos previous pretends, including
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* previous port pretend.
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*/
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SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
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SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
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SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
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if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
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fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
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p_ptt->pxp.pretend.control = cpu_to_le16(control);
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p_ptt->pxp.pretend.fid.concrete_fid.fid = cpu_to_le16(fid);
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REG_WR(p_hwfn,
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qed_ptt_config_addr(p_ptt) +
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offsetof(struct pxp_ptt_entry, pretend),
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*(u32 *)&p_ptt->pxp.pretend);
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}
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void qed_port_pretend(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u8 port_id)
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{
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u16 control = 0;
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SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
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SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
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SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
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p_ptt->pxp.pretend.control = cpu_to_le16(control);
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REG_WR(p_hwfn,
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qed_ptt_config_addr(p_ptt) +
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offsetof(struct pxp_ptt_entry, pretend),
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*(u32 *)&p_ptt->pxp.pretend);
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}
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void qed_port_unpretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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u16 control = 0;
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SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
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SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
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SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
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p_ptt->pxp.pretend.control = cpu_to_le16(control);
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REG_WR(p_hwfn,
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qed_ptt_config_addr(p_ptt) +
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offsetof(struct pxp_ptt_entry, pretend),
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*(u32 *)&p_ptt->pxp.pretend);
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}
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void qed_port_fid_pretend(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, u8 port_id, u16 fid)
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{
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u16 control = 0;
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SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
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SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
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SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
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SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
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SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
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if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
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fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
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p_ptt->pxp.pretend.control = cpu_to_le16(control);
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p_ptt->pxp.pretend.fid.concrete_fid.fid = cpu_to_le16(fid);
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REG_WR(p_hwfn,
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qed_ptt_config_addr(p_ptt) +
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offsetof(struct pxp_ptt_entry, pretend),
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*(u32 *)&p_ptt->pxp.pretend);
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}
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u32 qed_vfid_to_concrete(struct qed_hwfn *p_hwfn, u8 vfid)
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{
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u32 concrete_fid = 0;
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SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id);
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SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid);
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SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1);
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return concrete_fid;
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}
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/* DMAE */
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#define QED_DMAE_FLAGS_IS_SET(params, flag) \
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((params) != NULL && GET_FIELD((params)->flags, QED_DMAE_PARAMS_##flag))
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static void qed_dmae_opcode(struct qed_hwfn *p_hwfn,
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const u8 is_src_type_grc,
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const u8 is_dst_type_grc,
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struct qed_dmae_params *p_params)
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{
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u8 src_pfid, dst_pfid, port_id;
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u16 opcode_b = 0;
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u32 opcode = 0;
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/* Whether the source is the PCIe or the GRC.
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* 0- The source is the PCIe
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* 1- The source is the GRC.
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*/
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SET_FIELD(opcode, DMAE_CMD_SRC,
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(is_src_type_grc ? dmae_cmd_src_grc : dmae_cmd_src_pcie));
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src_pfid = QED_DMAE_FLAGS_IS_SET(p_params, SRC_PF_VALID) ?
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p_params->src_pfid : p_hwfn->rel_pf_id;
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SET_FIELD(opcode, DMAE_CMD_SRC_PF_ID, src_pfid);
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/* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
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SET_FIELD(opcode, DMAE_CMD_DST,
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(is_dst_type_grc ? dmae_cmd_dst_grc : dmae_cmd_dst_pcie));
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dst_pfid = QED_DMAE_FLAGS_IS_SET(p_params, DST_PF_VALID) ?
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p_params->dst_pfid : p_hwfn->rel_pf_id;
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SET_FIELD(opcode, DMAE_CMD_DST_PF_ID, dst_pfid);
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/* Whether to write a completion word to the completion destination:
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* 0-Do not write a completion word
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* 1-Write the completion word
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*/
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SET_FIELD(opcode, DMAE_CMD_COMP_WORD_EN, 1);
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SET_FIELD(opcode, DMAE_CMD_SRC_ADDR_RESET, 1);
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if (QED_DMAE_FLAGS_IS_SET(p_params, COMPLETION_DST))
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SET_FIELD(opcode, DMAE_CMD_COMP_FUNC, 1);
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/* swapping mode 3 - big endian */
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SET_FIELD(opcode, DMAE_CMD_ENDIANITY_MODE, DMAE_CMD_ENDIANITY);
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port_id = (QED_DMAE_FLAGS_IS_SET(p_params, PORT_VALID)) ?
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p_params->port_id : p_hwfn->port_id;
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SET_FIELD(opcode, DMAE_CMD_PORT_ID, port_id);
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/* reset source address in next go */
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SET_FIELD(opcode, DMAE_CMD_SRC_ADDR_RESET, 1);
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/* reset dest address in next go */
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SET_FIELD(opcode, DMAE_CMD_DST_ADDR_RESET, 1);
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/* SRC/DST VFID: all 1's - pf, otherwise VF id */
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if (QED_DMAE_FLAGS_IS_SET(p_params, SRC_VF_VALID)) {
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SET_FIELD(opcode, DMAE_CMD_SRC_VF_ID_VALID, 1);
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SET_FIELD(opcode_b, DMAE_CMD_SRC_VF_ID, p_params->src_vfid);
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} else {
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SET_FIELD(opcode_b, DMAE_CMD_SRC_VF_ID, 0xFF);
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}
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if (QED_DMAE_FLAGS_IS_SET(p_params, DST_VF_VALID)) {
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SET_FIELD(opcode, DMAE_CMD_DST_VF_ID_VALID, 1);
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SET_FIELD(opcode_b, DMAE_CMD_DST_VF_ID, p_params->dst_vfid);
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} else {
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SET_FIELD(opcode_b, DMAE_CMD_DST_VF_ID, 0xFF);
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}
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p_hwfn->dmae_info.p_dmae_cmd->opcode = cpu_to_le32(opcode);
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p_hwfn->dmae_info.p_dmae_cmd->opcode_b = cpu_to_le16(opcode_b);
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}
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u32 qed_dmae_idx_to_go_cmd(u8 idx)
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{
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/* All the DMAE 'go' registers form an array in internal memory */
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return DMAE_REG_GO_C0 + (idx << 2);
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}
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static int qed_dmae_post_command(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt)
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{
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struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd;
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u8 idx_cmd = p_hwfn->dmae_info.channel, i;
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int qed_status = 0;
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/* verify address is not NULL */
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if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) ||
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((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) {
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DP_NOTICE(p_hwfn,
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"source or destination address 0 idx_cmd=%d\n"
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"opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n",
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idx_cmd,
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le32_to_cpu(p_command->opcode),
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le16_to_cpu(p_command->opcode_b),
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le16_to_cpu(p_command->length_dw),
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le32_to_cpu(p_command->src_addr_hi),
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le32_to_cpu(p_command->src_addr_lo),
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le32_to_cpu(p_command->dst_addr_hi),
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le32_to_cpu(p_command->dst_addr_lo));
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return -EINVAL;
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}
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DP_VERBOSE(p_hwfn,
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NETIF_MSG_HW,
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"Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n",
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idx_cmd,
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le32_to_cpu(p_command->opcode),
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le16_to_cpu(p_command->opcode_b),
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le16_to_cpu(p_command->length_dw),
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le32_to_cpu(p_command->src_addr_hi),
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le32_to_cpu(p_command->src_addr_lo),
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le32_to_cpu(p_command->dst_addr_hi),
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le32_to_cpu(p_command->dst_addr_lo));
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/* Copy the command to DMAE - need to do it before every call
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* for source/dest address no reset.
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* The first 9 DWs are the command registers, the 10 DW is the
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* GO register, and the rest are result registers
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* (which are read only by the client).
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*/
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for (i = 0; i < DMAE_CMD_SIZE; i++) {
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u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ?
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*(((u32 *)p_command) + i) : 0;
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qed_wr(p_hwfn, p_ptt,
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DMAE_REG_CMD_MEM +
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(idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) +
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(i * sizeof(u32)), data);
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}
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qed_wr(p_hwfn, p_ptt, qed_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE);
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return qed_status;
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}
|
|
int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn)
|
{
|
dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr;
|
struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd;
|
u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer;
|
u32 **p_comp = &p_hwfn->dmae_info.p_completion_word;
|
|
*p_comp = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
|
sizeof(u32), p_addr, GFP_KERNEL);
|
if (!*p_comp)
|
goto err;
|
|
p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr;
|
*p_cmd = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
|
sizeof(struct dmae_cmd),
|
p_addr, GFP_KERNEL);
|
if (!*p_cmd)
|
goto err;
|
|
p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr;
|
*p_buff = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
|
sizeof(u32) * DMAE_MAX_RW_SIZE,
|
p_addr, GFP_KERNEL);
|
if (!*p_buff)
|
goto err;
|
|
p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id;
|
|
return 0;
|
err:
|
qed_dmae_info_free(p_hwfn);
|
return -ENOMEM;
|
}
|
|
void qed_dmae_info_free(struct qed_hwfn *p_hwfn)
|
{
|
dma_addr_t p_phys;
|
|
/* Just make sure no one is in the middle */
|
mutex_lock(&p_hwfn->dmae_info.mutex);
|
|
if (p_hwfn->dmae_info.p_completion_word) {
|
p_phys = p_hwfn->dmae_info.completion_word_phys_addr;
|
dma_free_coherent(&p_hwfn->cdev->pdev->dev,
|
sizeof(u32),
|
p_hwfn->dmae_info.p_completion_word, p_phys);
|
p_hwfn->dmae_info.p_completion_word = NULL;
|
}
|
|
if (p_hwfn->dmae_info.p_dmae_cmd) {
|
p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr;
|
dma_free_coherent(&p_hwfn->cdev->pdev->dev,
|
sizeof(struct dmae_cmd),
|
p_hwfn->dmae_info.p_dmae_cmd, p_phys);
|
p_hwfn->dmae_info.p_dmae_cmd = NULL;
|
}
|
|
if (p_hwfn->dmae_info.p_intermediate_buffer) {
|
p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
|
dma_free_coherent(&p_hwfn->cdev->pdev->dev,
|
sizeof(u32) * DMAE_MAX_RW_SIZE,
|
p_hwfn->dmae_info.p_intermediate_buffer,
|
p_phys);
|
p_hwfn->dmae_info.p_intermediate_buffer = NULL;
|
}
|
|
mutex_unlock(&p_hwfn->dmae_info.mutex);
|
}
|
|
static int qed_dmae_operation_wait(struct qed_hwfn *p_hwfn)
|
{
|
u32 wait_cnt_limit = 10000, wait_cnt = 0;
|
int qed_status = 0;
|
|
barrier();
|
while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) {
|
udelay(DMAE_MIN_WAIT_TIME);
|
if (++wait_cnt > wait_cnt_limit) {
|
DP_NOTICE(p_hwfn->cdev,
|
"Timed-out waiting for operation to complete. Completion word is 0x%08x expected 0x%08x.\n",
|
*p_hwfn->dmae_info.p_completion_word,
|
DMAE_COMPLETION_VAL);
|
qed_status = -EBUSY;
|
break;
|
}
|
|
/* to sync the completion_word since we are not
|
* using the volatile keyword for p_completion_word
|
*/
|
barrier();
|
}
|
|
if (qed_status == 0)
|
*p_hwfn->dmae_info.p_completion_word = 0;
|
|
return qed_status;
|
}
|
|
static int qed_dmae_execute_sub_operation(struct qed_hwfn *p_hwfn,
|
struct qed_ptt *p_ptt,
|
u64 src_addr,
|
u64 dst_addr,
|
u8 src_type,
|
u8 dst_type,
|
u32 length_dw)
|
{
|
dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
|
struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
|
int qed_status = 0;
|
|
switch (src_type) {
|
case QED_DMAE_ADDRESS_GRC:
|
case QED_DMAE_ADDRESS_HOST_PHYS:
|
cmd->src_addr_hi = cpu_to_le32(upper_32_bits(src_addr));
|
cmd->src_addr_lo = cpu_to_le32(lower_32_bits(src_addr));
|
break;
|
/* for virtual source addresses we use the intermediate buffer. */
|
case QED_DMAE_ADDRESS_HOST_VIRT:
|
cmd->src_addr_hi = cpu_to_le32(upper_32_bits(phys));
|
cmd->src_addr_lo = cpu_to_le32(lower_32_bits(phys));
|
memcpy(&p_hwfn->dmae_info.p_intermediate_buffer[0],
|
(void *)(uintptr_t)src_addr,
|
length_dw * sizeof(u32));
|
break;
|
default:
|
return -EINVAL;
|
}
|
|
switch (dst_type) {
|
case QED_DMAE_ADDRESS_GRC:
|
case QED_DMAE_ADDRESS_HOST_PHYS:
|
cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(dst_addr));
|
cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(dst_addr));
|
break;
|
/* for virtual source addresses we use the intermediate buffer. */
|
case QED_DMAE_ADDRESS_HOST_VIRT:
|
cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(phys));
|
cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(phys));
|
break;
|
default:
|
return -EINVAL;
|
}
|
|
cmd->length_dw = cpu_to_le16((u16)length_dw);
|
|
qed_dmae_post_command(p_hwfn, p_ptt);
|
|
qed_status = qed_dmae_operation_wait(p_hwfn);
|
|
if (qed_status) {
|
DP_NOTICE(p_hwfn,
|
"qed_dmae_host2grc: Wait Failed. source_addr 0x%llx, grc_addr 0x%llx, size_in_dwords 0x%x\n",
|
src_addr, dst_addr, length_dw);
|
return qed_status;
|
}
|
|
if (dst_type == QED_DMAE_ADDRESS_HOST_VIRT)
|
memcpy((void *)(uintptr_t)(dst_addr),
|
&p_hwfn->dmae_info.p_intermediate_buffer[0],
|
length_dw * sizeof(u32));
|
|
return 0;
|
}
|
|
static int qed_dmae_execute_command(struct qed_hwfn *p_hwfn,
|
struct qed_ptt *p_ptt,
|
u64 src_addr, u64 dst_addr,
|
u8 src_type, u8 dst_type,
|
u32 size_in_dwords,
|
struct qed_dmae_params *p_params)
|
{
|
dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr;
|
u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0;
|
struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
|
u64 src_addr_split = 0, dst_addr_split = 0;
|
u16 length_limit = DMAE_MAX_RW_SIZE;
|
int qed_status = 0;
|
u32 offset = 0;
|
|
if (p_hwfn->cdev->recov_in_prog) {
|
DP_VERBOSE(p_hwfn,
|
NETIF_MSG_HW,
|
"Recovery is in progress. Avoid DMAE transaction [{src: addr 0x%llx, type %d}, {dst: addr 0x%llx, type %d}, size %d].\n",
|
src_addr, src_type, dst_addr, dst_type,
|
size_in_dwords);
|
|
/* Let the flow complete w/o any error handling */
|
return 0;
|
}
|
|
qed_dmae_opcode(p_hwfn,
|
(src_type == QED_DMAE_ADDRESS_GRC),
|
(dst_type == QED_DMAE_ADDRESS_GRC),
|
p_params);
|
|
cmd->comp_addr_lo = cpu_to_le32(lower_32_bits(phys));
|
cmd->comp_addr_hi = cpu_to_le32(upper_32_bits(phys));
|
cmd->comp_val = cpu_to_le32(DMAE_COMPLETION_VAL);
|
|
/* Check if the grc_addr is valid like < MAX_GRC_OFFSET */
|
cnt_split = size_in_dwords / length_limit;
|
length_mod = size_in_dwords % length_limit;
|
|
src_addr_split = src_addr;
|
dst_addr_split = dst_addr;
|
|
for (i = 0; i <= cnt_split; i++) {
|
offset = length_limit * i;
|
|
if (!QED_DMAE_FLAGS_IS_SET(p_params, RW_REPL_SRC)) {
|
if (src_type == QED_DMAE_ADDRESS_GRC)
|
src_addr_split = src_addr + offset;
|
else
|
src_addr_split = src_addr + (offset * 4);
|
}
|
|
if (dst_type == QED_DMAE_ADDRESS_GRC)
|
dst_addr_split = dst_addr + offset;
|
else
|
dst_addr_split = dst_addr + (offset * 4);
|
|
length_cur = (cnt_split == i) ? length_mod : length_limit;
|
|
/* might be zero on last iteration */
|
if (!length_cur)
|
continue;
|
|
qed_status = qed_dmae_execute_sub_operation(p_hwfn,
|
p_ptt,
|
src_addr_split,
|
dst_addr_split,
|
src_type,
|
dst_type,
|
length_cur);
|
if (qed_status) {
|
qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_DMAE_FAIL,
|
"qed_dmae_execute_sub_operation Failed with error 0x%x. source_addr 0x%llx, destination addr 0x%llx, size_in_dwords 0x%x\n",
|
qed_status, src_addr,
|
dst_addr, length_cur);
|
break;
|
}
|
}
|
|
return qed_status;
|
}
|
|
int qed_dmae_host2grc(struct qed_hwfn *p_hwfn,
|
struct qed_ptt *p_ptt,
|
u64 source_addr, u32 grc_addr, u32 size_in_dwords,
|
struct qed_dmae_params *p_params)
|
{
|
u32 grc_addr_in_dw = grc_addr / sizeof(u32);
|
int rc;
|
|
|
mutex_lock(&p_hwfn->dmae_info.mutex);
|
|
rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr,
|
grc_addr_in_dw,
|
QED_DMAE_ADDRESS_HOST_VIRT,
|
QED_DMAE_ADDRESS_GRC,
|
size_in_dwords, p_params);
|
|
mutex_unlock(&p_hwfn->dmae_info.mutex);
|
|
return rc;
|
}
|
|
int qed_dmae_grc2host(struct qed_hwfn *p_hwfn,
|
struct qed_ptt *p_ptt,
|
u32 grc_addr,
|
dma_addr_t dest_addr, u32 size_in_dwords,
|
struct qed_dmae_params *p_params)
|
{
|
u32 grc_addr_in_dw = grc_addr / sizeof(u32);
|
int rc;
|
|
|
mutex_lock(&p_hwfn->dmae_info.mutex);
|
|
rc = qed_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw,
|
dest_addr, QED_DMAE_ADDRESS_GRC,
|
QED_DMAE_ADDRESS_HOST_VIRT,
|
size_in_dwords, p_params);
|
|
mutex_unlock(&p_hwfn->dmae_info.mutex);
|
|
return rc;
|
}
|
|
int qed_dmae_host2host(struct qed_hwfn *p_hwfn,
|
struct qed_ptt *p_ptt,
|
dma_addr_t source_addr,
|
dma_addr_t dest_addr,
|
u32 size_in_dwords, struct qed_dmae_params *p_params)
|
{
|
int rc;
|
|
mutex_lock(&(p_hwfn->dmae_info.mutex));
|
|
rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr,
|
dest_addr,
|
QED_DMAE_ADDRESS_HOST_PHYS,
|
QED_DMAE_ADDRESS_HOST_PHYS,
|
size_in_dwords, p_params);
|
|
mutex_unlock(&(p_hwfn->dmae_info.mutex));
|
|
return rc;
|
}
|
|
void qed_hw_err_notify(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
|
enum qed_hw_err_type err_type, const char *fmt, ...)
|
{
|
char buf[QED_HW_ERR_MAX_STR_SIZE];
|
va_list vl;
|
int len;
|
|
if (fmt) {
|
va_start(vl, fmt);
|
len = vsnprintf(buf, QED_HW_ERR_MAX_STR_SIZE, fmt, vl);
|
va_end(vl);
|
|
if (len > QED_HW_ERR_MAX_STR_SIZE - 1)
|
len = QED_HW_ERR_MAX_STR_SIZE - 1;
|
|
DP_NOTICE(p_hwfn, "%s", buf);
|
}
|
|
/* Fan failure cannot be masked by handling of another HW error */
|
if (p_hwfn->cdev->recov_in_prog &&
|
err_type != QED_HW_ERR_FAN_FAIL) {
|
DP_VERBOSE(p_hwfn,
|
NETIF_MSG_DRV,
|
"Recovery is in progress. Avoid notifying about HW error %d.\n",
|
err_type);
|
return;
|
}
|
|
qed_hw_error_occurred(p_hwfn, err_type);
|
|
if (fmt)
|
qed_mcp_send_raw_debug_data(p_hwfn, p_ptt, buf, len);
|
}
|
|
int qed_dmae_sanity(struct qed_hwfn *p_hwfn,
|
struct qed_ptt *p_ptt, const char *phase)
|
{
|
u32 size = PAGE_SIZE / 2, val;
|
int rc = 0;
|
dma_addr_t p_phys;
|
void *p_virt;
|
u32 *p_tmp;
|
|
p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
|
2 * size, &p_phys, GFP_KERNEL);
|
if (!p_virt) {
|
DP_NOTICE(p_hwfn,
|
"DMAE sanity [%s]: failed to allocate memory\n",
|
phase);
|
return -ENOMEM;
|
}
|
|
/* Fill the bottom half of the allocated memory with a known pattern */
|
for (p_tmp = (u32 *)p_virt;
|
p_tmp < (u32 *)((u8 *)p_virt + size); p_tmp++) {
|
/* Save the address itself as the value */
|
val = (u32)(uintptr_t)p_tmp;
|
*p_tmp = val;
|
}
|
|
/* Zero the top half of the allocated memory */
|
memset((u8 *)p_virt + size, 0, size);
|
|
DP_VERBOSE(p_hwfn,
|
QED_MSG_SP,
|
"DMAE sanity [%s]: src_addr={phys 0x%llx, virt %p}, dst_addr={phys 0x%llx, virt %p}, size 0x%x\n",
|
phase,
|
(u64)p_phys,
|
p_virt, (u64)(p_phys + size), (u8 *)p_virt + size, size);
|
|
rc = qed_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size,
|
size / 4, NULL);
|
if (rc) {
|
DP_NOTICE(p_hwfn,
|
"DMAE sanity [%s]: qed_dmae_host2host() failed. rc = %d.\n",
|
phase, rc);
|
goto out;
|
}
|
|
/* Verify that the top half of the allocated memory has the pattern */
|
for (p_tmp = (u32 *)((u8 *)p_virt + size);
|
p_tmp < (u32 *)((u8 *)p_virt + (2 * size)); p_tmp++) {
|
/* The corresponding address in the bottom half */
|
val = (u32)(uintptr_t)p_tmp - size;
|
|
if (*p_tmp != val) {
|
DP_NOTICE(p_hwfn,
|
"DMAE sanity [%s]: addr={phys 0x%llx, virt %p}, read_val 0x%08x, expected_val 0x%08x\n",
|
phase,
|
(u64)p_phys + ((u8 *)p_tmp - (u8 *)p_virt),
|
p_tmp, *p_tmp, val);
|
rc = -EINVAL;
|
goto out;
|
}
|
}
|
|
out:
|
dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2 * size, p_virt, p_phys);
|
return rc;
|
}
|
