/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/* QLogic qed NIC Driver
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* Copyright (c) 2015-2017 QLogic Corporation
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* Copyright (c) 2019-2020 Marvell International Ltd.
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*/
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#ifndef _QED_H
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#define _QED_H
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/workqueue.h>
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#include <linux/zlib.h>
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#include <linux/hashtable.h>
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#include <linux/qed/qed_if.h>
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#include "qed_debug.h"
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#include "qed_hsi.h"
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extern const struct qed_common_ops qed_common_ops_pass;
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#define QED_MAJOR_VERSION 8
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#define QED_MINOR_VERSION 37
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#define QED_REVISION_VERSION 0
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#define QED_ENGINEERING_VERSION 20
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#define QED_VERSION \
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((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
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(QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION)
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#define STORM_FW_VERSION \
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((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
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(FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
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#define MAX_HWFNS_PER_DEVICE (4)
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#define NAME_SIZE 16
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#define VER_SIZE 16
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#define QED_WFQ_UNIT 100
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#define QED_WID_SIZE (1024)
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#define QED_MIN_WIDS (4)
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#define QED_PF_DEMS_SIZE (4)
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/* cau states */
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enum qed_coalescing_mode {
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QED_COAL_MODE_DISABLE,
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QED_COAL_MODE_ENABLE
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};
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enum qed_nvm_cmd {
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QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
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QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
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QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
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QED_GET_MCP_NVM_RESP = 0xFFFFFF00
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};
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struct qed_eth_cb_ops;
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struct qed_dev_info;
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union qed_mcp_protocol_stats;
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enum qed_mcp_protocol_type;
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enum qed_mfw_tlv_type;
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union qed_mfw_tlv_data;
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/* helpers */
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#define QED_MFW_GET_FIELD(name, field) \
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(((name) & (field ## _MASK)) >> (field ## _SHIFT))
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#define QED_MFW_SET_FIELD(name, field, value) \
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do { \
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(name) &= ~(field ## _MASK); \
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(name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
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} while (0)
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static inline u32 qed_db_addr(u32 cid, u32 DEMS)
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{
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u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
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(cid * QED_PF_DEMS_SIZE);
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return db_addr;
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}
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static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
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{
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u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
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FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
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return db_addr;
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}
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#define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
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((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
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~((1 << (p_hwfn->cdev->cache_shift)) - 1))
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#define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
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#define D_TRINE(val, cond1, cond2, true1, true2, def) \
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(val == (cond1) ? true1 : \
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(val == (cond2) ? true2 : def))
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/* forward */
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struct qed_ptt_pool;
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struct qed_spq;
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struct qed_sb_info;
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struct qed_sb_attn_info;
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struct qed_cxt_mngr;
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struct qed_sb_sp_info;
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struct qed_ll2_info;
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struct qed_mcp_info;
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struct qed_llh_info;
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struct qed_rt_data {
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u32 *init_val;
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bool *b_valid;
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};
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enum qed_tunn_mode {
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QED_MODE_L2GENEVE_TUNN,
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QED_MODE_IPGENEVE_TUNN,
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QED_MODE_L2GRE_TUNN,
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QED_MODE_IPGRE_TUNN,
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QED_MODE_VXLAN_TUNN,
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};
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enum qed_tunn_clss {
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QED_TUNN_CLSS_MAC_VLAN,
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QED_TUNN_CLSS_MAC_VNI,
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QED_TUNN_CLSS_INNER_MAC_VLAN,
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QED_TUNN_CLSS_INNER_MAC_VNI,
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QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
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MAX_QED_TUNN_CLSS,
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};
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struct qed_tunn_update_type {
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bool b_update_mode;
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bool b_mode_enabled;
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enum qed_tunn_clss tun_cls;
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};
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struct qed_tunn_update_udp_port {
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bool b_update_port;
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u16 port;
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};
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struct qed_tunnel_info {
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struct qed_tunn_update_type vxlan;
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struct qed_tunn_update_type l2_geneve;
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struct qed_tunn_update_type ip_geneve;
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struct qed_tunn_update_type l2_gre;
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struct qed_tunn_update_type ip_gre;
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struct qed_tunn_update_udp_port vxlan_port;
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struct qed_tunn_update_udp_port geneve_port;
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bool b_update_rx_cls;
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bool b_update_tx_cls;
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};
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struct qed_tunn_start_params {
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unsigned long tunn_mode;
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u16 vxlan_udp_port;
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u16 geneve_udp_port;
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u8 update_vxlan_udp_port;
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u8 update_geneve_udp_port;
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u8 tunn_clss_vxlan;
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u8 tunn_clss_l2geneve;
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u8 tunn_clss_ipgeneve;
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u8 tunn_clss_l2gre;
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u8 tunn_clss_ipgre;
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};
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struct qed_tunn_update_params {
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unsigned long tunn_mode_update_mask;
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unsigned long tunn_mode;
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u16 vxlan_udp_port;
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u16 geneve_udp_port;
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u8 update_rx_pf_clss;
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u8 update_tx_pf_clss;
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u8 update_vxlan_udp_port;
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u8 update_geneve_udp_port;
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u8 tunn_clss_vxlan;
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u8 tunn_clss_l2geneve;
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u8 tunn_clss_ipgeneve;
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u8 tunn_clss_l2gre;
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u8 tunn_clss_ipgre;
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};
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/* The PCI personality is not quite synonymous to protocol ID:
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* 1. All personalities need CORE connections
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* 2. The Ethernet personality may support also the RoCE/iWARP protocol
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*/
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enum qed_pci_personality {
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QED_PCI_ETH,
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QED_PCI_FCOE,
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QED_PCI_ISCSI,
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QED_PCI_ETH_ROCE,
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QED_PCI_ETH_IWARP,
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QED_PCI_ETH_RDMA,
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QED_PCI_DEFAULT, /* default in shmem */
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};
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/* All VFs are symmetric, all counters are PF + all VFs */
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struct qed_qm_iids {
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u32 cids;
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u32 vf_cids;
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u32 tids;
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};
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/* HW / FW resources, output of features supported below, most information
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* is received from MFW.
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*/
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enum qed_resources {
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QED_SB,
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QED_L2_QUEUE,
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QED_VPORT,
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QED_RSS_ENG,
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QED_PQ,
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QED_RL,
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QED_MAC,
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QED_VLAN,
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QED_RDMA_CNQ_RAM,
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QED_ILT,
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QED_LL2_RAM_QUEUE,
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QED_LL2_CTX_QUEUE,
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QED_CMDQS_CQS,
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QED_RDMA_STATS_QUEUE,
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QED_BDQ,
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QED_MAX_RESC,
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};
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enum QED_FEATURE {
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QED_PF_L2_QUE,
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QED_VF,
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QED_RDMA_CNQ,
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QED_ISCSI_CQ,
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QED_FCOE_CQ,
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QED_VF_L2_QUE,
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QED_MAX_FEATURES,
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};
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enum qed_dev_cap {
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QED_DEV_CAP_ETH,
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QED_DEV_CAP_FCOE,
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QED_DEV_CAP_ISCSI,
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QED_DEV_CAP_ROCE,
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QED_DEV_CAP_IWARP,
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};
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enum qed_wol_support {
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QED_WOL_SUPPORT_NONE,
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QED_WOL_SUPPORT_PME,
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};
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enum qed_db_rec_exec {
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DB_REC_DRY_RUN,
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DB_REC_REAL_DEAL,
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DB_REC_ONCE,
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};
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struct qed_hw_info {
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/* PCI personality */
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enum qed_pci_personality personality;
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#define QED_IS_RDMA_PERSONALITY(dev) \
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((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
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(dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
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(dev)->hw_info.personality == QED_PCI_ETH_RDMA)
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#define QED_IS_ROCE_PERSONALITY(dev) \
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((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
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(dev)->hw_info.personality == QED_PCI_ETH_RDMA)
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#define QED_IS_IWARP_PERSONALITY(dev) \
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((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
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(dev)->hw_info.personality == QED_PCI_ETH_RDMA)
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#define QED_IS_L2_PERSONALITY(dev) \
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((dev)->hw_info.personality == QED_PCI_ETH || \
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QED_IS_RDMA_PERSONALITY(dev))
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#define QED_IS_FCOE_PERSONALITY(dev) \
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((dev)->hw_info.personality == QED_PCI_FCOE)
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#define QED_IS_ISCSI_PERSONALITY(dev) \
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((dev)->hw_info.personality == QED_PCI_ISCSI)
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/* Resource Allocation scheme results */
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u32 resc_start[QED_MAX_RESC];
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u32 resc_num[QED_MAX_RESC];
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#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
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#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
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#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
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RESC_NUM(_p_hwfn, resc))
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u32 feat_num[QED_MAX_FEATURES];
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#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
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/* Amount of traffic classes HW supports */
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u8 num_hw_tc;
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/* Amount of TCs which should be active according to DCBx or upper
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* layer driver configuration.
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*/
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u8 num_active_tc;
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u8 offload_tc;
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bool offload_tc_set;
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bool multi_tc_roce_en;
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#define IS_QED_MULTI_TC_ROCE(p_hwfn) ((p_hwfn)->hw_info.multi_tc_roce_en)
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u32 concrete_fid;
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u16 opaque_fid;
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u16 ovlan;
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u32 part_num[4];
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unsigned char hw_mac_addr[ETH_ALEN];
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u64 node_wwn;
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u64 port_wwn;
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u16 num_fcoe_conns;
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struct qed_igu_info *p_igu_info;
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u32 hw_mode;
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unsigned long device_capabilities;
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u16 mtu;
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enum qed_wol_support b_wol_support;
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};
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/* maximun size of read/write commands (HW limit) */
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#define DMAE_MAX_RW_SIZE 0x2000
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struct qed_dmae_info {
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/* Mutex for synchronizing access to functions */
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struct mutex mutex;
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u8 channel;
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dma_addr_t completion_word_phys_addr;
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/* The memory location where the DMAE writes the completion
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* value when an operation is finished on this context.
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*/
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u32 *p_completion_word;
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dma_addr_t intermediate_buffer_phys_addr;
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/* An intermediate buffer for DMAE operations that use virtual
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* addresses - data is DMA'd to/from this buffer and then
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* memcpy'd to/from the virtual address
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*/
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u32 *p_intermediate_buffer;
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dma_addr_t dmae_cmd_phys_addr;
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struct dmae_cmd *p_dmae_cmd;
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};
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struct qed_wfq_data {
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/* when feature is configured for at least 1 vport */
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u32 min_speed;
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bool configured;
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};
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struct qed_qm_info {
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struct init_qm_pq_params *qm_pq_params;
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struct init_qm_vport_params *qm_vport_params;
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struct init_qm_port_params *qm_port_params;
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u16 start_pq;
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u8 start_vport;
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u16 pure_lb_pq;
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u16 first_ofld_pq;
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u16 first_llt_pq;
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u16 pure_ack_pq;
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u16 ooo_pq;
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u16 first_vf_pq;
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u16 first_mcos_pq;
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u16 first_rl_pq;
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u16 num_pqs;
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u16 num_vf_pqs;
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u8 num_vports;
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u8 max_phys_tcs_per_port;
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u8 ooo_tc;
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bool pf_rl_en;
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bool pf_wfq_en;
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bool vport_rl_en;
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bool vport_wfq_en;
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u8 pf_wfq;
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u32 pf_rl;
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struct qed_wfq_data *wfq_data;
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u8 num_pf_rls;
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};
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#define QED_OVERFLOW_BIT 1
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struct qed_db_recovery_info {
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struct list_head list;
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/* Lock to protect the doorbell recovery mechanism list */
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spinlock_t lock;
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bool dorq_attn;
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u32 db_recovery_counter;
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unsigned long overflow;
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};
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struct storm_stats {
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u32 address;
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u32 len;
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};
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struct qed_storm_stats {
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struct storm_stats mstats;
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struct storm_stats pstats;
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struct storm_stats tstats;
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struct storm_stats ustats;
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};
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struct qed_fw_data {
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struct fw_ver_info *fw_ver_info;
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const u8 *modes_tree_buf;
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union init_op *init_ops;
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const u32 *arr_data;
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const u32 *fw_overlays;
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u32 fw_overlays_len;
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u32 init_ops_size;
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};
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enum qed_mf_mode_bit {
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/* Supports PF-classification based on tag */
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QED_MF_OVLAN_CLSS,
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/* Supports PF-classification based on MAC */
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QED_MF_LLH_MAC_CLSS,
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/* Supports PF-classification based on protocol type */
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QED_MF_LLH_PROTO_CLSS,
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/* Requires a default PF to be set */
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QED_MF_NEED_DEF_PF,
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/* Allow LL2 to multicast/broadcast */
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QED_MF_LL2_NON_UNICAST,
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/* Allow Cross-PF [& child VFs] Tx-switching */
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QED_MF_INTER_PF_SWITCH,
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/* Unified Fabtic Port support enabled */
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QED_MF_UFP_SPECIFIC,
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/* Disable Accelerated Receive Flow Steering (aRFS) */
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QED_MF_DISABLE_ARFS,
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/* Use vlan for steering */
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QED_MF_8021Q_TAGGING,
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/* Use stag for steering */
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QED_MF_8021AD_TAGGING,
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/* Allow DSCP to TC mapping */
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QED_MF_DSCP_TO_TC_MAP,
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/* Do not insert a vlan tag with id 0 */
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QED_MF_DONT_ADD_VLAN0_TAG,
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};
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enum qed_ufp_mode {
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QED_UFP_MODE_ETS,
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QED_UFP_MODE_VNIC_BW,
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QED_UFP_MODE_UNKNOWN
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};
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enum qed_ufp_pri_type {
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QED_UFP_PRI_OS,
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QED_UFP_PRI_VNIC,
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QED_UFP_PRI_UNKNOWN
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};
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struct qed_ufp_info {
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enum qed_ufp_pri_type pri_type;
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enum qed_ufp_mode mode;
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u8 tc;
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};
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enum BAR_ID {
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BAR_ID_0, /* used for GRC */
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BAR_ID_1 /* Used for doorbells */
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};
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struct qed_nvm_image_info {
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u32 num_images;
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struct bist_nvm_image_att *image_att;
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bool valid;
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};
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enum qed_hsi_def_type {
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QED_HSI_DEF_MAX_NUM_VFS,
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QED_HSI_DEF_MAX_NUM_L2_QUEUES,
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QED_HSI_DEF_MAX_NUM_PORTS,
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QED_HSI_DEF_MAX_SB_PER_PATH,
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QED_HSI_DEF_MAX_NUM_PFS,
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QED_HSI_DEF_MAX_NUM_VPORTS,
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QED_HSI_DEF_NUM_ETH_RSS_ENGINE,
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QED_HSI_DEF_MAX_QM_TX_QUEUES,
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QED_HSI_DEF_NUM_PXP_ILT_RECORDS,
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QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS,
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QED_HSI_DEF_MAX_QM_GLOBAL_RLS,
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QED_HSI_DEF_MAX_PBF_CMD_LINES,
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QED_HSI_DEF_MAX_BTB_BLOCKS,
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QED_NUM_HSI_DEFS
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};
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#define DRV_MODULE_VERSION \
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__stringify(QED_MAJOR_VERSION) "." \
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__stringify(QED_MINOR_VERSION) "." \
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__stringify(QED_REVISION_VERSION) "." \
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__stringify(QED_ENGINEERING_VERSION)
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struct qed_simd_fp_handler {
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void *token;
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void (*func)(void *);
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};
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enum qed_slowpath_wq_flag {
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QED_SLOWPATH_MFW_TLV_REQ,
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QED_SLOWPATH_PERIODIC_DB_REC,
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};
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struct qed_hwfn {
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struct qed_dev *cdev;
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u8 my_id; /* ID inside the PF */
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#define IS_LEAD_HWFN(edev) (!((edev)->my_id))
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u8 rel_pf_id; /* Relative to engine*/
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u8 abs_pf_id;
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#define QED_PATH_ID(_p_hwfn) \
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(QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
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u8 port_id;
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bool b_active;
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u32 dp_module;
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u8 dp_level;
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char name[NAME_SIZE];
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bool hw_init_done;
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u8 num_funcs_on_engine;
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u8 enabled_func_idx;
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/* BAR access */
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void __iomem *regview;
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void __iomem *doorbells;
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u64 db_phys_addr;
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unsigned long db_size;
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/* PTT pool */
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struct qed_ptt_pool *p_ptt_pool;
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/* HW info */
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struct qed_hw_info hw_info;
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/* rt_array (for init-tool) */
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struct qed_rt_data rt_data;
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/* SPQ */
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struct qed_spq *p_spq;
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/* EQ */
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struct qed_eq *p_eq;
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/* Consolidate Q*/
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struct qed_consq *p_consq;
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/* Slow-Path definitions */
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struct tasklet_struct sp_dpc;
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bool b_sp_dpc_enabled;
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struct qed_ptt *p_main_ptt;
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struct qed_ptt *p_dpc_ptt;
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/* PTP will be used only by the leading function.
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* Usage of all PTP-apis should be synchronized as result.
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*/
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struct qed_ptt *p_ptp_ptt;
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struct qed_sb_sp_info *p_sp_sb;
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struct qed_sb_attn_info *p_sb_attn;
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/* Protocol related */
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bool using_ll2;
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struct qed_ll2_info *p_ll2_info;
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struct qed_ooo_info *p_ooo_info;
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struct qed_rdma_info *p_rdma_info;
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struct qed_iscsi_info *p_iscsi_info;
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struct qed_fcoe_info *p_fcoe_info;
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struct qed_pf_params pf_params;
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bool b_rdma_enabled_in_prs;
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u32 rdma_prs_search_reg;
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struct qed_cxt_mngr *p_cxt_mngr;
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/* Flag indicating whether interrupts are enabled or not*/
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bool b_int_enabled;
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bool b_int_requested;
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/* True if the driver requests for the link */
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bool b_drv_link_init;
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struct qed_vf_iov *vf_iov_info;
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struct qed_pf_iov *pf_iov_info;
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struct qed_mcp_info *mcp_info;
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|
struct qed_dcbx_info *p_dcbx_info;
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|
struct qed_ufp_info ufp_info;
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|
struct qed_dmae_info dmae_info;
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|
/* QM init */
|
struct qed_qm_info qm_info;
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struct qed_storm_stats storm_stats;
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|
/* Buffer for unzipping firmware data */
|
void *unzip_buf;
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|
struct dbg_tools_data dbg_info;
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void *dbg_user_info;
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struct virt_mem_desc dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE];
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|
/* PWM region specific data */
|
u16 wid_count;
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u32 dpi_size;
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u32 dpi_count;
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|
/* This is used to calculate the doorbell address */
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u32 dpi_start_offset;
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|
/* If one of the following is set then EDPM shouldn't be used */
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u8 dcbx_no_edpm;
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u8 db_bar_no_edpm;
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|
/* L2-related */
|
struct qed_l2_info *p_l2_info;
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|
/* Mechanism for recovering from doorbell drop */
|
struct qed_db_recovery_info db_recovery_info;
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|
/* Nvm images number and attributes */
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struct qed_nvm_image_info nvm_info;
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|
struct phys_mem_desc *fw_overlay_mem;
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struct qed_ptt *p_arfs_ptt;
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|
struct qed_simd_fp_handler simd_proto_handler[64];
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|
#ifdef CONFIG_QED_SRIOV
|
struct workqueue_struct *iov_wq;
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struct delayed_work iov_task;
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unsigned long iov_task_flags;
|
#endif
|
struct z_stream_s *stream;
|
bool slowpath_wq_active;
|
struct workqueue_struct *slowpath_wq;
|
struct delayed_work slowpath_task;
|
unsigned long slowpath_task_flags;
|
u32 periodic_db_rec_count;
|
};
|
|
struct pci_params {
|
int pm_cap;
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|
unsigned long mem_start;
|
unsigned long mem_end;
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unsigned int irq;
|
u8 pf_num;
|
};
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|
struct qed_int_param {
|
u32 int_mode;
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u8 num_vectors;
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u8 min_msix_cnt; /* for minimal functionality */
|
};
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|
struct qed_int_params {
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struct qed_int_param in;
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struct qed_int_param out;
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struct msix_entry *msix_table;
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bool fp_initialized;
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u8 fp_msix_base;
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u8 fp_msix_cnt;
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u8 rdma_msix_base;
|
u8 rdma_msix_cnt;
|
};
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|
struct qed_dbg_feature {
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struct dentry *dentry;
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u8 *dump_buf;
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u32 buf_size;
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u32 dumped_dwords;
|
};
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|
struct qed_dev {
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u32 dp_module;
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u8 dp_level;
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char name[NAME_SIZE];
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|
enum qed_dev_type type;
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/* Translate type/revision combo into the proper conditions */
|
#define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
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#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && CHIP_REV_IS_B0(dev))
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#define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
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#define QED_IS_K2(dev) QED_IS_AH(dev)
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#define QED_IS_E4(dev) (QED_IS_BB(dev) || QED_IS_AH(dev))
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#define QED_IS_E5(dev) ((dev)->type == QED_DEV_TYPE_E5)
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|
u16 vendor_id;
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|
u16 device_id;
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#define QED_DEV_ID_MASK 0xff00
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#define QED_DEV_ID_MASK_BB 0x1600
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#define QED_DEV_ID_MASK_AH 0x8000
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|
u16 chip_num;
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#define CHIP_NUM_MASK 0xffff
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#define CHIP_NUM_SHIFT 16
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|
u16 chip_rev;
|
#define CHIP_REV_MASK 0xf
|
#define CHIP_REV_SHIFT 12
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#define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
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|
u16 chip_metal;
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#define CHIP_METAL_MASK 0xff
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#define CHIP_METAL_SHIFT 4
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|
u16 chip_bond_id;
|
#define CHIP_BOND_ID_MASK 0xf
|
#define CHIP_BOND_ID_SHIFT 0
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|
u8 num_engines;
|
u8 num_ports;
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u8 num_ports_in_engine;
|
u8 num_funcs_in_port;
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|
u8 path_id;
|
|
unsigned long mf_bits;
|
|
int pcie_width;
|
int pcie_speed;
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|
/* Add MF related configuration */
|
u8 mcp_rev;
|
u8 boot_mode;
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|
/* WoL related configurations */
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u8 wol_config;
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u8 wol_mac[ETH_ALEN];
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|
u32 int_mode;
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enum qed_coalescing_mode int_coalescing_mode;
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u16 rx_coalesce_usecs;
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u16 tx_coalesce_usecs;
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|
/* Start Bar offset of first hwfn */
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void __iomem *regview;
|
void __iomem *doorbells;
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u64 db_phys_addr;
|
unsigned long db_size;
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|
/* PCI */
|
u8 cache_shift;
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|
/* Init */
|
const u32 *iro_arr;
|
#define IRO ((const struct iro *)p_hwfn->cdev->iro_arr)
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|
/* HW functions */
|
u8 num_hwfns;
|
struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
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|
/* Engine affinity */
|
u8 l2_affin_hint;
|
u8 fir_affin;
|
u8 iwarp_affin;
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|
/* SRIOV */
|
struct qed_hw_sriov_info *p_iov_info;
|
#define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
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struct qed_tunnel_info tunnel;
|
bool b_is_vf;
|
u32 drv_type;
|
struct qed_eth_stats *reset_stats;
|
struct qed_fw_data *fw_data;
|
|
u32 mcp_nvm_resp;
|
|
/* Recovery */
|
bool recov_in_prog;
|
|
/* Indicates whether should prevent attentions from being reasserted */
|
bool attn_clr_en;
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|
/* LLH info */
|
u8 ppfid_bitmap;
|
struct qed_llh_info *p_llh_info;
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|
/* Linux specific here */
|
struct qed_dev_info common_dev_info;
|
struct qede_dev *edev;
|
struct pci_dev *pdev;
|
u32 flags;
|
#define QED_FLAG_STORAGE_STARTED (BIT(0))
|
int msg_enable;
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|
struct pci_params pci_params;
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|
struct qed_int_params int_params;
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|
u8 protocol;
|
#define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
|
#define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE)
|
|
/* Callbacks to protocol driver */
|
union {
|
struct qed_common_cb_ops *common;
|
struct qed_eth_cb_ops *eth;
|
struct qed_fcoe_cb_ops *fcoe;
|
struct qed_iscsi_cb_ops *iscsi;
|
} protocol_ops;
|
void *ops_cookie;
|
|
#ifdef CONFIG_QED_LL2
|
struct qed_cb_ll2_info *ll2;
|
u8 ll2_mac_address[ETH_ALEN];
|
#endif
|
struct qed_dbg_feature dbg_features[DBG_FEATURE_NUM];
|
u8 engine_for_debug;
|
bool disable_ilt_dump;
|
bool dbg_bin_dump;
|
|
DECLARE_HASHTABLE(connections, 10);
|
const struct firmware *firmware;
|
|
bool print_dbg_data;
|
|
u32 rdma_max_sge;
|
u32 rdma_max_inline;
|
u32 rdma_max_srq_sge;
|
u16 tunn_feature_mask;
|
|
bool iwarp_cmt;
|
};
|
|
u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type);
|
|
#define NUM_OF_VFS(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VFS)
|
#define NUM_OF_L2_QUEUES(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_L2_QUEUES)
|
#define NUM_OF_PORTS(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PORTS)
|
#define NUM_OF_SBS(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_SB_PER_PATH)
|
#define NUM_OF_ENG_PFS(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PFS)
|
#define NUM_OF_VPORTS(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VPORTS)
|
#define NUM_OF_RSS_ENGINES(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_ETH_RSS_ENGINE)
|
#define NUM_OF_QM_TX_QUEUES(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_TX_QUEUES)
|
#define NUM_OF_PXP_ILT_RECORDS(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_PXP_ILT_RECORDS)
|
#define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS)
|
#define NUM_OF_QM_GLOBAL_RLS(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_GLOBAL_RLS)
|
#define NUM_OF_PBF_CMD_LINES(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_PBF_CMD_LINES)
|
#define NUM_OF_BTB_BLOCKS(dev) \
|
qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_BTB_BLOCKS)
|
|
|
/**
|
* @brief qed_concrete_to_sw_fid - get the sw function id from
|
* the concrete value.
|
*
|
* @param concrete_fid
|
*
|
* @return inline u8
|
*/
|
static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
|
u32 concrete_fid)
|
{
|
u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
|
u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
|
u8 vf_valid = GET_FIELD(concrete_fid,
|
PXP_CONCRETE_FID_VFVALID);
|
u8 sw_fid;
|
|
if (vf_valid)
|
sw_fid = vfid + MAX_NUM_PFS;
|
else
|
sw_fid = pfid;
|
|
return sw_fid;
|
}
|
|
#define PKT_LB_TC 9
|
#define MAX_NUM_VOQS_E4 20
|
|
int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
|
void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
|
struct qed_ptt *p_ptt,
|
u32 min_pf_rate);
|
|
void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
|
int qed_device_num_engines(struct qed_dev *cdev);
|
void qed_set_fw_mac_addr(__le16 *fw_msb,
|
__le16 *fw_mid, __le16 *fw_lsb, u8 *mac);
|
|
#define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
|
#define QED_IS_CMT(dev) ((dev)->num_hwfns > 1)
|
/* Macros for getting the engine-affinitized hwfn (FIR: fcoe,iscsi,roce) */
|
#define QED_FIR_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->fir_affin])
|
#define QED_IWARP_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->iwarp_affin])
|
#define QED_AFFIN_HWFN(dev) \
|
(QED_IS_IWARP_PERSONALITY(QED_LEADING_HWFN(dev)) ? \
|
QED_IWARP_AFFIN_HWFN(dev) : QED_FIR_AFFIN_HWFN(dev))
|
#define QED_AFFIN_HWFN_IDX(dev) (IS_LEAD_HWFN(QED_AFFIN_HWFN(dev)) ? 0 : 1)
|
|
/* Flags for indication of required queues */
|
#define PQ_FLAGS_RLS (BIT(0))
|
#define PQ_FLAGS_MCOS (BIT(1))
|
#define PQ_FLAGS_LB (BIT(2))
|
#define PQ_FLAGS_OOO (BIT(3))
|
#define PQ_FLAGS_ACK (BIT(4))
|
#define PQ_FLAGS_OFLD (BIT(5))
|
#define PQ_FLAGS_VFS (BIT(6))
|
#define PQ_FLAGS_LLT (BIT(7))
|
#define PQ_FLAGS_MTC (BIT(8))
|
|
/* physical queue index for cm context intialization */
|
u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);
|
u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);
|
u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
|
u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc);
|
u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc);
|
|
/* doorbell recovery mechanism */
|
void qed_db_recovery_dp(struct qed_hwfn *p_hwfn);
|
void qed_db_recovery_execute(struct qed_hwfn *p_hwfn);
|
bool qed_edpm_enabled(struct qed_hwfn *p_hwfn);
|
|
/* Other Linux specific common definitions */
|
#define DP_NAME(cdev) ((cdev)->name)
|
|
#define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
|
(cdev->regview) + \
|
(offset))
|
|
#define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
|
#define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
|
#define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
|
|
#define DOORBELL(cdev, db_addr, val) \
|
writel((u32)val, (void __iomem *)((u8 __iomem *)\
|
(cdev->doorbells) + (db_addr)))
|
|
#define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
|
qed_device_num_ports((_p_hwfn)->cdev))
|
int qed_device_num_ports(struct qed_dev *cdev);
|
|
/* Prototypes */
|
int qed_fill_dev_info(struct qed_dev *cdev,
|
struct qed_dev_info *dev_info);
|
void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
|
void qed_bw_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
|
u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
|
u32 input_len, u8 *input_buf,
|
u32 max_size, u8 *unzip_buf);
|
int qed_recovery_process(struct qed_dev *cdev);
|
void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn);
|
void qed_hw_error_occurred(struct qed_hwfn *p_hwfn,
|
enum qed_hw_err_type err_type);
|
void qed_get_protocol_stats(struct qed_dev *cdev,
|
enum qed_mcp_protocol_type type,
|
union qed_mcp_protocol_stats *stats);
|
int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
|
void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn);
|
int qed_mfw_tlv_req(struct qed_hwfn *hwfn);
|
|
int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn,
|
enum qed_mfw_tlv_type type,
|
union qed_mfw_tlv_data *tlv_data);
|
|
void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc);
|
|
void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn);
|
#endif /* _QED_H */
|
