/*
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* Copyright 2008-2015 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include "fman_tgec.h"
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#include "fman.h"
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#include <linux/slab.h>
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#include <linux/bitrev.h>
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#include <linux/io.h>
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#include <linux/crc32.h>
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/* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */
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#define TGEC_TX_IPG_LENGTH_MASK 0x000003ff
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/* Command and Configuration Register (COMMAND_CONFIG) */
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#define CMD_CFG_EN_TIMESTAMP 0x00100000
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#define CMD_CFG_NO_LEN_CHK 0x00020000
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#define CMD_CFG_PAUSE_IGNORE 0x00000100
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#define CMF_CFG_CRC_FWD 0x00000040
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#define CMD_CFG_PROMIS_EN 0x00000010
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#define CMD_CFG_RX_EN 0x00000002
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#define CMD_CFG_TX_EN 0x00000001
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/* Interrupt Mask Register (IMASK) */
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#define TGEC_IMASK_MDIO_SCAN_EVENT 0x00010000
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#define TGEC_IMASK_MDIO_CMD_CMPL 0x00008000
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#define TGEC_IMASK_REM_FAULT 0x00004000
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#define TGEC_IMASK_LOC_FAULT 0x00002000
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#define TGEC_IMASK_TX_ECC_ER 0x00001000
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#define TGEC_IMASK_TX_FIFO_UNFL 0x00000800
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#define TGEC_IMASK_TX_FIFO_OVFL 0x00000400
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#define TGEC_IMASK_TX_ER 0x00000200
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#define TGEC_IMASK_RX_FIFO_OVFL 0x00000100
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#define TGEC_IMASK_RX_ECC_ER 0x00000080
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#define TGEC_IMASK_RX_JAB_FRM 0x00000040
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#define TGEC_IMASK_RX_OVRSZ_FRM 0x00000020
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#define TGEC_IMASK_RX_RUNT_FRM 0x00000010
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#define TGEC_IMASK_RX_FRAG_FRM 0x00000008
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#define TGEC_IMASK_RX_LEN_ER 0x00000004
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#define TGEC_IMASK_RX_CRC_ER 0x00000002
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#define TGEC_IMASK_RX_ALIGN_ER 0x00000001
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/* Hashtable Control Register (HASHTABLE_CTRL) */
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#define TGEC_HASH_MCAST_SHIFT 23
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#define TGEC_HASH_MCAST_EN 0x00000200
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#define TGEC_HASH_ADR_MSK 0x000001ff
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#define DEFAULT_TX_IPG_LENGTH 12
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#define DEFAULT_MAX_FRAME_LENGTH 0x600
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#define DEFAULT_PAUSE_QUANT 0xf000
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/* number of pattern match registers (entries) */
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#define TGEC_NUM_OF_PADDRS 1
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/* Group address bit indication */
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#define GROUP_ADDRESS 0x0000010000000000LL
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/* Hash table size (= 32 bits*8 regs) */
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#define TGEC_HASH_TABLE_SIZE 512
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/* tGEC memory map */
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struct tgec_regs {
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u32 tgec_id; /* 0x000 Controller ID */
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u32 reserved001[1]; /* 0x004 */
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u32 command_config; /* 0x008 Control and configuration */
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u32 mac_addr_0; /* 0x00c Lower 32 bits of the MAC adr */
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u32 mac_addr_1; /* 0x010 Upper 16 bits of the MAC adr */
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u32 maxfrm; /* 0x014 Maximum frame length */
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u32 pause_quant; /* 0x018 Pause quanta */
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u32 rx_fifo_sections; /* 0x01c */
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u32 tx_fifo_sections; /* 0x020 */
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u32 rx_fifo_almost_f_e; /* 0x024 */
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u32 tx_fifo_almost_f_e; /* 0x028 */
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u32 hashtable_ctrl; /* 0x02c Hash table control */
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u32 mdio_cfg_status; /* 0x030 */
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u32 mdio_command; /* 0x034 */
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u32 mdio_data; /* 0x038 */
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u32 mdio_regaddr; /* 0x03c */
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u32 status; /* 0x040 */
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u32 tx_ipg_len; /* 0x044 Transmitter inter-packet-gap */
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u32 mac_addr_2; /* 0x048 Lower 32 bits of 2nd MAC adr */
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u32 mac_addr_3; /* 0x04c Upper 16 bits of 2nd MAC adr */
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u32 rx_fifo_ptr_rd; /* 0x050 */
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u32 rx_fifo_ptr_wr; /* 0x054 */
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u32 tx_fifo_ptr_rd; /* 0x058 */
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u32 tx_fifo_ptr_wr; /* 0x05c */
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u32 imask; /* 0x060 Interrupt mask */
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u32 ievent; /* 0x064 Interrupt event */
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u32 udp_port; /* 0x068 Defines a UDP Port number */
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u32 type_1588v2; /* 0x06c Type field for 1588v2 */
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u32 reserved070[4]; /* 0x070 */
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/* 10Ge Statistics Counter */
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u32 tfrm_u; /* 80 aFramesTransmittedOK */
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u32 tfrm_l; /* 84 aFramesTransmittedOK */
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u32 rfrm_u; /* 88 aFramesReceivedOK */
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u32 rfrm_l; /* 8c aFramesReceivedOK */
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u32 rfcs_u; /* 90 aFrameCheckSequenceErrors */
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u32 rfcs_l; /* 94 aFrameCheckSequenceErrors */
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u32 raln_u; /* 98 aAlignmentErrors */
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u32 raln_l; /* 9c aAlignmentErrors */
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u32 txpf_u; /* A0 aPAUSEMACCtrlFramesTransmitted */
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u32 txpf_l; /* A4 aPAUSEMACCtrlFramesTransmitted */
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u32 rxpf_u; /* A8 aPAUSEMACCtrlFramesReceived */
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u32 rxpf_l; /* Ac aPAUSEMACCtrlFramesReceived */
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u32 rlong_u; /* B0 aFrameTooLongErrors */
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u32 rlong_l; /* B4 aFrameTooLongErrors */
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u32 rflr_u; /* B8 aInRangeLengthErrors */
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u32 rflr_l; /* Bc aInRangeLengthErrors */
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u32 tvlan_u; /* C0 VLANTransmittedOK */
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u32 tvlan_l; /* C4 VLANTransmittedOK */
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u32 rvlan_u; /* C8 VLANReceivedOK */
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u32 rvlan_l; /* Cc VLANReceivedOK */
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u32 toct_u; /* D0 if_out_octets */
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u32 toct_l; /* D4 if_out_octets */
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u32 roct_u; /* D8 if_in_octets */
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u32 roct_l; /* Dc if_in_octets */
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u32 ruca_u; /* E0 if_in_ucast_pkts */
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u32 ruca_l; /* E4 if_in_ucast_pkts */
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u32 rmca_u; /* E8 ifInMulticastPkts */
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u32 rmca_l; /* Ec ifInMulticastPkts */
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u32 rbca_u; /* F0 ifInBroadcastPkts */
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u32 rbca_l; /* F4 ifInBroadcastPkts */
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u32 terr_u; /* F8 if_out_errors */
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u32 terr_l; /* Fc if_out_errors */
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u32 reserved100[2]; /* 100-108 */
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u32 tuca_u; /* 108 if_out_ucast_pkts */
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u32 tuca_l; /* 10c if_out_ucast_pkts */
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u32 tmca_u; /* 110 ifOutMulticastPkts */
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u32 tmca_l; /* 114 ifOutMulticastPkts */
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u32 tbca_u; /* 118 ifOutBroadcastPkts */
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u32 tbca_l; /* 11c ifOutBroadcastPkts */
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u32 rdrp_u; /* 120 etherStatsDropEvents */
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u32 rdrp_l; /* 124 etherStatsDropEvents */
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u32 reoct_u; /* 128 etherStatsOctets */
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u32 reoct_l; /* 12c etherStatsOctets */
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u32 rpkt_u; /* 130 etherStatsPkts */
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u32 rpkt_l; /* 134 etherStatsPkts */
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u32 trund_u; /* 138 etherStatsUndersizePkts */
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u32 trund_l; /* 13c etherStatsUndersizePkts */
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u32 r64_u; /* 140 etherStatsPkts64Octets */
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u32 r64_l; /* 144 etherStatsPkts64Octets */
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u32 r127_u; /* 148 etherStatsPkts65to127Octets */
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u32 r127_l; /* 14c etherStatsPkts65to127Octets */
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u32 r255_u; /* 150 etherStatsPkts128to255Octets */
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u32 r255_l; /* 154 etherStatsPkts128to255Octets */
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u32 r511_u; /* 158 etherStatsPkts256to511Octets */
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u32 r511_l; /* 15c etherStatsPkts256to511Octets */
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u32 r1023_u; /* 160 etherStatsPkts512to1023Octets */
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u32 r1023_l; /* 164 etherStatsPkts512to1023Octets */
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u32 r1518_u; /* 168 etherStatsPkts1024to1518Octets */
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u32 r1518_l; /* 16c etherStatsPkts1024to1518Octets */
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u32 r1519x_u; /* 170 etherStatsPkts1519toX */
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u32 r1519x_l; /* 174 etherStatsPkts1519toX */
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u32 trovr_u; /* 178 etherStatsOversizePkts */
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u32 trovr_l; /* 17c etherStatsOversizePkts */
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u32 trjbr_u; /* 180 etherStatsJabbers */
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u32 trjbr_l; /* 184 etherStatsJabbers */
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u32 trfrg_u; /* 188 etherStatsFragments */
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u32 trfrg_l; /* 18C etherStatsFragments */
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u32 rerr_u; /* 190 if_in_errors */
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u32 rerr_l; /* 194 if_in_errors */
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};
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struct tgec_cfg {
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bool pause_ignore;
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bool promiscuous_mode_enable;
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u16 max_frame_length;
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u16 pause_quant;
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u32 tx_ipg_length;
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};
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struct fman_mac {
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/* Pointer to the memory mapped registers. */
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struct tgec_regs __iomem *regs;
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/* MAC address of device; */
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u64 addr;
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u16 max_speed;
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void *dev_id; /* device cookie used by the exception cbs */
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fman_mac_exception_cb *exception_cb;
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fman_mac_exception_cb *event_cb;
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/* pointer to driver's global address hash table */
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struct eth_hash_t *multicast_addr_hash;
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/* pointer to driver's individual address hash table */
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struct eth_hash_t *unicast_addr_hash;
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u8 mac_id;
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u32 exceptions;
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struct tgec_cfg *cfg;
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void *fm;
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struct fman_rev_info fm_rev_info;
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bool allmulti_enabled;
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};
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static void set_mac_address(struct tgec_regs __iomem *regs, u8 *adr)
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{
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u32 tmp0, tmp1;
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tmp0 = (u32)(adr[0] | adr[1] << 8 | adr[2] << 16 | adr[3] << 24);
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tmp1 = (u32)(adr[4] | adr[5] << 8);
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iowrite32be(tmp0, ®s->mac_addr_0);
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iowrite32be(tmp1, ®s->mac_addr_1);
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}
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static void set_dflts(struct tgec_cfg *cfg)
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{
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cfg->promiscuous_mode_enable = false;
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cfg->pause_ignore = false;
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cfg->tx_ipg_length = DEFAULT_TX_IPG_LENGTH;
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cfg->max_frame_length = DEFAULT_MAX_FRAME_LENGTH;
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cfg->pause_quant = DEFAULT_PAUSE_QUANT;
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}
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static int init(struct tgec_regs __iomem *regs, struct tgec_cfg *cfg,
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u32 exception_mask)
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{
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u32 tmp;
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/* Config */
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tmp = CMF_CFG_CRC_FWD;
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if (cfg->promiscuous_mode_enable)
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tmp |= CMD_CFG_PROMIS_EN;
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if (cfg->pause_ignore)
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tmp |= CMD_CFG_PAUSE_IGNORE;
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/* Payload length check disable */
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tmp |= CMD_CFG_NO_LEN_CHK;
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iowrite32be(tmp, ®s->command_config);
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/* Max Frame Length */
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iowrite32be((u32)cfg->max_frame_length, ®s->maxfrm);
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/* Pause Time */
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iowrite32be(cfg->pause_quant, ®s->pause_quant);
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/* clear all pending events and set-up interrupts */
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iowrite32be(0xffffffff, ®s->ievent);
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iowrite32be(ioread32be(®s->imask) | exception_mask, ®s->imask);
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return 0;
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}
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static int check_init_parameters(struct fman_mac *tgec)
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{
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if (tgec->max_speed < SPEED_10000) {
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pr_err("10G MAC driver only support 10G speed\n");
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return -EINVAL;
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}
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if (!tgec->exception_cb) {
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pr_err("uninitialized exception_cb\n");
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return -EINVAL;
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}
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if (!tgec->event_cb) {
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pr_err("uninitialized event_cb\n");
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return -EINVAL;
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}
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return 0;
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}
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static int get_exception_flag(enum fman_mac_exceptions exception)
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{
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u32 bit_mask;
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switch (exception) {
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case FM_MAC_EX_10G_MDIO_SCAN_EVENT:
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bit_mask = TGEC_IMASK_MDIO_SCAN_EVENT;
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break;
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case FM_MAC_EX_10G_MDIO_CMD_CMPL:
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bit_mask = TGEC_IMASK_MDIO_CMD_CMPL;
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break;
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case FM_MAC_EX_10G_REM_FAULT:
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bit_mask = TGEC_IMASK_REM_FAULT;
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break;
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case FM_MAC_EX_10G_LOC_FAULT:
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bit_mask = TGEC_IMASK_LOC_FAULT;
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break;
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case FM_MAC_EX_10G_TX_ECC_ER:
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bit_mask = TGEC_IMASK_TX_ECC_ER;
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break;
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case FM_MAC_EX_10G_TX_FIFO_UNFL:
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bit_mask = TGEC_IMASK_TX_FIFO_UNFL;
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break;
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case FM_MAC_EX_10G_TX_FIFO_OVFL:
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bit_mask = TGEC_IMASK_TX_FIFO_OVFL;
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break;
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case FM_MAC_EX_10G_TX_ER:
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bit_mask = TGEC_IMASK_TX_ER;
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break;
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case FM_MAC_EX_10G_RX_FIFO_OVFL:
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bit_mask = TGEC_IMASK_RX_FIFO_OVFL;
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break;
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case FM_MAC_EX_10G_RX_ECC_ER:
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bit_mask = TGEC_IMASK_RX_ECC_ER;
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break;
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case FM_MAC_EX_10G_RX_JAB_FRM:
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bit_mask = TGEC_IMASK_RX_JAB_FRM;
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break;
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case FM_MAC_EX_10G_RX_OVRSZ_FRM:
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bit_mask = TGEC_IMASK_RX_OVRSZ_FRM;
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break;
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case FM_MAC_EX_10G_RX_RUNT_FRM:
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bit_mask = TGEC_IMASK_RX_RUNT_FRM;
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break;
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case FM_MAC_EX_10G_RX_FRAG_FRM:
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bit_mask = TGEC_IMASK_RX_FRAG_FRM;
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break;
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case FM_MAC_EX_10G_RX_LEN_ER:
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bit_mask = TGEC_IMASK_RX_LEN_ER;
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break;
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case FM_MAC_EX_10G_RX_CRC_ER:
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bit_mask = TGEC_IMASK_RX_CRC_ER;
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break;
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case FM_MAC_EX_10G_RX_ALIGN_ER:
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bit_mask = TGEC_IMASK_RX_ALIGN_ER;
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break;
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default:
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bit_mask = 0;
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break;
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}
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return bit_mask;
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}
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static void tgec_err_exception(void *handle)
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{
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struct fman_mac *tgec = (struct fman_mac *)handle;
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struct tgec_regs __iomem *regs = tgec->regs;
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u32 event;
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/* do not handle MDIO events */
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event = ioread32be(®s->ievent) &
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~(TGEC_IMASK_MDIO_SCAN_EVENT |
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TGEC_IMASK_MDIO_CMD_CMPL);
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event &= ioread32be(®s->imask);
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iowrite32be(event, ®s->ievent);
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if (event & TGEC_IMASK_REM_FAULT)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_REM_FAULT);
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if (event & TGEC_IMASK_LOC_FAULT)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_LOC_FAULT);
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if (event & TGEC_IMASK_TX_ECC_ER)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_ECC_ER);
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if (event & TGEC_IMASK_TX_FIFO_UNFL)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_FIFO_UNFL);
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if (event & TGEC_IMASK_TX_FIFO_OVFL)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_FIFO_OVFL);
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if (event & TGEC_IMASK_TX_ER)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_TX_ER);
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if (event & TGEC_IMASK_RX_FIFO_OVFL)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_FIFO_OVFL);
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if (event & TGEC_IMASK_RX_ECC_ER)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_ECC_ER);
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if (event & TGEC_IMASK_RX_JAB_FRM)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_JAB_FRM);
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if (event & TGEC_IMASK_RX_OVRSZ_FRM)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_OVRSZ_FRM);
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if (event & TGEC_IMASK_RX_RUNT_FRM)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_RUNT_FRM);
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if (event & TGEC_IMASK_RX_FRAG_FRM)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_FRAG_FRM);
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if (event & TGEC_IMASK_RX_LEN_ER)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_LEN_ER);
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if (event & TGEC_IMASK_RX_CRC_ER)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_CRC_ER);
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if (event & TGEC_IMASK_RX_ALIGN_ER)
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tgec->exception_cb(tgec->dev_id, FM_MAC_EX_10G_RX_ALIGN_ER);
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}
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static void free_init_resources(struct fman_mac *tgec)
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{
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fman_unregister_intr(tgec->fm, FMAN_MOD_MAC, tgec->mac_id,
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FMAN_INTR_TYPE_ERR);
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/* release the driver's group hash table */
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free_hash_table(tgec->multicast_addr_hash);
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tgec->multicast_addr_hash = NULL;
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/* release the driver's individual hash table */
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free_hash_table(tgec->unicast_addr_hash);
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tgec->unicast_addr_hash = NULL;
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}
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static bool is_init_done(struct tgec_cfg *cfg)
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{
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/* Checks if tGEC driver parameters were initialized */
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if (!cfg)
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return true;
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return false;
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}
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int tgec_enable(struct fman_mac *tgec, enum comm_mode mode)
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{
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struct tgec_regs __iomem *regs = tgec->regs;
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u32 tmp;
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if (!is_init_done(tgec->cfg))
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return -EINVAL;
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tmp = ioread32be(®s->command_config);
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if (mode & COMM_MODE_RX)
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tmp |= CMD_CFG_RX_EN;
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if (mode & COMM_MODE_TX)
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tmp |= CMD_CFG_TX_EN;
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iowrite32be(tmp, ®s->command_config);
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return 0;
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}
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int tgec_disable(struct fman_mac *tgec, enum comm_mode mode)
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{
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struct tgec_regs __iomem *regs = tgec->regs;
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u32 tmp;
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if (!is_init_done(tgec->cfg))
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return -EINVAL;
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tmp = ioread32be(®s->command_config);
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if (mode & COMM_MODE_RX)
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tmp &= ~CMD_CFG_RX_EN;
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if (mode & COMM_MODE_TX)
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tmp &= ~CMD_CFG_TX_EN;
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iowrite32be(tmp, ®s->command_config);
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return 0;
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}
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int tgec_set_promiscuous(struct fman_mac *tgec, bool new_val)
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{
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struct tgec_regs __iomem *regs = tgec->regs;
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u32 tmp;
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if (!is_init_done(tgec->cfg))
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return -EINVAL;
|
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tmp = ioread32be(®s->command_config);
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if (new_val)
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tmp |= CMD_CFG_PROMIS_EN;
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else
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tmp &= ~CMD_CFG_PROMIS_EN;
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iowrite32be(tmp, ®s->command_config);
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return 0;
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}
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int tgec_cfg_max_frame_len(struct fman_mac *tgec, u16 new_val)
|
{
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if (is_init_done(tgec->cfg))
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return -EINVAL;
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tgec->cfg->max_frame_length = new_val;
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return 0;
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}
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int tgec_set_tx_pause_frames(struct fman_mac *tgec, u8 __maybe_unused priority,
|
u16 pause_time, u16 __maybe_unused thresh_time)
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{
|
struct tgec_regs __iomem *regs = tgec->regs;
|
|
if (!is_init_done(tgec->cfg))
|
return -EINVAL;
|
|
iowrite32be((u32)pause_time, ®s->pause_quant);
|
|
return 0;
|
}
|
|
int tgec_accept_rx_pause_frames(struct fman_mac *tgec, bool en)
|
{
|
struct tgec_regs __iomem *regs = tgec->regs;
|
u32 tmp;
|
|
if (!is_init_done(tgec->cfg))
|
return -EINVAL;
|
|
tmp = ioread32be(®s->command_config);
|
if (!en)
|
tmp |= CMD_CFG_PAUSE_IGNORE;
|
else
|
tmp &= ~CMD_CFG_PAUSE_IGNORE;
|
iowrite32be(tmp, ®s->command_config);
|
|
return 0;
|
}
|
|
int tgec_modify_mac_address(struct fman_mac *tgec, enet_addr_t *p_enet_addr)
|
{
|
if (!is_init_done(tgec->cfg))
|
return -EINVAL;
|
|
tgec->addr = ENET_ADDR_TO_UINT64(*p_enet_addr);
|
set_mac_address(tgec->regs, (u8 *)(*p_enet_addr));
|
|
return 0;
|
}
|
|
int tgec_add_hash_mac_address(struct fman_mac *tgec, enet_addr_t *eth_addr)
|
{
|
struct tgec_regs __iomem *regs = tgec->regs;
|
struct eth_hash_entry *hash_entry;
|
u32 crc = 0xFFFFFFFF, hash;
|
u64 addr;
|
|
if (!is_init_done(tgec->cfg))
|
return -EINVAL;
|
|
addr = ENET_ADDR_TO_UINT64(*eth_addr);
|
|
if (!(addr & GROUP_ADDRESS)) {
|
/* Unicast addresses not supported in hash */
|
pr_err("Unicast Address\n");
|
return -EINVAL;
|
}
|
/* CRC calculation */
|
crc = crc32_le(crc, (u8 *)eth_addr, ETH_ALEN);
|
crc = bitrev32(crc);
|
/* Take 9 MSB bits */
|
hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK;
|
|
/* Create element to be added to the driver hash table */
|
hash_entry = kmalloc(sizeof(*hash_entry), GFP_ATOMIC);
|
if (!hash_entry)
|
return -ENOMEM;
|
hash_entry->addr = addr;
|
INIT_LIST_HEAD(&hash_entry->node);
|
|
list_add_tail(&hash_entry->node,
|
&tgec->multicast_addr_hash->lsts[hash]);
|
iowrite32be((hash | TGEC_HASH_MCAST_EN), ®s->hashtable_ctrl);
|
|
return 0;
|
}
|
|
int tgec_set_allmulti(struct fman_mac *tgec, bool enable)
|
{
|
u32 entry;
|
struct tgec_regs __iomem *regs = tgec->regs;
|
|
if (!is_init_done(tgec->cfg))
|
return -EINVAL;
|
|
if (enable) {
|
for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++)
|
iowrite32be(entry | TGEC_HASH_MCAST_EN,
|
®s->hashtable_ctrl);
|
} else {
|
for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++)
|
iowrite32be(entry & ~TGEC_HASH_MCAST_EN,
|
®s->hashtable_ctrl);
|
}
|
|
tgec->allmulti_enabled = enable;
|
|
return 0;
|
}
|
|
int tgec_set_tstamp(struct fman_mac *tgec, bool enable)
|
{
|
struct tgec_regs __iomem *regs = tgec->regs;
|
u32 tmp;
|
|
if (!is_init_done(tgec->cfg))
|
return -EINVAL;
|
|
tmp = ioread32be(®s->command_config);
|
|
if (enable)
|
tmp |= CMD_CFG_EN_TIMESTAMP;
|
else
|
tmp &= ~CMD_CFG_EN_TIMESTAMP;
|
|
iowrite32be(tmp, ®s->command_config);
|
|
return 0;
|
}
|
|
int tgec_del_hash_mac_address(struct fman_mac *tgec, enet_addr_t *eth_addr)
|
{
|
struct tgec_regs __iomem *regs = tgec->regs;
|
struct eth_hash_entry *hash_entry = NULL;
|
struct list_head *pos;
|
u32 crc = 0xFFFFFFFF, hash;
|
u64 addr;
|
|
if (!is_init_done(tgec->cfg))
|
return -EINVAL;
|
|
addr = ((*(u64 *)eth_addr) >> 16);
|
|
/* CRC calculation */
|
crc = crc32_le(crc, (u8 *)eth_addr, ETH_ALEN);
|
crc = bitrev32(crc);
|
/* Take 9 MSB bits */
|
hash = (crc >> TGEC_HASH_MCAST_SHIFT) & TGEC_HASH_ADR_MSK;
|
|
list_for_each(pos, &tgec->multicast_addr_hash->lsts[hash]) {
|
hash_entry = ETH_HASH_ENTRY_OBJ(pos);
|
if (hash_entry && hash_entry->addr == addr) {
|
list_del_init(&hash_entry->node);
|
kfree(hash_entry);
|
break;
|
}
|
}
|
|
if (!tgec->allmulti_enabled) {
|
if (list_empty(&tgec->multicast_addr_hash->lsts[hash]))
|
iowrite32be((hash & ~TGEC_HASH_MCAST_EN),
|
®s->hashtable_ctrl);
|
}
|
|
return 0;
|
}
|
|
int tgec_get_version(struct fman_mac *tgec, u32 *mac_version)
|
{
|
struct tgec_regs __iomem *regs = tgec->regs;
|
|
if (!is_init_done(tgec->cfg))
|
return -EINVAL;
|
|
*mac_version = ioread32be(®s->tgec_id);
|
|
return 0;
|
}
|
|
int tgec_set_exception(struct fman_mac *tgec,
|
enum fman_mac_exceptions exception, bool enable)
|
{
|
struct tgec_regs __iomem *regs = tgec->regs;
|
u32 bit_mask = 0;
|
|
if (!is_init_done(tgec->cfg))
|
return -EINVAL;
|
|
bit_mask = get_exception_flag(exception);
|
if (bit_mask) {
|
if (enable)
|
tgec->exceptions |= bit_mask;
|
else
|
tgec->exceptions &= ~bit_mask;
|
} else {
|
pr_err("Undefined exception\n");
|
return -EINVAL;
|
}
|
if (enable)
|
iowrite32be(ioread32be(®s->imask) | bit_mask, ®s->imask);
|
else
|
iowrite32be(ioread32be(®s->imask) & ~bit_mask, ®s->imask);
|
|
return 0;
|
}
|
|
int tgec_init(struct fman_mac *tgec)
|
{
|
struct tgec_cfg *cfg;
|
enet_addr_t eth_addr;
|
int err;
|
|
if (is_init_done(tgec->cfg))
|
return -EINVAL;
|
|
if (DEFAULT_RESET_ON_INIT &&
|
(fman_reset_mac(tgec->fm, tgec->mac_id) != 0)) {
|
pr_err("Can't reset MAC!\n");
|
return -EINVAL;
|
}
|
|
err = check_init_parameters(tgec);
|
if (err)
|
return err;
|
|
cfg = tgec->cfg;
|
|
if (tgec->addr) {
|
MAKE_ENET_ADDR_FROM_UINT64(tgec->addr, eth_addr);
|
set_mac_address(tgec->regs, (u8 *)eth_addr);
|
}
|
|
/* interrupts */
|
/* FM_10G_REM_N_LCL_FLT_EX_10GMAC_ERRATA_SW005 Errata workaround */
|
if (tgec->fm_rev_info.major <= 2)
|
tgec->exceptions &= ~(TGEC_IMASK_REM_FAULT |
|
TGEC_IMASK_LOC_FAULT);
|
|
err = init(tgec->regs, cfg, tgec->exceptions);
|
if (err) {
|
free_init_resources(tgec);
|
pr_err("TGEC version doesn't support this i/f mode\n");
|
return err;
|
}
|
|
/* Max Frame Length */
|
err = fman_set_mac_max_frame(tgec->fm, tgec->mac_id,
|
cfg->max_frame_length);
|
if (err) {
|
pr_err("Setting max frame length FAILED\n");
|
free_init_resources(tgec);
|
return -EINVAL;
|
}
|
|
/* FM_TX_FIFO_CORRUPTION_ERRATA_10GMAC_A007 Errata workaround */
|
if (tgec->fm_rev_info.major == 2) {
|
struct tgec_regs __iomem *regs = tgec->regs;
|
u32 tmp;
|
|
/* restore the default tx ipg Length */
|
tmp = (ioread32be(®s->tx_ipg_len) &
|
~TGEC_TX_IPG_LENGTH_MASK) | 12;
|
|
iowrite32be(tmp, ®s->tx_ipg_len);
|
}
|
|
tgec->multicast_addr_hash = alloc_hash_table(TGEC_HASH_TABLE_SIZE);
|
if (!tgec->multicast_addr_hash) {
|
free_init_resources(tgec);
|
pr_err("allocation hash table is FAILED\n");
|
return -ENOMEM;
|
}
|
|
tgec->unicast_addr_hash = alloc_hash_table(TGEC_HASH_TABLE_SIZE);
|
if (!tgec->unicast_addr_hash) {
|
free_init_resources(tgec);
|
pr_err("allocation hash table is FAILED\n");
|
return -ENOMEM;
|
}
|
|
fman_register_intr(tgec->fm, FMAN_MOD_MAC, tgec->mac_id,
|
FMAN_INTR_TYPE_ERR, tgec_err_exception, tgec);
|
|
kfree(cfg);
|
tgec->cfg = NULL;
|
|
return 0;
|
}
|
|
int tgec_free(struct fman_mac *tgec)
|
{
|
free_init_resources(tgec);
|
|
kfree(tgec->cfg);
|
kfree(tgec);
|
|
return 0;
|
}
|
|
struct fman_mac *tgec_config(struct fman_mac_params *params)
|
{
|
struct fman_mac *tgec;
|
struct tgec_cfg *cfg;
|
void __iomem *base_addr;
|
|
base_addr = params->base_addr;
|
/* allocate memory for the UCC GETH data structure. */
|
tgec = kzalloc(sizeof(*tgec), GFP_KERNEL);
|
if (!tgec)
|
return NULL;
|
|
/* allocate memory for the 10G MAC driver parameters data structure. */
|
cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
|
if (!cfg) {
|
tgec_free(tgec);
|
return NULL;
|
}
|
|
/* Plant parameter structure pointer */
|
tgec->cfg = cfg;
|
|
set_dflts(cfg);
|
|
tgec->regs = base_addr;
|
tgec->addr = ENET_ADDR_TO_UINT64(params->addr);
|
tgec->max_speed = params->max_speed;
|
tgec->mac_id = params->mac_id;
|
tgec->exceptions = (TGEC_IMASK_MDIO_SCAN_EVENT |
|
TGEC_IMASK_REM_FAULT |
|
TGEC_IMASK_LOC_FAULT |
|
TGEC_IMASK_TX_ECC_ER |
|
TGEC_IMASK_TX_FIFO_UNFL |
|
TGEC_IMASK_TX_FIFO_OVFL |
|
TGEC_IMASK_TX_ER |
|
TGEC_IMASK_RX_FIFO_OVFL |
|
TGEC_IMASK_RX_ECC_ER |
|
TGEC_IMASK_RX_JAB_FRM |
|
TGEC_IMASK_RX_OVRSZ_FRM |
|
TGEC_IMASK_RX_RUNT_FRM |
|
TGEC_IMASK_RX_FRAG_FRM |
|
TGEC_IMASK_RX_CRC_ER |
|
TGEC_IMASK_RX_ALIGN_ER);
|
tgec->exception_cb = params->exception_cb;
|
tgec->event_cb = params->event_cb;
|
tgec->dev_id = params->dev_id;
|
tgec->fm = params->fm;
|
|
/* Save FMan revision */
|
fman_get_revision(tgec->fm, &tgec->fm_rev_info);
|
|
return tgec;
|
}
|
