/*
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* Copyright 2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of NXP nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY NXP ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL NXP BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/slab.h>
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#include "fman_keygen.h"
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/* Maximum number of HW Ports */
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#define FMAN_MAX_NUM_OF_HW_PORTS 64
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/* Maximum number of KeyGen Schemes */
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#define FM_KG_MAX_NUM_OF_SCHEMES 32
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/* Number of generic KeyGen Generic Extract Command Registers */
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#define FM_KG_NUM_OF_GENERIC_REGS 8
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/* Dummy port ID */
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#define DUMMY_PORT_ID 0
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/* Select Scheme Value Register */
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#define KG_SCH_DEF_USE_KGSE_DV_0 2
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#define KG_SCH_DEF_USE_KGSE_DV_1 3
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/* Registers Shifting values */
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#define FM_KG_KGAR_NUM_SHIFT 16
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#define KG_SCH_DEF_L4_PORT_SHIFT 8
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#define KG_SCH_DEF_IP_ADDR_SHIFT 18
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#define KG_SCH_HASH_CONFIG_SHIFT_SHIFT 24
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/* KeyGen Registers bit field masks: */
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/* Enable bit field mask for KeyGen General Configuration Register */
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#define FM_KG_KGGCR_EN 0x80000000
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/* KeyGen Global Registers bit field masks */
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#define FM_KG_KGAR_GO 0x80000000
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#define FM_KG_KGAR_READ 0x40000000
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#define FM_KG_KGAR_WRITE 0x00000000
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#define FM_KG_KGAR_SEL_SCHEME_ENTRY 0x00000000
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#define FM_KG_KGAR_SCM_WSEL_UPDATE_CNT 0x00008000
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#define FM_KG_KGAR_ERR 0x20000000
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#define FM_KG_KGAR_SEL_CLS_PLAN_ENTRY 0x01000000
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#define FM_KG_KGAR_SEL_PORT_ENTRY 0x02000000
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#define FM_KG_KGAR_SEL_PORT_WSEL_SP 0x00008000
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#define FM_KG_KGAR_SEL_PORT_WSEL_CPP 0x00004000
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/* Error events exceptions */
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#define FM_EX_KG_DOUBLE_ECC 0x80000000
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#define FM_EX_KG_KEYSIZE_OVERFLOW 0x40000000
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/* Scheme Registers bit field masks */
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#define KG_SCH_MODE_EN 0x80000000
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#define KG_SCH_VSP_NO_KSP_EN 0x80000000
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#define KG_SCH_HASH_CONFIG_SYM 0x40000000
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/* Known Protocol field codes */
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#define KG_SCH_KN_PORT_ID 0x80000000
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#define KG_SCH_KN_MACDST 0x40000000
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#define KG_SCH_KN_MACSRC 0x20000000
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#define KG_SCH_KN_TCI1 0x10000000
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#define KG_SCH_KN_TCI2 0x08000000
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#define KG_SCH_KN_ETYPE 0x04000000
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#define KG_SCH_KN_PPPSID 0x02000000
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#define KG_SCH_KN_PPPID 0x01000000
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#define KG_SCH_KN_MPLS1 0x00800000
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#define KG_SCH_KN_MPLS2 0x00400000
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#define KG_SCH_KN_MPLS_LAST 0x00200000
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#define KG_SCH_KN_IPSRC1 0x00100000
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#define KG_SCH_KN_IPDST1 0x00080000
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#define KG_SCH_KN_PTYPE1 0x00040000
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#define KG_SCH_KN_IPTOS_TC1 0x00020000
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#define KG_SCH_KN_IPV6FL1 0x00010000
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#define KG_SCH_KN_IPSRC2 0x00008000
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#define KG_SCH_KN_IPDST2 0x00004000
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#define KG_SCH_KN_PTYPE2 0x00002000
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#define KG_SCH_KN_IPTOS_TC2 0x00001000
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#define KG_SCH_KN_IPV6FL2 0x00000800
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#define KG_SCH_KN_GREPTYPE 0x00000400
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#define KG_SCH_KN_IPSEC_SPI 0x00000200
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#define KG_SCH_KN_IPSEC_NH 0x00000100
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#define KG_SCH_KN_IPPID 0x00000080
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#define KG_SCH_KN_L4PSRC 0x00000004
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#define KG_SCH_KN_L4PDST 0x00000002
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#define KG_SCH_KN_TFLG 0x00000001
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/* NIA values */
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#define NIA_ENG_BMI 0x00500000
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#define NIA_BMI_AC_ENQ_FRAME 0x00000002
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#define ENQUEUE_KG_DFLT_NIA (NIA_ENG_BMI | NIA_BMI_AC_ENQ_FRAME)
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/* Hard-coded configuration:
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* These values are used as hard-coded values for KeyGen configuration
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* and they replace user selections for this hard-coded version
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*/
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/* Hash distribution shift */
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#define DEFAULT_HASH_DIST_FQID_SHIFT 0
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/* Hash shift */
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#define DEFAULT_HASH_SHIFT 0
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/* Symmetric hash usage:
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* Warning:
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* - the value for symmetric hash usage must be in accordance with hash
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* key defined below
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* - according to tests performed, spreading is not working if symmetric
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* hash is set on true
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* So ultimately symmetric hash functionality should be always disabled:
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*/
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#define DEFAULT_SYMMETRIC_HASH false
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/* Hash Key extraction fields: */
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#define DEFAULT_HASH_KEY_EXTRACT_FIELDS \
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(KG_SCH_KN_IPSRC1 | KG_SCH_KN_IPDST1 | \
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KG_SCH_KN_L4PSRC | KG_SCH_KN_L4PDST | \
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KG_SCH_KN_IPSEC_SPI)
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/* Default values to be used as hash key in case IPv4 or L4 (TCP, UDP)
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* don't exist in the frame
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*/
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/* Default IPv4 address */
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#define DEFAULT_HASH_KEY_IPv4_ADDR 0x0A0A0A0A
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/* Default L4 port */
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#define DEFAULT_HASH_KEY_L4_PORT 0x0B0B0B0B
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/* KeyGen Memory Mapped Registers: */
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/* Scheme Configuration RAM Registers */
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struct fman_kg_scheme_regs {
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u32 kgse_mode; /* 0x100: MODE */
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u32 kgse_ekfc; /* 0x104: Extract Known Fields Command */
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u32 kgse_ekdv; /* 0x108: Extract Known Default Value */
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u32 kgse_bmch; /* 0x10C: Bit Mask Command High */
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u32 kgse_bmcl; /* 0x110: Bit Mask Command Low */
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u32 kgse_fqb; /* 0x114: Frame Queue Base */
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u32 kgse_hc; /* 0x118: Hash Command */
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u32 kgse_ppc; /* 0x11C: Policer Profile Command */
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u32 kgse_gec[FM_KG_NUM_OF_GENERIC_REGS];
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/* 0x120: Generic Extract Command */
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u32 kgse_spc;
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/* 0x140: KeyGen Scheme Entry Statistic Packet Counter */
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u32 kgse_dv0; /* 0x144: KeyGen Scheme Entry Default Value 0 */
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u32 kgse_dv1; /* 0x148: KeyGen Scheme Entry Default Value 1 */
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u32 kgse_ccbs;
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/* 0x14C: KeyGen Scheme Entry Coarse Classification Bit*/
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u32 kgse_mv; /* 0x150: KeyGen Scheme Entry Match vector */
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u32 kgse_om; /* 0x154: KeyGen Scheme Entry Operation Mode bits */
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u32 kgse_vsp;
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/* 0x158: KeyGen Scheme Entry Virtual Storage Profile */
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};
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/* Port Partition Configuration Registers */
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struct fman_kg_pe_regs {
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u32 fmkg_pe_sp; /* 0x100: KeyGen Port entry Scheme Partition */
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u32 fmkg_pe_cpp;
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/* 0x104: KeyGen Port Entry Classification Plan Partition */
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};
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/* General Configuration and Status Registers
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* Global Statistic Counters
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* KeyGen Global Registers
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*/
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struct fman_kg_regs {
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u32 fmkg_gcr; /* 0x000: KeyGen General Configuration Register */
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u32 res004; /* 0x004: Reserved */
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u32 res008; /* 0x008: Reserved */
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u32 fmkg_eer; /* 0x00C: KeyGen Error Event Register */
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u32 fmkg_eeer; /* 0x010: KeyGen Error Event Enable Register */
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u32 res014; /* 0x014: Reserved */
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u32 res018; /* 0x018: Reserved */
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u32 fmkg_seer; /* 0x01C: KeyGen Scheme Error Event Register */
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u32 fmkg_seeer; /* 0x020: KeyGen Scheme Error Event Enable Register */
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u32 fmkg_gsr; /* 0x024: KeyGen Global Status Register */
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u32 fmkg_tpc; /* 0x028: Total Packet Counter Register */
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u32 fmkg_serc; /* 0x02C: Soft Error Capture Register */
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u32 res030[4]; /* 0x030: Reserved */
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u32 fmkg_fdor; /* 0x034: Frame Data Offset Register */
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u32 fmkg_gdv0r; /* 0x038: Global Default Value Register 0 */
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u32 fmkg_gdv1r; /* 0x03C: Global Default Value Register 1 */
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u32 res04c[6]; /* 0x040: Reserved */
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u32 fmkg_feer; /* 0x044: Force Error Event Register */
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u32 res068[38]; /* 0x048: Reserved */
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union {
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u32 fmkg_indirect[63]; /* 0x100: Indirect Access Registers */
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struct fman_kg_scheme_regs fmkg_sch; /* Scheme Registers */
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struct fman_kg_pe_regs fmkg_pe; /* Port Partition Registers */
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};
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u32 fmkg_ar; /* 0x1FC: KeyGen Action Register */
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};
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/* KeyGen Scheme data */
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struct keygen_scheme {
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bool used; /* Specifies if this scheme is used */
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u8 hw_port_id;
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/* Hardware port ID
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* schemes sharing between multiple ports is not
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* currently supported
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* so we have only one port id bound to a scheme
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*/
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u32 base_fqid;
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/* Base FQID:
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* Must be between 1 and 2^24-1
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* If hash is used and an even distribution is
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* expected according to hash_fqid_count,
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* base_fqid must be aligned to hash_fqid_count
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*/
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u32 hash_fqid_count;
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/* FQ range for hash distribution:
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* Must be a power of 2
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* Represents the range of queues for spreading
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*/
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bool use_hashing; /* Usage of Hashing and spreading over FQ */
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bool symmetric_hash; /* Symmetric Hash option usage */
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u8 hashShift;
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/* Hash result right shift.
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* Select the 24 bits out of the 64 hash result.
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* 0 means using the 24 LSB's, otherwise
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* use the 24 LSB's after shifting right
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*/
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u32 match_vector; /* Match Vector */
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};
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/* KeyGen driver data */
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struct fman_keygen {
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struct keygen_scheme schemes[FM_KG_MAX_NUM_OF_SCHEMES];
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/* Array of schemes */
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struct fman_kg_regs __iomem *keygen_regs; /* KeyGen registers */
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};
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/* keygen_write_ar_wait
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*
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* Write Action Register with specified value, wait for GO bit field to be
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* idle and then read the error
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*
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* regs: KeyGen registers
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* fmkg_ar: Action Register value
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*
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* Return: Zero for success or error code in case of failure
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*/
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static int keygen_write_ar_wait(struct fman_kg_regs __iomem *regs, u32 fmkg_ar)
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{
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iowrite32be(fmkg_ar, ®s->fmkg_ar);
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/* Wait for GO bit field to be idle */
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while (fmkg_ar & FM_KG_KGAR_GO)
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fmkg_ar = ioread32be(®s->fmkg_ar);
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if (fmkg_ar & FM_KG_KGAR_ERR)
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return -EINVAL;
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return 0;
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}
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/* build_ar_scheme
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*
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* Build Action Register value for scheme settings
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*
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* scheme_id: Scheme ID
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* update_counter: update scheme counter
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* write: true for action to write the scheme or false for read action
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*
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* Return: AR value
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*/
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static u32 build_ar_scheme(u8 scheme_id, bool update_counter, bool write)
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{
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u32 rw = (u32)(write ? FM_KG_KGAR_WRITE : FM_KG_KGAR_READ);
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return (u32)(FM_KG_KGAR_GO |
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rw |
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FM_KG_KGAR_SEL_SCHEME_ENTRY |
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DUMMY_PORT_ID |
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((u32)scheme_id << FM_KG_KGAR_NUM_SHIFT) |
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(update_counter ? FM_KG_KGAR_SCM_WSEL_UPDATE_CNT : 0));
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}
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/* build_ar_bind_scheme
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*
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* Build Action Register value for port binding to schemes
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*
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* hwport_id: HW Port ID
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* write: true for action to write the bind or false for read action
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*
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* Return: AR value
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*/
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static u32 build_ar_bind_scheme(u8 hwport_id, bool write)
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{
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u32 rw = write ? (u32)FM_KG_KGAR_WRITE : (u32)FM_KG_KGAR_READ;
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return (u32)(FM_KG_KGAR_GO |
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rw |
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FM_KG_KGAR_SEL_PORT_ENTRY |
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hwport_id |
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FM_KG_KGAR_SEL_PORT_WSEL_SP);
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}
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/* keygen_write_sp
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*
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* Write Scheme Partition Register with specified value
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*
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* regs: KeyGen Registers
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* sp: Scheme Partition register value
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* add: true to add a scheme partition or false to clear
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*
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* Return: none
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*/
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static void keygen_write_sp(struct fman_kg_regs __iomem *regs, u32 sp, bool add)
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{
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u32 tmp;
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tmp = ioread32be(®s->fmkg_pe.fmkg_pe_sp);
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if (add)
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tmp |= sp;
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else
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tmp &= ~sp;
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iowrite32be(tmp, ®s->fmkg_pe.fmkg_pe_sp);
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}
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/* build_ar_bind_cls_plan
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*
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* Build Action Register value for Classification Plan
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*
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* hwport_id: HW Port ID
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* write: true for action to write the CP or false for read action
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*
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* Return: AR value
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*/
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static u32 build_ar_bind_cls_plan(u8 hwport_id, bool write)
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{
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u32 rw = write ? (u32)FM_KG_KGAR_WRITE : (u32)FM_KG_KGAR_READ;
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return (u32)(FM_KG_KGAR_GO |
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rw |
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FM_KG_KGAR_SEL_PORT_ENTRY |
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hwport_id |
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FM_KG_KGAR_SEL_PORT_WSEL_CPP);
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}
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/* keygen_write_cpp
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*
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* Write Classification Plan Partition Register with specified value
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*
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* regs: KeyGen Registers
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* cpp: CPP register value
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*
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* Return: none
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*/
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static void keygen_write_cpp(struct fman_kg_regs __iomem *regs, u32 cpp)
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{
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iowrite32be(cpp, ®s->fmkg_pe.fmkg_pe_cpp);
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}
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/* keygen_write_scheme
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*
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* Write all Schemes Registers with specified values
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*
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* regs: KeyGen Registers
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* scheme_id: Scheme ID
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* scheme_regs: Scheme registers values desired to be written
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* update_counter: update scheme counter
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*
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* Return: Zero for success or error code in case of failure
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*/
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static int keygen_write_scheme(struct fman_kg_regs __iomem *regs, u8 scheme_id,
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struct fman_kg_scheme_regs *scheme_regs,
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bool update_counter)
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{
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u32 ar_reg;
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int err, i;
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/* Write indirect scheme registers */
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iowrite32be(scheme_regs->kgse_mode, ®s->fmkg_sch.kgse_mode);
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iowrite32be(scheme_regs->kgse_ekfc, ®s->fmkg_sch.kgse_ekfc);
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iowrite32be(scheme_regs->kgse_ekdv, ®s->fmkg_sch.kgse_ekdv);
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iowrite32be(scheme_regs->kgse_bmch, ®s->fmkg_sch.kgse_bmch);
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iowrite32be(scheme_regs->kgse_bmcl, ®s->fmkg_sch.kgse_bmcl);
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iowrite32be(scheme_regs->kgse_fqb, ®s->fmkg_sch.kgse_fqb);
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iowrite32be(scheme_regs->kgse_hc, ®s->fmkg_sch.kgse_hc);
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iowrite32be(scheme_regs->kgse_ppc, ®s->fmkg_sch.kgse_ppc);
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iowrite32be(scheme_regs->kgse_spc, ®s->fmkg_sch.kgse_spc);
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iowrite32be(scheme_regs->kgse_dv0, ®s->fmkg_sch.kgse_dv0);
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iowrite32be(scheme_regs->kgse_dv1, ®s->fmkg_sch.kgse_dv1);
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iowrite32be(scheme_regs->kgse_ccbs, ®s->fmkg_sch.kgse_ccbs);
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iowrite32be(scheme_regs->kgse_mv, ®s->fmkg_sch.kgse_mv);
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iowrite32be(scheme_regs->kgse_om, ®s->fmkg_sch.kgse_om);
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iowrite32be(scheme_regs->kgse_vsp, ®s->fmkg_sch.kgse_vsp);
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for (i = 0 ; i < FM_KG_NUM_OF_GENERIC_REGS ; i++)
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iowrite32be(scheme_regs->kgse_gec[i],
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®s->fmkg_sch.kgse_gec[i]);
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/* Write AR (Action register) */
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ar_reg = build_ar_scheme(scheme_id, update_counter, true);
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err = keygen_write_ar_wait(regs, ar_reg);
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if (err != 0) {
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pr_err("Writing Action Register failed\n");
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return err;
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}
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return err;
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}
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/* get_free_scheme_id
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*
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* Find the first free scheme available to be used
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*
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* keygen: KeyGen handle
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* scheme_id: pointer to scheme id
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*
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* Return: 0 on success, -EINVAL when the are no available free schemes
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*/
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static int get_free_scheme_id(struct fman_keygen *keygen, u8 *scheme_id)
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{
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u8 i;
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for (i = 0; i < FM_KG_MAX_NUM_OF_SCHEMES; i++)
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if (!keygen->schemes[i].used) {
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*scheme_id = i;
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return 0;
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}
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return -EINVAL;
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}
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/* get_scheme
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*
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* Provides the scheme for specified ID
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*
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* keygen: KeyGen handle
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* scheme_id: Scheme ID
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*
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* Return: handle to required scheme
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*/
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static struct keygen_scheme *get_scheme(struct fman_keygen *keygen,
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u8 scheme_id)
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{
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if (scheme_id >= FM_KG_MAX_NUM_OF_SCHEMES)
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return NULL;
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return &keygen->schemes[scheme_id];
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}
|
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/* keygen_bind_port_to_schemes
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*
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* Bind the port to schemes
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*
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* keygen: KeyGen handle
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* scheme_id: id of the scheme to bind to
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* bind: true to bind the port or false to unbind it
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*
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* Return: Zero for success or error code in case of failure
|
*/
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static int keygen_bind_port_to_schemes(struct fman_keygen *keygen,
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u8 scheme_id,
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bool bind)
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{
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struct fman_kg_regs __iomem *keygen_regs = keygen->keygen_regs;
|
struct keygen_scheme *scheme;
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u32 ar_reg;
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u32 schemes_vector = 0;
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int err;
|
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scheme = get_scheme(keygen, scheme_id);
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if (!scheme) {
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pr_err("Requested Scheme does not exist\n");
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return -EINVAL;
|
}
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if (!scheme->used) {
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pr_err("Cannot bind port to an invalid scheme\n");
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return -EINVAL;
|
}
|
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schemes_vector |= 1 << (31 - scheme_id);
|
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ar_reg = build_ar_bind_scheme(scheme->hw_port_id, false);
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err = keygen_write_ar_wait(keygen_regs, ar_reg);
|
if (err != 0) {
|
pr_err("Reading Action Register failed\n");
|
return err;
|
}
|
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keygen_write_sp(keygen_regs, schemes_vector, bind);
|
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ar_reg = build_ar_bind_scheme(scheme->hw_port_id, true);
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err = keygen_write_ar_wait(keygen_regs, ar_reg);
|
if (err != 0) {
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pr_err("Writing Action Register failed\n");
|
return err;
|
}
|
|
return 0;
|
}
|
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/* keygen_scheme_setup
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*
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* Setup the scheme according to required configuration
|
*
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* keygen: KeyGen handle
|
* scheme_id: scheme ID
|
* enable: true to enable scheme or false to disable it
|
*
|
* Return: Zero for success or error code in case of failure
|
*/
|
static int keygen_scheme_setup(struct fman_keygen *keygen, u8 scheme_id,
|
bool enable)
|
{
|
struct fman_kg_regs __iomem *keygen_regs = keygen->keygen_regs;
|
struct fman_kg_scheme_regs scheme_regs;
|
struct keygen_scheme *scheme;
|
u32 tmp_reg;
|
int err;
|
|
scheme = get_scheme(keygen, scheme_id);
|
if (!scheme) {
|
pr_err("Requested Scheme does not exist\n");
|
return -EINVAL;
|
}
|
if (enable && scheme->used) {
|
pr_err("The requested Scheme is already used\n");
|
return -EINVAL;
|
}
|
|
/* Clear scheme registers */
|
memset(&scheme_regs, 0, sizeof(struct fman_kg_scheme_regs));
|
|
/* Setup all scheme registers: */
|
tmp_reg = 0;
|
|
if (enable) {
|
/* Enable Scheme */
|
tmp_reg |= KG_SCH_MODE_EN;
|
/* Enqueue frame NIA */
|
tmp_reg |= ENQUEUE_KG_DFLT_NIA;
|
}
|
|
scheme_regs.kgse_mode = tmp_reg;
|
|
scheme_regs.kgse_mv = scheme->match_vector;
|
|
/* Scheme don't override StorageProfile:
|
* valid only for DPAA_VERSION >= 11
|
*/
|
scheme_regs.kgse_vsp = KG_SCH_VSP_NO_KSP_EN;
|
|
/* Configure Hard-Coded Rx Hashing: */
|
|
if (scheme->use_hashing) {
|
/* configure kgse_ekfc */
|
scheme_regs.kgse_ekfc = DEFAULT_HASH_KEY_EXTRACT_FIELDS;
|
|
/* configure kgse_ekdv */
|
tmp_reg = 0;
|
tmp_reg |= (KG_SCH_DEF_USE_KGSE_DV_0 <<
|
KG_SCH_DEF_IP_ADDR_SHIFT);
|
tmp_reg |= (KG_SCH_DEF_USE_KGSE_DV_1 <<
|
KG_SCH_DEF_L4_PORT_SHIFT);
|
scheme_regs.kgse_ekdv = tmp_reg;
|
|
/* configure kgse_dv0 */
|
scheme_regs.kgse_dv0 = DEFAULT_HASH_KEY_IPv4_ADDR;
|
/* configure kgse_dv1 */
|
scheme_regs.kgse_dv1 = DEFAULT_HASH_KEY_L4_PORT;
|
|
/* configure kgse_hc */
|
tmp_reg = 0;
|
tmp_reg |= ((scheme->hash_fqid_count - 1) <<
|
DEFAULT_HASH_DIST_FQID_SHIFT);
|
tmp_reg |= scheme->hashShift << KG_SCH_HASH_CONFIG_SHIFT_SHIFT;
|
|
if (scheme->symmetric_hash) {
|
/* Normally extraction key should be verified if
|
* complies with symmetric hash
|
* But because extraction is hard-coded, we are sure
|
* the key is symmetric
|
*/
|
tmp_reg |= KG_SCH_HASH_CONFIG_SYM;
|
}
|
scheme_regs.kgse_hc = tmp_reg;
|
} else {
|
scheme_regs.kgse_ekfc = 0;
|
scheme_regs.kgse_hc = 0;
|
scheme_regs.kgse_ekdv = 0;
|
scheme_regs.kgse_dv0 = 0;
|
scheme_regs.kgse_dv1 = 0;
|
}
|
|
/* configure kgse_fqb: Scheme FQID base */
|
tmp_reg = 0;
|
tmp_reg |= scheme->base_fqid;
|
scheme_regs.kgse_fqb = tmp_reg;
|
|
/* features not used by hard-coded configuration */
|
scheme_regs.kgse_bmch = 0;
|
scheme_regs.kgse_bmcl = 0;
|
scheme_regs.kgse_spc = 0;
|
|
/* Write scheme registers */
|
err = keygen_write_scheme(keygen_regs, scheme_id, &scheme_regs, true);
|
if (err != 0) {
|
pr_err("Writing scheme registers failed\n");
|
return err;
|
}
|
|
/* Update used field for Scheme */
|
scheme->used = enable;
|
|
return 0;
|
}
|
|
/* keygen_init
|
*
|
* KeyGen initialization:
|
* Initializes and enables KeyGen, allocate driver memory, setup registers,
|
* clear port bindings, invalidate all schemes
|
*
|
* keygen_regs: KeyGen registers base address
|
*
|
* Return: Handle to KeyGen driver
|
*/
|
struct fman_keygen *keygen_init(struct fman_kg_regs __iomem *keygen_regs)
|
{
|
struct fman_keygen *keygen;
|
u32 ar;
|
int i;
|
|
/* Allocate memory for KeyGen driver */
|
keygen = kzalloc(sizeof(*keygen), GFP_KERNEL);
|
if (!keygen)
|
return NULL;
|
|
keygen->keygen_regs = keygen_regs;
|
|
/* KeyGen initialization (for Master partition):
|
* Setup KeyGen registers
|
*/
|
iowrite32be(ENQUEUE_KG_DFLT_NIA, &keygen_regs->fmkg_gcr);
|
|
iowrite32be(FM_EX_KG_DOUBLE_ECC | FM_EX_KG_KEYSIZE_OVERFLOW,
|
&keygen_regs->fmkg_eer);
|
|
iowrite32be(0, &keygen_regs->fmkg_fdor);
|
iowrite32be(0, &keygen_regs->fmkg_gdv0r);
|
iowrite32be(0, &keygen_regs->fmkg_gdv1r);
|
|
/* Clear binding between ports to schemes and classification plans
|
* so that all ports are not bound to any scheme/classification plan
|
*/
|
for (i = 0; i < FMAN_MAX_NUM_OF_HW_PORTS; i++) {
|
/* Clear all pe sp schemes registers */
|
keygen_write_sp(keygen_regs, 0xffffffff, false);
|
ar = build_ar_bind_scheme(i, true);
|
keygen_write_ar_wait(keygen_regs, ar);
|
|
/* Clear all pe cpp classification plans registers */
|
keygen_write_cpp(keygen_regs, 0);
|
ar = build_ar_bind_cls_plan(i, true);
|
keygen_write_ar_wait(keygen_regs, ar);
|
}
|
|
/* Enable all scheme interrupts */
|
iowrite32be(0xFFFFFFFF, &keygen_regs->fmkg_seer);
|
iowrite32be(0xFFFFFFFF, &keygen_regs->fmkg_seeer);
|
|
/* Enable KyeGen */
|
iowrite32be(ioread32be(&keygen_regs->fmkg_gcr) | FM_KG_KGGCR_EN,
|
&keygen_regs->fmkg_gcr);
|
|
return keygen;
|
}
|
EXPORT_SYMBOL(keygen_init);
|
|
/* keygen_port_hashing_init
|
*
|
* Initializes a port for Rx Hashing with specified configuration parameters
|
*
|
* keygen: KeyGen handle
|
* hw_port_id: HW Port ID
|
* hash_base_fqid: Hashing Base FQID used for spreading
|
* hash_size: Hashing size
|
*
|
* Return: Zero for success or error code in case of failure
|
*/
|
int keygen_port_hashing_init(struct fman_keygen *keygen, u8 hw_port_id,
|
u32 hash_base_fqid, u32 hash_size)
|
{
|
struct keygen_scheme *scheme;
|
u8 scheme_id;
|
int err;
|
|
/* Validate Scheme configuration parameters */
|
if (hash_base_fqid == 0 || (hash_base_fqid & ~0x00FFFFFF)) {
|
pr_err("Base FQID must be between 1 and 2^24-1\n");
|
return -EINVAL;
|
}
|
if (hash_size == 0 || (hash_size & (hash_size - 1)) != 0) {
|
pr_err("Hash size must be power of two\n");
|
return -EINVAL;
|
}
|
|
/* Find a free scheme */
|
err = get_free_scheme_id(keygen, &scheme_id);
|
if (err) {
|
pr_err("The maximum number of available Schemes has been exceeded\n");
|
return -EINVAL;
|
}
|
|
/* Create and configure Hard-Coded Scheme: */
|
|
scheme = get_scheme(keygen, scheme_id);
|
if (!scheme) {
|
pr_err("Requested Scheme does not exist\n");
|
return -EINVAL;
|
}
|
if (scheme->used) {
|
pr_err("The requested Scheme is already used\n");
|
return -EINVAL;
|
}
|
|
/* Clear all scheme fields because the scheme may have been
|
* previously used
|
*/
|
memset(scheme, 0, sizeof(struct keygen_scheme));
|
|
/* Setup scheme: */
|
scheme->hw_port_id = hw_port_id;
|
scheme->use_hashing = true;
|
scheme->base_fqid = hash_base_fqid;
|
scheme->hash_fqid_count = hash_size;
|
scheme->symmetric_hash = DEFAULT_SYMMETRIC_HASH;
|
scheme->hashShift = DEFAULT_HASH_SHIFT;
|
|
/* All Schemes in hard-coded configuration
|
* are Indirect Schemes
|
*/
|
scheme->match_vector = 0;
|
|
err = keygen_scheme_setup(keygen, scheme_id, true);
|
if (err != 0) {
|
pr_err("Scheme setup failed\n");
|
return err;
|
}
|
|
/* Bind Rx port to Scheme */
|
err = keygen_bind_port_to_schemes(keygen, scheme_id, true);
|
if (err != 0) {
|
pr_err("Binding port to schemes failed\n");
|
return err;
|
}
|
|
return 0;
|
}
|
EXPORT_SYMBOL(keygen_port_hashing_init);
|
