// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Driver for the Macintosh 68K onboard MACE controller with PSC
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* driven DMA. The MACE driver code is derived from mace.c. The
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* Mac68k theory of operation is courtesy of the MacBSD wizards.
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*
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* Copyright (C) 1996 Paul Mackerras.
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* Copyright (C) 1998 Alan Cox <alan@lxorguk.ukuu.org.uk>
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*
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* Modified heavily by Joshua M. Thompson based on Dave Huang's NetBSD driver
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*
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* Copyright (C) 2007 Finn Thain
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*
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* Converted to DMA API, converted to unified driver model,
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* sync'd some routines with mace.c and fixed various bugs.
|
*/
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|
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/crc32.h>
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#include <linux/bitrev.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_device.h>
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#include <linux/gfp.h>
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#include <linux/interrupt.h>
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#include <asm/io.h>
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#include <asm/macints.h>
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#include <asm/mac_psc.h>
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#include <asm/page.h>
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#include "mace.h"
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|
static char mac_mace_string[] = "macmace";
|
|
#define N_TX_BUFF_ORDER 0
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#define N_TX_RING (1 << N_TX_BUFF_ORDER)
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#define N_RX_BUFF_ORDER 3
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#define N_RX_RING (1 << N_RX_BUFF_ORDER)
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|
#define TX_TIMEOUT HZ
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#define MACE_BUFF_SIZE 0x800
|
|
/* Chip rev needs workaround on HW & multicast addr change */
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#define BROKEN_ADDRCHG_REV 0x0941
|
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/* The MACE is simply wired down on a Mac68K box */
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|
#define MACE_BASE (void *)(0x50F1C000)
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#define MACE_PROM (void *)(0x50F08001)
|
|
struct mace_data {
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volatile struct mace *mace;
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unsigned char *tx_ring;
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dma_addr_t tx_ring_phys;
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unsigned char *rx_ring;
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dma_addr_t rx_ring_phys;
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int dma_intr;
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int rx_slot, rx_tail;
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int tx_slot, tx_sloti, tx_count;
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int chipid;
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struct device *device;
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};
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|
struct mace_frame {
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u8 rcvcnt;
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u8 pad1;
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u8 rcvsts;
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u8 pad2;
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u8 rntpc;
|
u8 pad3;
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u8 rcvcc;
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u8 pad4;
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u32 pad5;
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u32 pad6;
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u8 data[1];
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/* And frame continues.. */
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};
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#define PRIV_BYTES sizeof(struct mace_data)
|
|
static int mace_open(struct net_device *dev);
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static int mace_close(struct net_device *dev);
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static netdev_tx_t mace_xmit_start(struct sk_buff *skb, struct net_device *dev);
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static void mace_set_multicast(struct net_device *dev);
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static int mace_set_address(struct net_device *dev, void *addr);
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static void mace_reset(struct net_device *dev);
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static irqreturn_t mace_interrupt(int irq, void *dev_id);
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static irqreturn_t mace_dma_intr(int irq, void *dev_id);
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static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue);
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static void __mace_set_address(struct net_device *dev, void *addr);
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/*
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* Load a receive DMA channel with a base address and ring length
|
*/
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static void mace_load_rxdma_base(struct net_device *dev, int set)
|
{
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struct mace_data *mp = netdev_priv(dev);
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psc_write_word(PSC_ENETRD_CMD + set, 0x0100);
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psc_write_long(PSC_ENETRD_ADDR + set, (u32) mp->rx_ring_phys);
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psc_write_long(PSC_ENETRD_LEN + set, N_RX_RING);
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psc_write_word(PSC_ENETRD_CMD + set, 0x9800);
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mp->rx_tail = 0;
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}
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/*
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* Reset the receive DMA subsystem
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*/
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static void mace_rxdma_reset(struct net_device *dev)
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{
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struct mace_data *mp = netdev_priv(dev);
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volatile struct mace *mace = mp->mace;
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u8 maccc = mace->maccc;
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|
mace->maccc = maccc & ~ENRCV;
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psc_write_word(PSC_ENETRD_CTL, 0x8800);
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mace_load_rxdma_base(dev, 0x00);
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psc_write_word(PSC_ENETRD_CTL, 0x0400);
|
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psc_write_word(PSC_ENETRD_CTL, 0x8800);
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mace_load_rxdma_base(dev, 0x10);
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psc_write_word(PSC_ENETRD_CTL, 0x0400);
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mace->maccc = maccc;
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mp->rx_slot = 0;
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psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800);
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psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800);
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}
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/*
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* Reset the transmit DMA subsystem
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*/
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static void mace_txdma_reset(struct net_device *dev)
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{
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struct mace_data *mp = netdev_priv(dev);
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volatile struct mace *mace = mp->mace;
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u8 maccc;
|
|
psc_write_word(PSC_ENETWR_CTL, 0x8800);
|
|
maccc = mace->maccc;
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mace->maccc = maccc & ~ENXMT;
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|
mp->tx_slot = mp->tx_sloti = 0;
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mp->tx_count = N_TX_RING;
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|
psc_write_word(PSC_ENETWR_CTL, 0x0400);
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mace->maccc = maccc;
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}
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|
/*
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* Disable DMA
|
*/
|
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static void mace_dma_off(struct net_device *dev)
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{
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psc_write_word(PSC_ENETRD_CTL, 0x8800);
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psc_write_word(PSC_ENETRD_CTL, 0x1000);
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psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100);
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psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100);
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psc_write_word(PSC_ENETWR_CTL, 0x8800);
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psc_write_word(PSC_ENETWR_CTL, 0x1000);
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psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100);
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psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100);
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}
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static const struct net_device_ops mace_netdev_ops = {
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.ndo_open = mace_open,
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.ndo_stop = mace_close,
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.ndo_start_xmit = mace_xmit_start,
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.ndo_tx_timeout = mace_tx_timeout,
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.ndo_set_rx_mode = mace_set_multicast,
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.ndo_set_mac_address = mace_set_address,
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.ndo_validate_addr = eth_validate_addr,
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};
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/*
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* Not really much of a probe. The hardware table tells us if this
|
* model of Macintrash has a MACE (AV macintoshes)
|
*/
|
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static int mace_probe(struct platform_device *pdev)
|
{
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int j;
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struct mace_data *mp;
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unsigned char *addr;
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struct net_device *dev;
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unsigned char checksum = 0;
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int err;
|
|
dev = alloc_etherdev(PRIV_BYTES);
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if (!dev)
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return -ENOMEM;
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|
mp = netdev_priv(dev);
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mp->device = &pdev->dev;
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platform_set_drvdata(pdev, dev);
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SET_NETDEV_DEV(dev, &pdev->dev);
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|
dev->base_addr = (u32)MACE_BASE;
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mp->mace = MACE_BASE;
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|
dev->irq = IRQ_MAC_MACE;
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mp->dma_intr = IRQ_MAC_MACE_DMA;
|
|
mp->chipid = mp->mace->chipid_hi << 8 | mp->mace->chipid_lo;
|
|
/*
|
* The PROM contains 8 bytes which total 0xFF when XOR'd
|
* together. Due to the usual peculiar apple brain damage
|
* the bytes are spaced out in a strange boundary and the
|
* bits are reversed.
|
*/
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addr = MACE_PROM;
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|
for (j = 0; j < 6; ++j) {
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u8 v = bitrev8(addr[j<<4]);
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checksum ^= v;
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dev->dev_addr[j] = v;
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}
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for (; j < 8; ++j) {
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checksum ^= bitrev8(addr[j<<4]);
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}
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if (checksum != 0xFF) {
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free_netdev(dev);
|
return -ENODEV;
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}
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dev->netdev_ops = &mace_netdev_ops;
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dev->watchdog_timeo = TX_TIMEOUT;
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|
pr_info("Onboard MACE, hardware address %pM, chip revision 0x%04X\n",
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dev->dev_addr, mp->chipid);
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err = register_netdev(dev);
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if (!err)
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return 0;
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|
free_netdev(dev);
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return err;
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}
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/*
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* Reset the chip.
|
*/
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static void mace_reset(struct net_device *dev)
|
{
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struct mace_data *mp = netdev_priv(dev);
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volatile struct mace *mb = mp->mace;
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int i;
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|
/* soft-reset the chip */
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i = 200;
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while (--i) {
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mb->biucc = SWRST;
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if (mb->biucc & SWRST) {
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udelay(10);
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continue;
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}
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break;
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}
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if (!i) {
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printk(KERN_ERR "macmace: cannot reset chip!\n");
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return;
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}
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mb->maccc = 0; /* turn off tx, rx */
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mb->imr = 0xFF; /* disable all intrs for now */
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i = mb->ir;
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|
mb->biucc = XMTSP_64;
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mb->utr = RTRD;
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mb->fifocc = XMTFW_8 | RCVFW_64 | XMTFWU | RCVFWU;
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mb->xmtfc = AUTO_PAD_XMIT; /* auto-pad short frames */
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mb->rcvfc = 0;
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/* load up the hardware address */
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__mace_set_address(dev, dev->dev_addr);
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/* clear the multicast filter */
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if (mp->chipid == BROKEN_ADDRCHG_REV)
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mb->iac = LOGADDR;
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else {
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mb->iac = ADDRCHG | LOGADDR;
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while ((mb->iac & ADDRCHG) != 0)
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;
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}
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for (i = 0; i < 8; ++i)
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mb->ladrf = 0;
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/* done changing address */
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if (mp->chipid != BROKEN_ADDRCHG_REV)
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mb->iac = 0;
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mb->plscc = PORTSEL_AUI;
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}
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/*
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* Load the address on a mace controller.
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*/
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static void __mace_set_address(struct net_device *dev, void *addr)
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{
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struct mace_data *mp = netdev_priv(dev);
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volatile struct mace *mb = mp->mace;
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unsigned char *p = addr;
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int i;
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/* load up the hardware address */
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if (mp->chipid == BROKEN_ADDRCHG_REV)
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mb->iac = PHYADDR;
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else {
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mb->iac = ADDRCHG | PHYADDR;
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while ((mb->iac & ADDRCHG) != 0)
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;
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}
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for (i = 0; i < 6; ++i)
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mb->padr = dev->dev_addr[i] = p[i];
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if (mp->chipid != BROKEN_ADDRCHG_REV)
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mb->iac = 0;
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}
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static int mace_set_address(struct net_device *dev, void *addr)
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{
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struct mace_data *mp = netdev_priv(dev);
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volatile struct mace *mb = mp->mace;
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unsigned long flags;
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u8 maccc;
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local_irq_save(flags);
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maccc = mb->maccc;
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__mace_set_address(dev, addr);
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mb->maccc = maccc;
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local_irq_restore(flags);
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return 0;
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}
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/*
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* Open the Macintosh MACE. Most of this is playing with the DMA
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* engine. The ethernet chip is quite friendly.
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*/
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static int mace_open(struct net_device *dev)
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{
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struct mace_data *mp = netdev_priv(dev);
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volatile struct mace *mb = mp->mace;
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/* reset the chip */
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mace_reset(dev);
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if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) {
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printk(KERN_ERR "%s: can't get irq %d\n", dev->name, dev->irq);
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return -EAGAIN;
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}
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if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) {
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printk(KERN_ERR "%s: can't get irq %d\n", dev->name, mp->dma_intr);
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free_irq(dev->irq, dev);
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return -EAGAIN;
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}
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/* Allocate the DMA ring buffers */
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|
mp->tx_ring = dma_alloc_coherent(mp->device,
|
N_TX_RING * MACE_BUFF_SIZE,
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&mp->tx_ring_phys, GFP_KERNEL);
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if (mp->tx_ring == NULL)
|
goto out1;
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|
mp->rx_ring = dma_alloc_coherent(mp->device,
|
N_RX_RING * MACE_BUFF_SIZE,
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&mp->rx_ring_phys, GFP_KERNEL);
|
if (mp->rx_ring == NULL)
|
goto out2;
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mace_dma_off(dev);
|
|
/* Not sure what these do */
|
|
psc_write_word(PSC_ENETWR_CTL, 0x9000);
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psc_write_word(PSC_ENETRD_CTL, 0x9000);
|
psc_write_word(PSC_ENETWR_CTL, 0x0400);
|
psc_write_word(PSC_ENETRD_CTL, 0x0400);
|
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mace_rxdma_reset(dev);
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mace_txdma_reset(dev);
|
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/* turn it on! */
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mb->maccc = ENXMT | ENRCV;
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/* enable all interrupts except receive interrupts */
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mb->imr = RCVINT;
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return 0;
|
|
out2:
|
dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE,
|
mp->tx_ring, mp->tx_ring_phys);
|
out1:
|
free_irq(dev->irq, dev);
|
free_irq(mp->dma_intr, dev);
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return -ENOMEM;
|
}
|
|
/*
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* Shut down the mace and its interrupt channel
|
*/
|
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static int mace_close(struct net_device *dev)
|
{
|
struct mace_data *mp = netdev_priv(dev);
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volatile struct mace *mb = mp->mace;
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mb->maccc = 0; /* disable rx and tx */
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mb->imr = 0xFF; /* disable all irqs */
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mace_dma_off(dev); /* disable rx and tx dma */
|
|
return 0;
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}
|
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/*
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* Transmit a frame
|
*/
|
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static netdev_tx_t mace_xmit_start(struct sk_buff *skb, struct net_device *dev)
|
{
|
struct mace_data *mp = netdev_priv(dev);
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unsigned long flags;
|
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/* Stop the queue since there's only the one buffer */
|
|
local_irq_save(flags);
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netif_stop_queue(dev);
|
if (!mp->tx_count) {
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printk(KERN_ERR "macmace: tx queue running but no free buffers.\n");
|
local_irq_restore(flags);
|
return NETDEV_TX_BUSY;
|
}
|
mp->tx_count--;
|
local_irq_restore(flags);
|
|
dev->stats.tx_packets++;
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dev->stats.tx_bytes += skb->len;
|
|
/* We need to copy into our xmit buffer to take care of alignment and caching issues */
|
skb_copy_from_linear_data(skb, mp->tx_ring, skb->len);
|
|
/* load the Tx DMA and fire it off */
|
|
psc_write_long(PSC_ENETWR_ADDR + mp->tx_slot, (u32) mp->tx_ring_phys);
|
psc_write_long(PSC_ENETWR_LEN + mp->tx_slot, skb->len);
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psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800);
|
|
mp->tx_slot ^= 0x10;
|
|
dev_kfree_skb(skb);
|
|
return NETDEV_TX_OK;
|
}
|
|
static void mace_set_multicast(struct net_device *dev)
|
{
|
struct mace_data *mp = netdev_priv(dev);
|
volatile struct mace *mb = mp->mace;
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int i;
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u32 crc;
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u8 maccc;
|
unsigned long flags;
|
|
local_irq_save(flags);
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maccc = mb->maccc;
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mb->maccc &= ~PROM;
|
|
if (dev->flags & IFF_PROMISC) {
|
mb->maccc |= PROM;
|
} else {
|
unsigned char multicast_filter[8];
|
struct netdev_hw_addr *ha;
|
|
if (dev->flags & IFF_ALLMULTI) {
|
for (i = 0; i < 8; i++) {
|
multicast_filter[i] = 0xFF;
|
}
|
} else {
|
for (i = 0; i < 8; i++)
|
multicast_filter[i] = 0;
|
netdev_for_each_mc_addr(ha, dev) {
|
crc = ether_crc_le(6, ha->addr);
|
/* bit number in multicast_filter */
|
i = crc >> 26;
|
multicast_filter[i >> 3] |= 1 << (i & 7);
|
}
|
}
|
|
if (mp->chipid == BROKEN_ADDRCHG_REV)
|
mb->iac = LOGADDR;
|
else {
|
mb->iac = ADDRCHG | LOGADDR;
|
while ((mb->iac & ADDRCHG) != 0)
|
;
|
}
|
for (i = 0; i < 8; ++i)
|
mb->ladrf = multicast_filter[i];
|
if (mp->chipid != BROKEN_ADDRCHG_REV)
|
mb->iac = 0;
|
}
|
|
mb->maccc = maccc;
|
local_irq_restore(flags);
|
}
|
|
static void mace_handle_misc_intrs(struct net_device *dev, int intr)
|
{
|
struct mace_data *mp = netdev_priv(dev);
|
volatile struct mace *mb = mp->mace;
|
static int mace_babbles, mace_jabbers;
|
|
if (intr & MPCO)
|
dev->stats.rx_missed_errors += 256;
|
dev->stats.rx_missed_errors += mb->mpc; /* reading clears it */
|
if (intr & RNTPCO)
|
dev->stats.rx_length_errors += 256;
|
dev->stats.rx_length_errors += mb->rntpc; /* reading clears it */
|
if (intr & CERR)
|
++dev->stats.tx_heartbeat_errors;
|
if (intr & BABBLE)
|
if (mace_babbles++ < 4)
|
printk(KERN_DEBUG "macmace: babbling transmitter\n");
|
if (intr & JABBER)
|
if (mace_jabbers++ < 4)
|
printk(KERN_DEBUG "macmace: jabbering transceiver\n");
|
}
|
|
static irqreturn_t mace_interrupt(int irq, void *dev_id)
|
{
|
struct net_device *dev = (struct net_device *) dev_id;
|
struct mace_data *mp = netdev_priv(dev);
|
volatile struct mace *mb = mp->mace;
|
int intr, fs;
|
unsigned long flags;
|
|
/* don't want the dma interrupt handler to fire */
|
local_irq_save(flags);
|
|
intr = mb->ir; /* read interrupt register */
|
mace_handle_misc_intrs(dev, intr);
|
|
if (intr & XMTINT) {
|
fs = mb->xmtfs;
|
if ((fs & XMTSV) == 0) {
|
printk(KERN_ERR "macmace: xmtfs not valid! (fs=%x)\n", fs);
|
mace_reset(dev);
|
/*
|
* XXX mace likes to hang the machine after a xmtfs error.
|
* This is hard to reproduce, resetting *may* help
|
*/
|
}
|
/* dma should have finished */
|
if (!mp->tx_count) {
|
printk(KERN_DEBUG "macmace: tx ring ran out? (fs=%x)\n", fs);
|
}
|
/* Update stats */
|
if (fs & (UFLO|LCOL|LCAR|RTRY)) {
|
++dev->stats.tx_errors;
|
if (fs & LCAR)
|
++dev->stats.tx_carrier_errors;
|
else if (fs & (UFLO|LCOL|RTRY)) {
|
++dev->stats.tx_aborted_errors;
|
if (mb->xmtfs & UFLO) {
|
dev->stats.tx_fifo_errors++;
|
mace_txdma_reset(dev);
|
}
|
}
|
}
|
}
|
|
if (mp->tx_count)
|
netif_wake_queue(dev);
|
|
local_irq_restore(flags);
|
|
return IRQ_HANDLED;
|
}
|
|
static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue)
|
{
|
struct mace_data *mp = netdev_priv(dev);
|
volatile struct mace *mb = mp->mace;
|
unsigned long flags;
|
|
local_irq_save(flags);
|
|
/* turn off both tx and rx and reset the chip */
|
mb->maccc = 0;
|
printk(KERN_ERR "macmace: transmit timeout - resetting\n");
|
mace_txdma_reset(dev);
|
mace_reset(dev);
|
|
/* restart rx dma */
|
mace_rxdma_reset(dev);
|
|
mp->tx_count = N_TX_RING;
|
netif_wake_queue(dev);
|
|
/* turn it on! */
|
mb->maccc = ENXMT | ENRCV;
|
/* enable all interrupts except receive interrupts */
|
mb->imr = RCVINT;
|
|
local_irq_restore(flags);
|
}
|
|
/*
|
* Handle a newly arrived frame
|
*/
|
|
static void mace_dma_rx_frame(struct net_device *dev, struct mace_frame *mf)
|
{
|
struct sk_buff *skb;
|
unsigned int frame_status = mf->rcvsts;
|
|
if (frame_status & (RS_OFLO | RS_CLSN | RS_FRAMERR | RS_FCSERR)) {
|
dev->stats.rx_errors++;
|
if (frame_status & RS_OFLO)
|
dev->stats.rx_fifo_errors++;
|
if (frame_status & RS_CLSN)
|
dev->stats.collisions++;
|
if (frame_status & RS_FRAMERR)
|
dev->stats.rx_frame_errors++;
|
if (frame_status & RS_FCSERR)
|
dev->stats.rx_crc_errors++;
|
} else {
|
unsigned int frame_length = mf->rcvcnt + ((frame_status & 0x0F) << 8 );
|
|
skb = netdev_alloc_skb(dev, frame_length + 2);
|
if (!skb) {
|
dev->stats.rx_dropped++;
|
return;
|
}
|
skb_reserve(skb, 2);
|
skb_put_data(skb, mf->data, frame_length);
|
|
skb->protocol = eth_type_trans(skb, dev);
|
netif_rx(skb);
|
dev->stats.rx_packets++;
|
dev->stats.rx_bytes += frame_length;
|
}
|
}
|
|
/*
|
* The PSC has passed us a DMA interrupt event.
|
*/
|
|
static irqreturn_t mace_dma_intr(int irq, void *dev_id)
|
{
|
struct net_device *dev = (struct net_device *) dev_id;
|
struct mace_data *mp = netdev_priv(dev);
|
int left, head;
|
u16 status;
|
u32 baka;
|
|
/* Not sure what this does */
|
|
while ((baka = psc_read_long(PSC_MYSTERY)) != psc_read_long(PSC_MYSTERY));
|
if (!(baka & 0x60000000)) return IRQ_NONE;
|
|
/*
|
* Process the read queue
|
*/
|
|
status = psc_read_word(PSC_ENETRD_CTL);
|
|
if (status & 0x2000) {
|
mace_rxdma_reset(dev);
|
} else if (status & 0x0100) {
|
psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100);
|
|
left = psc_read_long(PSC_ENETRD_LEN + mp->rx_slot);
|
head = N_RX_RING - left;
|
|
/* Loop through the ring buffer and process new packages */
|
|
while (mp->rx_tail < head) {
|
mace_dma_rx_frame(dev, (struct mace_frame*) (mp->rx_ring
|
+ (mp->rx_tail * MACE_BUFF_SIZE)));
|
mp->rx_tail++;
|
}
|
|
/* If we're out of buffers in this ring then switch to */
|
/* the other set, otherwise just reactivate this one. */
|
|
if (!left) {
|
mace_load_rxdma_base(dev, mp->rx_slot);
|
mp->rx_slot ^= 0x10;
|
} else {
|
psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800);
|
}
|
}
|
|
/*
|
* Process the write queue
|
*/
|
|
status = psc_read_word(PSC_ENETWR_CTL);
|
|
if (status & 0x2000) {
|
mace_txdma_reset(dev);
|
} else if (status & 0x0100) {
|
psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100);
|
mp->tx_sloti ^= 0x10;
|
mp->tx_count++;
|
}
|
return IRQ_HANDLED;
|
}
|
|
MODULE_LICENSE("GPL");
|
MODULE_DESCRIPTION("Macintosh MACE ethernet driver");
|
MODULE_ALIAS("platform:macmace");
|
|
static int mac_mace_device_remove(struct platform_device *pdev)
|
{
|
struct net_device *dev = platform_get_drvdata(pdev);
|
struct mace_data *mp = netdev_priv(dev);
|
|
unregister_netdev(dev);
|
|
free_irq(dev->irq, dev);
|
free_irq(IRQ_MAC_MACE_DMA, dev);
|
|
dma_free_coherent(mp->device, N_RX_RING * MACE_BUFF_SIZE,
|
mp->rx_ring, mp->rx_ring_phys);
|
dma_free_coherent(mp->device, N_TX_RING * MACE_BUFF_SIZE,
|
mp->tx_ring, mp->tx_ring_phys);
|
|
free_netdev(dev);
|
|
return 0;
|
}
|
|
static struct platform_driver mac_mace_driver = {
|
.probe = mace_probe,
|
.remove = mac_mace_device_remove,
|
.driver = {
|
.name = mac_mace_string,
|
},
|
};
|
|
module_platform_driver(mac_mace_driver);
|
